Apparatus and method for delay locked loop clock control
By using a delay locking ring (DLL) circuit system in semiconductor memory to tightly control the window of internal clock signals, the high power consumption problem caused by rapid clock signal generation is solved, and more efficient memory operation is achieved.
Patent Information
- Application Number
- CN202411088501.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-19
- Filing Date
- 2024-08-09
- Publication Date
- 2025-06-20
AI Technical Summary
In semiconductor memory, when clock signals are generated quickly to improve memory access speed, power consumption is large, and the window control of clock signals is not strict, which affects the operating efficiency of the memory.
The delay locking loop (DLL) circuit system is used to strictly control the window of the internal clock signal. By measuring the total number of periods of the clock signal along the propagation path, the delay of the DLL circuit is adjusted to match the phase of the input clock signal, and the phase-adjusted internal clock signal is stopped after the predetermined count value exceeds.
By strictly controlling the window of clock signals, the power consumption of semiconductor memory is reduced and the memory operation efficiency is improved.
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Figure CN120179020A_ABST
Abstract
Description
Technical Field
[0001] This application relates to devices and methods for clock control of a delay-locked loop. Background Art
[0002] High data reliability, high-speed memory access, low power consumption, and reduced chip size are characteristics required for semiconductor memories. To achieve a higher memory access speed, a clock signal is used as a reference signal to adjust the operation timing in a semiconductor memory. A semiconductor device may generate an internal clock signal, and the faster the clock signal, the greater the power likely required to continuously generate the clock signal. By more strictly controlling the window for generating the clock signal, there may be an opportunity to reduce power consumption. Summary of the Invention
[0003] In one aspect, this application provides a device including: a clock input circuit configured to provide an internal clock signal based on an external clock signal; a command decoder configured to provide a command signal based on a received command; an internal clock generator having a delay-locked loop (DLL) circuit, the DLL circuit configured to receive the internal clock signal and the command signal and provide a phase-adjusted internal clock signal based on the internal clock signal, wherein, in response to receiving the command signal, the DLL circuit is configured to enable the phase-adjusted internal clock signal to be provided to an input / output circuit and stop providing the phase-adjusted internal clock signal after the count of the clock cycles of the internal clock signal exceeds a predetermined count value, wherein the predetermined count value is based on the total signal propagation time of the internal clock signal from the output of the internal clock circuit to the output terminal of the input / output circuit.
[0004] In one aspect, this application provides a device including: a clock input circuit configured to receive an external clock signal and provide an internal clock signal; a command decoder configured to receive a command and provide a command signal; an internal clock generator having a delay-locked loop (DLL) circuit, the DLL circuit configured to receive the internal clock signal and the command signal and provide the internal clock signal through a delay line to provide a phase-adjusted internal clock signal, wherein, in response to receiving the command signal, the DLL circuit is configured to enable the internal clock signal to be provided to the delay line in response to receiving the command signal and stop providing the internal clock signal after the count of the clock cycles of the internal clock signal exceeds a predetermined count value, wherein the predetermined count value is based on the total signal propagation time of the internal clock signal from the output of the internal clock circuit to the output terminal of the input / output circuit.
[0005] In one aspect, the present application provides a method, which includes: receiving an external clock signal and a command at a semiconductor device; generating an internal clock signal in response to the external clock signal; generating a command signal in response to the command; in response to receiving the command signal: enabling a phase-adjusted internal clock signal generated based on the internal clock signal to be provided to an input / output circuit; and stopping providing the phase-adjusted internal clock signal to the input / output circuit after the count of the clock cycles of the internal clock signal exceeds a predetermined count value, where the predetermined count value is based on the total signal propagation time from the output of the internal clock circuit to the output terminal of the input / output circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 Schematic block diagram illustrating a semiconductor device 100 according to an embodiment of the present disclosure.
[0007] Figure 2 Block diagram of a semiconductor device 200 including a DLL circuit 220 according to an embodiment of the present disclosure.
[0008] Figure 3 Block diagram of a semiconductor device 300 including a DLL circuit 320 according to an embodiment of the present disclosure.
[0009] Figure 4 Block diagram of a clock control circuit 400 according to an embodiment of the present disclosure.
[0010] Figure 5 Block diagram of an edge detection circuit 500 according to an embodiment of the present disclosure.
[0011] Figure 6 Explanation of a timing diagram 600 depicting the operation of a clock circuit system during a read operation according to an embodiment of the present disclosure.
[0012] Figure 7 Block diagram of a semiconductor device 700 including a DLL circuit 220 according to an embodiment of the present disclosure.
[0013] Figure 8 Explanation of a timing diagram 800 depicting the operation of a clock circuit system during an ODT operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0014] Certain details are set forth below to provide a sufficient understanding of embodiments of the present disclosure. However, those skilled in the art will appreciate that embodiments of the present disclosure may be practiced without these specific details. In addition, specific embodiments of the present disclosure described herein are provided by way of example and are not intended to limit the scope of the present disclosure to these specific embodiments.
[0015] This application describes examples of semiconductor devices that include a delay locked loop (DLL) circuit system that more tightly controls the window in which an internal clock signal can be generated. When an external clock signal is received at the semiconductor device, the clock phase of the internal clock signal based on the external clock signal may be delayed due to the inherent delays of the components of the semiconductor device. At high operating speeds, distortion of the clock signal duty cycle can adversely affect the operation of the semiconductor device. To accommodate these delay and distortion effects, the clock path can include delay circuits. A DLL circuit can be used to adjust the clock phase to match the phase of the external clock.
[0016] The DLL circuit can include a delay line that includes a series of adjustable delays configured to align the phase of an input signal with the phase of an output signal. When powered on, the DLL circuit can perform an initialization of the measurement of the phase difference between the input clock and the clock used at the downstream circuit system. During initialization, the DLL circuit can include a detector that detects the number of cycles longer than the inherent delay and can thus adjust the delay of the delay line to match the phase of the input clock signal.
[0017] The adjusted internal clock signal can be provided to the downstream circuit system to control the timing of certain operations. To limit power consumption, the circuitry of the semiconductor device can control the window when generating the internal clock signal or providing it to the downstream circuit system. Due to the timing differences between different semiconductor devices, these windows can be many clock cycles longer than needed to complete the desired operation. Thus, the DLL circuit can include additional circuitry configured to measure the length of the entire delay path and more tightly control the window in which the internal clock signal is generated. By more tightly controlling the window, the semiconductor device can consume less power compared to embodiments with longer windows.
[0018] Figure 1 A schematic block diagram illustrating a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a memory die. The memory die can include a command / address input circuit 105, an address decoder 110, a command decoder 115, a clock input circuit 120, an internal clock generator 130, a row decoder 140, a column decoder 145, a memory array 150, read / write amplifiers 155, an I / O circuit 160, and a power circuit 170.
[0019] In some embodiments, the semiconductor device 100 may include, but is not limited to, a dynamic random access memory (DRAM) device integrated into, for example, a single semiconductor chip, such as double data rate (DDR) DDR4, DDR5, low power DDR (LPDDR), graphics DDR (GDDR) GDDR5, GDDR5X, GDDR6. The die may be mounted on an external substrate, such as a memory module substrate, a motherboard, etc. The semiconductor device 100 may further include a memory array 150. The memory array 150 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 140, and selection of the bit lines BL is performed by a column decoder 145. Sense amplifiers (SA) are located for their corresponding bit lines BL and connected to at least one respective local I / O line (LIOT / B), which in turn is coupled via a transfer gate (TG) acting as a switch to a respective one of at least two main I / O line pairs (MIOT / B).
[0020] The semiconductor device 100 may employ a plurality of external terminals, the plurality of external terminals including address and command terminals coupled to a command / address bus (C / A), clock terminals CK and / CK, data terminals DQ, DQS, and DM, power supply terminals VDD2, VSS, VDDQ, and VSSQ.
[0021] Address signals and bank address signals may be supplied externally to the command / address terminals. The address signals and bank address signals supplied to the address terminals are transmitted via a command / address input circuit 105 to an address decoder 110. The address decoder 110 receives the address signals and decodes the address signals to provide decoded address signals ADD. The ADD signals include a decoded row address signal and a decoded column address signal. The decoded row address signal is provided to the row decoder 140, and the decoded column address signal is provided to the column decoder 145. The address decoder 110 also receives the bank address signals and supplies the bank address signals to the row decoder 140 and the column decoder 145.
[0022] Command signals may further be supplied externally (such as, for example, from a memory controller) to the command / address terminals. The command signals may be provided via the C / A bus via the command / address input circuit 105 to a command decoder 115. The command decoder 115 decodes the command signals to generate various internal commands, the internal commands including a row command signal ACT for selecting word lines and a column command signal read / write for selecting bit lines, such as a read command or a write command, and a test mode signal.
[0023] Therefore, when a read command is issued and a row address and a column address are supplied in a timely manner with the read command, read data is read from the memory cells specified by these row and column addresses in the memory array 150. The read data DQ is output to the outside from the data terminals DQ (data), DQS (data strobe), and DM via the read / write amplifier 155 and the input / output circuit 160. Similarly, when a write command is issued and a row address and a column address are supplied in a timely manner with this command, and then write data is supplied to the data terminals DQ, DQS, DM, the write data is received by the data receiver in the input / output circuit 160 and is supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155 and is written into the memory cells specified by the row address and the column address.
[0024] Turning to the external terminals included in the semiconductor device 100, an external clock signal and a complementary external clock signal are supplied to the clock terminals CK and / CK, respectively. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 105. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generator 130, and thus a phase-controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. The phase-controlled internal clock signal LCLK is supplied to the input / output circuit 160 and is used as a timing signal for determining the output timing of the read data.
[0025] In some instances, the internal clock generator 130 can include a DLL circuit 132. The DLL circuit 132 can include a delay line that includes a series of adjustable delays configured to align the phase of an input signal with the phase of an output signal. When power is turned on, the DLL circuit can perform initialization of the measurement of the phase difference between the ICLK signal and the LCLK signal. During initialization, the DLL circuit 132 can include a detector that detects the number of cycles longer than the inherent delay, and can thus adjust the delay of the delay line to match the phase of the input clock signal. The provision of the LCLK signal can be based on the command signal CMD received from the command decoder 115. However, compared with the corresponding operations using the LCLK signal, the operation based only on the CMD signal may result in a longer window for generating the LCLK signal. Therefore, the DLL circuit 132 can include a circuit that more strictly controls the window for generating the LCLK signal by measuring the total number of cycles of the ICLK signal that the signal takes to propagate along the propagation path to the I / O circuit 160. Using this measurement, the DLL circuit 132 can control when to stop providing the LCLK signal based on this count of the clock cycles. By more strictly controlling the window, the semiconductor device 100 can consume less power compared to setting the window to a fixed time or number of clock cycles without considering the implementation of the device.
[0026] Power supply potentials VDD and VSS are supplied to the power terminals. These power supply potentials VDD2 and VSS are supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 generates various internal potentials VARY, VKK, VPERI, etc. based on the power supply potentials VDD2 and VSS. The internal potential VARY is mainly used in the sense amplifiers included in the memory array 150, the internal potential VKK is mainly used in the row decoder 140, and the internal potential VPERI is used in many other circuit blocks.
[0027] Power supply potentials VDDQ and VSSQ are also supplied to the power terminals. These power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 160. The power supply potentials VDDQ and VSSQ are generally the same potentials as the power supply potentials VDD2 and VSS, respectively. However, dedicated power supply potentials VDDQ and VSSQ can be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.
[0028] Figure 2 A block diagram of a semiconductor device 200 including a DLL circuit 220 according to an embodiment of the present disclosure. In some examples, Figure 1 The semiconductor device 100 can implement the semiconductor device 200. The semiconductor device 200 may include a clock input circuit 210, a command decoder 212, a DLL circuit 220, a clock enable circuit 230, and a QED and QES generation circuit 240, and an input / output circuit 250.
[0029] The clock input circuit 210 can receive an external clock signal and can generate an internal clock signal ICLK based on the external clock signal. The internal clock signal ICLK is supplied to internal clock generators (e.g., the DLL circuit 220, the clock enable circuit 230, and the QED and QES generation circuit 240), and thus a phase-controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. The phase-controlled internal clock signal LCLK is supplied to the input / output circuit 250 and is used as a timing signal for determining the output timing of the read data.
[0030] Command signals can be provided to the command decoder 212 via the C / A bus. The command decoder 212 decodes the command signals to generate various internal commands, the internal commands including a row command signal for selecting a word line and a column command signal RD_cmd for selecting a bit line, such as a read command. Thus, when a read command is issued and the read command is supplied to the row address and the column address in a timely manner, read data (not shown) is read from the memory cells specified by these row addresses and column addresses in the memory array (not shown) and the read data is provided to the input / output circuit 250 to support the output of the read data.
[0031] The DLL circuit 220 can receive the ICLK signal and the RD_cmd signal. The DLL circuit 220 can include a clock delay line 222, a read delay line 224, a DLL control circuit 228, and a clock control circuit 226. The clock delay line 222 and the read delay line 224 can each include a series of adjustable delays configured to align the phase of the ICLK signal with the phase of the LCLK signal. The clock delay line 222 can provide a delayed version of the ICLK signal as the LCLK signal to the output, and the read delay line 224 can provide a delayed version of the RD_cmd as the RD_dll signal to the output. When power is turned on, the DLL control circuit 228 can perform an initialization of the measurement of the phase difference between the ICLK signal and the LCLK signal. During the initialization, the DLL control circuit 228 can include a detector that detects the number of LCLK cycles that are longer than the inherent delay, and can thus adjust the delays of the clock delay line 222 and the read delay line 224 to match the phase of the ICLK signal.
[0032] While determining the phase alignment of the ICLK and the LCLK, the DLL control circuit 228 of the DLL circuit 220 can measure the total number of clock cycles of the ICLK signal that it takes for the ICLK to propagate along the propagation path to the input / output circuit 250. To perform this measurement, the DLL control circuit 228 can receive the ICLK signal and can start counting the clock cycles. At the same time, the ICLK signal can propagate through the clock delay line 222 to the DLL control circuit 228. The DLL control circuit 228 can include a replica delay circuit that simulates the delay of the transmission path of the ICLK signal from the DLL circuit 220 to one of the plurality of data input / output terminals of the input / output circuit 250. Once the clock signal has propagated through the DLL control circuit 228, the DLL control circuit 228 can provide a LoopN signal that has a value indicating the number of clock cycles that the ICLK signal took to propagate through the clock delay line 222 and the DLL control circuit 228.
[0033] Using the LoopN signal, the clock control circuit 226 can control the provision of the clock data output strobe (QES) enable signal Clk_QES_En based on the RD_cmd and the count value. That is, starting from the time when the RD_cmd signal is received, the clock control circuit 226 can set the Clk_QES_En signal to be enabled in response to the RD_cmd signal, and can set the Clk_QES_En to be disabled after the number of clock cycles of the ICLK exceeds the count value. By controlling the window more strictly, compared with setting the window to a fixed time or number of clock cycles without considering the implementation of the device, the semiconductor device 200 can consume less power.
[0034] The clock enable circuit 230 can receive the LCLK signal and the Clk_QES_En signal. Using NAND logic, when the Clk_QES_En signal is enabled, the clock enable circuit 230 can provide the LCLK signal as the Clk_QES signal to the QED and QES generation circuit 240. When the Clk_QES_En signal is disabled, the clock enable circuit 230 can set the Clk_QES signal to a constant aperiodic value. Thus, the QES and QED signals are only enabled when it is necessary to complete the read command operation. By controlling this window more strictly, compared with setting the window to a fixed time or number of clock cycles without considering the implementation of the device, the semiconductor device 200 can consume less power.
[0035] The QED and QES generation circuit 240 can control the operation of the data output enable signal QED and the data output strobe signal QES based on the RD_dll and the Clk_QES signal. The input / output circuit 250 can provide the read data at the output (not shown) in response to the LCLK signal and the QES and QED signals.
[0036] In the operation of initial power-on, the DLL control circuit 228 of the DLL circuit 220 can start counting the clock cycles of the ICLK signal when the ICLK signal propagates through the clock delay line 222 and the DLL control circuit 228. In response to the ICLK signal propagating through the DLL control circuit 228, the DLL control circuit 228 can set the LoopN signal to a value indicating the total number of clock cycles of the ICLK signal propagating through the DLL circuit 220 to the output terminal of the input / output circuit 250, and can provide the LoopN signal to the clock control circuit 226.
[0037] Meanwhile, the DLL control circuit 228 can perform initialization of the measurement of the phase difference between the ICLK signal and the LCLK signal. During initialization, the DLL control circuit 228 can include a detector that detects the number of LCLK cycles longer than the inherent delay, and can thus adjust the delays of the clock delay line 222 and the read delay line 224 to match the phase of the ICLK signal. The clock delay line 222 and the read delay line 224 can each include a series of adjustable delays configured to align the phase of the ICLK signal with the phase of the LCLK signal. The clock delay line 222 can provide a delayed version of the ICLK signal as the LCLK signal to the output, and the read delay line 224 can provide a delayed version of the RD_cmd as the RD_dll signal to the output.
[0038] When initializing the DLL circuit 220, establishing the LoopN signal, and the DLL circuit 220 is in the phase-locked state, the CLK input circuit 210 can receive an external clock signal, and the command decoder 212 can receive a read command. In response, the CLK input circuit 210 can provide the LCLK signal, and the command decoder can provide the RD_cmd signal. In response to receiving the RD_cmd signal and the ICLK signal, the clock control circuit 226 can control the provision of the clock data output strobe (QES) enable signal Clk_QES_En. That is, starting from the time of receiving the RD_cmd signal, the clock control circuit 226 can set the Clk_QES_En signal to be enabled in response to the RD_cmd signal, and can set Clk_QES_En to be disabled after the number of clock cycles of the ICLK exceeds the LoopN count value.
[0039] When the Clk_QES_En signal is enabled, the clock enable circuit 230 can provide the LCLK signal as the Clk_QES signal to the QED and QES generation circuit 240, and when the Clk_QES_En signal is disabled, can set the Clk_QES signal to a constant aperiodic value. The QED and QES generation circuit 240 can control the operation of the data output enable signal QED and the data output strobe signal QES based on the RD_dll and the Clk_QES signal. The input / output circuit 250 can provide read data at the output (not shown) in response to the LCLK signal and the QES and QED signals.
[0040] Figure 3 Block diagram of a semiconductor device 300 including a DLL circuit 320 according to an embodiment of the present disclosure. In some instances, Figure 1 the semiconductor device 100 and / or Figure 2 the semiconductor device 200 can implement the semiconductor device 300. The semiconductor device 300 can include a clock input circuit 310 and a DLL circuit 320.
[0041] The clock input circuit 310 can receive an external clock signal and can generate an internal clock signal ICLK based on the external clock signal. The internal clock signal ICLK is supplied to the DLL circuit 320, and thus a phase-controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. The phase-controlled internal clock signal LCLK is supplied to the input / output circuit and can be used as a timing signal for determining the output timing of the read data.
[0042] The DLL circuit 320 can receive the ICLK signal and the RD_cmd signal. The DLL circuit 320 can include a delay line 322 and a DLL control circuit 328. The delay line 322 can include a series of adjustable delays configured to align the phase of the ICLK signal with the phase of the LCLK signal. The delay line 322 can provide a delayed version of the ICLK signal as the LCLK signal to the output. When power is turned on, the DLL control circuit 328 can perform initialization of the measurement of the phase difference between the ICLK signal and the LCLK signal.
[0043] The DLL control circuit 328 can include a delay pointer circuit 343, a phase detector 344, a clock path replica circuit 345, and a clock counter 346. The clock path replica circuit 345 can simulate the delay of the transmission path of the ICLK signal from the DLL circuit 320 to one of the multiple data input / output terminals of the input / output circuit. During initialization, the phase detector 344 can detect the number of LCLK cycles that are longer than the inherent delay, and can thus set the delay pointer circuit 343 to adjust the delay of the delay line 322 to match the phase of the ICLK signal.
[0044] While determining the phase alignment of ICLK and LCLK, the clock counter 346 can count the total number of ICLK signal cycles that ICLK takes to propagate along the propagation path through the clock path replica circuit 345. To perform this measurement, the clock counter 346 can receive the ICLK signal and can start counting the clock cycles. At the same time, the ICLK signal can propagate through the delay line 322 and the clock counter 346. Once the clock signal propagates through the clock counter 346, 346 can provide LoopN <x:0>signal, the LoopN <x:0>The signal has a value indicating the number of clock cycles it takes for the ICLK signal to propagate through the delay line 322 and the clock counter 346. LoopN <x:0>The signal can be used to provide a controllable clock data output strobe enable signal (not shown).
[0045] During an initial power-on operation, the clock counter 346 of the DLL circuit 320 can start counting the clock cycles of the ICLK signal as the ICLK signal propagates through the delay line 322 and the clock counter 346. In response to the ICLK signal propagating through the clock counter 346, the clock counter 346 can set LoopN <x:0>The signal is set to a value indicating the total number of clock cycles for the ICLK signal to propagate through the DLL circuit 320 to the output terminal of the input / output circuit 350.
[0046] Meanwhile, the phase detector 344 can perform initialization of the measurement of the phase difference between the ICLK signal and the LCLK signal. During initialization, the clock counter 346 can include a detector that detects the number of LCLK cycles longer than the inherent delay, and can thus set the delay pointer circuit 343 to adjust the delay of the delay line 322 to match the phase of the ICLK signal. The delay line 322 can include a series of adjustable delays configured to align the phase of the ICLK signal with the phase of the LCLK signal. The delay line 322 can provide a delayed version of the ICLK signal as the LCLK signal to the output.
[0047] Figure 4 FIG. is a block diagram of a clock control circuit 400 according to an embodiment of the present disclosure. In some instances, Figure 1 semiconductor device 100 of Figure 2 and / or semiconductor device 200 of
[0048] The edge detection circuit 410 can be configured to receive the RD_cmd signal, and after detecting that the RD_cmd signal transitions to a logic high value, can set the output Q of each of the set of serially-coupled flip-flops 420(0)-(N) to a high value.
[0049] The set of serially-coupled flip-flops 420(0)-(N) can each receive an internal clock signal ICLK, and the first flip-flop 420(0) can receive a low voltage supply signal VSS (e.g., a logic low value). In response to the ICLK signal, the first flip-flop 420(0) can transition its output Q to the VSS signal value, which is coupled to the input D of the second flip-flop 420(1). In response to a second transition of the ICLK signal, the second flip-flop 420(1) can transition its output Q to the VSS signal value, which is coupled to the input D of the third flip-flop 420(2). This propagation of the VSS signal can continue to the flip-flop 420(N).
[0050] The multiplexer 430 may include different respective inputs coupled to each individual output Q of the set of serially-coupled flip-flops 420(0)-(N). Based on the value of the LoopN signal, the multiplexer 430 may strobe one of those signals as the clock data output strobe (QES) enable signal Clk_QES_En to the output. The LoopN value may be set based on the ICLK signal propagated through the DLL circuit to the output terminal of the input / output circuit.
[0051] Figure 5 FIG. 5 is a block diagram of an edge detection circuit 500 according to an embodiment of the present disclosure. In some examples, Figure 1 semiconductor device 100 of Figure 2 semiconductor device 200 and / or Figure 4 the clock control circuit 400 of may implement the edge detection circuit 500. The semiconductor device edge detection circuit 500 may include an inverter 510, a delay circuit 520, a NAND gate 530, an OR gate 540, and a NAND gate 550. The edge detection circuit 500 may detect an edge transition of the RD_cmd signal to provide a set signal in response to the edge detection.
[0052] The inverter 510 and the delay circuit 520 may be configured to receive the RD_cmd signal. The inverter 510 may provide an inverted version of the RD_cmd signal to the NAND gate 530 and the OR gate 540. The delay circuit 520 may provide a delayed version of the RD_cmd signal to the NAND gate 530 and the OR gate 540. Using NAND logic, the NAND gate 530 may be configured to provide a first input to the NAND gate 550 based on the outputs of the inverter 510 and the delay circuit 520. Using OR logic, the OR gate 540 may be configured to provide a second input to the NAND gate 550 based on the outputs of the inverter 510 and the delay circuit 520. Using NAND logic, the NAND gate 550 may be configured to provide the set signal based on the outputs of the NAND gate 530 and the OR gate 540.
[0053] Figure 6 FIG. 6 is an illustration of a timing diagram 600 depicting the operation of a clock circuit system according to an embodiment of the present disclosure during a read operation. In some examples, the RD_cmd signal may correspond to Figure 1 the CMD signal of Figure 2 , 4 and the RD_cmd signal of 5. The RD_dll signal, the Clk_QES signal, and the QES / QED signal may correspond to the RD_dll signal, the Clk_QES signal, and the QES / QED signal of Figure 2 respectively. The Clk_QES_En signal may correspond to Figure 2 and 4 The Clk_QES_En signal. The first timing diagram 610 may correspond to a short read case, and the second timing diagram 620 may correspond to a burst read case (as used in DDR4). Unless otherwise specified, the above description will apply to both the first timing diagram 610 and the second timing diagram 620.
[0054] At time T0, the RD_cmd signal may transition to a high value. In response, the Clk_QES_En signal may transition to a logic high value (e.g., Figure 2 of the clock control circuit 226), and in response to the Clk_QES_En signal transitioning to a logic high value, the Clk_QES signal may start switching according to a clock signal (e.g., Figure 2 of the clock enable circuit 230).
[0055] At time T1, the RD_dll signal may transition to a logic high value (e.g., Figure 2 of the read delay line 224). At time T2, the QES and QED signals may transition to a logic high value (e.g., Figure 2 of the QED and QES generation circuit 240).
[0056] For the first timing diagram 610, at time T3, the QES and QED signals may transition to a logic low value (e.g., short read). At time T5, the Clk_QES_En signal may transition to a logic low value, which may cause the Clk_QES signal to stop switching (e.g., Figure 2 of the clock enable circuit 230).
[0057] For the second timing diagram 620, at time T4, the Clk_QES_En signal may transition to a logic low value, which may cause the Clk_QES signal to stop switching (e.g., Figure 2 of the clock enable circuit 230) (burst read case), even though the QES / QED signals continue to remain high. In response to a subsequent RD_cmd, the Clk_QES_En signal will transition to a low value, which may cause the Clk_QES signal to start switching.
[0058] The timing diagram 600 is exemplary and is used to illustrate the operation of the various described embodiments. Although the timing diagram 600 depicts a particular arrangement of signal transitions of the included signals, those skilled in the art will understand that additional or different transitions may be included in different scenarios without departing from the scope of the present disclosure. Additionally, the depiction of the magnitudes of the signals represented in the timing diagram 600 is not intended to be to scale, and the representative timing is an illustrative example of the timing characteristics.
[0059] Figure 7 is a block diagram of a semiconductor device 700 including a DLL circuit 220 according to an embodiment of the present disclosure. In some instances, Figure 1 The semiconductor device 100 can implement the semiconductor device 700. The semiconductor device 700 is depicted as processing an on-die termination command ODT_cmd. The semiconductor device 700 can include a clock input circuit 210, a command decoder 212, a DLL circuit 220, a clock enable circuit 730, and an ODT circuit 740, as well as an input / output circuit 250. The semiconductor device 700 can include elements previously described with respect to Figure 2 the semiconductor device 200. Figure 7 In Figure 2 the same reference numerals as those used in
[0060] The command decoder 212 can decode the command signal to generate various internal commands, including the ODT_cmd that propagates to the input / output circuit 250.
[0061] The DLL circuit 220 can receive the ICLK signal and the ODT_cmd signal. When power is turned on, the DLL control circuit 228 can perform initialization of the measurement of the phase difference between the ICLK signal and the LCLK signal. During initialization, the DLL control circuit 228 can include a detector that detects the number of LCLK cycles longer than the inherent delay, and can thus adjust the delays of the clock delay line 222 and the read delay line 224 to match the phase of the ICLK signal. While determining the phase alignment of the ICLK and the LCLK, the DLL control circuit 228 of the DLL circuit 220 can measure the total number of ICLK signal cycles that the ICLK takes to propagate to the input / output circuit 250 along the propagation path, and can provide the measurement as the LoopN signal.
[0062] Using the LoopN signal, the clock control circuit 226 can control the provision of the clock start signal CLK_En based on the ODT_cmd and the count value. That is, starting from the time the RD_cmd signal is received, the clock control circuit 226 can set the CLK_En signal to be enabled in response to the ODT_cmd signal, and can set the CLK_En to be disabled after the number of clock cycles of the ICLK exceeds the count value. By more strictly controlling the window, the semiconductor device 700 can consume less power compared to setting the window to a fixed time or number of clock cycles without considering the implementation of the device.
[0063] Not as Figure 2 The clock enable circuit 230 shown is located after the clock delay line 222, and the clock enable circuit 730 can be located before the clock delay line 222 to save additional power by eliminating the power used by the clock delay line 222. The clock enable circuit 730 can receive the ICLK signal and the CLK_En signal. Using NAND logic, when the CLK_En signal is enabled, the clock enable circuit 730 can provide the ICLK signal to the clock delay line 222. When the CLK_En signal is disabled, the clock enable circuit 230 can set the ICLK signal to a constant aperiodic value. The ODT circuit 740 can control the operation of the ODT signal based on the LCLK signal and the ODT_dll signal from the read delay line 224. The input / output circuit 250 can provide a full ODT operation based on the ODT signal.
[0064] Figure 8 Explanation of the timing diagram 800 depicting the operation of the clock circuit system according to an embodiment of the present disclosure during the ODT operation. The ODT_cmd, ODT_dll, LCLK, Clk_EN, and ODT signals can respectively correspond to Figure 7 the ODT_cmd, ODT_dll, LCLK, Clk_En, and ODT signals of
[0065] At time T0, the ODT_cmd signal can transition to a high value. In response, the Clk_En signal can transition to a logic high value (e.g., Figure 7 the clock control circuit 226 of Figure 7 ), and in response to the Clk_En signal transitioning to a logic high value, the LCLK signal can start switching according to the clock signal (e.g.,
[0066] the clock enable circuit 730 and the clock delay line 222 of Figure 7 At time T1, the RD_dll signal can transition to a logic high value (e.g., Figure 7 the read delay line 224 of
[0067] For the first timing diagram 810, at time T3, the QES and QED signals can transition to logic low values (e.g., short read). At time T5, the Clk_En signal can transition to a logic low value, which can cause the LCLK signal to stop switching (e.g., Figure 7 the clock enable circuit 730 and the clock delay line 222 of
[0068] For the second timing diagram 820, at time T4, the Clk_En signal may transition to a logic low value, which may cause the LCLK signal to stop toggling (e.g., Figure 7 the clock enable circuit 730 and clock delay line 222 of )(long ODT case), even if the QES / QED signals continue to remain high. In response to a subsequent ODT_cmd, the Clk_En signal will transition to a low value, which may cause the LCLK signal to start toggling.
[0069] Timing diagram 800 is exemplary and is used to illustrate the operation of the various described embodiments. Although timing diagram 800 depicts a particular arrangement of signal transitions of the included signals, those skilled in the art will appreciate that additional or different transitions may be included in different scenarios without departing from the scope of the present disclosure. Additionally, the depiction of the magnitudes of the signals represented in timing diagram 800 is not intended to be to scale, and the representative timing is an illustrative example of the timing characteristics.
[0070] From the foregoing, it should be understood that although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims.
Claims
1. A device comprising: a clock input circuit configured to provide an internal clock signal based on an external clock signal; a command decoder configured to provide a command signal based on the received command; An internal clock generator having a delay locked loop (DLL) circuit, the DLL circuit being configured to receive the internal clock signal and the command signal and to provide a phase-adjusted internal clock signal based on the internal clock signal, wherein, in response to receiving the command signal, the DLL circuit is configured to enable the phase-adjusted internal clock signal to be provided to an input / output circuit and to stop providing the phase-adjusted internal clock signal after a count of clock cycles of the internal clock signal exceeds a predetermined count value, wherein the predetermined count value is based on a total signal propagation time of the internal clock signal from an output of the internal clock circuit to an output terminal of the input / output circuit.
2. The apparatus of claim 1 , wherein the DLL circuit comprises a clock control circuit configured to start counting the clock cycles of the internal clock signal in response to receiving the command signal and to compare the count with the predetermined count value.
3. The apparatus of claim 2 , wherein the clock control circuit comprises a set of serially coupled flip-flops having respective outputs coupled to respective inputs of a multiplexer, wherein the respective outputs of the set of serially coupled flip-flops switch in series in response to cycles of the internal clock signal, wherein the multiplexer is configured to provide an enable signal to control provision of the phase-adjusted internal clock signal selected from one of the respective outputs of the set of serially coupled flip-flops based on the predetermined count value.
4. The apparatus of claim 4 , wherein the clock control circuit further comprises an edge detection circuit configured to set the respective output of each of the set of serially coupled flip-flops to a common value in response to receiving the command signal.
5. The apparatus of claim 1, wherein the internal clock generator comprises logic circuitry configured to control provision of the phase adjusted internal clock signal based on the enable signal.
6. The apparatus of claim 1, wherein the logic circuit comprises a NAND gate configured to provide an output based on a combination of the phase adjusted internal clock signal and the enable signal.
7. The apparatus of claim 1, wherein the DLL circuit comprises a DLL control circuit that determines the predetermined count value during an initialization phase.
8. The apparatus of claim 1, wherein the command comprises a read command.
9. A device comprising: a clock input circuit configured to receive an external clock signal and provide an internal clock signal; a command decoder configured to receive a command and provide a command signal; An internal clock generator having a delay locked loop (DLL) circuit, the DLL circuit being configured to receive the internal clock signal and the command signal, and to provide the internal clock signal through a delay line to provide a phase-adjusted internal clock signal, wherein, in response to receiving the command signal, the DLL circuit is configured to enable the internal clock signal to be provided to the delay line in response to receiving the command signal, and to stop providing the internal clock signal after a count of clock cycles of the internal clock signal exceeds a predetermined count value, wherein the predetermined count value is based on a total signal propagation time of the internal clock signal from the output of the internal clock circuit to the output terminal of the input / output circuit.
10. The apparatus of claim 9, wherein the DLL circuit comprises a clock control circuit configured to provide an enable signal having a value based on a comparison between the count of clock cycles of the internal clock signal initiated in response to receiving the command signal and the predetermined count value.
11. The apparatus of claim 10, wherein the clock control circuit comprises an edge detection circuit configured to reset the count of clock cycles in response to receiving the command signal.
12. The apparatus of claim 11, wherein the internal clock generator comprises a logic circuit configured to control providing the internal clock signal to the delay line based on the enable signal.
13. The apparatus of claim 9, wherein the DLL circuit comprises a DLL control circuit that determines the predetermined count value during an initialization phase.
14. The apparatus of claim 9, wherein the command comprises an on-die terminate command.
15. A method comprising: receiving an external clock signal and a command at a semiconductor device; generating an internal clock signal in response to the external clock signal; generating a command signal in response to the command; In response to receiving the command signal: enabling a phase-adjusted internal clock signal generated based on the internal clock signal to be provided to an input / output circuit; and The phase-adjusted internal clock signal is ceased to be provided to the input / output circuit after a count of clock cycles of the internal clock signal exceeds a predetermined count value, wherein the predetermined count value is based on a total signal propagation time of the internal clock signal from an output of the internal clock circuit to an output terminal of the input / output circuit.
16. The method of claim 15, further comprising in response to receiving the command signal, starting: counting the clock cycles of the internal clock signal; and The count of the clock cycles is compared to the predetermined count value.
17. The method of claim 16, further comprising resetting the count of the clock cycles in response to receiving the command signal and before starting the count of the clock cycles.
18. The method of claim 15, further comprising using NAND logic to control providing the phase adjusted internal clock signal to the input / output circuit.
19. The method of claim 15, further comprising determining the predetermined count value during an initialization phase.
20. The method of claim 15, wherein the command comprises a read command.