Branch predictor and operating method, processor, electronic device and storage medium

Abstract

Embodiments of the present disclosure provide a branch predictor for multiple threads, an operating method, a processor, an electronic device and a storage medium. The branch predictor comprises multiple tag prediction tables of different levels, and the multiple threads share the multiple tag prediction tables. The operating method comprises: setting a tag offset value for the multiple threads; and in response to an operation of a target thread in the multiple threads on the multiple tag prediction tables, determining a storage area corresponding to the target thread for each tag prediction table based on a target tag offset value corresponding to the target thread and a prediction table identifier of each tag prediction table. The operating method can alleviate the capacity competition problem of different threads on the same branch predictor, reduce the interference between threads, and improve the branch prediction accuracy.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a branch predictor and operation method for multiple threads, a processor, an electronic device, and a storage medium. Background Technology

[0002] In high-performance out-of-order execution processors, an accurate branch predictor plays a crucial role in maximizing processor throughput. It proactively anticipates branch decisions along the program's execution path, allowing the processor to begin executing the predicted instruction flow before actually determining the branch condition. In this way, the branch predictor effectively avoids pipeline stalls and instruction execution sequence interruptions caused by waiting for branch results, significantly improving overall instruction-level parallelism and processor resource utilization, ensuring continuous high-efficiency operation. Accurate branch prediction is particularly critical for system performance optimization when dealing with code that heavily relies on branch logic. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an operation method for a branch predictor for multiple threads, wherein the branch predictor includes multiple label prediction tables at different levels, and multiple threads share the multiple label prediction tables. The operation method includes: setting label offset values ​​for multiple threads; and in response to the operation of a target thread on the multiple label prediction tables, determining the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables.

[0004] For example, in the operation method provided in at least one embodiment of this disclosure, the branch predictor includes N label prediction tables and N storage areas, each storage area storing 2m entries, where N and m are positive integers. Based on the target label offset value corresponding to the target thread and the prediction table identifiers of the multiple label prediction tables, the storage area corresponding to each label prediction table and the target thread is determined, including: for the first label prediction table among the N label prediction tables, in response to (Tage_Offset + Table_id) ≤ N, the area identifier of the storage area corresponding to the first label prediction table and the target thread is determined to be (Tage_Offset + Table_id); or, in response to (Tage_Offset + Table_id) > N, the area identifier of the storage area corresponding to the first label prediction table and the target thread is determined to be (Tage_Offset + Table_id - N), where Table_id is the prediction table identifier of the first label prediction table and Tage_Offset is the target label offset value.

[0005] For example, in the operation method provided in at least one embodiment of this disclosure, the operation of the target thread on multiple label prediction tables includes a query operation. After determining the storage area corresponding to each label prediction table and the target thread, the operation method further includes: reading the table entries stored in the storage area corresponding to each label prediction table and the target thread to query whether the branch instruction to be predicted by the target thread hits N label prediction tables.

[0006] For example, at least one embodiment of the present disclosure provides an operation method that further includes: responding to a target thread’s branch instruction to be predicted hitting a first entry in at least one label prediction table, taking the highest-level label prediction table in the hit at least one label prediction table as the target label prediction table, and reading the prediction result of the first entry in the storage area of ​​the target label prediction table corresponding to the target thread to obtain the target prediction result.

[0007] For example, the operation method provided in at least one embodiment of this disclosure further includes: in response to an error in the target prediction result, updating a first entry in at least one hit label prediction table based on the actual result of the branch instruction to be predicted, and applying to allocate a new entry in a label prediction table at a higher level than the target label prediction table to store the instruction information and actual result corresponding to the branch instruction to be predicted.

[0008] For example, the operation method provided in at least one embodiment of this disclosure further includes: in response to an error in the target prediction result and the target label prediction table having the highest rank among multiple label prediction tables, updating the first entry in at least one hit label prediction table based on the actual result of the branch instruction to be predicted.

[0009] For example, at least one embodiment of this disclosure provides an operation method that further includes: recording the demand information of multiple threads for each label prediction table, and adjusting the label offset values ​​of the multiple threads based on the demand information.

[0010] For example, in the operation method provided in at least one embodiment of this disclosure, the demand information includes the number of times each label prediction table is requested to be allocated a new table entry, and adjusting the label offset values ​​of multiple threads based on the demand information includes: adjusting the label offset values ​​of multiple threads in response to the number of times at least one label prediction table is requested to be allocated a new table entry exceeding a preset threshold within a preset time.

[0011] For example, at least one embodiment of the present disclosure provides an operation method that further includes: dividing multiple threads into at least two groups of threads, wherein each group of threads shares the same label offset value.

[0012] At least one embodiment of this disclosure also provides a branch predictor for multiple threads. The branch predictor includes: multiple label prediction tables of different levels, a shift register, and a branch prediction control logic module. Multiple threads share the multiple label prediction tables. The shift register is configured to store label offset values ​​set for the multiple threads. The branch prediction control logic module is configured to, in response to an operation of the target thread on the multiple label prediction tables, determine the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifiers of the multiple label prediction tables.

[0013] For example, the branch predictor provided in at least one embodiment of this disclosure further includes a hardware control logic module. The hardware control logic module is configured to record demand information for each label prediction table from multiple threads and adjust the label offset values ​​stored in the shift register based on the demand information.

[0014] For example, in the branch predictor provided in at least one embodiment of this disclosure, the tag offset value in the shift register is configured to be modifiable externally.

[0015] At least one embodiment of this disclosure also provides a processor that includes a branch predictor according to at least one embodiment of this disclosure, wherein the processor is configured to support multiple threads.

[0016] At least one embodiment of this disclosure also provides an electronic device, which includes the processor provided in at least one embodiment of this disclosure.

[0017] At least one embodiment of this disclosure also provides an electronic device including at least one storage unit and at least one processing unit. The at least one storage unit is configured to store computer-readable instructions; the at least one processing unit is configured to execute the computer-readable instructions stored in the storage unit to implement the operation method for a branch predictor provided in at least one embodiment of this disclosure.

[0018] At least one embodiment of this disclosure also provides a computer-readable storage medium. The computer-readable storage medium stores computer-readable instructions that, when executed by a processor, implement the operation method for a branch predictor provided in at least one embodiment of this disclosure. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0020] Figure 1A A schematic diagram of a processor core pipeline is shown;

[0021] Figure 1B A schematic diagram of a TAGE branch predictor is shown;

[0022] Figure 2A and Figure 2B A schematic diagram showing two threads sharing a label prediction table is shown;

[0023] Figure 3 A flowchart illustrating the operation method of a branch predictor provided in at least one embodiment of the present disclosure is shown;

[0024] Figure 4 A schematic diagram of a thread query label prediction table provided in at least one embodiment of this disclosure is shown;

[0025] Figure 5A A schematic diagram illustrating the adjustment of label offset values ​​provided in at least one embodiment of this disclosure is shown;

[0026] Figure 5B This illustration shows a schematic diagram of thread usage of storage areas after adjusting the tag offset value, provided in at least one embodiment of this disclosure.

[0027] Figure 6 A schematic diagram of the structure of a branch predictor provided in at least one embodiment of this disclosure is shown;

[0028] Figure 7 A schematic diagram illustrating at least one embodiment of the present disclosure provides for adjusting the tag offset value in a shift register;

[0029] Figure 8 A schematic block diagram of a processor provided in at least one embodiment of the present disclosure is shown; and

[0030] Figure 9 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0033] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0034] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0035] Figure 1A A schematic diagram of a processor core pipeline is shown, in which dashed lines with arrows represent redirected instruction flows.

[0036] like Figure 1AAs shown, processor cores (such as CPU cores) in single-core or multi-core processors improve instruction parallelism through pipeline technology. The processor core internally includes multiple pipeline stages. For example, after program counters from various sources are fed into the pipeline and a multiplexer (Mux) selects the next program counter (PC), the instruction corresponding to that program counter undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and renaming, instruction execution, and instruction termination. Waiting queues are set up between each pipeline stage as needed; these queues are typically First-In-First-Out (FIFO) queues. For example, after the branch prediction unit, a branch prediction (BP) FIFO queue is set up to store branch prediction results; after the instruction fetch unit, an instruction cache (IC) FIFO is set up to cache fetched instructions; after the instruction decode unit, a decode (DE) FIFO is set up to cache decoded instructions; and after the instruction dispatch and renaming unit, a termination (RT) FIFO is set up to cache instructions waiting for confirmation of termination after execution. The processor core pipeline also includes an instruction queue to cache instructions after instruction dispatch and renaming, waiting for the instruction execution unit to execute the instructions.

[0037] To support high operating frequencies, each pipeline stage may contain multiple pipeline stages (operation cycles). Each pipeline stage performs a limited number of operations to further improve the performance of the processor core. Although each pipeline stage performs a limited number of operations, this minimizes the clock cycle, thereby increasing the CPU core's performance by increasing the CPU's operating frequency. Each pipeline stage can also further improve the processor core's performance by accommodating more instructions (i.e., superscalar technology). Superscalar refers to the method of executing multiple instructions in parallel within a single cycle, exhibiting increased instruction-level parallelism. A processor capable of processing multiple instructions within a single cycle is called a superscalar processor. Superscalar processors add extra resources to a typical scalar processor, creating multiple pipelines, each executing the instructions assigned to it, thus achieving parallelism.

[0038] Branch prediction is a crucial component of high-performance, multi-pipeline processor cores. By predicting the execution path of conditional branch instructions in a program, it allows the processor to prefetch and execute subsequent instructions before the actual result of a branch is determined, thus reducing latency caused by waiting for branch results. Without branch prediction, a multi-pipeline CPU core must wait until each branch instruction has finished executing to determine which instruction to jump to, resulting in multiple pipeline stages running idle from the front end to execution, causing significant performance degradation. Figure 1AAs shown, branch prediction occurs at the very beginning of the processor core pipeline, continuously predicting the start and end addresses of the next instruction based on the result of the previous branch prediction. When a branch prediction error is detected in a subsequent pipeline stage (such as after instruction decoding or instruction execution), all instructions younger than the erroneous branch instruction in the pipeline are flushed out, i.e., a pipeline flush is performed. Then, the branch predictor continues to predict the instruction stream from that point and fills the pipeline.

[0039] Branch prediction involves three steps: identifying whether the instruction fetched in the current instruction fetch stage is a branch instruction; if it is a branch instruction, determining whether it is a conditional branch instruction; and if it is a conditional branch instruction, determining its jump destination address. During program execution, the target address of a conditional branch instruction is usually fixed, meaning it is determined during program compilation.

[0040] The Global History Register (GHR) is a variable-width register used to record the execution results of all branch instructions within a recent period (also known as the "global branch history"). Each time a new branch instruction is executed, the GHR is updated to reflect the latest branch execution result. The information stored in the GHR can be used to assist in prediction using the execution results of other branch instructions; this prediction method is called global history-based branch prediction.

[0041] For example, the Tagged Geometric History Length (TAGE) branch predictor is a typical global history-based branch predictor. The TAGE branch predictor is designed by combining the advantages of Partial Pattern Matching (PPM) and Optimal Geometric History Length (OGHL / OGEHL) techniques. Specifically, the TAGE branch predictor includes a base prediction table and multiple tag prediction tables (hereinafter also referred to as "TAGE tables"). For different tag prediction tables, branch history sequences of different lengths from the global branch history can be used for index calculation. Therefore, the TAGE branch predictor can simultaneously perform branch prediction for a given branch instruction based on branch history sequences of different lengths, and evaluate the accuracy of that branch instruction under each branch history sequence, selecting the one with the highest historical accuracy as the final branch prediction criterion.

[0042] For example, Figure 1B A schematic diagram of a TAGE branch predictor is shown.

[0043] like Figure 1B As shown, the TAGE branch predictor includes a base prediction table T0 and label prediction tables T1~T4. The base prediction table T0 is directly indexed using the address (program counter value, hereinafter referred to as the PC value) of the branch instruction to be predicted, providing a basic prediction result when none of the label prediction tables T1~T4 can be hit. Different levels of label prediction tables use branch history sequences of different lengths from the Global Branch History (GBH) to index the entries, allowing each level of prediction table to capture historical patterns of different lengths. For example, lower-level label prediction tables (e.g., T1) correspond to shorter branch history sequences, and higher-level label prediction tables (e.g., T4) correspond to longer branch history sequences. Specifically, each label prediction table uses the PC value and the corresponding length of the branch history sequence through a first hash operation (i.e., ... Figure 1B The branch predictor also includes a global branch history register (Hash1) for indexing. Figure 1B (Not shown in the image), used to record the global branch history.

[0044] As the label prediction table level increases, the length of its corresponding branch history sequence grows exponentially. For example, the calculation formula can be... Where L(i) represents the length of the branch history sequence corresponding to the i-th level label prediction table Ti. L(1) is the scaling factor of the geometric series, and L(1) is the length of the branch history sequence corresponding to the label prediction table T1. The branch history sequence corresponding to the length L(i) can be represented as ghist[0:L(i)].

[0045] The base prediction table and each label prediction table each contain a certain number of entries. For example... Figure 1B As shown, each entry in the basic prediction table T0 may include a 2-bit saturation counter. Each entry in each tag prediction table (also known as the "TAGE table") includes a tag value, a predicted value pred, and a valid value u.

[0046] For example, such as Figure 1B As shown, the tag value is the PC value and the corresponding length of the branch history sequence ghist[0:L(i)] after a second hash operation (i.e., ...) during the initialization of the table entry. Figure 1BThe hash value obtained from Hash2 is used to confirm whether the indexed table entry corresponds to the branch instruction to be predicted (i.e., whether the table entry is hit). Here, the first hash operation Hash1 used to generate the index and the second hash operation Hash2 used to generate the tag value are different. The prediction value pred is the target address of the branch instruction to be predicted, which is the prediction result provided by the corresponding table entry. The valid value u indicates the reliability of the corresponding table entry. The larger the valid value u, the more reliable the corresponding table entry. When performing table entry replacement operations on the tag prediction table, table entries with smaller valid values ​​u can be replaced first.

[0047] For example, using Figure 1B The TAGE branch predictor performs branch prediction as shown below.

[0048] For the label prediction table Ti (i=1, 2, 3, or 4), perform a first hash operation (Hash1) on the PC value and ghist[0:L(i)] to obtain the index index_i, and perform a second hash operation (Hash2) on the PC value and ghist[0:L(i)] to obtain the label value tag_i. Based on the index index_i, read the label value tag1 of the entry (e.g., entry 1) in the label prediction table Ti. Compare the label value tag_i and the label value tag1 to determine if entry 1 is matched (this step corresponds to...). Figure 1B The "=?" in the table indicates that if the label value `tag_i` equals the label value `tag` recorded in entry 1, then entry 1 of the label prediction table `Ti` is considered to be matched, and the predicted value `pred` of entry 1 in label prediction table `Ti` is provided as the prediction result obtained by branching based on label prediction table `Ti`. When no entries in multiple label prediction tables `T1` to `T4` are matched, the prediction result provided by the base prediction table `T0` is used as the target prediction result. When entries in multiple label prediction tables are matched, the predicted value `pred` of the matched entry in the highest-level label prediction table is selected as the target prediction result. If the target prediction result differs from the actual result (i.e., branching prediction error), the matched entries in multiple label prediction tables are updated using the actual result. Furthermore, in the case of a branching prediction error, if the label prediction table providing the target prediction result (e.g., `T2`) is not the highest-level label prediction table, a new entry needs to be allocated to a higher-level label prediction table (e.g., `T3`).

[0049] Because different programs have different numbers of branches with varying branch association distances, during program execution, the program will request entries from higher-level label prediction tables in the TAGE branch predictor level by level until the branch association distance that the label prediction table can cover is greater than or equal to the branch association distance required by the program's branch instructions.

[0050] To make fuller use of processor resources and improve system concurrency, Simultaneous Multi-Threading (SMT) technology is applied to some processors. In multi-threaded processors (such as SMT processors), the branch predictor is shared by multiple threads (hardware threads) in a time-sharing manner. Different threads jointly use, for example, the TAGE branch predictor to perform branch prediction. During this process, each thread competes for capacity in each label prediction table, and interference between threads leads to a decrease in branch prediction accuracy.

[0051] For example, Figure 2A and Figure 2B This diagram illustrates two threads sharing a label prediction table.

[0052] In this example, "gray" represents the entries currently occupied by thread 0, "black" represents the entries currently occupied by thread 1, and "white" represents the entries currently in an idle state.

[0053] like Figure 2A As shown, in the SMT2 scenario, both thread 0 and thread 1 request new entries from the tag prediction table T1. Thread 0 and thread 1 are likely to compete for the same entry in tag prediction table T1. For example, when thread 1 requests a new entry from tag prediction table T1, it first generates an index (e.g., denoted as "index1") corresponding to the branch instruction of thread 1 through a first hash operation to locate the position of the new entry in tag prediction table T1. If the generated index index1 is the same as the index of entry 2 in tag prediction table T1, and entry 2 is currently occupied by thread 0, then thread 1 will directly replace the entry 2 occupied by thread 0 with the new entry corresponding to thread 1, without querying an empty entry in tag prediction table T1 for replacement.

[0054] Furthermore, the demand for each label prediction table within the same program roughly follows a normal distribution. That is, compared to lower-level label prediction tables (e.g., label prediction table T1) and higher-level label prediction tables (e.g., label prediction table T4), the program has a greater demand for intermediate-level label prediction tables (e.g., label prediction tables T2 and T3). Therefore, because different programs have significantly different demands for each label prediction table, when multiple threads run concurrently, this imbalance in demand for each label prediction table is further exacerbated. This intensifies the competition for capacity in intermediate-level label prediction tables among multiple threads, ultimately leading to a decrease in branch prediction accuracy.

[0055] For example, such as Figure 2BAs shown, because threads 0 and 1 have a high demand for label prediction tables T2 and T3, and all entries in T2 and T3 are occupied by threads 0 and 1 with no free entries, threads 0 and 1 will frequently access and replace entries in T2 and T3. This frequent replacement of entries in T2 and T3 reduces the retention time of high-value entries and corrupts the branch history information recorded during the branch prediction period. It also exacerbates the capacity contention between threads 0 and 1 for T2 and T3, ultimately leading to a decrease in branch prediction accuracy.

[0056] Furthermore, as the number of threads increases, the competition for capacity in the intermediate-level label prediction table intensifies. Shared TAGE resources cannot achieve control flow isolation for multiple users; an attacker process can infer or manipulate the victim process's control flow during execution, thereby leaking the victim process's memory contents.

[0057] At least one embodiment of this disclosure provides an operation method for a branch predictor for multiple threads, wherein the branch predictor includes multiple label prediction tables at different levels, and the multiple threads share the multiple label prediction tables. The operation method includes: setting label offset values ​​for the multiple threads; and, in response to the operation of a target thread on the multiple label prediction tables, determining the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables.

[0058] In the above-described branch predictor operation method, by setting a label offset value for each thread, the storage area corresponding to the same label prediction table is different when used by different threads. This alleviates the capacity contention of different threads for the same branch predictor, reduces interference between threads, and thus improves branch prediction accuracy. Simultaneously, this operation method breaks the shared mode of multiple threads / programs on the branch predictor, achieving isolation of control flow for multiple users and enhancing the security of multi-user systems.

[0059] The branch predictor operation method provided in at least one embodiment of this disclosure is applicable to Simultaneous Multi-Threading (SMT) application scenarios. For example, the branch predictor can be the TAGE branch predictor described above. The branch predictor includes multiple label prediction tables at different levels, which are shared by different threads (hardware threads) of the multi-threaded processor for branch prediction. Each label prediction table includes multiple entries, and each entry includes a label value (tag), a predicted value (pred), and a valid value (u). For details, please refer to the above description of... Figure 1B The description will not be repeated here.

[0060] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0061] Figure 3 A flowchart illustrating the operation method of a branch predictor provided in at least one embodiment of the present disclosure is shown.

[0062] For example, such as Figure 3 As shown, the operation method of the branch predictor provided in at least one embodiment of this disclosure includes steps S310 to S320.

[0063] Step S310: Set label offset values ​​for multiple threads.

[0064] Step S320: In response to the operation of the target thread on multiple label prediction tables in multiple threads, determine the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables.

[0065] For example, in step S310, different tag offset values ​​can be set for different threads. For example, the tag offset values ​​can be stored in a shift register in binary data format. Taking the SMT4 scenario as an example, the tag offset value of thread 0 can be set to 00, the tag offset value of thread 1 can be set to 01, the tag offset value of thread 2 can be set to 10, and the tag offset value of thread 3 can be set to 11.

[0066] For example, in step S310, multiple threads can be divided into at least two groups, with each group sharing the same offset value. Taking the SMT4 scenario as an example, threads 0 and 1 can be divided into the first group, and threads 2 and 3 into the second group. Threads 0 and 1 share the same label offset value (e.g., 00), while threads 2 and 3 share another label offset value (e.g., 10). This division method is merely illustrative and is not intended to limit the scope of this disclosure.

[0067] The embodiments disclosed herein do not limit the way the label offset value is set, and the label offset value of each thread is not fixed and can be adjusted and changed according to the actual situation, thereby more efficiently alleviating the capacity competition problem between different threads, and thus improving the branch prediction accuracy of the branch predictor used for multiple threads.

[0068] For example, in step S320, the target thread is the thread that performs branch prediction operations based on multiple label prediction tables among multiple threads. The operations of the target thread on the multiple label prediction tables include querying, replacing, creating new table entries, updating, etc.

[0069] For example, each label prediction table has a corresponding prediction table identifier (or prediction table number), for example, Figure 1B The four label prediction tables T1 to T4 are labeled with 1, 2, 3, and 4 respectively. The prediction table label can also represent the level of the corresponding label prediction table. For example, the larger the value of the prediction table label label, the higher the level of the label prediction table corresponding to that label label.

[0070] For example, the storage area determined in step S320 (also called a "physical storage area" or "physical region") is configured to store entries in the corresponding label prediction table for the target thread. That is, when multiple threads perform this operation on the same label prediction table, entries in the same label prediction table for different threads (here, "different threads" refers to threads with different label offset values) are mapped (stored) to these different storage areas.

[0071] In at least one embodiment of this disclosure, the branch predictor includes N label prediction tables and N storage areas, each storage area storing 2 m There are 3 entries, where N and m are positive integers. Each storage region has a corresponding region identifier.

[0072] For example, step S320 above may include: for the first label prediction table among N label prediction tables, in response to (Tage_Offset + Table_id) ≤ N, determining the region identifier of the storage area corresponding to the first label prediction table and the target thread as (Tage_Offset + Table_id); or, in response to (Tage_Offset + Table_id) > N, determining the region identifier of the storage area corresponding to the first label prediction table and the target thread as (Tage_Offset + Table_id - N), where Table_id is the prediction table identifier of the first label prediction table, and Tage_Offset is the target label offset value.

[0073] Here, the first label prediction table is any one of the N label prediction tables.

[0074] In at least one embodiment of this disclosure, the number of label prediction tables in the branch predictor is the same as the number of storage areas. The number of label prediction tables can be set according to actual conditions, generally 4 to 8, and this disclosure does not limit this.

[0075] For example, Figure 4A schematic diagram of a thread query label prediction table provided in at least one embodiment of the present disclosure is shown.

[0076] like Figure 4 As shown, in the SMT4 scenario, the tag offset values ​​for threads 0 through 3 are set to binary 00, 01, 10, and 11 (i.e., 0, 1, 2, and 3 in decimal data format, and similar notation will be used below). The branch predictor includes four tag prediction tables T1 through T4 and four storage areas 1 through 4.

[0077] When the target thread is thread 0, in response to thread 0 (i=0) querying the tag prediction table T1, the tag offset value of thread 0 is 00 (i.e., 0). Since Tage_Offset + Table_id = 0 + 1 = 1 ≤ 4, the region identifier of the storage area corresponding to the tag prediction table T1 and thread 0 is 1 (e.g., ...). Figure 4 (As shown by the solid arrow indicating i=0), the entry in label prediction table T1 for thread 0 is mapped to storage area 1. Similarly, the entry in label prediction table T1 for thread 1 is mapped to storage area 2 (e.g., ...). Figure 4 (As shown by the solid arrow indicating i=1 in the text), the entry in label prediction table T1 for thread 2 is mapped to storage area 3 (as shown by the solid arrow indicating i=1 in the text). Figure 4 (As shown by the solid arrow indicating i=2 in the text), the entry in label prediction table T1 for thread 3 is mapped to storage area 4 (as shown by the solid arrow indicating i=2 in the text). Figure 4 (As shown by the solid arrow indicating i=3).

[0078] For example, in response to thread 0 (i=0) querying the label prediction table T4, the label offset value of thread 0 is 00 (i.e., 0). Since Tage_Offset + Table_id = 0 + 4 = 4, the region identifier of the storage area corresponding to the label prediction table T4 and thread 0 is 4 (e.g., ...). Figure 4 (As shown by the dashed arrow indicating i=0), the entry in label prediction table T4 for thread 0 is mapped to storage area 4. For example, in response to thread 1 (i=1) querying label prediction table T4, thread 1's label offset value is 01 (i.e., 1). Since Tage_Offset + Table_id = 1 + 4 = 5 > 4, the area identifier of the storage area corresponding to label prediction table T4 and thread 1 is 5 - 4 = 1 (as shown by the dashed arrow indicating i=0). Figure 4 As shown by the dashed arrow indicating i=1, entries in label prediction table T4 for thread 1 are mapped to storage area 1. Similarly, entries in label prediction table T4 for thread 2 are mapped to storage area 2 (e.g., ...). Figure 4 (As shown by the dashed arrow indicating i=2), the entry in label prediction table T4 for thread 3 is mapped to storage area 3 (e.g., ...). Figure 4 (As shown by the dashed arrow indicating i=3).

[0079] Following the method described above for determining the storage area corresponding to each label prediction table and the target thread (step S320), when the target threads are thread 0, thread 1, thread 2, and thread 3 in sequence, Figure 4 The mapping relationship between the label prediction tables T1~T4 and storage areas 1~4 is shown in Table 1.

[0080] Table 1: Mapping relationship between tag prediction table and storage area

[0081]

[0082] exist Figure 4 In the example shown, before setting label offset values ​​for multiple threads (i.e., threads 0 to 3), entries in the label prediction table are mapped to storage areas whose region identifiers are equal to the prediction table identifiers of the label prediction tables. For example, entries in label prediction table T1 are all mapped to storage area 1, entries in label prediction table T2 are all mapped to storage area 2, entries in label prediction table T3 are all mapped to storage area 3, and entries in label prediction table T4 are all mapped to storage area 4. Since the program's demand for each label prediction table is not uniformly distributed (e.g., normally distributed), threads 0 to 3 all have a greater demand for intermediate-level label prediction tables (e.g., label prediction tables T2 and T3). That is, entries in label prediction tables T2 and T3 used by threads 0 to 3 are centrally mapped (stored) to storage areas 2 and 3. Since the number of entries that can be stored in each storage area is limited, threads 0 to 3 will perform more frequent replacement operations on the entries stored in storage areas 2 and 3. That is, compared with the competition between threads 0 and 3 for storage areas 1 and 4, the competition between threads 0 and 3 for storage areas 2 and 3 is more intense.

[0083] exist Figure 4 In the example shown, after setting label offset values ​​for multiple threads (i.e., threads 0 to 3), referring to Table 1 above, the entries in label prediction table T2 for threads 0, 1, 2, and 3 are mapped to storage areas 2, 3, 4, and 1, respectively. Similarly, the entries in label prediction table T3 for threads 0, 1, 2, and 3 are mapped to storage areas 3, 4, 1, and 2, respectively. Although threads 0 to 3 still have significant demands on label prediction tables T2 and T3, the set label offset values ​​ensure that the entries in T2 and T3 for threads 0 to 3 are distributed across storage areas 1, 2, 3, and 4, rather than being concentrated in storage areas 2 and 3. This effectively alleviates competition for storage areas between different threads, improves the overall resource utilization of storage areas, and enhances branch prediction accuracy.

[0084] For example, at least one embodiment of this disclosure provides an operation method that further includes: recording the demand information of multiple threads for each label prediction table, and adjusting the label offset values ​​of the multiple threads based on the demand information.

[0085] For example, demand information is used to characterize the capacity contention among multiple threads for each label prediction table. Demand information may include information in multiple dimensions, such as the number of times each label prediction table is requested to allocate new entries, the number of times each label prediction table provides the target prediction result, and the number of times the target prediction result provided by each label prediction table is incorrect. This disclosure does not limit this.

[0086] For example, when the demand information includes the number of times each label prediction table is requested to be allocated a new table entry, the label offset values ​​of multiple threads are adjusted based on the demand information, including: adjusting the label offset values ​​of multiple threads in response to the number of times at least one label prediction table is requested to be allocated a new table entry exceeding a preset threshold within a preset time.

[0087] For example, Figure 5A A schematic diagram of adjusting the label offset value is shown, according to at least one embodiment of the present disclosure.

[0088] like Figure 5A As shown, a hardware control logic module 530 can be set in the branch predictor. This hardware control logic module 530 can record the demand information of multiple threads for each label prediction table, such as the number of times thread 0 and thread 1 request the allocation of new table entries for each label prediction table (i.e., Figure 5A (e.g., TageTable1_AllocNum_Thread0, TageTable2_AllocNum_Thread0, TageTable3_AllocNum_Thread0, etc.). Then, the hardware control logic module 530 adjusts the label offset values ​​of thread 0 and thread 1 based on the demand information, thereby realizing dynamic adjustment of the label offset values, so that the branch predictor can adapt to the program's requirements for each label prediction table.

[0089] It should be noted that when adjusting the label offset values ​​of multiple threads, the label offset value of each thread can be adjusted, or only the label offset values ​​of some threads can be adjusted while the label offset values ​​of the remaining threads remain unchanged. For example, the specific adjustment method can be set in advance (e.g., programmed) in the hardware control logic module 530 so that the hardware control logic module 530 can automatically adjust the label offset values ​​of the threads when the demand information meets certain conditions.

[0090] For example, such as Figure 5AAs shown, in the STM2 scenario, the initial tag offset values ​​of both thread 0 and thread 1 are set to 00. Then, all entries in tag prediction table T1 are mapped to storage area 1, all entries in tag prediction table T2 are mapped to storage area 2, all entries in tag prediction table T3 are mapped to storage area 3, and all entries in tag prediction table T4 are mapped to storage area 4. If the hardware control logic module 530 detects that the sum of the number of times each thread (i.e., thread 0 and thread 1) requests the allocation of new entries to the label prediction table T2 (i.e., TageTable2_AllocNum_Thread0 + TageTable3_AllocNum_Thread1) exceeds a preset threshold (e.g., 500 times) within a preset time, and the sum of the number of times each thread (i.e., thread 0 and thread 1) requests the allocation of new entries to the label prediction table T3 (i.e., TageTable3_AllocNum_Thread0 + TageTable3_AllocNum_Thread1) also exceeds the preset threshold (e.g., 500 times) within a preset time, then it is determined that thread 0 and thread 1 have a greater demand for label prediction tables T2 and T3.

[0091] like Figure 5A As shown, the entries for thread 0 and thread 1 almost occupy all of storage areas 2 and 3, while there are still free storage locations in storage areas 1 and 4 (i.e., Figure 5A The white entries indicate that threads 0 and 1 use storage areas 2 and 3 more frequently, and storage areas 1 and 4 less frequently. In other words, threads 0 and 1 are highly competitive for storage areas 2 and 3. At this point, the label offset value for thread 1 can be adjusted from 00 to 10, thus changing the storage area corresponding to the entries in the label prediction tables T1~T4 used for thread 1.

[0092] For example, after adjusting the label offset value of thread 1 from 00 to 10, such as Figure 5A As shown by the dashed arrows (or see Table 2 below), the entries for thread 1 in label prediction table T1 are mapped to storage area 3, the entries for thread 1 in label prediction table T2 are mapped to storage area 4, the entries for thread 1 in label prediction table T3 are mapped to storage area 1, and the entries for thread 1 in label prediction table T4 are mapped to storage area 2.

[0093] Table 2: Mapping relationship between tag prediction table and storage area

[0094]

[0095] For example, Figure 5B A schematic diagram of thread usage of storage area after adjusting tag offset value is shown, according to at least one embodiment of the present disclosure.

[0096] like Figure 5B As shown, by adjusting the label offset value of thread 1 from 00 to 10, the contention between threads 0 and 1 for storage regions 2 and 3 can be alleviated, allowing threads 0 and 1 to use storage regions 1-4 more evenly. The specific method for determining the region identifier can be referred to the above. Figure 4 The examples shown will not be repeated here. It is important to note that... Figure 5B The usage of storage areas 1-4 by threads 0 and 1 after adjusting the tag offset values ​​shown is only illustrative; actual usage may differ. Figure 5B different.

[0097] For example, after adjusting the label offset value of thread 1 from 00 to 10, the needs of threads 0 and 1 for label prediction tables T1~T4 may change again. For example, if the sum of the number of times threads 0 and 1 request new entries for label prediction table T1 (i.e., TageTable1_AllocNum_Thread0 + TageTable1_AllocNum_Thread1) exceeds a preset threshold within a preset time, and the sum of the number of times threads 0 and 1 request new entries for label prediction table T3 (i.e., TageTable3_AllocNum_Thread0 + TageTable3_AllocNum_Thread1) also exceeds the preset threshold within a preset time, then it is determined that threads 0 and 1 have a greater need for label prediction tables T1 and T3. If the current label offset values ​​are continued (the label offset value for thread 0 is 00, and the label offset value for thread 1 is 10), as shown in Table 2, both thread 0 and thread 1 will use storage areas 1 and 3 more frequently and storage areas 2 and 4 less frequently. This will lead to intense competition between thread 0 and thread 1 for storage areas 1 and 3. Therefore, the label offset values ​​for thread 0 and thread 1 need to be adjusted again. For example, the label offset value for thread 1 can be adjusted from 10 to 01, which will change the storage area corresponding to the entries in the label prediction tables T1~T4 used for thread 1. Please refer to Table 3 below for details.

[0098] As shown in Table 3, after adjusting the label offset value of thread 1 to 01, the entries for thread 1 in label prediction table T1 are mapped to storage area 4, the entries for thread 1 in label prediction table T2 are mapped to storage area 1, the entries for thread 1 in label prediction table T3 are mapped to storage area 2, and the entries for thread 1 in label prediction table T4 are mapped to storage area 3. The adjusted label offset value allows thread 0 and thread 1 to use storage areas 1-4 more evenly, thereby alleviating the competition for storage areas between different threads.

[0099] Table 3: Mapping relationship between tag prediction table and storage area

[0100]

[0101] For example, the target thread's operations on multiple label prediction tables include query operations. After determining the storage area corresponding to each label prediction table and the target thread, the operation method provided in at least one embodiment of this disclosure further includes: reading the table entries stored in the storage area corresponding to each label prediction table and the target thread to query whether the branch instruction to be predicted by the target thread hits N label prediction tables. The specific method for querying whether a match has been found can be referred to the above description. Figure 1B Examples are not repeated here.

[0102] For example, at least one embodiment of the present disclosure provides an operation method that further includes: responding to a target thread’s branch instruction to be predicted hitting a first entry in at least one label prediction table, taking the highest-level label prediction table in the hit at least one label prediction table as the target label prediction table, and reading the prediction result of the first entry in the storage area of ​​the target label prediction table corresponding to the target thread to obtain the target prediction result.

[0103] For example, the operation method provided in at least one embodiment of this disclosure further includes: in response to an error in the target prediction result, updating a first entry in at least one hit label prediction table based on the actual result of the branch instruction to be predicted, and applying to allocate a new entry in a label prediction table at a higher level than the target label prediction table to store the instruction information and actual result corresponding to the branch instruction to be predicted.

[0104] For example, the operation method provided in at least one embodiment of this disclosure further includes: in response to an error in the target prediction result and the target label prediction table having the highest rank among multiple label prediction tables, updating the first entry in at least one hit label prediction table based on the actual result of the branch instruction to be predicted.

[0105] For example, see Figure 4 If it is determined that the predicted branch instruction of the target thread (e.g., thread 2) hits the first entry in label prediction tables T2, T3, and T4, then the highest-ranking label prediction table T4 is used as the target label prediction table. The prediction result of the first entry in storage area 2 corresponding to thread 2 in label prediction table T4 is read. The prediction result of the first entry in storage area 2 is the target prediction result obtained by thread 2 performing the branch prediction operation. In response to an error in the target prediction result, i.e., the target prediction result is different from the actual result of the predicted branch instruction of thread 2, the first entries in label prediction tables T2, T3, and T4 that hit are updated based on the actual result. Since the target label prediction table (i.e., label prediction table T4) has the highest rank among all label prediction tables T1~T4, it is not necessary to request a new entry from a label prediction table at a higher level than label prediction table T4.

[0106] like Figure 4 The branch predictor shown also includes a label prediction table T5, which is one level higher than the label prediction table T4. It is necessary to apply for a new table entry from the label prediction table T5 and create a new table entry or replace the old table entry with a new table entry in the storage area corresponding to thread 2 in the label prediction table T5, so as to store the instruction information and actual results corresponding to the branch instruction to be predicted of thread 2.

[0107] Therefore, the branch predictor operation method provided in at least one embodiment of this disclosure can alleviate the capacity competition problem of different threads for the same branch predictor and reduce interference between threads by setting a label offset value for each thread to divide the storage area corresponding to the same label prediction table for different threads. This can improve the branch prediction accuracy.

[0108] Figure 6 A schematic diagram of the structure of a branch predictor provided in at least one embodiment of this disclosure is shown. This branch predictor is applicable to multiple threads.

[0109] like Figure 6 As shown, the branch predictor 600 includes multiple label prediction tables T1~TN of different levels, a shift register 610, and a branch prediction control logic module 620.

[0110] Multiple threads share multiple label prediction tables T1~TN. Shift register 610 is configured to store label offset values ​​set for the multiple threads. Branch prediction control logic module 620 is configured to, in response to the target thread's operation on the multiple label prediction tables, determine the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifiers of the multiple label prediction tables.

[0111] For example, in at least one embodiment of this disclosure, the branch predictor 600 further includes a hardware control logic module configured to record the demand information of multiple threads for each label prediction table, and adjust the label offset value stored in the shift register 610 based on the demand information. See the above description for details. Figure 5A The description will not be repeated here.

[0112] For example, in at least one embodiment of this disclosure, the demand information includes the number of times each label prediction table is requested to be allocated a new entry, and the hardware control logic module is further configured to adjust the label offset values ​​of multiple threads in response to the number of times at least one label prediction table is requested to be allocated a new entry exceeding a preset threshold within a preset time.

[0113] For example, software can be used to record and analyze the demand information of multiple threads for each tag prediction table, and then the hardware control logic module can adjust the tag offset value stored in shift register 610 based on the analysis results. Alternatively, the hardware control logic module can further include a storage component to store the tag offset value adjustment methods for multiple threads.

[0114] For example, in at least one embodiment of this disclosure, the tag offset value in shift register 610 is configured to be modifiable externally. For example, a software interface is provided in branch predictor 600 so that a user can dynamically adjust the tag offset value in shift register 610 via the software interface.

[0115] For example, Figure 7 A schematic diagram is shown illustrating at least one embodiment of the present disclosure of adjusting the tag offset value in a shift register.

[0116] like Figure 7 As shown, in a multi-user scenario, the software (or software scheduler) is responsible for managing and allocating system resources (such as CPU time) to different tasks or users. For example, the software manages a pool (also called a "user pool") containing multiple users, such as users 1 to 4. The software presets a different tag offset value, Tage_Offset, for each user. For example, user 1's Tage_Offset is 00, user 2's is 01, user 3's is 10, and user 4's is 11. Through the software's scheduling management, multiple users share (or time-sharingly share) the same branch predictor using corresponding threads (also called "physical threads") on the processor. Here, the processor can be a multi-core SMT processor, meaning it supports multiple threads and includes at least processor core 0 and processor core 1.

[0117] For example, if the software schedules user 1 to thread 0 of processor core 0 in the first operating cycle and user 2 to thread 0 of processor core 0 in the second operating cycle, then user 1 and user 2 share the same branch predictor in a time-sharing manner.

[0118] For example, when the software schedules a user to any physical thread on any processor core, the software sets the offset register for that thread to the user's preset tag offset value. Figure 7As shown, when the software schedules user 2 and user 3 to thread 0 and thread 1 of processor core 0 respectively, the software adjusts the tag offset value of thread 0 of processor core 0 stored in shift register 0 to the Tage_Offset corresponding to user 2 (i.e., 01), and adjusts the tag offset value of thread 1 of processor core 0 to the Tage_Offset corresponding to user 3 (i.e., 10). This ensures that when user 2 and user 3 use the shared branch predictor, user 2 and user 3 are in different storage areas corresponding to the same tag prediction table, thus ensuring that user 2 and user 3 are isolated from each other when using the shared branch predictor.

[0119] Therefore, in multi-user scenarios, by setting different label offset values ​​for different users and adjusting the label offset values ​​corresponding to each thread in the shift register based on software scheduling, it is possible to ensure that different users are isolated from each other when using the shared branch predictor, thereby achieving the independence and isolation of control flow among multiple users and significantly improving the overall security and reliability of the multi-user system.

[0120] For example, in at least one embodiment of this disclosure, the branch predictor 600 includes N label prediction tables and N storage areas, each storage area storing 2 m There are n entries, where N and m are positive integers. The branch prediction control logic module 620 is also configured to: for the first label prediction table among the N label prediction tables, in response to (Tage_Offset + Table_id) ≤ N, determine the region identifier of the storage area corresponding to the first label prediction table and the target thread as (Tage_Offset + Table_id); or, in response to (Tage_Offset + Table_id) > N, determine the region identifier of the storage area corresponding to the first label prediction table and the target thread as (Tage_Offset + Table_id - N), where Table_id is the prediction table identifier of the first label prediction table, and Tage_Offset is the target label offset value.

[0121] For example, in at least one embodiment of this disclosure, the target thread's operation on multiple label prediction tables includes a query operation, and the branch predictor 600 further includes a query module. After determining the storage area corresponding to each label prediction table and the target thread, the query module is configured to read the table entries stored in the storage area corresponding to each label prediction table and the target thread to query whether the branch instruction to be predicted by the target thread hits N label prediction tables.

[0122] For example, in at least one embodiment of this disclosure, the branch predictor 600 further includes a prediction module. This prediction module is configured to: in response to a target thread's branch prediction instruction hitting a first entry in at least one label prediction table, use the highest-ranking label prediction table in the hit label prediction table as the target label prediction table, and read the prediction result of the first entry located in the storage area corresponding to the target thread in the target label prediction table to obtain the target prediction result.

[0123] For example, in at least one embodiment of this disclosure, the branch predictor 600 further includes a judgment module. This judgment module is configured to determine whether the target prediction result is correct.

[0124] For example, in at least one embodiment of this disclosure, the judgment module is further configured to, in response to an error in the target prediction result, update the first entry in at least one hit label prediction table based on the actual branch result of the branch instruction to be predicted, and apply for allocation of a new entry in a label prediction table at a higher level than the target label prediction table to store the instruction information and the actual branch result corresponding to the branch instruction to be predicted.

[0125] For example, in at least one embodiment of this disclosure, the determination module is further configured to update the first entry in at least one hit label prediction table based on the actual branch result of the branch instruction to be predicted in response to an error in the target prediction result and the target label prediction table having the highest level.

[0126] For example, in at least one embodiment of this disclosure, the branch predictor 600 further includes a thread partitioning module configured to partition multiple threads into at least two groups of threads, wherein each group of threads shares the same label offset value.

[0127] For example, the above modules (such as branch prediction control logic module, hardware control logic module, thread partitioning module) or units can be implemented by hardware, firmware, software or any combination thereof.

[0128] Figure 8 A schematic block diagram of a processor provided in at least one embodiment of the present disclosure is shown.

[0129] For example, such as Figure 8 As shown, at least one embodiment of this disclosure provides a processor 800 including a branch predictor 801. The processor 800 is, for example, an SMT processor, which can support a maximum number of threads, such as 2, 4, or 8. The SMT processor can be a single-core or multi-core processor. For example, the branch predictor 801 can be any of the branch predictors provided in the above embodiments.

[0130] For example, in addition to the branch predictor 801, the processor 800 may also include an instruction fetch unit, a decoding unit, an allocation unit, a fixed-point execution unit, a floating-point execution unit, and a memory access unit. The processor includes multiple pipeline stages. The instruction corresponding to the program counter is sent to the instruction fetch unit after being predicted by the branch predictor 801 so that it can enter the processor pipeline for processing. The specific operation will not be described in detail here.

[0131] At least one embodiment of this disclosure also provides an electronic device including at least one storage unit and at least one processing unit. The at least one storage unit is configured to store computer-readable instructions. The at least one processing unit is configured to execute the computer-readable instructions stored in the storage unit to implement an operation method for a branch predictor according to any embodiment of this disclosure.

[0132] At least one embodiment of this disclosure also provides an electronic device that includes the processor of any of the above embodiments.

[0133] Figure 9 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0134] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device 900 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0135] For example, such as Figure 9 As shown, in some examples, electronic device 900 includes a processing device (e.g., central processing unit, graphics processor, etc.) 901, which may include the processor of any of the above embodiments, capable of performing various appropriate actions and processes according to a program stored in read-only memory (ROM) 902 or a program loaded from storage device 908 into random access memory (RAM) 903. RAM 903 also stores various programs and data required for the operation of the computer system. Processor 901, ROM 902, and RAM 903 are connected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0136] For example, the following components can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909, such as network interface cards like LAN cards and modems, etc. Communication device 909 allows electronic device 900 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 910 is also connected to I / O interface 905 as needed. Removable media 911, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 910 as needed so that computer programs read from them can be installed into storage device 908 as needed. Although Figure 9 An electronic device 900 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0137] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 909 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0138] For example, the electronic device 900 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0139] At least one embodiment of this disclosure also provides a computer-readable storage medium storing computer-readable instructions that, when executed by a processor, implement the operation method for a branch predictor provided in any embodiment of this disclosure.

[0140] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0141] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0142] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0143] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0144] The following points should be noted regarding this disclosure:

[0145] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0146] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0147] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0148] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A method for operating a branch predictor for multiple threads, wherein, The branch predictor includes multiple label prediction tables at different levels, and the multiple threads share the multiple label prediction tables. The operation method includes: Set label offset values ​​for the multiple threads; In response to the operation of the target thread on the multiple label prediction tables in the multiple threads, based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables, the storage area corresponding to the target thread for each label prediction table is determined; The branch predictor includes N label prediction tables and N storage areas, each storage area storing 2 m There are n entries, where N and m are positive integers. The step of determining the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables includes: For the first label prediction table among the N label prediction tables, in response to (Tage_Offset + Table_id) ≤ N, the region identifier of the storage area corresponding to the first label prediction table and the target thread is determined to be (Tage_Offset + Table_id); or, in response to (Tage_Offset + Table_id) > N, the region identifier of the storage area corresponding to the first label prediction table and the target thread is determined to be (Tage_Offset + Table_id - N). Where Table_id is the prediction table identifier of the first label prediction table, and Tage_Offset is the target label offset value.

2. The operating method according to claim 1, wherein, The target thread's operations on the multiple label prediction tables include query operations. After determining the storage area corresponding to each label prediction table and the target thread, the operation method further includes: Read the table entries stored in the storage area corresponding to each of the label prediction tables and the target thread to query whether the branch instruction to be predicted of the target thread hits the N label prediction tables.

3. The operating method according to claim 2 further includes: In response to the prediction branch instruction of the target thread hitting at least one first entry in the label prediction table, the label prediction table with the highest level among the hit at least one label prediction tables is taken as the target label prediction table, and the prediction result of the first entry in the storage area corresponding to the target label prediction table and the target thread is read to obtain the target prediction result.

4. The operating method according to claim 3 further includes: In response to an error in the target prediction result, the first entry in the at least one label prediction table that was hit is updated based on the actual result of the branch instruction to be predicted, and a new entry is requested to be allocated in a label prediction table at a higher level than the target label prediction table to store the instruction information corresponding to the branch instruction to be predicted and the actual result.

5. The operating method according to claim 3 further includes: In response to an error in the target prediction result, and the target label prediction table having the highest ranking among the plurality of label prediction tables, the first entry in the at least one label prediction table that has been hit is updated based on the actual result of the branch to be predicted instruction.

6. The operating method according to any one of claims 1-5, further comprising: Record the demand information of the multiple threads for each label prediction table, and adjust the label offset value of the multiple threads based on the demand information.

7. The operating method according to claim 6, wherein, The demand information includes the number of times each label prediction table has requested the allocation of new entries. Adjusting the label offset values ​​of the multiple threads based on the demand information includes: In response to the fact that the number of times at least one label prediction table is requested to allocate the new table entry exceeds a preset threshold within a preset time, the label offset values ​​of the multiple threads are adjusted.

8. The method according to any one of claims 1-5, further comprising: The multiple threads are divided into at least two groups of threads, where each group of threads shares the same label offset value.

9. A branch predictor for multiple threads, comprising: Multiple label prediction tables at different levels, wherein the multiple threads share the multiple label prediction tables; A shift register is configured to store tag offset values ​​set for the plurality of threads; The branch prediction control logic module is configured to respond to the operation of the target thread on the multiple label prediction tables in the multiple threads, and determine the storage area corresponding to the target thread for each label prediction table based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables. The branch predictor includes N label prediction tables and N storage areas, each storage area storing 2 m There are n entries, where N and m are positive integers. The step of determining the storage area corresponding to each label prediction table and the target thread based on the target label offset value corresponding to the target thread and the prediction table identifier of each of the multiple label prediction tables includes: For the first label prediction table among the N label prediction tables, in response to (Tage_Offset + Table_id) ≤ N, the region identifier of the storage area corresponding to the first label prediction table and the target thread is determined to be (Tage_Offset + Table_id); or, in response to (Tage_Offset + Table_id) > N, the region identifier of the storage area corresponding to the first label prediction table and the target thread is determined to be (Tage_Offset + Table_id - N). Where Table_id is the prediction table identifier of the first label prediction table, and Tage_Offset is the target label offset value.

10. The branch predictor of claim 9, further comprising: The hardware control logic module is configured to record the demand information of the multiple threads for each tag prediction table, and adjust the tag offset value stored in the shift register based on the demand information.

11. The branch predictor of claim 9, wherein, The tag offset value in the shift register is configured to be modified externally.

12. A processor comprising a branch predictor according to any one of claims 9-11, wherein, The processor is configured to support multiple threads.

13. An electronic device comprising the processor according to claim 12.

14. An electronic device comprising: At least one storage unit is configured to store computer-readable instructions; as well as At least one processing unit is configured to execute the computer-readable instructions stored in the storage unit to implement the operation method according to any one of claims 1-8.

15. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the operation method according to any one of claims 1-8.

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