PCIe physical layer link establishment abnormity positioning method, controller, medium and program product

Abstract

The invention relates to the technical field of PCIe hardware debugging, and discloses a PCIe physical layer link establishment abnormity positioning method, a controller, a medium and a program product, the method is applied to a PCIe controller, a recording module is arranged in the PCIe controller, and the method comprises the steps that when a state machine of PCIe equipment is in a first state, the state machine of the PCIe equipment is detected in real time; if it is detected that the state machine changes, the change information of the state machine is compared with a preset triggering condition; if the change information of the state machine meets a preset triggering condition, performing data sampling on a target information channel of the PCIe equipment through a recording module to obtain sampling data; the sampling data is used for analyzing to obtain abnormal positioning in PCIe physical layer link establishment. According to the method and the device, the accuracy and the efficiency of abnormal problem positioning in PCIe physical layer link establishment can be improved.

Description

Technical Field

[0001] This application relates to the technical field of PCIe hardware debugging, and specifically relates to a method, a controller, a medium, and a program product for locating abnormal link establishment in the PCIe physical layer. Background Art

[0002] With the development of PCIe technology, for devices with a rate of 16GT / s and above, the requirements for the signal quality, stability, and reliability of the link are further improved, and the demand for analyzing link establishment problems is increasing. During the product testing process, due to differences in conditions such as the test environment, docking devices, and the laboratory, various unexpected reasons may cause link establishment failures. Due to test condition limitations, it is impossible to dock with an analysis device (protocol analyzer). Therefore, when locating link establishment problems, it is impossible to determine the specific reasons for the abnormal jump of the state machine and the data currently received and sent, resulting in the inability to draw a conclusion on the current abnormality, and the solution is given by speculation, with low efficiency and prone to misjudgment, reducing the accuracy rate. Summary of the Invention

[0003] In view of this, this application provides a method, a device, a medium, and a controller for locating abnormal link establishment in the PCIe physical layer to improve the accuracy rate and efficiency of locating abnormal problems in PCIe physical layer link establishment.

[0004] In a first aspect, this application provides a method for locating abnormal link establishment in the PCIe physical layer. The method is applied to a PCIe controller, and a recording module is set in the PCIe controller. The method includes: when the state machine of the PCIe device is in a first state, the state machine of the PCIe device is detected in real time; when the state machine of the PCIe device is in the first state includes one of the following: detecting a change in the state machine of the PCIe device; a change in the state machine of the PCIe device and a pre-configured signal change is matched; the number of times a change in the state machine of the PCIe device and a pre-configured signal change is matched reaches a quantity threshold; if a change in the state machine is detected, the change information of the state machine is compared with a preset trigger condition; if the change information of the state machine meets the preset trigger condition, data sampling is performed on the target information channel of the PCIe device through the recording module to obtain sampling data; the sampling data is used to analyze and obtain the abnormal location in PCIe physical layer link establishment.

[0005] The method provided by this application can accurately obtain data related to anomalies by detecting the changes in the state machine of the PCIe device in real time and performing data sampling when the state machine change information meets the preset trigger conditions. It provides detailed and accurate information for analyzing anomalies in the PCIe physical layer link establishment, thereby improving the accuracy and efficiency of anomaly problem localization in the PCIe physical layer link establishment. Through the first state setting, the changes in the state machine related to link establishment anomalies can be obtained more precisely, thereby improving the efficiency and accuracy of debugging, and helping to quickly locate and solve problems.

[0006] In an alternative embodiment, the target information channels include independent tracking channels and hybrid tracking channels; the independent tracking channels include a transmit tracking channel, a receive tracking channel, a state machine tracking channel, and an equalization tracking channel; the hybrid tracking channels include at least two of the transmit tracking channel, the receive tracking channel, the state machine tracking channel, and the equalization tracking channel.

[0007] In an alternative embodiment, the target information channels include at least one of the following: a transmit tracking channel, a receive tracking channel, a state machine tracking channel, and an equalization tracking channel.

[0008] In an alternative embodiment, the target information channels further include a hybrid tracking channel; the hybrid tracking channels include at least two of the transmit tracking channel, the receive tracking channel, the state machine tracking channel, and the equalization tracking channel.

[0009] This alternative embodiment provides independent and hybrid tracking channels, allows specific channels to be selected according to requirements, enables flexible data sampling, and improves the problem localization efficiency.

[0010] In an alternative embodiment, a configuration register and a storage unit are provided in the recording module; performing data sampling on the target information channels of the PCIe device by the recording module includes: selecting the target information channels according to the configuration register; performing data sampling on the target information channels of the PCIe device, and saving the sampling results to the storage unit.

[0011] This alternative embodiment realizes flexible selection and precise sampling of specific information channels of the PCIe device, ensures the accuracy and reliability of the sampled data, provides strong support for subsequent analysis, improves the working efficiency of the recording module at the same time, and helps to quickly locate and solve anomalies in the PCIe physical layer link establishment.

[0012] In an alternative embodiment, after obtaining the sampled data, it further includes: stopping data sampling based on the stop mode condition; the stop mode condition includes one of the following: the optimized stop mode is to stop recording when a pre-configured signal changes, and after reaching the full count, it also starts recording from 0; the further optimized stop mode is to add the number of matches as a condition on the basis of the optimized stop mode, and only stop recording when the nth match is expected, and after reaching the full count, it also starts recording from 0.

[0013] In this alternative embodiment, by setting different stop mode conditions, the stop timing of data sampling can be flexibly controlled according to actual needs, avoiding unnecessary data sampling and improving the sampling efficiency.

[0014] In an alternative embodiment, the method further includes:

[0015] When the recorded information in the storage unit of the recording module reaches the full count, recording starts again from the 0 address.

[0016] In a second aspect, the present application provides a PCIe controller, which includes a data processing unit and a recording module; the data processing unit is used for: when the state machine of the PCIe device is in the first state, detecting the state machine of the PCIe device in real time; when the state machine of the PCIe device is in the first state includes one of the following: detecting a change in the state machine of the PCIe device; a change in the state machine of the PCIe device and a change in a pre-configured signal is detected; the number of times a change in the state machine of the PCIe device and a change in a pre-configured signal is detected reaches a quantity threshold; if a change in the state machine is detected, comparing the change information of the state machine with a preset trigger condition; if the change information of the state machine meets the preset trigger condition, sampling data from the target information channel of the PCIe device through the recording module to obtain sampled data; the sampled data is used to analyze and obtain the abnormal location in the PCIe physical layer link establishment.

[0017] In an alternative embodiment, the recording module includes a configuration register and a storage unit; the configuration register and the storage unit are used for: selecting the target information channel according to the configuration register; sampling data from the target information channel of the PCIe device and saving the sampling result to the storage unit.

[0018] In a third aspect, the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the PCIe physical layer link establishment abnormal location method in the first aspect or any corresponding embodiment thereof.

[0019] Fourthly, the present application provides a computer program product, including computer instructions for causing a computer to execute the PCIe physical layer link establishment anomaly location method according to the first aspect or any corresponding embodiment thereof as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 is a schematic diagram of LTSSM state machine jumps involved in the embodiments of the present application;

[0022] Figure 2 is a schematic flowchart of a PCIe physical layer link establishment anomaly location method according to an exemplary embodiment of the present application;

[0023] Figure 3 is a block diagram of a PCIe device data sampling structure according to an exemplary embodiment of the present application;

[0024] Figure 4 is a schematic hardware structure diagram of a computer device in the embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0026] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect corresponding relationship between two, may also indicate an associated relationship between two, or may be a relationship such as indication and being indicated, configuration and being configured, etc.

[0027] Please refer to Figure 1 , which shows a schematic diagram of LTSSM state machine jumps involved in the embodiments of the present application. As Figure 1As shown, the LTSSM (Link Training and Status State Machine) is the state machine that controls the physical layer link negotiation in a PCIe device. PCIe is a high-speed serial computer expansion bus standard. The LTSSM state machine has a total of 11 major states and 36 minor states. Among them, "Initial State" refers to the initial state; "Detect" means detection; "Polling" means polling; "Disabled" means disabled; "Configuration" means configuration; "Hot Reset" means hot reset; "Loopback" means loopback. And "L0, L1, L2, L0s" represent different low-power states in the PCIe protocol respectively. Among them, L0 is the normal working state, L0s is the shallow sleep state, and L1 and L2 are deeper low-power states. "Recovery" means recovery. The state machine will make an unexpected jump under abnormal conditions. There is no intuitive record of the state machine jump. The existing means can only infer the possible causes of the current problem through a protocol analyzer. There may be multiple causes for some abnormal states, and only one can be inferred one by one. It is impossible to see the most direct cause that leads to the abnormal jump of the state machine in the digital circuit implementation.

[0028] In different states, the controller needs to send a specific TS (Training Sequence, an ordered set for link training) code stream, and at the same time needs to receive a specific TS code stream. After the handshake is completed, the link is established to L0. When an abnormal state jump occurs, the existing means can only observe the TS sent and received by the link through a protocol analyzer. However, there is a PHY module (Physical Layer, the physical layer in the PCIe protocol stack, responsible for sending and receiving electrical signals on the physical medium), a functional module responsible for processing signal transmission on the physical medium) between the link and the controller. It is impossible to see whether the data is normal when the data reaches the inside of the controller through the link, and it is impossible to define whether the abnormality is caused by the controller or the PHY.

[0029] In the Equalization stage, the PHYs on both sides of the link need to adjust parameters with each other so that the signal quality of the TX transmitted data can meet the bit error rate range specified by the protocol. When an abnormal adjustment occurs, the existing means can only judge the current situation by observing the Equalization information in the TS data in the link through a protocol analyzer, and it is impossible to directly see the key information of the Equalization process. Among them, Equalization is signal equalization, a key technology used in PCIe to improve signal quality.

[0030] The embodiment of the present application provides a method for locating abnormal link establishment in the PCIe physical layer. Combining the implementation of the LTSSM state machine in the internal digital circuit of the controller, it provides the conditional information that needs to be concerned when the state machine jumps and the key data information in the TX and RX directions, and also provides the feedback information of the PHY and the behavior of the controller in the Equalization stage, which can significantly improve the location efficiency and effectively assist in the analysis of abnormal causes under the condition of lacking auxiliary devices.

[0031] According to the embodiment of the present application, an embodiment of a method for locating abnormal link establishment in the PCIe physical layer is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0032] In this embodiment, a method for locating abnormal link establishment in the PCIe physical layer is provided. The method is applied to a PCIe controller, and a recording module is set in the PCIe controller. Figure 2 It is a flowchart of a method for locating abnormal link establishment in the PCIe physical layer shown according to an exemplary embodiment, as Figure 2 shown, and the process includes the following steps:

[0033] Step S201, when the state machine of the PCIe device is in the first state, the state machine of the PCIe device is detected in real time.

[0034] When the state machine of the PCIe device is in the first state, it means that the TRACE function startup condition is met. Only when the state machine is in the first state can the TRACE function be started, and the two are closely related. Optionally, the TRACE function is configured to be started to make it enter the active state, and then the detection of the state machine of the PCIe device is prepared.

[0035] Monitor the jump of the state machine of the PCIe device from one state to another state.

[0036] When the state machine of the PCIe device is in the first state, it includes one of the following:

[0037] The change of the state machine of the PCIe device is detected;

[0038] The state machine of the PCIe device changes and matches the pre-configured signal change;

[0039] The state machine of the PCIe device changes and the number of times of matching the pre-configured signal change reaches the quantity threshold.

[0040] Specifically, when any change occurs in the PCIe device state machine, the first state condition is satisfied. For example, when the state machine jumps from the "idle" state to the "active" state, this change may be a sign that the device starts initialization or link establishment. This is the first startup condition.

[0041] Furthermore, when the state machine jumps, the pre-configured signals (such as data signals, clock signals, etc.) also change. For example, when the state machine jumps from the "unlinked" state to the "linked" state, a certain data signal changes from low level to high level, which may indicate that the device has successfully established a link. This is the second startup condition.

[0042] Moreover, when the state machine jumps and the number of changes in the pre-configured signals reaches a preset threshold. For example, when the state machine jumps to the "unlinked" state multiple times, and the number of occurrences of a certain error signal reaches 10 times frequently, this may mean that there are serious potential problems in the physical layer. This is the third startup condition.

[0043] When the PCIe device state machine meets any of the above conditions, the real-time detection state machine function is enabled.

[0044] Optionally, the first startup condition is initially default selected to determine whether the PCIe device state machine is in the first state.

[0045] During the test process, if it is observed that the PCIe device state machine jumps multiple times and the reasons for each jump are different, when it is necessary to locate the problem for a specific reason, the second startup condition is selected to determine whether the PCIe device state machine is in the first state.

[0046] If it is found that the PCIe device state machine triggers state jumps multiple times and the conditions for each trigger are the same, but it is necessary to locate the reason for the nth trigger of the state jump, at this time, the third startup condition is selected to determine whether the PCIe device state machine is in the first state.

[0047] Through the first state setting, the state machine changes related to abnormal link establishment can be obtained more accurately, thereby improving the efficiency and accuracy of debugging, and helping to quickly locate and solve problems.

[0048] Step S202, if a change in the state machine is detected, the change information of the state machine is compared with the preset trigger condition.

[0049] Common state changes include state jumps, entering an error state, and resetting or restoring the state. For state jumps, for example, the state machine jumps from the "Initial State" to the "L0" state. This situation may indicate that the device starts to enter the working state and begins the data transmission or link establishment process; or jumps from the "Configuration" state to the "L0" state, meaning that the device configuration work is completed and it is about to enter the normal operation mode. For entering an error state, for example, if the state machine jumps to the "Detect / Recovery" state, it may indicate communication problems in the physical layer, such as unstable links, signal attenuation, clock synchronization problems, etc. For resetting or restoring the state, for example, when the device is interfered or an error occurs, it may automatically reset to the initialization state and restart processes such as link establishment; or recover from the error state to the normal operation state and then continue subsequent data transmission operations.

[0050] The state information includes the state the state machine was in before the change, the state it is in after the change, and the jump condition of the change. The preset trigger condition is a pre-set rule, and its function is to filter out specific state machine changes. Compare each element in the change information (such as the current state, jump condition, etc.) with the preset trigger condition. Specifically, the state information can be a jump from "Configuration" to "L0", or a jump from "L0" to "Recovery". The trigger condition can be that the peer meets the conditions for state jump, such as receiving a TS stream that meets the expectations, detecting that the peer enters or exits the electrical idle state, etc.

[0051] Step S203, if the change information of the state machine meets the preset trigger condition, then sample the data of the target information channel of the PCIe device through the recording module to obtain the sampled data; the sampled data is used to analyze and obtain the abnormal positioning in the PCIe physical layer link establishment.

[0052] When the change information of the state machine is exactly the same as the pre-set trigger condition, that is, it meets the preset trigger condition. When the change information of the state machine meets the preset trigger condition, sample the data of the target information channel of the PCIe device through the recording module. Data sampling refers to the process of obtaining data from the target information channel at specific time intervals.

[0053] Sampled data refers to the data obtained through data sampling, which contains the status and information of the target information channel at specific time points. The sampled data can include the status of the LTSSM state machine, jump conditions, link rate, link width, current state duration, TS data stream, error records, etc. For example, in the MAC_TX_TRACE mode, the sampled data can include the TS code stream or data stream in the Tx direction and the abnormal error records of the Tx direction transmission channel. Parse the read sampled data to extract key information. For example, parse the status and jump conditions of the LTSSM state machine, analyze the link rate and width, and check the TS data stream and error records. Determine the abnormalities in the PCIe physical layer link establishment based on the parsed data.

[0054] In summary, the method provided in this embodiment can accurately obtain data related to abnormalities by detecting the changes of the state machine of the PCIe device in real time and performing data sampling when the state machine change information meets the preset trigger conditions. It provides detailed and accurate information for analyzing the abnormalities in the PCIe physical layer link establishment, thereby improving the accuracy and efficiency of locating the abnormality problems in the PCIe physical layer link establishment.

[0055] Among them, the above-mentioned target information channel includes at least one of the following: transmission trace channel, reception trace channel, state machine trace channel, and equalization trace channel.

[0056] Furthermore, the target information channel also includes a hybrid trace channel; the hybrid trace channel includes at least two of the transmission trace channel, reception trace channel, state machine trace channel, and equalization trace channel.

[0057] Specifically, the transmission trace channel (MAC_TX_TRACE) is used to monitor and record the relevant information during data transmission, such as the TS code stream or data stream in the Tx direction and the abnormal error records of the Tx direction transmission channel.

[0058] The reception trace channel (MAC_RX_TRACE) is used to monitor and record the relevant information during data reception, such as the TS code stream or data stream in the Rx direction and whether there are errors in the Rx direction reception channel (such as disparity error, code error, deskew error, framing error specified in the protocol).

[0059] The state machine trace channel (MAC_LTSSM_TRACE) is used to record the state and jump conditions of the state machine, such as the state of the LTSSM state machine, jump conditions, current link rate, link width, current state duration, LANE indication of the TS received by the current link, and data information sent by the current link.

[0060] The Equalization Tracking Channel (EQ_CTRL_TRACE) is used to monitor and record relevant information during the link equalization process, such as the state of the Equalization state machine; the PRESET (a preset value, a mechanism in PCIe for optimizing signal transmission quality) and Coefficient (an important parameter for signal equalization) used when the local end acts as the master during the Equalization process, as well as whether the peer end rejects and the evaluation results returned by the local PHY; whether the local end rejects the peer end's request when acting as the slave during the Equalization process.

[0061] The hybrid tracking channel includes at least two of the transmit tracking channel, receive tracking channel, state machine tracking channel, and equalization tracking channel.

[0062] For example, LTSSM_RXTX_MIX_TRACE includes the state machine tracking channel and the transmit and receive tracking channels, and is used to simultaneously monitor the state of the state machine and the transmission and reception of data; LTSSM_EQTX_MIX_TARACE includes the state machine tracking channel and the transmit and equalization tracking channels, and is used to simultaneously monitor the state of the state machine, data transmission, and the link equalization process. Selecting a specific channel according to requirements can flexibly perform data sampling and improve the efficiency of problem location.

[0063] In an alternative embodiment, a configuration register and a storage unit are provided in the recording module;

[0064] The data sampling of the target information channel of the PCIe device by the recording module in the above step S203 includes:

[0065] Step S2031, select the target information channel according to the configuration register.

[0066] The configuration register determines the target information channel to be selected. When data sampling of a specific information channel is required, corresponding parameters (such as channel selection signals, etc.) are set through the configuration register, so that the recording module can identify and select the target information channel. Selecting means selecting the channel that needs to perform data sampling from multiple information channels.

[0067] Step S2032, perform data sampling on the target information channel of the PCIe device and save the sampling result to the storage unit.

[0068] The storage unit is used to store sampling data and can be an internal SRAM. When the recording module completes data sampling, it will store the sampling results (such as the transmitted data stream, received data stream, state machine state changes, etc.) in the storage unit.

[0069] Please refer to Figure 3 , Figure 3It is a block diagram of a PCIe device data sampling structure shown according to an exemplary embodiment. MAC_RX_TRACE, MAC_TX_TRACE, MAC_LTSSM_TRAC, and EQ_CTRL_TRACE are independent trace channels, and LTSSM_RX_TX_MIX_TRACE, LTSSM_TX_EQ_MIX_TRACE, and LTSSM_RX_EQ_MIX_TRACE are mixed trace channels. TRACE_CTRL is responsible for controlling and managing the recording functions of each information channel. It receives data from each information channel, and according to the settings of the configuration register, gates the target information channel to sample the data of the target information channel of the PCIe device. The SRAM storage unit is used to store the data sampled by the TRACE_CTRL module.

[0070] Each information channel (such as MAC_RX_TRACE, MAC_TX_TRACE) sends data to the TRACE_CTRL module. The TRACE_CTRL module gates the target information channel according to the settings of the configuration register to sample the data of the target information channel of the PCIe device. The sampled data is transmitted to the SRAM through the AXI interface for storage.

[0071] Optionally, the MAC_LTSSM_TRACE channel is initially selected by default to obtain the conditions for the current state machine exception. According to the conditions, judge whether the cause of the exception originates from the transmit (TX) end, the receive (RX) end, or the equalization (EQ) link. After completing the preliminary cause determination, the hybrid mode can be further selected to achieve more accurate positioning of the abnormal problem.

[0072] This optional implementation method realizes the flexible gating and accurate sampling of specific information channels of the PCIe device, ensures the accuracy and reliability of the sampled data, provides strong support for subsequent analysis, improves the working efficiency of the recording module at the same time, and helps to quickly locate and solve abnormal problems in the PCIe physical layer link establishment.

[0073] In an optional implementation method, after obtaining the sampled data, it further includes:

[0074] Based on the stop mode condition, stop data sampling;

[0075] The stop mode condition includes one of the following:

[0076] The optimized stop mode is to stop recording when a pre-configured signal change is matched, and start recording from 0 again after reaching the count limit;

[0077] A further optimized stop method is to add the number of matches as a condition on the basis of the optimized stop method. Only when it is expected to stop recording at the nth match, after counting up, it starts recording from 0 again.

[0078] Specifically, after obtaining the sampled data, the data sampling can also be stopped according to the preset stop method conditions. When a pre-configured signal change is detected, the recording stops. This stop method is applicable to scenarios where sampling needs to be stopped when a specific signal changes. Suppose the pre-configured signal is a certain data signal or control signal. When this signal changes, the recording module stops data sampling.

[0079] Furthermore, the number of matches is added as a condition. Only when it is expected to stop recording at the nth match, the recording stops. This stop method is applicable to scenarios where sampling needs to be stopped when a specific number of signal changes occur. Suppose the pre-configured signal is a certain data signal or control signal, and the expected number of matches is 3 times. When the number of times this signal changes reaches 3 times, the recording module stops data sampling.

[0080] In this optional implementation manner, by setting different stop method conditions, the stop timing of data sampling can be flexibly controlled according to actual needs, avoiding unnecessary data sampling and improving the sampling efficiency.

[0081] Furthermore, when the recorded information in the storage unit of the recording module is full, it starts recording again from the 0 address.

[0082] When the recorded information in the storage unit of the recording module is full, starting recording again from the 0 address ensures the continuity of data sampling. Even if the storage unit is full, new data will not be lost.

[0083] A PCIe controller, the controller includes a data processing unit and a recording module; the data processing unit is used for:

[0084] When the state machine of the PCIe device is in the first state, the state machine of the PCIe device is detected in real time;

[0085] When the state machine of the PCIe device is in the first state, it includes one of the following:

[0086] The change of the state machine of the PCIe device is detected;

[0087] The state machine of the PCIe device changes and a pre-configured signal change is detected;

[0088] The state machine of the PCIe device changes and the number of times a pre-configured signal change is detected reaches a quantity threshold;

[0089] If a state machine change is detected, the change information of the state machine is compared with a preset trigger condition;

[0090] If the change information of the state machine meets the preset trigger condition, the recording module samples the data of the target information channel of the PCIe device to obtain the sampled data; the sampled data is used to analyze and obtain the abnormal location in the PCIe physical layer link establishment.

[0091] In an alternative embodiment, the recording module includes a configuration register and a storage unit; the configuration register and the storage unit are used for:

[0092] Select the target information channel according to the configuration register;

[0093] Sample the data of the target information channel of the PCIe device and save the sampling result in the storage unit.

[0094] The embodiment of the present application further provides a computer device having the above PCIe controller.

[0095] Please refer to Figure 4 , Figure 4 FIG. is a schematic structural diagram of a computer device provided by an alternative embodiment of the present application. As shown in Figure 4 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (such as a server array, a set of blade servers, or a multi-processor system). Figure 4 In

[0096] FIG., one processor 10 is taken as an example.

[0097] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device can be a complex programmable logic device, a field programmable gate array, a general array logic, or any combination thereof.

[0098] The memory 20 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created according to the use of the computer device and the like. In addition, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely provided with respect to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0099] The memory 20 may include volatile memory, such as random access memory. The memory may also include non-volatile memory, such as flash memory, a hard disk, or a solid-state drive. The memory 20 may also include a combination of the above types of memory.

[0100] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 may be connected through a bus or other means. Figure 4 Taking connection through a bus as an example.

[0101] The input device 30 may receive input digital or character information and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (such as an LED), and a haptic feedback device (such as a vibration motor), etc. The above-mentioned display device includes, but is not limited to, a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device may be a touch screen.

[0102] The embodiments of the present application also provide a computer-readable storage medium. The methods according to the embodiments of the present application can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium. Thus, the methods described herein can be stored as such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0103] A part of the present application can be applied as a computer program product, for example, computer program instructions. When executed by a computer, through the operation of the computer, the methods and / or technical solutions according to the present application can be invoked or provided. Those skilled in the art should be able to understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0104] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for locating abnormal link establishment at the PCIe physical layer, characterized in that: The method is applied to a PCIe controller, in which a recording module is provided, and the method comprises: When the state machine of the PCIe device is in the first state, detecting the state machine of the PCIe device in real time; When the state machine of the PCIe device is in the first state, it includes one of the following: Detecting a state machine change of the PCIe device; The state machine of the PCIe device changes and matches the change of the pre-configured signal; The number of times that the state machine of the PCIe device changes and matches the pre-configured signal changes reaches a quantity threshold; If a change in the state machine is detected, comparing the change information of the state machine with a preset trigger condition; If the change information of the state machine meets the preset trigger condition, the target information channel of the PCIe device is sampled by the recording module to obtain sampled data; the sampled data is used to analyze and locate the abnormality in the PCIe physical layer link establishment.

2. The method according to claim 1, characterized in that The target information channel includes at least one of the following: Transmit tracking channel, receive tracking channel, state machine tracking channel and equalization tracking channel.

3. The method according to claim 2, characterized in that The target information channel also includes a hybrid tracking channel; The hybrid tracking channel includes at least two of the transmission tracking channel, the reception tracking channel, the state machine tracking channel and the equalization tracking channel.

4. The method according to claim 3, characterized in that The recording module is provided with a configuration register and a storage unit; The performing data sampling on the target information channel of the PCIe device by the recording module includes: According to the configuration register, gating the target information channel; Data sampling is performed on the target information channel of the PCIe device, and the sampling result is stored in the storage unit.

5. The method according to any one of claims 1 to 4, characterized in that: After obtaining the sampling data, the method further includes: Based on the stop mode condition, stop data sampling; The stop mode condition includes one of the following: The optimized stop mode is to stop recording when a pre-configured signal changes, and start recording from 0 after the count is full; A further optimized stopping method is to add the number of matches as a condition based on the optimized stopping method. Recording is stopped only when the nth match is expected, and recording starts from 0 again after the number is reached.

6. The method according to claim 5, characterized in that The method further comprises: When the recording information in the storage unit of the recording module is full, recording starts again from address 0.

7. A PCIe controller, characterized in that: The controller includes a data processing unit and a recording module; the data processing unit is used to: When the state machine of the PCIe device is in the first state, detecting the state machine of the PCIe device in real time; When the state machine of the PCIe device is in the first state, it includes one of the following: Detecting a state machine change of the PCIe device; The state machine of the PCIe device changes and matches the change of the pre-configured signal; The number of times that the state machine of the PCIe device changes and matches the pre-configured signal changes reaches a quantity threshold; If a change in the state machine is detected, comparing the change information of the state machine with a preset trigger condition; If the change information of the state machine meets the preset trigger condition, data sampling is performed on the target information channel of the PCIe device through the recording module to obtain sampled data; The sampled data is used to analyze and locate abnormalities in the PCIe physical layer link establishment.

8. The PCIe controller according to claim 7, wherein: The recording module includes a configuration register and a storage unit; the configuration register and the storage unit are used to: According to the configuration register, gating the target information channel; Data sampling is performed on the target information channel of the PCIe device, and the sampling result is stored in the storage unit.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the PCIe physical layer link establishment anomaly locating method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the PCIe physical layer link establishment anomaly locating method according to any one of claims 1 to 6.

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