V-R type in-memory three-valued logic operation method based on resistive random access memory unit
By adopting the V-R in-memory three-value logic operation method based on the resistive variable memory cell in the in-memory logic, and using voltage to control the resistive state of the resistive variable memory, the problem that binary Boolean logic in the prior art is difficult to achieve multi-value logic operation, and efficient three-value logic operation and resource utilization efficiency are achieved.
Patent Information
- Application Number
- CN202510282371.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-06-20
AI Technical Summary
The prior art mainly studies in-memory logic based on binary Boolean logic, and it is difficult to achieve efficient multi-value logic operations, which limits the performance and resource utilization efficiency of computer systems.
The V-R in-memory three-valued logic operation method based on the resistive variable memory cell is adopted, and the resistive state change of the resistive variable memory is controlled by voltage to realize the in-memory three-valued IMPLY, NAND, NOR, XNOR, and XOR logic operations.
It realizes the completion of a variety of three-value logic operations in the 1T1R array, which reduces the circuit area and operating time, and improves the reliability and anti-interference ability of logic operations.
Smart Images
Figure CN120179604A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor devices and integrated circuits, and more particularly to a V-R type in-memory ternary logic operation method based on a resistive random access memory (RRAM) cell. Background Art
[0002] In-memory logic circuits are a new architecture for solving the von Neumann bottleneck and memory wall problems in current computers. Memories that implement the functions of in-memory logic circuits can be divided into volatile memories (SRAM, DRAM) and non-volatile memories (RRAM, PCRAM, MRAM). In-memory logic circuits based on the non-volatile memory RRAM have the following advantages: non-volatility after logic completion, the ability to store logic results in-situ; zero static power consumption, no power supply voltage needs to be applied in the standby state when the system is not performing logic operations; and online programmability of logic, enabling specific calculation methods according to different computing requirements. Therefore, in-memory logic circuits based on new non-volatile memories are an important new computer paradigm of the non-von Neumann architecture.
[0003] Traditional in-memory logic based on non-volatile memories mainly studies binary Boolean logic. Although current computer systems are all based on binary logic, studies have shown that calculations based on multi-valued logic (MVL) can reduce the interconnection difficulty and minimize chip space and power consumption by up to 50%. Therefore, multi-valued logic has great potential in replacing traditional computing. In terms of data representation ability, the number of bits required to represent the same value in ternary is about 58.5% less than that in binary, which reduces the complexity of data, especially when dealing with a large number of problems such as data encryption. Therefore, in-memory ternary logic has a very broad application space. Summary of the Invention
[0004] (I) Technical Problems to be Solved
[0005] In view of the above problems, the present disclosure provides a V-R type in-memory ternary logic operation method based on a resistive random access memory (RRAM) cell, where "V" represents voltage and "R" represents resistive, that is, voltage is used to control the resistance state change of a resistive random access memory (such as RRAM) to implement logical operations. This method can implement the functions of a ternary logic gate circuit in a resistive random access memory cell (1T1R) composed of an N-type metal oxide semiconductor transistor (NMOS transistor) and a resistive random access memory (RRAM), including in-memory ternary implication (IMPLY) logic operation, in-memory ternary NAND logic operation, in-memory ternary NOR logic operation, in-memory ternary exclusive NOR (XNOR) logic operation, and in-memory ternary exclusive OR (XOR) logic operation.
[0006] (II) Technical Solutions
[0007] In view of the above technical problems, embodiments of the present disclosure propose a V-R in-memory ternary exclusive OR logic operation method based on a resistive random access memory (RRAM) cell.
[0008] According to a first aspect of the present disclosure, there is provided a V-R in-memory ternary implication logic operation method based on a resistive random access memory (RRAM) cell. The resistive random access memory (RRAM) cell includes an NMOS transistor and a resistive random access memory (RRAM). The lower electrode of the resistive random access memory (RRAM) is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory (RRAM) is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source of the NMOS transistor is connected to a source line. The method includes: initializing the resistance state of the resistive random access memory (RRAM) to a high resistance state by using a reset operation; setting the bit line terminal voltage V BL of the resistive random access memory (RRAM) cell to HV; applying a gate voltage V p = V gate at the gate of the NMOS transistor according to the voltage V p corresponding to the logical value of the logical input P to complete the writing of the logical variable P; applying a terminal voltage V q at the source line of the resistive random access memory (RRAM) cell according to the voltage V SL = V q corresponding to the logical value of the logical input Q to complete the writing of the logical variable Q; after the resistive random access memory (RRAM) device completes the resistive operation, reading the resistance state of the resistive random access memory (RRAM) after the resistance change to obtain the logical value of the output Y.
[0009] According to a second aspect of the present disclosure, there is provided a V-R in-memory ternary NAND logic operation method based on a resistive random access memory (RRAM) cell. The resistive random access memory (RRAM) cell includes an NMOS transistor and a resistive random access memory (RRAM). The lower electrode of the resistive random access memory (RRAM) is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory (RRAM) is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source of the NMOS transistor is connected to a source line. The method includes: initializing the resistance state of the resistive random access memory (RRAM) to a high resistance state by using a reset operation; setting the source line terminal voltage V SL of the resistive random access memory (RRAM) cell to 0V; applying a gate voltage V p = V gate at the gate of the NMOS transistor according to the voltage V p corresponding to the logical value of the logical input P to complete the writing of the logical variable P; applying a terminal voltage V q at the bit line of the resistive random access memory (RRAM) cell according to the voltage V BL = V q corresponding to the logical value of the logical input Q to complete the writing of the logical variable Q; after the resistive random access memory (RRAM) device completes the resistive operation, reading the resistance state of the resistive random access memory (RRAM) after the resistance change to obtain the logical value of the output Y.
[0010] According to the third aspect of the present disclosure, a V-R type in-memory ternary NOR logic operation method based on a resistive random access memory (RRAM) cell is provided. The RRAM cell includes an NMOS transistor and a resistive random access memory. The lower electrode of the resistive random access memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source of the NMOS transistor is connected to the source line. The method includes: setting a first fixed voltage offset V offset1 and a second fixed voltage offset V offset2 ; initializing the resistance state of the resistive random access memory to a high resistance state using a reset operation; setting the source line terminal voltage V SL of the RRAM cell to 0V; applying a gate voltage V p = V offset1 + V gate to the gate of the NMOS transistor according to the voltage V p corresponding to the logical value of the logical input P and the first fixed voltage offset V offset1 , to complete the writing of the logical variable P; applying a terminal voltage V q = V offset2 + V BL to the bit line of the RRAM cell according to the voltage V q corresponding to the logical value of the logical input Q and the second fixed voltage offset V offset2 , to complete the writing of the logical variable Q; after the RRAM device completes the resistive operation, reading the resistance state of the resistive random access memory after the resistance change to obtain the logical value of the output Y.
[0011] According to the fourth aspect of the present disclosure, a V-R type in-memory ternary XNOR logic operation method based on a resistive random access memory (RRAM) cell is provided. The RRAM cell includes an NMOS transistor and a resistive random access memory. The lower electrode of the resistive random access memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source of the NMOS transistor is connected to the source line. The method includes: initializing the resistance state of the resistive random access memory to a high resistance state using a reset operation; applying a terminal voltage V p = max(V q , V BL ) to the bit line of the RRAM cell and a terminal voltage V p = min(V q , V SL ) to the source line of the RRAM cell according to the voltage V p corresponding to the logical value of the logical input P and the voltage V q corresponding to the logical value of the logical input Q, to complete the writing of the logical variables P and Q; applying a gate voltage V gate = V gate(SET), where V gate(SET) is the voltage for the set operation; after the resistive switching operation of the resistive random access memory device is completed, the resistance state of the resistive random access memory after resistive switching is read to obtain the logical value of the output Y.
[0012] According to the fifth aspect of the present disclosure, a V-R type in-memory ternary exclusive-OR logic operation method based on a resistive memory cell is provided. The resistive memory cell includes an NMOS transistor and a resistive random access memory. The lower electrode of the resistive random access memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source of the NMOS transistor is connected to the source line. The method includes: initializing the resistance state of the resistive random access memory to a low resistance state using a set operation; according to the voltage V p corresponding to the logical value of the logical input P and the voltage V q corresponding to the logical value of the logical input Q, applying a terminal voltage V BL = min(V p , V q ) to the bit line of the resistive memory cell, applying a terminal voltage V SL = max(V p , V q ) to the source line of the resistive memory cell to complete the writing of the logical variables P and Q; applying a gate voltage V gate = V gate(RESET) , where V gate(RESET) is the voltage for the reset operation; after the resistive switching operation of the resistive random access memory device is completed, the resistance state of the resistive random access memory after resistive switching is read to obtain the logical value of the output Y.
[0013] In some exemplary embodiments, when the logical value of P is 2, the corresponding voltage V p is a high voltage V p (HV); when the logical value of P is 1, the corresponding voltage V p is a medium voltage V p (MV); when the logical value of P is 0, the corresponding voltage V p is a low-medium voltage V p (LV); when the logical value of Q is 2, the corresponding voltage V q is a high voltage V q (HV); when the logical value of Q is 1, the corresponding voltage V q is a medium voltage V q (MV); when the logical value of Q is 0, the corresponding voltage V q is a low-medium voltage V q (LV).
[0014] In some exemplary embodiments, when the resistance state of the resistive random access memory (RRAM) is a high resistance state, the corresponding logical value of the output Y is 2; when the resistance state of the RRAM is an intermediate resistance state, the corresponding logical value of the output Y is 1; when the resistance state of the RRAM is a low resistance state, the corresponding logical value of the output Y is 0.
[0015] In some exemplary embodiments, when the resistance state of the RRAM is at the 1000 kΩ level, it corresponds to the high resistance state; when the resistance state of the RRAM is at the 100 kΩ level, it corresponds to the intermediate resistance state; when the resistance state of the RRAM is at the 10 kΩ level, it corresponds to the low resistance state.
[0016] (III) Beneficial Effects
[0017] As can be seen from the above technical solutions, a V-R type in-memory ternary logic operation method based on a resistive memory device provided by the embodiments of the present disclosure has at least the following beneficial effects:
[0018] (1) The circuit structure is simple. By utilizing the resistive characteristics of the SET / RESET process of the RRAM, voltage pulses of different magnitudes are applied to the RRAM, thereby controlling the RRAM to change into three different resistance states and completing the overall logic operation process. The entire circuit only requires a 1T1R array to complete, without any additional circuit area overhead.
[0019] (2) It can implement in-memory ternary IMPLY, NAND, NOR, XNOR, and XOR logic operations in one memory write cycle. The overall operation time includes the time for writing logic to the memory and the time for reading the logic output, providing a V-R type in-memory ternary logic operation method with low logic operation steps and low logic operation time.
[0020] (3) It has strong logical reliability and anti-interference ability. Compared with R-R logic (where "R" represents resistive, and "R-R logic" is a logic operation implemented based on the interaction between resistive materials) and V / R-R logic (where "V" represents voltage, the first "R" represents resistance, and the second "R" represents resistive. Therefore, V / R-R logic is a scheme that combines voltage and resistance signals and realizes logic operations through resistive materials), the inputs of V-R logic are all voltages, which has better reliability and anti-interference ability for resistive random access memories and is also convenient for testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above content and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:
[0022] Figure 1 Schematically shows a flowchart of a V-R type in-memory ternary IMPLY logic operation method based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0023] Figure 2 Schematically shows a circuit diagram of a V-R type in-memory ternary IMPLY logic operation based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0024] Figure 3 Schematically shows a flowchart of a V-R type in-memory ternary NAND logic operation method based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0025] Figure 4 Schematically shows a circuit diagram of a V-R type in-memory ternary NAND logic operation based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0026] Figure 5 Schematically shows a flowchart of a V-R type in-memory ternary NOR logic operation method based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0027] Figure 6 Schematically shows a circuit diagram of a V-R type in-memory ternary NOR logic operation based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0028] Figure 7 Schematically shows a flowchart of a V-R type in-memory ternary XNOR logic operation method based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0029] Figure 8 Schematically shows a circuit diagram of a V-R type in-memory ternary XNOR logic operation based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure;
[0030] Figure 9 Schematically shows a flowchart of a V-R type in-memory ternary XOR logic operation method based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure; and
[0031] Figure 10 Schematically shows a circuit diagram of a V-R type in-memory ternary XOR logic operation based on a resistive random access memory (RRAM) cell according to an embodiment of the present disclosure. Detailed implementation manners
[0032] To make the objectives, technical solutions, and advantages of the present disclosure more apparent, the following further elaborates on the present disclosure in detail with reference to specific embodiments and the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.
[0033] The present disclosure provides a V-R type in-memory ternary logic operation method based on a resistive random access memory (RRAM) device, including: quantifying input and output logic variables V p , V q ; initializing the resistance value of the resistive random access memory according to the logic operation; applying a corresponding operation voltage to the resistive memory cell according to the logic input; and reading the resistance value of the resistive random access memory after the operation to obtain the result of the logic calculation Y. The entire circuit only requires a 1T1R array to complete. The circuit structure is simple. The SET / RESET resistive characteristics of the RRAM device are used to achieve a three-state conversion, and further to achieve in-memory ternary IMPLY, NAND, NOR, XNOR, and XOR logic operations. This method avoids a large number of auxiliary memory cells in the traditional Boolean logic operation method, as well as the circuit area and speed overhead caused by multiple cycles of memory writing. The in-memory ternary IMPLY, NAND, NOR, XNOR, and XOR logic operations are introduced in detail in combination with Figures 1 - 10
[0034] Figure 1 Schematically shows a flowchart of a V-R type in-memory ternary IMPLY logic operation method based on a resistive memory cell according to an embodiment of the present disclosure. The resistive memory cell used in this method includes an NMOS transistor and a resistive random access memory. The lower electrode of the resistive random access memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source of the NMOS transistor is connected to the source line. See Figure 2
[0035] As shown in Figure 1 and Figure 2 , a V-R type in-memory ternary IMPLY logic operation method based on a resistive memory cell according to an embodiment of the present disclosure includes steps S110 - S150.
[0036] In step S110, the resistance state of the resistive random access memory is initialized to a high resistance state using a reset operation.
[0037] In step S120, the bit line terminal voltage V BL of the resistive memory cell is set to HV.
[0038] For example, HV = 2V.
[0039] In step S130, according to the voltage V corresponding to the logical value of the logical input P p , a gate voltage V is applied to the gate of the NMOS transistor gate = V p , completing the writing of the logical variable P.
[0040] In the embodiment of the present disclosure, the logical input P is the gate voltage V of the NMOS transistor in the resistive memory cell gate , when the logical value of P is 2, the corresponding voltage V p is the high voltage V p (HV); when the logical value of P is 1, the corresponding voltage V p is the medium voltage V p (MV); when the logical value of P is 0, the corresponding voltage V p is the medium-low voltage V p (LV). It can be understood that in the embodiment of the present disclosure, the high gate voltage V gate (HV) is defined as logic 2, the medium gate voltage V gate (MV) is defined as logic 1, and the low gate voltage V gate (LV) is defined as logic 0.
[0041] In step S140, according to the voltage V corresponding to the logical value of the logical input Q q , a terminal voltage V is applied to the source line of the resistive memory cell SL = V q , completing the writing of the logical variable Q.
[0042] In the embodiment of the present disclosure, the logical input Q is the terminal voltage V of the source line in the 1T1R cell SL , when the logical value of Q is 2, the corresponding voltage V q is the high voltage V q (HV); when the logical value of Q is 1, the corresponding voltage V q is the medium voltage V q (MV); when the logical value of Q is 0, the corresponding voltage V q is the medium-low voltage V q (LV). It can be understood that in the embodiment of the present disclosure, the high voltage V SL (HV) is defined as logic 2, the medium voltage V SL (MV) is defined as logic 1, and the low voltage V SL (LV) is defined as logic 0.
[0043] It can be understood that steps S120, S130, and S140 can be performed synchronously.
[0044] In step S150, after the resistive switching operation of the resistive random access memory (RRAM) device is completed, the resistance state of the RRAM after resistive switching is read to obtain the logical value of the output Y.
[0045] In the embodiments of the present disclosure, when the resistance state of the RRAM is at the 1000 kΩ level, it corresponds to the high resistance state; when the resistance state of the RRAM is at the 100 kΩ level, it corresponds to the intermediate resistance state; when the resistance state of the RRAM is at the 10 kΩ level, it corresponds to the low resistance state. The truth table of the in-memory ternary IMPLY logic operation is shown in Table 1.
[0046] Table 1 Truth table of the in-memory ternary IMPLY logic operation
[0047]
[0048] For example, P = 2, Q = 1, P = 2 represents V gate as the high voltage level (HV), with a typical value of 2.0 V, and Q = 1 represents V SL as the medium voltage level (MV), with a typical value of 1.5 V. At this time, the ternary IMPLY operation is as follows: First, the RRAM is resistively switched to the high resistance state (HRS) using the RESET operation. Secondly, a voltage pulse of V gate = 2.0 V, V SL = 1.5 V, V BL = 2.0 V is applied to the 1T1R cell. Finally, the resistance state Y of the RRAM after resistive switching is read to obtain the 100 kΩ level, representing the output result as the intermediate resistance state (MRS) logic "1", and the in-memory ternary IMPLY calculation operation is completed.
[0049] Figure 3 Schematically shows a flowchart of a V-R type in-memory ternary NAND logic operation method based on a resistive memory cell according to an embodiment of the present disclosure. The resistive memory cell used in this method includes an NMOS transistor and a resistive random access memory. The lower electrode of the resistive random access memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive random access memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source of the NMOS transistor is connected to the source line. See Figure 4 .
[0050] As Figure 3 and Figure 4 shown, a V-R type in-memory ternary NAND logic operation method based on a resistive memory cell according to an embodiment of the present disclosure includes steps S210 - S250.
[0051] In step S210, the resistance state of the resistive random access memory is initialized to the high resistance state using the reset operation.
[0052] In step S220, the source line terminal voltage V of the resistive memory cellSL Set to 0V.
[0053] In step S230, according to the voltage V corresponding to the logic value of the logic input P p , apply the gate voltage V to the gate of the NMOS transistor gate = V p , and complete the writing of the logic variable P.
[0054] In the embodiment of the present disclosure, the logic input P is the gate voltage V of the NMOS transistor in the resistive memory cell gate , when the logic value of P is 2, the corresponding voltage V p is the high voltage V p (HV); when the logic value of P is 1, the corresponding voltage V p is the medium voltage V p (MV); when the logic value of P is 0, the corresponding voltage V p is the medium-low voltage V p (LV). It can be understood that in the embodiment of the present disclosure, the high gate voltage V gate (HV) is defined as logic 2, the medium gate voltage V gate (MV) is defined as logic 1, and the low gate voltage V gate (LV) is defined as logic 0.
[0055] In step S240, according to the voltage V corresponding to the logic value of the logic input Q q , apply the terminal voltage V to the bit line of the resistive memory cell BL = V q , and complete the writing of the logic variable Q.
[0056] In the embodiment of the present disclosure, the logic input Q is the terminal voltage V of the bit line in the 1T1R cell SL , when the logic value of Q is 2, the corresponding voltage V q is the high voltage V q (HV); when the logic value of Q is 1, the corresponding voltage V q is the medium voltage V q (MV); when the logic value of Q is 0, the corresponding voltage V q is the medium-low voltage V q (LV). It can be understood that in the embodiment of the present disclosure, the high voltage V BL (HV) is defined as logic 2, the medium voltage V BL (MV) is defined as logic 1, and the low voltage V BL (LV) is defined as logic 0.
[0057] It can be understood that steps S220, S230, and S240 can be performed synchronously.
[0058] In step S250, after the resistive memory device completes the resistive switching operation, the resistance state of the resistive memory after the resistive switching is read to obtain the logic value of the output Y.
[0059] In the disclosed embodiment, when the resistance state of the resistive memory is at the level of 1000 kΩ, it corresponds to a high resistance state; when the resistance state of the resistive memory is at the level of 100 kΩ, it corresponds to an intermediate resistance state; when the resistance state of the resistive memory is at the level of 10 kΩ, it corresponds to a low resistance state. The truth table of the three-valued NAND logic operation in the memory is shown in Table 2.
[0060] Table 2 Truth table of the three-value NAND logic operation in memory
[0061]
[0062] For example, P=2, Q=1, P=2 represents V gate is the high voltage level (HV), with a typical value of 2.0V, and Q=1 represents V BL The MV is a medium voltage level (MV), with a typical value of 1.5V. At this time, the three-value NAND operation is as follows: first, the RRAM is changed to a high resistance state (HRS) using a RESET operation, and then V is applied to the 1T1R cell. gate =2.0V,V SL =0V,V BL =1.5V voltage pulse, and finally read the resistance state Y after the RRAM resistance change, and get 100kΩ level, which means the output result is the middle resistance state (MRS) logic "1", completing the in-memory three-value NAND calculation operation.
[0063] Figure 5 A flowchart of a VR-type in-memory three-value NOR logic operation method based on a resistive memory cell according to an embodiment of the present disclosure is schematically shown. The resistive memory cell used in the method includes an NMOS transistor and a resistive memory. The lower electrode of the resistive memory is connected to the drain end of the NMOS transistor, the upper electrode of the resistive memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source end of the NMOS transistor is connected to the source line. Figure 6 .
[0064] like Figure 5 and Figure 6 As shown, a VR-type in-memory three-value NOR logic operation method based on a resistive memory cell according to an embodiment of the present disclosure includes steps S310 to S360.
[0065] In step S310, a first fixed voltage offset V is set. offset1 and a second fixed voltage offset V offset2 .
[0066] In step S320, the resistance state of the resistive memory is initialized to a high-resistance state using a reset operation.
[0067] In step S330, the source-line terminal voltage V of the resistive memory cell is set to 0V. SL Set to 0V.
[0068] In step S340, according to the voltage V corresponding to the logical value of the logical input P and the first fixed voltage offset V, a gate voltage V = V + V is applied to the gate of the NMOS transistor, completing the writing of the logical variable P. p And the first fixed voltage offset V offset1 , a gate voltage V is applied to the gate of the NMOS transistor gate = V p + V offset1 , completing the writing of the logical variable P.
[0069] In the embodiment of the present disclosure, the input P is the difference V = V - V between the gate voltage Vgate of the NMOS transistor in the 1T1R cell and the fixed voltage offset V. When the logical value of P is 2, the corresponding voltage V is a high voltage V (HV); when the logical value of P is 1, the corresponding voltage V is a medium voltage V (MV); when the logical value of P is 0, the corresponding voltage V is a medium-low voltage V (LV). offset1 Difference V p = V gate - V offset1 , when the logical value of P is 2, the corresponding voltage V p Is a high voltage V p (HV); when the logical value of P is 1, the corresponding voltage V p Is a medium voltage V p (MV); when the logical value of P is 0, the corresponding voltage V p Is a medium-low voltage V p (LV).
[0070] In step S350, according to the voltage V corresponding to the logical value of the logical input Q and the second fixed voltage offset V, a terminal voltage V = V + V is applied to the bit line of the resistive memory cell, completing the writing of the logical variable Q. q And the second fixed voltage offset V offset2 , a terminal voltage V is applied to the bit line of the resistive memory cell BL = V q + V offset2 , completing the writing of the logical variable Q.
[0071] In the embodiment of the present disclosure, the logical input Q is the difference V = V - V between the bit line terminal voltage V in the 1T1R cell and the fixed voltage offset V. When the logical value of Q is 2, the corresponding voltage V is a high voltage V (HV); when the logical value of Q is 1, the corresponding voltage V is a medium voltage V (MV); BL And the fixed voltage offset V offset1 Difference V q = V BL - V offset2 . When the logical value of Q is 2, the corresponding voltage V q Is a high voltage V q (HV); when the logical value of Q is 1, the corresponding voltage V q Is a medium voltage V q(MV); when the logical value of Q is 0, the corresponding voltage V q is a medium to low voltage V q (LV).
[0072] It can be understood that steps S330, S340, and S350 can be performed synchronously.
[0073] In step S360, after the resistive switching operation of the resistive memory device is completed, the resistive state of the resistive memory after resistive switching is read to obtain the logical value of the output Y.
[0074] In the embodiments of the present disclosure, when the resistive state of the resistive memory is at the 1000 kΩ level, it corresponds to the high resistive state; when the resistive state of the resistive memory is at the 100 kΩ level, it corresponds to the intermediate resistive state; when the resistive state of the resistive memory is at the 10 kΩ level, it corresponds to the low resistive state. The truth table of the in-memory ternary NOR logic operation is shown in Table 3.
[0075] Table 3 Truth table of the in-memory ternary NOR logic operation
[0076]
[0077] For example, P = 2, Q = 1, P = 2 represents V p is at the high voltage level (HV), with a typical value of 2.0 V, and Q = 1 represents V q is at the medium voltage level (MV), with a typical value of 1.0 V. At the same time, V offset1 = V offset2 = 1.0 V. At this time, the ternary NOR operation is as follows: First, the RRAM is resistively switched to the high resistive state (HRS) using the RESET operation. Secondly, voltage pulses of V p + V offset1 = 2.0 V + 1.0 V = 3.0 V, V SL = 0 V, V q + V offset2 = 1.0 V + 1.0 V = 2.0 V are applied to the 1T1R cell. Finally, the resistive state Y of the RRAM after resistive switching is read to obtain the 10 kΩ level, representing the output result as the low resistive state (LRS) logic "0", completing the in-memory ternary NOR calculation operation.
[0078] Figure 7 Schematically shows a flowchart of a V-R type in-memory ternary XNOR logic operation method based on a resistive memory cell according to an embodiment of the present disclosure. The resistive memory cell used in this method includes an NMOS transistor and a resistive memory. The lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source terminal of the NMOS transistor is connected to the source line. See Figure 8 .
[0079] As Figure 7 and Figure 8 shown, a V-R type in-memory ternary XNOR logic operation method based on a resistive random access memory cell according to an embodiment of the present disclosure includes steps S410 to S440.
[0080] In step S410, the resistance state of the resistive random access memory is initialized to a high resistance state by using a reset operation.
[0081] In step S420, according to the voltage V p corresponding to the logical value of the logical input P q and the voltage V BL corresponding to the logical value of the logical input Q, a terminal voltage V p = max(V q ) is applied to the bit line of the resistive random access memory cell, and a terminal voltage V SL = min(V p , Vq) is applied to the source line of the resistive random access memory cell, thereby completing the writing of the logical variables P and Q.
[0082] In the embodiment of the present disclosure, the logical input P is V p , and the logical input Q is V q . For the logical input P, we define the high voltage V p (HV) as logic 2, the medium voltage V p (MV) as logic 1, and the low voltage V p (LV) as logic 0. For the logical input Q, we define the high voltage V q (HV) as logic 2, the medium voltage V q (MV) as logic 1, and the low voltage V q (LV) as logic 0. In this operation scheme, the voltage value V SL input to the source line end of the 1T1R cell is the smaller value min(V p , V q ) between V p and V q , and the voltage value V BL input to the bit line end is the larger value max(V p , V q ) between V p and V q .
[0083] In step S430, a gate voltage V gate = V gate(SET) is applied to the gate of the NMOS transistor, where V gate(SET)To set the voltage for the operation.
[0084] For example, V gate =V gate(SET) = 2.5V.
[0085] It can be understood that steps S420 and S430 can be performed synchronously.
[0086] In step S440, after the resistive switching operation of the resistive random access memory (RRAM) device is completed, the resistance state of the RRAM after resistive switching is read to obtain the logical value of the output Y.
[0087] In the embodiment of the present disclosure, when the resistance state of the RRAM is at the 1000 kΩ level, it corresponds to the high resistance state; when the resistance state of the RRAM is at the 100 kΩ level, it corresponds to the intermediate resistance state; when the resistance state of the RRAM is at the 10 kΩ level, it corresponds to the low resistance state. The truth table of the in-memory ternary XNOR logic operation is shown in Table 4.
[0088] Table 4 Truth table of the in-memory ternary XNOR logic operation
[0089]
[0090] For example, P = 2, Q = 1, P = 2 represents V p as the high voltage level (HV), with a typical value of 2.8V, and Q = 1 represents V q as the medium voltage level (MV), with a typical value of 1.4V. At this time, the ternary XNOR operation is as follows: First, the RRAM is resistively switched to the high resistance state (HRS) using the RESET operation. Secondly, a voltage pulse of V p = 2.8V, V q = 1.4V, V gate = 2.5V is applied to the 1T1R cell. Finally, the resistance state Y of the RRAM after resistive switching is read, obtaining the 100 kΩ level, representing the output result as the intermediate resistance state (MRS) logic "1", completing the in-memory ternary XNOR calculation operation.
[0091] For example, P = 2, Q = 2, P = 2 represents V p as the high voltage level (HV), with a typical value of 2.8V, and Q = 2 represents V q as the high voltage level (HV), with a typical value of 2.8V. At this time, the ternary XNOR operation is as follows: First, the RRAM is resistively switched to the high resistance state (HRS) using the RESET operation. Secondly, a voltage pulse of V p = 2.8V, V q = 2.8V, V gateA voltage pulse of 2.5V is applied, and finally the resistance state Y of the RRAM after resistance change is read, obtaining a level of 1000 kΩ, representing that the output result is a high resistance state (HRS) logic "2", thus completing the in-memory ternary XNOR calculation operation.
[0092] For example, P = 2, Q = 0, and P = 2 represents V p as a high voltage level (HV), with a typical value of 2.8V, and Q = 0 represents V q as a low voltage level (LV), with a typical value of 0.1V. At this time, the ternary XNOR operation is as follows: First, the RRAM is changed to a high resistance state (HRS) using the RESET operation. Secondly, a voltage V p = 2.8V, V q = 0.1V, V gate = 2.5V voltage pulse is applied, and finally the resistance state Y of the RRAM after resistance change is read, obtaining a level of 10 kΩ, representing that the output result is a low resistance state (LRS) logic "0", thus completing the in-memory ternary XNOR calculation operation.
[0093] Figure 9 Schematically shows a flowchart of a V-R type in-memory ternary XOR logic operation method based on a resistive memory cell according to an embodiment of the present disclosure. The resistive memory cell used in this method includes an NMOS transistor and a resistive memory. The lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to the bit line, the gate of the NMOS transistor is connected to the word line, and the source terminal of the NMOS transistor is connected to the source line. Refer to Figure 10 .
[0094] As Figure 9 and Figure 10 shown, a V-R type in-memory ternary XOR logic operation method based on a resistive memory cell according to an embodiment of the present disclosure includes steps S510 - S540.
[0095] In step S510, the resistance state of the resistive memory is initialized to a low resistance state using a SET operation.
[0096] In step S520, according to the voltage V p corresponding to the logical value of the logical input P and the voltage V q corresponding to the logical value of the logical input Q, an end voltage V BL = min(V p , V q ) is applied to the bit line application end of the resistive memory cell, and an end voltage V SL = max(V p , V q ) is applied to the source line application end of the resistive memory cell, thus completing the writing of the logical variables P and Q.
[0097] In an embodiment of the present disclosure, the logical input P is V p , and the logical input Q is V q . For the logical input P, we define the high voltage V p (HV) as logic 2, the medium voltage V p (MV) as logic 1, and the low voltage V p (LV) as logic 0. For the logical input Q, we define the high voltage V q (HV) as logic 2, the medium voltage V q (MV) as logic 1, and the low voltage V q (LV) as logic 0. In this operation scheme, the voltage value V SL input at the source line end of the 1T1R cell is the larger value between V p and V q , i.e., max(V p , V q ), and the voltage value V BL input at the bit line end is the smaller value between V p and V q , i.e., min(V p , V q ).
[0098] In step S530, a gate voltage V gate = V gate(RESET) is applied to the gate of the NMOS transistor, where V gate(RESET) is the voltage for the reset operation.
[0099] For example, V gate = V gate(RESET) = 2.5V.
[0100] It can be understood that steps S520 and S530 can be performed synchronously.
[0101] In step S540, after the resistive switching operation is completed on the resistive random access memory device, the resistive state of the resistive random access memory after the resistive switching is read to obtain the logical value of the output Y.
[0102] In an embodiment of the present disclosure, when the resistive state of the resistive random access memory is at the 1000 kΩ level, it corresponds to the high resistive state; when the resistive state of the resistive random access memory is at the 100 kΩ level, it corresponds to the intermediate resistive state; when the resistive state of the resistive random access memory is at the 10 kΩ level, it corresponds to the low resistive state. The truth table of the in-memory ternary XOR logic operation is shown in Table 5.
[0103] Table 5 Truth table of the in-memory ternary XOR logic operation
[0104]
[0105] For example, P = 2, Q = 1, P = 2 represents V p as the high voltage level (HV), with a typical value of 3.8V, and Q = 1 represents V q as the medium voltage level (MV), with a typical value of 1.8V. At this time, the three - valued XOR operation is as follows: First, the RRAM is resistively changed to the low resistance state (LRS) using the SET operation. Second, a voltage pulse of V p = 3.8V, V q = 1.8V, V gate = 2.5V is applied to the 1T1R cell. Finally, the resistive state Y of the RRAM after resistive change is read, obtaining a level of 100 kΩ, representing that the output result is the middle resistive state (MRS) logic "1", completing the in - memory three - valued XOR calculation operation.
[0106] For example, taking P = 2, Q = 2 as an example, P = 2 represents V p as the high voltage level (HV), with a typical value of 3.8V, and Q = 2 represents V q as the high voltage level (HV), with a typical value of 3.8V. At this time, the three - valued XOR operation is as follows: First, the RRAM is resistively changed to the low resistance state (LRS) using the SET operation. Second, a voltage pulse of V p = 3.8V, V q = 3.8V, V gate = 2.5V is applied to the 1T1R cell. Finally, the resistive state Y of the RRAM after resistive change is read, obtaining a level of 10 kΩ, representing that the output result is the low resistance state (LRS) logic "0", completing the in - memory three - valued XOR calculation operation.
[0107] For example, P = 2, Q = 0, P = 2 represents V p as the high voltage level (HV), with a typical value of 3.8V, and Q = 0 represents V q as the low voltage level (LV), with a typical value of 0.1V. At this time, the three - valued XOR operation is as follows: First, the RRAM is resistively changed to the low resistance state (LRS) using the SET operation. Second, a voltage pulse of V p = 3.8V, V q = 0.1V, V gate = 2.5V is applied to the 1T1R cell. Finally, the resistive state Y of the RRAM after resistive change is read, obtaining a level of 1000 kΩ, representing that the output result is the high resistance state (HRS) logic "2", completing the in - memory three - valued XOR calculation operation.
[0108] The circuit structure of the embodiments of the present disclosure is simple. By utilizing the resistance-variable characteristics of the SET / RESET process of the RRAM, different magnitudes of voltage pulses are applied to the RRAM, thereby controlling the RRAM to change into three different resistance states to complete the overall logical operation process. The entire circuit only requires a 1T1R array to complete, without any additional circuit area overhead. It can achieve in-memory ternary IMPLY, NAND, NOR, XNOR, and XOR logical operations in one step of the memory writing cycle. The overall operation time includes the time for logically writing to the memory and the time for reading the logical output, providing a V-R type in-memory ternary logic operation method with low logical operation steps and low logical operation time.
[0109] Those skilled in the art can understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.
Claims
1. A method for three-value implicit logic operation in a VR type memory based on a resistive memory unit, wherein the resistive memory unit comprises an NMOS transistor and a resistive memory, wherein the lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source terminal of the NMOS transistor is connected to a source line, wherein: include: Initialize the resistance state of the resistive memory to a high-resistance state using a reset operation; The bit line terminal voltage V BL Set to HV; The voltage V corresponding to the logic value of the logic input P p , a gate voltage V is applied to the gate of the NMOS transistor gate =V p , complete the writing of the logical variable P; The voltage V corresponding to the logic value of the logic input Q q , a voltage V is applied to the source line of the resistive memory cell SL =V q , complete the writing of the logical variable Q; After the resistive switching memory device completes the resistive switching operation, the resistance state of the resistive switching memory after the resistance switching is read to obtain the logic value of the output Y.
2. A method for performing three-valued AND-NOT logic operations in a VR-type memory based on a resistive memory unit, wherein the resistive memory unit comprises an NMOS transistor and a resistive memory, wherein the lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source terminal of the NMOS transistor is connected to a source line, wherein: include: Initialize the resistance state of the resistive memory to a high-resistance state using a reset operation; The source line voltage V SL Set to 0V; The voltage V corresponding to the logic value of the logic input P p , a gate voltage V is applied to the gate of the NMOS transistor gate =V p , complete the writing of the logical variable P; The voltage V corresponding to the logic value of the logic input Q q , a terminal voltage V is applied to the bit line of the resistive memory cell BL =V q , complete the writing of the logical variable Q; After the resistive switching memory device completes the resistive switching operation, the resistance state of the resistive switching memory after the resistance switching is read to obtain the logic value of the output Y.
3. A method for performing three-value or non-logical operation in a VR-type memory based on a resistive memory unit, wherein the resistive memory unit comprises an NMOS transistor and a resistive memory, wherein the lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source terminal of the NMOS transistor is connected to a source line, wherein: include: Set the first fixed voltage offset V offset1 and a second fixed voltage offset V offset2 ; Initialize the resistance state of the resistive memory to a high-resistance state using a reset operation; The source line voltage V SL Set to 0V; The voltage V corresponding to the logic value of the logic input P p and the first fixed voltage offset V offset1 , a gate voltage V is applied to the gate of the NMOS transistor gate =V p + V offset1 , complete the writing of the logical variable P; The voltage V corresponding to the logic value of the logic input Q q and a second fixed voltage offset V offset2 , a terminal voltage V is applied to the bit line of the resistive memory cell BL = V q + V offset2 , complete the writing of the logical variable Q; After the resistive switching memory device completes the resistive switching operation, the resistance state of the resistive switching memory after the resistance switching is read to obtain the logic value of the output Y.
4. A method for three-valued XOR logic operation in a VR type memory based on a resistive memory unit, wherein the resistive memory unit comprises an NMOS transistor and a resistive memory, wherein the lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source terminal of the NMOS transistor is connected to a source line, wherein: include: Initialize the resistance state of the resistive memory to a high-resistance state using a reset operation; The voltage V corresponding to the logic value of the logic input P p The voltage V corresponding to the logic value of the logic input Q q , a terminal voltage V is applied to the bit line of the resistive memory cell BL =max(V p , V q ), a voltage V is applied to the source line of the resistive memory cell SL =min(V p , V q ), complete the writing of logical variables P and Q; The gate voltage V is applied to the gate of the NMOS transistor. gate =V gate(SET) , where V gate(SET) To set the operating voltage; After the resistive switching memory device completes the resistive switching operation, the resistance state of the resistive switching memory after the resistance switching is read to obtain the logic value of the output Y.
5. A method for three-value XOR logic operation in a VR-type memory based on a resistive memory unit, wherein the resistive memory unit comprises an NMOS transistor and a resistive memory, wherein the lower electrode of the resistive memory is connected to the drain terminal of the NMOS transistor, the upper electrode of the resistive memory is connected to a bit line, the gate of the NMOS transistor is connected to a word line, and the source terminal of the NMOS transistor is connected to a source line, wherein: include: Initialize the resistance state of the resistive memory to a low resistance state using a set operation; The voltage V corresponding to the logic value of the logic input P p The voltage V corresponding to the logic value of the logic input Q q , a terminal voltage V is applied to the bit line of the resistive memory cell BL = min(V p , V q ), a voltage V is applied to the source line of the resistive memory cell SL = max(V p , V q ), complete the writing of logical variables P and Q; The gate voltage V is applied to the gate of the NMOS transistor. gate = V gate(RESET) , where V gate(RESET) The voltage for reset operation; After the resistive switching memory device completes the resistive switching operation, the resistance state of the resistive switching memory after the resistance switching is read to obtain the logic value of the output Y.
6. The logic operation method according to any one of claims 1 to 5, characterized in that: When the logic value of P is 2, the corresponding voltage V p For high voltage V p (HV); When the logic value of P is 1, the corresponding voltage V p For medium voltage V p (MV); When the logic value of P is 0, the corresponding voltage V p For medium and low voltage V p (LV); When the logic value of Q is 2, the corresponding voltage V q For high voltage V q (HV); When the logic value of Q is 1, the corresponding voltage V q For medium voltage V q (MV); When the logic value of Q is 0, the corresponding voltage V q For medium and low voltage V q (LV).
7. The logic operation method according to any one of claims 1 to 5, characterized in that: When the resistance state of the resistive memory is a high resistance state, the corresponding logic value of the output Y is 2; When the resistance state of the resistive memory is an intermediate resistance state, the corresponding logic value of the output Y is 1; When the resistance state of the resistive memory is a low resistance state, the corresponding logic value of the output Y is 0.
8. The logic operation method according to claim 7, characterized in that: When the resistance state of the resistive memory is at the level of 1000 kΩ, it corresponds to a high resistance state; When the resistance state of the resistive random access memory is at the 100 kΩ level, it corresponds to an intermediate resistance state; When the resistance state of the resistive random access memory is at the level of 10 kΩ, it corresponds to a low resistance state.