Test data storage method

Abstract

The invention discloses a test data storage method, and belongs to the technical field of chip production and manufacturing, and the test data storage method comprises the steps: providing a to-be-tested wafer, the to-be-tested wafer is provided with a plurality of to-be-tested crystal grains, and each to-be-tested crystal grain comprises a plurality of light-emitting channels; performing a wafer-level test on the to-be-tested wafer to obtain test data of the to-be-tested wafer; wherein the sequence of the wafer level test is that after all the light-emitting channels of one to-be-tested crystal grain are tested in sequence, the next to-be-tested crystal grain is switched; and storing the test data. Wherein the stored test data carries position labels of the light-emitting channels on the to-be-tested crystal grains to which the light-emitting channels belong. Therefore, under the condition of numerous chip channels, the wafer performance test data of each channel is associated with the position label of each channel on the to-be-tested crystal grain to be stored, so that the test data is clear and convenient to search, and meanwhile, the storage precision of the test data is also improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip production and manufacturing, and particularly relates to a method for storing test data. Background Art

[0002] A wafer is the initial material for semiconductor chip manufacturing, carrying all the technological processes of chip manufacturing. The main types are: GaAs (gallium arsenide), InGaAs (indium gallium arsenide), GaN (gallium nitride), InGaN (indium gallium nitride), AlInGaP (aluminum indium gallium phosphide). During semiconductor manufacturing, multiple dies are formed on the wafer (Wafer), that is, through a cutting process (such as dicing or laser cutting), the wafer is divided into individual dies. Dies usually appear as tiny rectangular or square thin slices, and their sizes vary depending on the application, ranging from a few millimeters to dozens of millimeters. A chip usually refers to a die after packaging. Common chips include 2DMA (Direct Memory Access, two-dimensional addressable array) two-dimensional addressable chips.

[0003] Perform back-end WT (Wafer Test) testing on the entire wafer, specifically, detect the electrical characteristics of each die on the wafer, such as power, etc., to ensure that the dies with qualified processes enter the packaging link. Perform back-end FT (Final Test) testing on the chip, specifically, conduct electrical connectivity testing, functional testing, parameter testing, etc. on the chip to screen out chips that meet the design specifications.

[0004] Whether testing the wafer or the chip, it is tested in units of channels. There are many channels on each chip, and a large amount of data will be generated for each channel. For example, the amount of data after spectral testing and LIV (Light-Current-Voltage) testing is very large. Then, in the case of a large number of channels, which data structure is used to store the test data so that the test data is clear and easy to search is a technical problem to be solved urgently. Summary of the Invention

[0005] The main technical problem to be solved by the present invention is how to improve the convenience of searching for test data in the case of a large number of channels on the wafer and the chip.

[0006] According to a first aspect, in one embodiment, a method for storing test data is provided, and the method includes: Provide a wafer to be tested, where there are multiple dies to be tested on the wafer to be tested, and each die to be tested includes multiple light-emitting channels; Perform wafer-level testing on the wafer to be tested to obtain the test data of the wafer to be tested; wherein, the order of wafer-level testing is to sequentially test all the light-emitting channels of one die to be tested and then switch to the next die to be tested; and Store the test data, where the stored test data is tagged with the positions of the respective light-emitting channels on the corresponding die under test.

[0007] According to the method for storing test data of the above embodiment, in the case of a large number of chip channels, by associating the wafer performance test data of each channel with the position tag of each channel on the corresponding die under test and then storing them, the convenience of searching for test data is further improved. Brief Description of the Drawings

[0008] Figure 1 It is a schematic flowchart of the method for storing test data provided by this embodiment; Figure 2 It is the identification bit of the chip direction provided by this embodiment; Figure 3 It is a schematic diagram of the data level after the FT test of the chip provided by this embodiment. Detailed Description of the Embodiment

[0009] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific embodiments. Similar elements in different embodiments are labeled with related similar element numbers. In the following embodiments, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid the core part of the present application being overwhelmed by excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and the general technical knowledge in the art.

[0010] In addition, the features, operations, or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be reordered or adjusted in an obvious manner by those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for clearly describing a certain embodiment and do not mean that they are necessary sequences, unless it is stated that a certain sequence must be followed.

[0011] The information association forms of conventional original test data at each stage are as follows: In the front-end test phase, the wafer has a unique wafer number information, represented by Wafer1, and the front-end test parameters are associated with the wafer form of Wafer1. In the back-end WT test phase, the WT test parameters are represented by the form of wafer number (Wafer2) + chip ID (die ID). That is, in the back-end WT test phase, the test data is associated with the wafer and a single chip. In the WT test phase, the wafer has not been cut yet, the actual object is in wafer form, and the test data is still associated with a specific single chip. In the back-end FT test phase, the FT test parameters are represented by the form of package batch number (PackageID) + chip ID (ChipID). In the FT test phase, the wafer has been cut, the actual object is a single chip, and the test data is associated with the package batch number and chip ID. There is a clear correspondence between Wafer1, Wafer2, and PackageID in the front-end, WT, and FT phases. All the Die IDs or Chip IDs that appear indicate the coordinate information of the chip on the wafer. For example, Die ID = (123, 456) means that the X coordinate of the die on the wafer is 123 and the Y coordinate is 456.

[0012] In the front-end testing phase, the information contained in the test data is shown in Table 1: In the WT test phase, the information contained in the test data is shown in Table 2: In the FT test phase, the information contained in the test data is shown in Table 3: The coordinate information of the chip coordinates in the packaging stage is the Chip ID, and the Chip ID in the packaging stage must correspond to the die ID in the wafer stage. In other words, the wafer die ID can be found through the packaging Chip ID.

[0013] The existing WT and FT data formats mainly associate test parameters through "wafer number + chip coordinates". For two-dimensional 2DMA chips, there are hundreds of channels on a chip, and each channel generates a large amount of data, such as spectral testing and LIV testing, and the amount of data is very large. When performing front-end and back-end tests, the 2DMA channels are tested in turn by switching switches, and each channel generates separate measurement data. However, it is difficult to associate 2DMA test data with the existing data format, or the data format will be very complicated when the existing data format is used to associate 2DMA test data. So, when there are many channels, what kind of data structure should be used to store the original test data so that it is clear and easy to view, and it can be associated with the data of each link is a technical problem that needs to be solved urgently.

[0014] To solve the above technical problems, the present application proposes that in the WT test session, the physical object of 2DMA is in the form of a wafer, and the data of each link in the WT test is associated in the form of "wafer serial number + chip coordinates + channel coordinates". In the WT test session, the object to be tested is a wafer, and the test data has been accurate to the channel level. In the FT test session, the data of each link in the FT test is associated in the form of "package batch number + chip coordinates + channel coordinates". In the FT test session, the object to be tested is a single chip, and the test data has also been accurate to the channel level. In this way, storing the test data in the data format at the channel level can make the original test data clear, easy to view, and establish an association relationship with the data of each link.

[0015] Please refer to Figure 1 , Figure 1 FIG. is a schematic flow chart of a method for storing test data provided by this embodiment. This method is applied to a wafer. The method specifically includes the following steps S101-S103: S101. Provide a wafer to be tested, where there are multiple grains to be tested on the wafer to be tested, and each grain to be tested includes multiple light-emitting channels.

[0016] S102. Perform wafer-level testing on the wafer to be tested to obtain the test data of the wafer to be tested; wherein, the order of the wafer-level testing is to test all the light-emitting channels of one grain to be tested in sequence and then switch to the next grain to be tested.

[0017] In this embodiment, performing wafer-level testing on the wafer to be tested includes: Performing multiple different item tests on each light-emitting channel of the same grain to be tested to obtain the test data of each light-emitting channel under different item tests.

[0018] That is to say, performing wafer-level testing on the wafer to be tested includes: performing tests on multiple light-emitting channels of multiple grains to be tested on the wafer to be tested for multiple test items associated with wafer-level testing, so that the test data of the wafer to be tested for each channel can be obtained.

[0019] It should be noted that the wafer to be tested includes, but is not limited to, silicon wafers, SOI wafers, and compound semiconductor wafers.

[0020] It should be noted that performing wafer-level testing on the wafer to be tested can be performing back-end WT (Wafer Test) testing on the entire wafer, that is, performing tests on multiple light-emitting channels of multiple grains to be tested on the wafer to be tested for multiple test items associated with back-end wafer testing. For example, electrical performance testing is used to screen out chips that do not meet the specification requirements during the production process, so as to judge the yield of the wafer.

[0021] It should be noted that WT tests usually include the verification of voltage, current, timing, and functions, such as threshold voltage, on-resistance, source-drain breakdown voltage, gate-source-drain current, drain-source-drain current, etc. These test items can be used to judge the yield rate of wafers.

[0022] It should be noted that the test data of the wafer to be tested can be the electrical performance data of each channel (such as circuit connection channels, data transmission channels, etc.) obtained after the wafer to be tested undergoes performance tests (such as wafer tests, i.e., WT tests).

[0023] S103. Store the test data; among them, the stored test data carries the position labels of each light-emitting channel on the corresponding die to be tested.

[0024] It should be noted that the position labels of each light-emitting channel on the corresponding die to be tested reflect the position of the light-emitting channel on the die to be tested.

[0025] In this embodiment, the stored test data also carries the position coordinates of the die to be tested and / or the wafer number identification of the wafer to be tested; among them, the position coordinates of the die to be tested reflect the position of the die to be tested on the wafer to be tested.

[0026] In this embodiment, for the test data of the wafer to be tested of each light-emitting channel, by numbering according to the position labels of each light-emitting channel on the corresponding die to be tested, the position coordinates of the die to be tested, and the wafer number identification of the wafer to be tested, the unique number of the test data of each light-emitting channel can be obtained, and this number is unique to clarify which channel of which die on which wafer the test data corresponds to.

[0027] In this embodiment, the test data of the wafer to be tested includes the test sub-data of each test item of each light-emitting channel.

[0028] It should be noted that the test sub-data includes but is not limited to voltage, current, resistance, capacitance, electrostatic immunity, power consumption, signal integrity, logic function, timing, interface function.

[0029] In this embodiment, the stored test data also carries the project test label.

[0030] In this embodiment, for the test sub-data of the wafer to be tested of each test item of each light-emitting channel, the test sub-data of the wafer to be tested is associated with the project test label, the position label of the light-emitting channel on the corresponding die to be tested, the position coordinates of the corresponding die to be tested, and the wafer number identification of the corresponding wafer to be tested and then stored.

[0031] It should be noted that associating the test sub-data of the wafer under test with the project test label, the position label of the light-emitting channel on the corresponding die under test, the position coordinates of the corresponding die under test, and the wafer number identifier of the corresponding wafer under test means numbering the test sub-data of the light-emitting channel corresponding to the test project with the project test label, the position label of the light-emitting channel on the corresponding die under test, the position coordinates of the corresponding die under test, and the wafer number identifier of the corresponding wafer under test, and this number is unique to clarify which channel on which die of which wafer the test sub-data corresponds to. Store the associated test sub-data for subsequent analysis, query, and traceability.

[0032] It should be noted that each wafer under test has a unique wafer number identifier to accurately identify and trace it in various links such as manufacturing, testing, and packaging. Specifically, through this wafer number identifier, the production history, test data, packaging information, etc. of the wafer can be traced, which is helpful for quality control and problem troubleshooting.

[0033] It should be noted that the wafer number identifier of the wafer under test usually contains the following information: the foundry identifier, which is used to represent the manufacturer or foundry of the wafer; the production batch number, which is used to represent the production batch of the wafer and helps to trace the production situation and quality of wafers in the same batch; the wafer number, and in the same production batch, each wafer has a unique number to distinguish different wafers. The wafer number identifier may also contain other information, such as the production date, wafer size, process node, etc.

[0034] It should be noted that each die under test on the wafer under test has unique position coordinates, which reflect the position of the die on the wafer under test. For example, in the wafer testing stage, by obtaining the position coordinates of the die under test, precise probe testing can be performed on each die under test on the wafer under test to ensure that the quality and performance of the die meet the specification requirements. In the packaging stage, this position information helps to accurately place the die under test on the lead frame or substrate to ensure good electrical and mechanical connections between the chip and the substrate.

[0035] It should be noted that each channel on each die under test on the wafer under test has a unique position label. This position label reflects the position of the channel on the corresponding die. For example, in the wafer testing stage, this position label helps to accurately test each channel to ensure its normal function. During the packaging process, this position label helps to accurately place the die on the lead frame or substrate to achieve good electrical and mechanical connections.

[0036] It should be noted that after associating the test data of the wafer under test in the light-emitting channel with its position label and storing it, the test data can be made clear and easy to search. At the same time, the storage level of the test data is increased from the die level to the channel level, thereby improving the storage accuracy of the test data.

[0037] In this embodiment, each light-emitting channel is numbered to obtain an index value corresponding to each light-emitting channel; the index values of each light-emitting channel are arranged in a preset order to construct a channel index table; wherein, the channel index table has a corresponding index relationship with the stored test data.

[0038] It should be noted that the channel index table includes the unique index value of each light-emitting channel. Through the index value in the channel index table, the information of each channel can be quickly searched and accessed, which is helpful for chip testing, fault diagnosis, and performance optimization. It should be noted that by numbering each light-emitting channel, an index value corresponding to each light-emitting channel can be obtained, and then the index values of each light-emitting channel are arranged in a preset order (for example, from bottom to top, from left to right) to construct a channel index table. Since the channel index table has a corresponding index relationship with the stored test data, the position of each light-emitting channel can be accurately located according to the channel index table, so as to find the test data stored in each light-emitting channel.

[0039] In practical applications, in the WT test session, the information contained in the wafer performance test data is shown in Table 4: In Table 4, WaferID2, die ID, and ChannelID represent the wafer ID label, die position coordinates, and channel coordinates (position label) respectively, and DATA1~DATAn represent the test data of test items 1 to test items n for the specific wafer ID, specific die, and specific channel. That is, the first three columns are physical objects, and test items 1~test items n are the test data corresponding to the first three physical objects. Among them, the die coordinates are 1015, that is, the coordinates of this die on the wafer are the 10th row and the 15th column. WaferID2 is W123456-01, that is, the LOT number of this wafer is W123456, and 01 is the first wafer of this LOT. ChannelID is 43, that is, the coordinates of this channel are 43.

[0040] In practical applications, the encoding of the channel coordinates is taken from the encoding form in Table 5, that is, the channel index table is shown in Table 5: Table 5 numbers all the light-emitting channels of all the dies under test on the wafer under test and uses its index value as the position label of the corresponding light-emitting channel.

[0041] It should be noted that, for example, Figure 2 each chip has an identification bit for the correct direction. For example, during WT and FT tests, the chips are aligned with this identifier, and the aligned die can be searched according to the channel number.

[0042] In this embodiment, column indexing and row indexing can also be performed on all the light-emitting channels of all the die to be tested on the wafer to be tested, and the column index and row index of the same light-emitting channel are combined into the position tag corresponding to this light-emitting channel, as shown in Table 6: It should be noted that the test data accuracy of this application is accurate to the channel level because in 2DMA tests, oxidation aperture tests, LIV (Light-Current-Voltage) tests, NF (Near Field) tests, FF (Far Filed) tests, and reverse voltage tests are all performed in units of channels. That is to say, the purpose of making the data structure of this application accurate to the channel level is the same as the requirement of accurate channel level in actual 2DMA tests.

[0043] It should be noted that this application uses the position tag (channel coordinates) as the associated information for WT tests and FT tests in order to convert the level of a single test data from the chip level to the channel level, so as to accurately determine the data storage dimension to the channel level and achieve the purpose of optimizing the data structure.

[0044] In this embodiment, before performing wafer-level tests on the wafer to be tested, the method further includes: Individually encapsulating multiple die to be tested on the wafer to be tested to obtain multiple chips to be tested; performing wafer-level tests on the wafer to be tested means performing wafer-level tests on each chip to be tested on the wafer to be tested to obtain test data of the chips to be tested.

[0045] It should be noted that the chips to be tested include but are not limited to logic chips, memory chips, analog chips, digital chips, microprocessor chips, graphics processor chips, sensor chips, and communication chips. This embodiment is described by taking a two-dimensional addressable chip as an example.

[0046] It should be noted that individually encapsulating multiple die to be tested on the wafer to be tested means wrapping a single die to be tested (also called a chip die) on the wafer to be tested in a supporting frame or housing to protect the chip and provide an interface for connection to an external circuit.

[0047] In practical applications, after encapsulating multiple die to be tested on the wafer to be tested, a packaged chip (Chip) is obtained. The correspondence table between the Chip ID of this chip and the wafer die ID is shown in Table 7: In this embodiment, the stored test data also carries the package number of the to-be-tested wafer to which it belongs and the package position information of the to-be-tested chip to which it belongs.

[0048] In this embodiment, the test data of the to-be-tested chip includes: test sub-data of each test item for each light-emitting channel.

[0049] Storing the test data includes: Storing the test sub-data; wherein, the stored test sub-data carries an item test label, a position label of each light-emitting channel on the to-be-tested chip to which it belongs, the package position information of the to-be-tested chip to which it belongs, and the package number of the to-be-tested wafer to which it belongs.

[0050] It should be noted that the package number of the to-be-tested wafer to which a light-emitting channel belongs refers to the unique number corresponding to the packaged to-be-tested chip or the package batch. This number is usually used to track and manage the packaged to-be-tested chips. Specifically, through this package number, the production history, test data, package information, etc. of the wafer can be traced, which helps with quality control and problem troubleshooting.

[0051] It should be noted that the package number of the to-be-tested wafer to which a light-emitting channel belongs usually contains the following information: a package type identifier. The number may contain a code for the package type, such as DIP (Dual In-line Package), SOP (Small Outline Package), QFP (Quad Flat Package), BGA (Ball Grid Array Package), etc. This package type identifier is used to indicate the package form adopted by the chip.

[0052] It should be noted that the package number of the to-be-tested wafer and the wafer number identifier of the to-be-tested wafer exist independently, but both are used to track and identify chips in the semiconductor manufacturing process.

[0053] It should be noted that the package position information of the to-be-tested chip refers to the information used to identify the specific position of the chip on the package carrier (such as a lead frame, a substrate, or a package housing) during the packaging process of the to-be-tested chip. Each to-be-tested chip has a unique package position information. This package position information helps to track the position and status of the chip during the production process, ensuring the smoothness and efficiency of the production process; it also helps with quality inspection and fault troubleshooting for chips at specific positions; and it also helps to quickly locate and replace a faulty chip when the chip fails or needs to be replaced.

[0054] It should be noted that each light-emitting channel of each to-be-tested chip has a unique position label. This position label reflects the position of the light-emitting channel on the to-be-tested chip. During the wafer test stage, this position label helps to quickly locate the fault point and improve the repair efficiency.

[0055] It should be noted that the light-emitting channels of the chip under test include but are not limited to microchannels, memory channels, data buses and address buses, and I / O interfaces. Among them, the microchannels are located in the internal structure of the chip and are usually designed as a fine pipeline network running through the entire chip. In a memory chip, multiple memory channels may consist of multiple memory modules with the same capacity, speed, and timing. The data bus and the address bus are between the CPU and the memory and I / O devices, and are used to transmit data information and address information. The I / O interface is the external interface of the chip and is used for data transmission and communication with external devices or systems.

[0056] It should be noted that the test sub-data of the chip under test includes but is not limited to current, electrostatic immunity, power consumption, logic function, interface function, package integrity, and pin coplanarity.

[0057] It should be noted that the test sub-data of the stored chip under test with the project test label, the position label of each light-emitting channel on its corresponding chip under test, the package position information of the corresponding chip under test, and the package number of the corresponding wafer under test means that the test sub-data of the channel corresponding to the test item is numbered with the project test label, the position label of each light-emitting channel on its corresponding chip under test, the package position information of the corresponding chip under test, and the package number of the corresponding wafer under test, and this number is unique, so as to clarify which chip's which channel the test sub-data corresponds to, and fast query and retrieval can be realized.

[0058] In this embodiment, the package number of the wafer under test to which the chip under test belongs is associated with and stored with the wafer number identification of the wafer under test, and the package position information of the chip under test is associated with and stored with the position information of the die to which the chip under test belongs before packaging.

[0059] It should be noted that associating the package number of the wafer under test to which the chip under test belongs with the wafer number identification of the wafer under test means establishing an association relationship between the package number and the wafer number identification. In this way, when there are quality problems with the chip under test, the wafer to which the problem chip belongs and the specific situation during the manufacturing process of the wafer can be quickly traced through this association information. Through this association information, the output situation of each wafer can also be understood, including the number and quality of the chips. This association information can be used as one of the unique identity identifiers of the chip for anti-counterfeiting and traceability.

[0060] It should be noted that the packaging position information of the chip under test is associated with the position information of the die to which the chip under test belonged before packaging, that is, an association relationship is established between the packaging position information and the position information of the die under test. In this way, when a quality problem or failure occurs in the chip under test, the die to which the problem chip belongs and its position on the wafer can be quickly traced through this association information. Through this association information, the position of each die after packaging can be understood, as well as the impact of the packaging process on the die position. This association information can also be used as one of the unique identity identifiers of the chip for anti-counterfeiting and traceability.

[0061] In this embodiment, the test data of the wafer of the light-emitting channel of the die under test is associated with the test data of the light-emitting channel of the chip under test obtained after packaging the die under test, to obtain the associated data of the light-emitting channel; the performance of the chip under test is evaluated according to the associated data of each light-emitting channel of the chip under test.

[0062] It should be noted that by matching and associating the test data of the wafer of the light-emitting channel and the test data of the chip under test according to the position label of the light-emitting channel, the associated data of the light-emitting channel can be obtained.

[0063] It should be noted that by comparing the test data of the wafer under test and the test data of the chip under test, the performance changes of the light-emitting channel before and after packaging can be analyzed. For example, the differences in parameters such as the resistance, capacitance, and transmission speed of the channel before and after packaging can be compared to evaluate the impact of the packaging process on the channel performance. For example, if a performance problem occurs in the chip after packaging, the problem location can be quickly located through the associated data. For example, if the test data of a certain light-emitting channel is abnormal after packaging, it can be judged whether the problem is introduced by the packaging process or the die itself by comparing the test data of the wafer under test and the test data of the chip under test.

[0064] In practical applications, as Figure 3 shown, in the FT test session, the physical object of 2DMA is in the form of a wafer, and the data of each link in the FT test is associated in the form of "packaging batch number + chip coordinates + channel coordinates". In the FT test session, although the object under test is a single chip, the test data has been accurate to the channel level.

[0065] In practical applications, in the FT test session, the information included in the chip performance test data is shown in Table 8: Encapsulation batch number Chip coordinates Channel coordinates Test item 1 Test item 2 … Test item n PackageID Chip ID ChannelID DATA1 DATA2 … DATAn 230620 - F03 - 002 - PKG56789 2116 43 8.6 12.8 15.9 The chip coordinates correspond to the packaging position information of the chip to which the test channel belongs; the packaging batch number corresponds to the packaging number of the wafer to which the test channel belongs.

[0066] This embodiment provides a method for storing test data. A wafer to be tested is provided, and there are multiple die to be tested on the wafer to be tested. Each die to be tested includes multiple light-emitting channels. A wafer-level test is performed on the wafer to be tested to obtain the test data of the wafer to be tested. Among them, the order of the wafer-level test is to sequentially test all the light-emitting channels of one die to be tested and then switch to the next die to be tested. And the test data is stored. Among them, the stored test data is tagged with the position of each light-emitting channel on the die to which it belongs. In this way, in the case of a large number of chip channels, by associating the wafer performance test data of each channel with the position tag of each channel on the die to which it belongs and then storing it, the test data is made clear and easy to find, and at the same time, the storage accuracy of the test data is improved.

[0067] Those skilled in the art can understand that all or part of the functions of the above methods can be implemented in a hardware manner or in a computer program manner. When all or part of the functions in the above embodiments are implemented in a computer program manner, the program can be stored in a computer-readable storage medium. The storage medium can include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc. The above functions are realized by a computer executing the program. For example, the program is stored in the memory of the device, and when the processor executes the program in the memory, the above all or part of the functions can be realized. In addition, when all or part of the functions in the above embodiments are implemented in a computer program manner, the program can also be stored in a storage medium such as a server, another computer, magnetic disk, optical disk, flash drive or mobile hard disk, downloaded or copied and saved to the memory of the local device, or the system of the local device is updated. When the processor executes the program in the memory, the above all or part of the functions in the above embodiments can be realized.

[0068] The above uses specific examples to elaborate on the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art of the present invention, according to the idea of the present invention, several simple deductions, deformations or substitutions can also be made.

Claims

1. A method for storing test data, characterized in that, The method includes: providing a wafer to be tested, where there are multiple die to be tested on the wafer to be tested, and each die to be tested includes multiple light-emitting channels; performing wafer-level testing on the wafer to be tested to obtain test data of the wafer to be tested; wherein, the order of the wafer-level testing is to sequentially test all the light-emitting channels of one die to be tested and then switch to the next die to be tested; and storing the test data; wherein, the stored test data carries position labels of the respective light-emitting channels on the die to which they belong.

2. The method according to claim 1, characterized in that, The stored test data also carries the position coordinates of the die to be tested and / or the wafer lot number identification of the wafer to be tested; wherein, the position coordinates of the die to be tested reflect the position of the die to be tested on the wafer to be tested.

3. The method according to claim 2, characterized in that, Performing the wafer-level testing on the wafer to be tested includes: performing multiple different item tests on each of the light-emitting channels of the same die to be tested to obtain test data of each of the light-emitting channels under different item tests.

4. The method according to claim 3, characterized in that, The stored test data also carries item test labels.

5. The method according to claim 1, characterized in that, Before performing the wafer-level testing on the wafer to be tested, the method further includes: encapsulating the multiple die to be tested on the wafer to be tested respectively to obtain multiple chips to be tested; Performing the wafer-level testing on the wafer to be tested is to perform wafer-level testing on each of the chips to be tested on the wafer to be tested to obtain test data of the chips to be tested.

6. The method according to claim 5, characterized in that, The stored test data also carries the package number of the wafer to which it belongs.

7. The method according to claim 6, characterized in that, The stored test data also carries the package position information of the chip to which it belongs.

8. The method according to claim 5, characterized in that, The test data of the chip to be tested includes: test sub-data of each test item of the respective light-emitting channels; Storing the test data includes: storing the test sub-data; wherein, the stored test sub-data carries item test labels, position labels of the respective light-emitting channels on the chip to which they belong, the package position information of the chip to which it belongs, and the package number of the wafer to which it belongs.

9. The method according to claim 8, characterized in that, The method further includes: associating the test data of the light-emitting channels of the die to be tested of the wafer to be tested with the test data of the light-emitting channels of the chip to be tested obtained after encapsulating the die to be tested to obtain associated data of the light-emitting channels; evaluating the performance of the chip to be tested according to the associated data of the respective light-emitting channels of the chip to be tested.

10. The method according to claim 1, characterized in that, The method further includes: numbering the respective light-emitting channels to obtain an index value corresponding to each light-emitting channel; arranging the index values of the respective light-emitting channels in a preset order to construct a channel index table; wherein, the channel index table has a corresponding index relationship with the stored test data.

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