A 3D IC MBIST Testing Method Based on Intelligent Algorithms

Abstract

The present invention belongs to the technical field of integrated circuit testability design, and discloses a 3D IC MBIST test method based on an intelligent algorithm. It performs isomorphic grouping by parsing the spatial coordinates, hierarchical attribution, and multi-dimensional attributes of memories; establishes a three-dimensional layout relationship based on an improved interlayer distance model; uses a hierarchical clustering algorithm to merge memory clusters according to spatial proximity, and constructs a grouping architecture with a minimized number of controllers; combines a multi-objective simulated annealing algorithm to establish a dynamic test scheduling model, and optimizes the test time under power consumption constraints through a temperature attenuation mechanism. The method of the present invention performs three-dimensional collaborative optimization of spatial layout, timing constraints, and power consumption budget, solves the contradiction between area overhead and test efficiency faced by traditional memory built-in self-test schemes in 3D ICs, effectively copes with the stacked layer test challenges under limited test temperature conditions, and significantly improves the test economy and reliability of heterogeneous integrated chips.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit testability design, and in particular relates to a 3D IC MBIST test method based on an intelligent algorithm. Background Art

[0002] With the increasing complexity of modern integrated circuit design, the widespread use of embedded memory has made memory testing costs account for a significant proportion of integrated circuit manufacturing costs. To meet this challenge, built-in self-test technology has become a mainstream solution. Its core mechanism is to generate test vectors and verify memory functions through a built-in MBIST controller. However, this technology will introduce additional chip area overhead due to auxiliary circuits such as controllers. This contradiction is particularly prominent in the design of three-dimensional integrated circuits (3D ICs). Since 3D ICs require pre-bond testing (Pre-bond) and post-bond testing before stacking, and each test stage is limited by power consumption, and post-stack testing is limited by the number of through-silicon vias (TSVs), traditional BIST solutions face a double dilemma in terms of test scheduling flexibility and resource optimization.

[0003] Built-In Self-Test (BIST) is a built-in test mechanism of integrated circuits that allows memory to perform self-test without relying on external test equipment. BIST can effectively improve the efficiency and reliability of memory production testing and is usually used in large-scale integrated circuits (such as DRAM, SRAM, etc.). The memory built-in self-test (BIST) process includes two key parts: memory grouping and scheduling. Memory grouping divides memory cells or modules into several groups according to function, structure or test requirements to improve test efficiency and parallelism. Each group is tested independently, and a suitable test method can be selected according to the characteristics of the memory cell; memory scheduling reasonably arranges the test order and execution timing of each group according to the priority of the test task and the constraints of hardware resources. In the scheduling process, it is necessary to comprehensively consider the test power consumption, temperature, parallel execution of the test, and resource management of the task to ensure that the test process is efficient and smooth. By optimizing grouping and scheduling, memory BIST can effectively shorten the test time, improve the test coverage, and reduce production costs.

[0004] DFT engineers need to balance the number of MBIST controllers and the complexity of the test network while meeting the test coverage. On the one hand, intelligent grouping is needed to reduce the redundant deployment of the test circuit. On the other hand, a dynamic scheduling strategy needs to be constructed to reduce the test time under constraints, so as to achieve the optimal trade-off between test time and area overhead. This multi-objective optimization process is essentially a three-dimensional collaboration of spatial layout, timing constraints, and power consumption budget. Although existing research has reduced the test time through memory grouping and test scheduling optimization, the test of three-dimensional structured memories is restricted by test power consumption and has problems such as high test temperature, making it difficult to obtain an optimal grouping method and test order. Therefore, how to reduce the number of groups to reduce the area overhead and how to adjust the test order to reduce the test time are also difficult problems to be solved urgently. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a 3D IC MBIST test method based on an intelligent algorithm, which optimizes the memory test process of 3D ICs, reduces the test groups, thereby reducing the circuit area overhead, and adjusts the test order to reduce the test time.

[0006] A 3D IC MBIST test method based on an intelligent algorithm according to the present invention includes the following steps:

[0007] Step 1: Extract the spatial coordinate information of the memories and analyze the hierarchical attribution of each memory;

[0008] Step 2: Extract the multi-dimensional attributes of each memory, and divide the memories into homogeneous sets based on the attribute consistency of the memories;

[0009] Step 3: Calculate the inter-layer distance between each memory and other memories based on an improved inter-layer distance model;

[0010] Step 4: Adopt a hierarchical clustering algorithm, and group the memories and allocate shared BIST controllers based on the inter-layer distance of the memories;

[0011] Step 5: Use a multi-objective simulated annealing algorithm to define the constraint conditions and optimization objective function of the memory test task, and solve to obtain the minimum test time.

[0012] Further, step 1 is specifically: read in the memory design.v file and the memory physical location.def file, parse the 3D IC physical layout file, obtain the memory coordinates and hierarchical attribution information, and model the three-dimensional distribution of the memories.

[0013] Further, step 2 is specifically as follows: Read the.mem power domain.upf file, the.clk file of the clock domain, the.lvlib file of the address bit width test algorithm, read the memory constraints, and the.spec file of the TSV constraints, and extract the multi-dimensional attributes of the memory; classify based on the multi-dimensional attributes of the memory to form a set of homogeneous memories.

[0014] Further, in step 3, the improved interlayer distance model is:

[0015] ,

[0016] where θ is the interlayer distance conversion coefficient, , Z is the number of intervening layers; X i , Y i represents the spatial coordinates of memory i, and X j , Y j represents the spatial coordinates of memory j.

[0017] Further, step 4 is specifically as follows: Calculate the distances between all memories, and sequentially select two clusters with the smallest distance for merging; during each merging process, determine whether the total power consumption after merging exceeds the maximum power consumption requirement; if so, abandon the merging; if not, perform the merging operation and update the distance of the new cluster.

[0018] Further, in step 5, the objective function and constraints are defined as follows:

[0019] Objective function: , where C is the minimized test time;

[0020] Power consumption constraint: , the power consumption P of the memories under parallel testing shall not exceed the given maximum power consumption P max ,

[0021] Temperature constraint: , the temperature T of the memories under parallel testing shall not exceed the given maximum chip test temperature T max ;

[0022] where n is the total number of memories.

[0023] Further, in step 5, the solution to the objective function is as follows:

[0024] Step 5-1: Randomly generate a test schedule for the memories, and set the initial temperature , the cooling rate and the maximum number of iterations ;

[0025] Step 5-2: Randomly change the test order of the memories to generate a neighborhood solution, compare the test time of the new solution with that of the current solution. If the test time obtained by the new neighborhood solution is less than that of the current solution, accept this solution; otherwise, accept this solution with a certain probability. The probability calculation formula is as follows:

[0026] ,

[0027] wherein, is the test time of the neighborhood solution, is the test time of the current solution, is the current temperature;

[0028] Step 5-3: For each new solution, check whether the power consumption and temperature constraints are satisfied; if the constraints are not satisfied, reject it; if the maximum number of iterations is reached, or when the temperature T drops to the preset threshold, the algorithm terminates and outputs the optimal solution, that is, the solution that minimizes the test time under the condition of satisfying the power consumption and temperature constraints.

[0029] The beneficial effects of the present invention are as follows: In view of the special requirements of 3D ICs and heterogeneous integrated chips, the present invention establishes a three-dimensional layout relationship based on an improved interlayer distance model, calculates the interlayer distance of memories, uses a hierarchical clustering algorithm to merge memory clusters according to spatial proximity, and constructs a grouping architecture that minimizes the number of controllers; the present invention groups memories in combination with spatial distribution, reduces the deployment of MBIST controllers and test networks, thereby effectively reducing the chip area overhead, reducing the number of controllers and the complexity of the test circuit, being able to arrange test tasks more reasonably, reducing redundant tests, reducing the test time, and helping to save the cost of chip manufacturing. The present invention combines a multi-objective simulated annealing algorithm to establish a dynamic test scheduling model, optimizes the test time under power consumption constraints through a temperature decay mechanism, provides a flexible phased optimization method, enables the memory test process to be dynamically adjusted according to different constraint conditions in practical applications, and has strong adaptability and flexibility. The present invention can ensure that the test task is completed under the condition of satisfying the power consumption and temperature constraints through an accurate power consumption and temperature control mechanism, and avoids hardware damage or performance degradation caused by too high power consumption and temperature. The method of the present invention innovatively performs three-dimensional collaborative optimization of spatial layout, timing constraints and power consumption budget, supports adaptive test order adjustment and dynamic evaluation of neighborhood solutions, effectively copes with the stacked test challenges under the condition of limited test temperature, significantly improves the test economy and reliability of heterogeneous integrated chips, and is applicable to more complex integrated circuit designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic flow chart of the method of the present invention;

[0031] Figure 2This is the architecture diagram of the memory test based on the IEEE1687 protocol in the embodiment of the present invention;

[0032] Figure 3 It is a schematic diagram for reading multi-dimensional attributes to divide homogeneous sets;

[0033] Figure 4 It is a schematic diagram of the hierarchical clustering algorithm;

[0034] Figure 5 It is a schematic diagram of grouping 3D IC memories divided based on the hierarchical clustering algorithm;

[0035] Figure 6 It is a diagram for defining the test scheduling optimization task;

[0036] Figure 7 It is a flowchart of the MBIST test. Detailed implementation manners

[0037] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to specific embodiments in conjunction with the accompanying drawings.

[0038] As Figure 1 shown, a 3D IC MBIST test method based on an intelligent algorithm according to the present invention includes the following steps:

[0039] Step 1: Read in the memory design.v file and the memory physical location.def file, parse the 3D IC physical layout file, extract the spatial coordinate information of the memory, and parse the hierarchical attribution of each memory;

[0040] Step 2: Read in the memory power domain.upf file, the clock domain.clk file, the address bit width test algorithm.lvlib file, read the memory constraints, and the TSV constraints.spec file, extract the multi-dimensional attributes of each memory, including the power domain, the clock domain, the address bit width, and the test algorithm, etc.; according to the attribute consistency of the memory, divide the memory into homogeneous sets; memories with different power domains, clock domains, address bit widths, or test algorithms cannot be divided into the same controller group;

[0041] Step 3: Based on the improved inter-layer distance model, calculate the inter-layer distance between each memory and other memories; the improved inter-layer distance model is:

[0042] ,

[0043] where θ is the inter-layer distance conversion coefficient, , Z is the number of intervening layers; X i , Y i represents the spatial coordinates of memory i, X j , Yj Represent the spatial coordinates of memory j;

[0044] Step 4: Use the hierarchical clustering algorithm (in a bottom-up manner) to group the memories, and gradually merge similar memory clusters; based on the distance between memories, select the most similar clusters for merging until the maximum power consumption requirement is met, group the memories and allocate shared BIST controllers;

[0045] Step 5: Use the multi-objective simulated annealing algorithm to define the constraint conditions and optimization objective function of the memory test task, and solve it to obtain the minimum test time.

[0046] Among them, in step 5, initialize the algorithm parameters, define the neighborhood structure and acceptance criterion. Randomly generate the test schedule of the memories, and set the initial temperature , cooling rate and the maximum number of iterations ; generate neighborhood solutions by changing the test order of the memories, compare the test times of the new solution and the current solution, and select the better solution; for solutions that do not meet the power consumption and temperature constraints, reject the solution.

[0047] In each iteration process, update the temperature according to the set cooling rate: , is the updated temperature, is the current temperature; if the maximum number of iterations is reached or the temperature T drops to a certain minimum value (i.e., the preset value), the algorithm terminates; output the optimal solution, that is, the solution that minimizes the test time under the premise of meeting the power consumption and temperature constraints.

[0048] The method of the present invention can effectively reduce the number of groups of 3D IC MBIST controllers, thereby reducing the chip area overhead, effectively optimizing the test schedule, and reducing the test time under the constraints of power consumption and temperature.

[0049] The method of the present invention is based on the memory built-in self-test standard structure of IEEE1687. As Figure 2As shown, the MBIST architecture consists of multiple key components, including the Segment Insertion Bit (SIB), the bist access port (BAP), the Controller, and the connected Memory. They work together to complete the self-test task of the memory cells. The SIB is responsible for coordinating the work among various components to ensure the smooth transmission of data and control signals; the BAP is responsible for generating test patterns and data, executing the test tasks, and feeding back the test results to the controller; the controller is the core of the MBIST system, generating the test addresses, data, and control signals for the memory cells and passing them to the memory; the memory receives these control signals, executes the test, and returns the output data to the controller for comparison and analysis. Multiple memories can share one MBIST controller, thus improving the test efficiency and reducing the area and power consumption. Through this collaborative work, MBIST can effectively detect faults in the memory cells and improve the reliability and quality of the chip. In the existing design, a single MBIST controller can control multiple memory cells, thus optimizing the area and power consumption of the chip. Since the MBIST circuit is an auxiliary test circuit, theoretically, its use should be minimized as much as possible to save chip area and improve the design efficiency; however, how to effectively plan and group the memory cells distributed at different positions on the chip and allocate them to different MBIST controllers is a complex design problem that requires comprehensive consideration of multiple factors, such as area, test power consumption, timing requirements, and the structural characteristics of the memory; memories with different parameters such as clock domain, power domain, and test algorithm cannot be tested using the same controller, such as Figure 3 shown, the memory cells of the 3D IC are partitioned according to these different parameters.

[0050] There are significant differences in the structure, performance, and connection method between three-dimensional integrated circuits and two-dimensional integrated circuits. Two-dimensional integrated circuits usually arrange all circuit elements and memory cells in a planar manner on the same layer and connect them through metal interconnections, while 3D ICs achieve high-speed connections between different layers by vertically stacking multiple chips or functional layers and using TSV technology. The TSV technology enables the memory cells of different layers to be directly connected through tiny vias that penetrate the silicon wafer vertically, thus achieving more efficient data transmission. In contrast, in 2D ICs, the memory and the controller need to be interconnected through long metal lines, resulting in increased signal transmission delay and power consumption. In 3D ICs, since the memory cells are connected through TSVs, multiple memory layers can operate and share the same controller for management, which not only reduces the number of control circuits but also decreases the chip area and power consumption, improving the overall system performance and response speed. However, it is necessary to define the distance between the memories across different layers to avoid timing problems caused by too far physical positions; therefore, the distance between memory i and memory j is defined , where θ is the interlayer distance conversion coefficient (θ≥1), and Z is the number of intervening layers (for example, if layer0 and layer1 differ by one layer, Z = 1); and since the three-dimensional stacked chip adopts a multi-layer stacking design, the dense stacking between the chips of each layer limits the heat dissipation channels, resulting in heat being more likely to accumulate inside the chip, thereby affecting the working stability and performance of the chip. To effectively control and manage the temperature of the chip and avoid test failures or damages caused by overheating, it is necessary to add a maximum test temperature limit to the memory scheduling.

[0051] Such as Figure 4 As shown, in the bottom-up hierarchical clustering process, each storage unit is initially regarded as an independent cluster, that is, each storage unit occupies a cluster separately. First, calculate the distances between all storage units, and select two clusters with the smallest distance for merging; when merging, it is necessary to check the total power consumption of the newly formed cluster: , if the total power consumption of the new cluster exceeds the power consumption constraint pre-bond power consumption, the merger is not allowed; if the power consumption of the merged cluster meets the constraint, the merge operation is performed, and the distance of the new cluster is updated. Each time a merge occurs, record the two clusters being merged and the power consumption and distance after the merge, which helps to track the clustering process and the final clustering result. This process is repeated continuously until all storage units are clustered into appropriate groups and the total power consumption of each group meets the power consumption constraint. The entire clustering process continues until the target clustering structure is reached and the power consumption limit is met. As Figure 5 shown, it is a schematic diagram of memory clustering and grouping. Memories of the same color are in the same cluster and share one controller.

[0052] Such as Figure 6 As shown, define the horizontal direction of memories M1 - M10 as the test time required for the memory test task, the vertical direction as the total test power consumption under the same test order, and the depth direction as the test temperature under the same test order. Three-dimensionally represent all memories. The horizontal direction, vertical direction, and depth direction respectively represent the test time, test power consumption, and the resulting test temperature required for testing this memory. Memories of the same color are memories controlled by the same controller. First, define the objective function and constraint conditions. Take the total time of the test process as the optimization objective, and the goal is to reduce the test time by reasonably arranging the test order of memories. The constraint conditions are the power consumption constraint, that is, when performing a memory test each time, the power consumption should not exceed the set maximum power consumption limit and the temperature constraint, that is, the heat generated during the test process should not cause the chip temperature to exceed a certain preset temperature limit . Initialize the algorithm parameters , the cooling rate Used to control the rate of temperature drop. The cooling rate determines the convergence rate of the algorithm and the maximum number of iterations . A set of initial solutions is randomly generated, and then the neighborhood solutions are generated by randomly swapping the test order of two memories or adding other memories in a test cycle. The acceptance criterion for the new solutions is based on the idea of simulated annealing. If the new solution is better than the current solution (i.e., the test time is shorter and the power consumption and temperature meet the constraints), then accept this solution; if the quality of the new solution is worse (i.e., the test time is longer), then accept the new solution with a certain probability, and this probability decreases as the temperature drops. The probability calculation formula is . For each new solution, check whether the power consumption and temperature constraints are met. If the constraints are not met, then this solution will be rejected; in each iteration, reduce the temperature T. Usually, the following formula is used to reduce the temperature: , and α usually takes values between 0.8 and 0.99. If the maximum number of iterations is reached, or when the temperature T drops to a certain minimum value, the algorithm terminates and outputs the optimal solution, that is, the solution that minimizes the test time under the condition of meeting the power consumption and temperature constraints. As Figure 7 shown, the test scheduling result is:

[0053] Controller 1: Step 1 (M1, M4, M8);

[0054] Controller 2: Step 1 (M10);

[0055] Controller 3: Step 1 (M2, M5, M3), Step 2 (M7);

[0056] Controller 4: Step 1 (M6, M9).

[0057] From Figure 7 it can be seen that the method described in the present invention optimizes the memory test scheduling and effectively reduces the test time.

[0058] The above is only the preferred solution of the present invention and is not used as a further limitation of the present invention. All equivalent changes made by using the content of the specification and drawings of the present invention are within the protection scope of the present invention.

Claims

1. A 3D IC MBIST test method based on an intelligent algorithm, characterized in that, Including the following steps: Step 1: Extract the spatial coordinate information of the memories and parse the hierarchical attribution of each memory; Step 2: Extract the multi-dimensional attributes of each memory and divide the memories into homogeneous sets based on the attribute consistency of the memories; Step 3: Calculate the inter-layer distance between each memory and other memories based on an improved inter-layer distance model; wherein, the improved inter-layer distance model is: ， Among them, θ is the interlayer distance conversion coefficient, , Z is the number of intervening layers; X i , Y i represents the spatial coordinates of memory i, X j , Y j represents the spatial coordinates of memory j; Step 4: Adopt a hierarchical clustering algorithm to group the memories and allocate a shared BIST controller based on the inter-layer distance of the memories; specifically: Calculate the distances between all memories and successively select two clusters with the smallest distance for merging; During each merging process, judge whether the total power consumption after merging exceeds the maximum power consumption requirement; if so, abandon the merging; if not, perform the merging operation and update the distance of the new cluster; Step 5: Use a multi-objective simulated annealing algorithm to define the constraint conditions and the optimization objective function of the memory test task and solve it to obtain the minimum test time; Among them, the objective function and the constraint conditions are defined as follows: Objective function: , where C is to minimize the test time; Power consumption constraint: The power consumption P of the memories under parallel testing shall not exceed the given maximum power consumption P max , Temperature constraint: , the temperature T of the memories under parallel testing shall not exceed the given maximum chip test temperature T max ; Among them, n is the total number of memories; Solve the objective function, specifically: Step 5-1: Randomly generate a test schedule for the memory, and set the initial temperature , cooling rate and the maximum number of iterations ; Step 5-2: Randomly change the test order of the memories to generate a neighborhood solution, compare the test time of the new solution with that of the current solution. If the test time obtained by the new neighborhood solution is less than that of the current solution, accept this solution; otherwise, accept this solution with a certain probability, and the probability calculation formula is as follows: ， Among them, is the test time of the neighborhood solution, is the test time of the current solution, is the current temperature; Step 5-3: For each new solution, check whether the power consumption and temperature constraints are satisfied; if the constraints are not satisfied, reject it; if the maximum number of iterations is reached, or when the temperature T drops to a preset threshold, the algorithm terminates and outputs the optimal solution, that is, the solution that minimizes the test time under the condition of satisfying the power consumption and temperature constraints.

2. The 3D IC MBIST test method based on an intelligent algorithm according to claim 1, wherein Step 1 is specifically: Read in the memory design.v file and the memory physical location.def file, parse the 3D IC physical layout file, obtain the memory coordinates and hierarchical attribution information, and model the three-dimensional distribution of the memories.

3. The 3D IC MBIST test method based on an intelligent algorithm according to claim 2, wherein, Step 2 is specifically: Read in the memory power domain.upf file, the clock domain.clk file, the address bit width test algorithm.lvlib file, read the memory constraints, and the TSV constraints.spec file, extract the multi-dimensional attributes of the memories; classify based on the multi-dimensional attributes of the memories to form a homogeneous memory set.

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