Chip wiring design method and chip

Abstract

The invention discloses a chip wiring design method and a chip, and relates to the field of chips, and the method comprises the steps: determining a planning path of a signal line group in the chip according to the starting position and the final position of the signal line group in the chip, and chip layout information; arranging the signal line group on a chip according to the planned path of the signal line group, wherein the signal line group comprises a plurality of signal lines; the phase inverters in any two adjacent signal lines in the signal line group are arranged at preset intervals in the direction of the planned path.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular, to a chip wiring design method and a chip. Background Art

[0002] In the wiring planning design of a chip, there are usually long-distance bus parallel wirings. The signal line spacing is small, the distance is long, and the inter-line coupling capacitance cannot be ignored.

[0003] Since the signal lines are made of metal, crosstalk problems will occur. Crosstalk refers to the mutual influence brought by the coupling capacitance between two or more adjacent metal lines. Crosstalk may affect the acceleration or delay of the conversion speed of adjacent signals, deteriorate the chip timing, or cause logical changes to other stable-state signals, resulting in errors in the chip function.

[0004] As the process becomes more and more advanced, the wiring density of the chip becomes higher, the signal lines become narrower, and the spacing becomes smaller, resulting in an increase in the coupling capacitance between lines, and the influence brought by crosstalk becomes more and more important. Summary of the Invention

[0005] A first aspect of this application provides a chip wiring design method, including:

[0006] Determine the planned path of the signal line group in the chip according to the starting position and the ending position of the signal line group in the chip, as well as the chip layout information;

[0007] Arrange the signal line group in the chip according to the planned path of the signal line group. The signal line group includes several signal lines; the setting positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance along the direction of the planned path.

[0008] In a possible implementation, arranging the signal line group in the chip according to the planned path of the signal line group includes:

[0009] Determine the signal path of each signal line in the signal line group according to the planned path of the signal line group in the chip;

[0010] Determine the setting positions of at least two inverters in the signal path of each signal line;

[0011] Set at least two inverters in the chip according to the setting positions;

[0012] Arrange each signal line in the signal line group on the chip in sequence according to the signal path of each signal line, and each signal line is connected in series with each inverter in the signal path.

[0013] In a possible implementation, determining the setting positions of at least two inverters in the signal path of each signal line includes:

[0014] Determine the driving distance of the inverter;

[0015] Determine a preset distance based on the driving distance;

[0016] In the signal path of each signal line, determine the setting positions of each inverter in each signal line in the signal line group according to the preset distance and the driving distance.

[0017] In a possible implementation, determining the setting positions of each inverter in each signal line in the signal line group according to the preset distance and the driving distance in the signal path of each signal line includes:

[0018] According to the starting position of the signal line group in the chip and the signal path of each signal line, determine the first setting position of the first-stage inverter in the signal path of each signal line in the signal line group;

[0019] In the first signal path of the first signal line, determine the setting positions of at least one inverter in sequence after the first-stage inverter in the first signal path according to the driving distance of the inverter;

[0020] In the second signal path of the second signal line, determine the second setting position of the second-stage inverter at a position spaced from the first-stage inverter by the preset distance; according to the driving distance of the inverter, determine the setting positions of at least one inverter in sequence after the second setting position in the second signal path; the first signal line and the second signal line are adjacent.

[0021] In a possible implementation, determining the setting positions of each inverter in each signal line in the signal line group according to the preset distance and the driving distance in the signal path of each signal line includes:

[0022] According to the starting position of the signal line group in the chip, the third signal path of the third signal line, and the driving distance of the inverter, determine a third setting position spaced from the starting position by the driving distance in the third signal path, and the third setting position is used to set the first-stage inverter; according to the driving distance of the inverter, determine the setting positions of at least one inverter in sequence after the third setting position in the third signal path;

[0023] According to the starting position of the signal line group in the chip, the fourth signal path of the fourth signal line, and the preset distance, in the fourth signal path, determine a fourth setting position that is spaced from the starting position by the preset distance, where the fourth setting position is used to set a first-stage inverter; according to the driving distance of the inverter, successively determine the setting positions of at least one inverter after the first-stage inverter in the fourth signal path; the third signal line and the fourth signal line are adjacent.

[0024] In a possible implementation, arranging the signal line group on the chip according to the planned path of the signal line group includes:

[0025] Statistically analyze the target length of the planned path of the signal line group;

[0026] Determine the type of the signal line group;

[0027] Based on the target length being greater than the length threshold and the type of the signal line group being a high-speed bus, arrange the signal line group on the chip according to the planned path of the signal line group.

[0028] In a possible implementation, arranging the signal line group on the chip according to the planned path of the signal line group includes:

[0029] Determine the driving distance of the inverter;

[0030] Determine the preset distance according to the driving distance;

[0031] Determine the setting positions of each inverter in the fifth signal line, where the distance between the fifth signal line and the target signal line in the signal line group is less than a preset distance threshold, the fifth signal line does not belong to the signal line group, and the target signal line is adjacent to the fifth signal line;

[0032] According to the setting positions of each inverter in the fifth signal line, the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance, determine the setting positions of each inverter in each signal line in the signal line group.

[0033] In a possible implementation, arranging the signal line group on the chip according to the planned path of the signal line group includes:

[0034] Determine the driving distance of the inverter;

[0035] Determine the preset distance according to the driving distance;

[0036] Determine the setting positions of the inverters for each signal line in the signal line sets located on different wiring layers in the signal line group according to the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance. The signal line group includes at least two signal line sets located on different wiring layers. For any two adjacent signal lines in the same signal line set, the setting positions of the inverters are spaced apart by a preset distance along the direction of the planned path.

[0037] In a possible implementation, the determining the preset distance according to the driving distance includes:

[0038] Determine half of the driving distance as the preset distance.

[0039] A second aspect of the present application provides a chip, including:

[0040] At least two modules;

[0041] A signal line group, where the signal line group contains several signal lines. For any two adjacent signal lines in the signal line group, the setting positions of the inverters are spaced apart by a preset distance along the direction of the planned path. The starting position of the signal line group is in the first module, and the ending position of the signal line group is in the second module. The first module and the second module belong to the at least two modules.

[0042] A third aspect of the present application provides a chip wiring design device, including:

[0043] A determination module, configured to determine the planned path of the signal line group in the chip according to the starting position and the ending position of the signal line group in the chip, and the chip layout information;

[0044] An arrangement module, configured to arrange the signal line group in the chip according to the planned path of the signal line group. The signal line group contains several signal lines; for any two adjacent signal lines in the signal line group, the setting positions of the inverters are spaced apart by a preset distance along the direction of the planned path.

[0045] A fourth aspect of the present application provides a computer program product, including computer-readable instructions. When the computer-readable instructions run on an electronic device, the electronic device is enabled to implement the chip wiring design method in the first aspect or any implementation manner of the first aspect.

[0046] A fifth aspect of the present application provides an electronic device, including at least one processor and a memory connected to the processor, where:

[0047] The memory is used to store a computer program;

[0048] The processor is used to execute the computer program, so that the electronic device can implement the chip wiring design method according to the first aspect or any implementation manner of the first aspect described above.

[0049] The sixth aspect of this application provides a computer storage medium. The storage medium carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement the chip wiring design method according to the first aspect or any implementation manner of the first aspect described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In combination with the accompanying drawings and with reference to the following specific implementation manners, the above and other features, advantages and aspects of the embodiments of the present disclosure will become more obvious. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0051] Figure 1 is a flowchart of a chip wiring design method provided by an embodiment of this application;

[0052] Figure 2 is a schematic diagram of chip design provided by an embodiment of this application;

[0053] Figure 3 is a schematic diagram of two adjacent signal lines provided by an embodiment of this application;

[0054] Figure 4 is a flowchart of the process of arranging the signal line group on the chip according to the planned path of the signal line group provided by an embodiment of this application;

[0055] Figure 5 is another schematic diagram of chip design provided by an embodiment of this application;

[0056] Figure 6 is a schematic diagram of the signal paths of multiple signal lines provided in an embodiment of this application;

[0057] Figure 7 is a flowchart of the process of determining the installation positions of at least two inverters in the signal path of each signal line provided by an embodiment of this application;

[0058] Figure 8 is a flowchart of the process of determining the installation positions of the inverters in each signal line of the signal line group according to a preset distance and a driving distance in the signal path of each signal line provided by an embodiment of this application;

[0059] Figure 9 is a schematic diagram of a signal line group provided by an embodiment of this application;

[0060] Figure 10It is another process schematic diagram provided by the embodiments of the present application for determining the setting positions of the inverters in each signal line of the signal line group according to a preset distance and a driving distance in the signal path of each signal line;

[0061] Figure 11 It is another schematic diagram of the signal line group provided by the embodiments of the present application;

[0062] Figure 12 It is a process schematic diagram provided by the embodiments of the present application for arranging the signal line group on the chip according to the planned path of the signal line group;

[0063] Figure 13 It is another process schematic diagram provided by the embodiments of the present application for arranging the signal line group on the chip according to the planned path of the signal line group;

[0064] Figure 14 It is another process schematic diagram provided by the embodiments of the present application for arranging the signal line group on the chip according to the planned path of the signal line group;

[0065] Figure 15 It is a schematic structural diagram of a chip provided by the embodiments of the present application;

[0066] Figure 16 It is a schematic structural diagram of a chip wiring design device provided by the embodiments of the present application;

[0067] Figure 17 It is a schematic structural diagram of an electronic device provided by the embodiments of the present application. Detailed implementation manners

[0068] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0069] The embodiments of the present application will be described below with reference to the accompanying drawings. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0070] In the description and claims of this application and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing embodiments of this application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device including a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices.

[0071] This application can be applied in the field of chips. This application can, but is not limited to, be applied in application programs with chip design functions (for example, EDA (Electronic Design Automation) tools). The following is a detailed introduction:

[0072] During the process of setting up a chip, after setting the positions of each module therein, the wiring between modules and between the signal input end of the chip and the modules is set. The chip wiring design method provided in the embodiments of this application is a process of setting the wiring on the chip.

[0073] Refer to Figure 1 , Figure 1 is a schematic flowchart of a chip wiring design method provided by an embodiment of this application. As Figure 1 shown, a chip wiring design method provided by an embodiment of this application may include steps 101 to 102. The following will describe these steps in detail.

[0074] 101. Determine the planned path of the signal line group in the chip based on the starting position and ending position of the signal line group in the chip and the chip layout information;

[0075] Among them, the chip layout information includes the position range of the modules already set on the chip, the position range where signal lines can be set on the chip, etc.

[0076] The position range where signal lines can be set on the chip is the position range where signal lines can be arranged in the idle space between the modules in the chip. The congestion situation of the chip layout needs to be considered, and it can be the situation where signal lines have been arranged in the idle space.

[0077] Among them, the starting position and ending position of the signal line group in the chip are obtained in advance.

[0078] Among them, the starting position can be the signal input terminal of the chip or the output pin of any module that emits signals. The ending position is the input pin of any module that receives signals or can also be the signal output terminal of the chip, etc. In this application, no restrictions are imposed on the starting position and the ending position.

[0079] Among them, when the starting position and the ending position of the signal line group in the chip are known, the planned path that the signal line group can adopt in the chip can be determined according to the chip layout information.

[0080] In a possible implementation, multiple wiring layers can be provided on the chip. When determining the planned path of the signal line in the chip, the idle state of the wiring layer is also considered.

[0081] Among them, the planned path is the path for setting the subsequent signal line group on the chip.

[0082] In a possible implementation, the chip can be an SOC (system on chip), and each module in the chip can be each functional module, such as a CPU (central processing unit) functional module, a GPU (Graphic Processing Unit) functional module, etc.; the chip can also be a chip with a single function, such as a CPU, a GPU, an NPU (Neural-network Processing Unit), a PMIC (Power Management Integrated Circuit) chip, etc. Each module in the chip can be a unit module divided according to each function, such as a control module, a register module, etc.

[0083] Figure 2 It is a schematic diagram of chip design provided by an embodiment of the present application. The schematic diagram of chip design includes 8 modules and the planned path 201 of the signal line group. In this schematic diagram, the 8 modules occupy different position ranges on the chip. Among them, the starting position A of the signal line group is in module 202, and the ending position E of the signal line group is in module 203. Among them, the signal line group reaches the ending position after three bends at positions B, C, and D from the starting position, and each signal line in the signal line group runs in parallel from the starting position to the ending position.

[0084] In a possible implementation, multiple wiring layers are provided in the chip structure, and the routing directions of any two adjacent wiring layers are perpendicular. For example, the single-layer wiring layer routes in the left-right direction on the chip, and the even-numbered wiring layer routes in the front-back direction on the chip.

[0085] Refer to this Figure 2In it, from the starting position, point A to point B, each signal line in the signal line group is in the first wiring layer; at the first bending point B, the signal line penetrates from the first wiring layer into the second wiring layer; between the first bending point B and the second bending point C, each signal line in the signal line group is in the second wiring layer; at point C, each signal line in the signal line group penetrates back into the first wiring layer, and between point C and point D, each signal line in the signal line group is in the first wiring layer, and so on, realizing the setting of a signal line group with bends in the chip. In this signal line group, line segments between point A and point B and between point C and point D are set in the first wiring layer, and line segments between point B and point C and between point D and point E are set in the second wiring layer. The first wiring layer and the second wiring layer are only used to represent two adjacent wiring layers, and their order in the chip's wiring layers can be either one on the lower layer and the other on the upper layer, not limited to the first wiring layer and the second wiring layer of the chip.

[0086] 102. Arrange the signal line group in the chip according to the planned path of the signal line group. The signal line group contains several signal lines; the setting positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance along the direction of the planned path.

[0087] Among them, after determining the planned path in the signal line group, arrange the signal line group in the chip.

[0088] Among them, the signal line group contains several parallel signal lines. When each signal line transmits a signal, there will be a problem of crosstalk. Therefore, an inverter is set on each signal line to solve the crosstalk problem.

[0089] As an example, the signal line group contains 128 signal lines to transmit a 128-bit signal between two connected modules.

[0090] In a possible implementation, multiple signal line groups can be arranged on the chip. The multiple signal line groups can be set on the same wiring layer or on different wiring layers.

[0091] Among them, the distance between any two adjacent signal lines in the same signal line group is very close. Therefore, there will be a crosstalk problem when transmitting signals, especially when transmitting high-speed signals, especially in the part arranged in parallel on the same wiring layer, the crosstalk problem will be very serious.

[0092] In this application, an inverter is set on the signal line in the signal line group. The setting positions of the inverters on any two adjacent signal lines are spaced apart by a preset distance along the direction of the planned path.

[0093] Among them, the preset distance spaced along the direction of the planned path means that the inverters on any two adjacent signal lines are not aligned.

[0094] Since the inverters on two adjacent signal lines are not aligned, the signals before and after the inverter on the interfering signal line are inverted. The crosstalk effects of different signal pairs on the signal on the interfered signal line are opposite, achieving partial cancellation of the crosstalk effect, reducing the overall crosstalk effect on the signal on the interfered signal line, and minimizing the influence of adjacent signal lines on the signal lines in the signal line group.

[0095] Figure 3 FIG. is a schematic diagram of two adjacent signal lines provided by an embodiment of the present application. In this schematic diagram, signal line 301 is used as the interfering line, and signal line 302 is used as the interfered line. Among them, an inverter 3011 is provided on signal line 301. The inverter divides signal line 301 into two segments, namely the first segment 3012 and the second segment 3013. The crosstalk between the first segment 3012 and signal line 302 is represented by capacitor 303, and the crosstalk between the second segment 3013 and signal line 302 is represented by capacitor 304. The capacitors 303 and 304 are only used to represent the coupling capacitors of crosstalk, and there is actually no such capacitor.

[0096] Among them, in SI (signal integrity) analysis, EDA tools usually consider the worst-case scenario, assuming that all interfering lines (aggressor nets) flip in the same direction, causing the signal transition speed of the interfered line (victim net) to increase or decrease. However, in some cases, due to the logical relationship between signals, the interfering lines do not flip in the same direction simultaneously. Refer to Figure 3 In the EDA tool considering the logical relationship before and after the inverter in, in the first segment 3012 of signal line 301, it flips from 0 to 1, and in the second segment 3013 of signal line 301, it flips from 1 to 0, or in the first segment 3012 of signal line 301, it flips from 1 to 0, and in the second segment 3013 of signal line 301, it flips from 0 to 1. Select one of the worse cases for SI analysis.

[0097] In the present application, the inverters on the signal lines are arranged regularly, and moreover, the inverters between two adjacent signal lines are spaced a preset distance. Refer to Figure 3 In, in the segments before and after the inverter in signal line 301 as the interfering line, the signal interference on the interfered signal line 302 is inverted in the opposite direction, alleviating the influence of the signal transition speed increase / decrease to a certain extent.

[0098] For example, the first sub - segment 3012 affects the signal conversion speed in the signal line 302 to increase, and the second sub - segment 3013 affects the signal rotation speed in the signal line 302 to slow down. The increase speed is greater than the slow - down speed, and the two effects have a canceling effect. Finally, the signal conversion speed in the signal line 302 is increased, but the increased amount is less than the increased amount of the signal conversion speed in the signal line 302 by the first sub - segment 3012.

[0099] Correspondingly, in the SI analysis of the interfered line using EDA tools, since it only considers the greater influence, such as acceleration / slow - down, it reduces the overall influence of the interfered line, making the SI evaluation more accurate and capable of improving the results of signal timing analysis (STA (static timing analysis)).

[0100] In this embodiment, according to the starting position and the ending position of the signal line group in the chip, as well as the chip layout information, the planned path of the signal line group in the chip is determined; the signal line group is arranged in the chip according to the planned path of the signal line group, and the signal line group includes several signal lines; the setting positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance along the direction of the planned path. By spacing the setting positions of the inverters in any two adjacent signal lines in the signal line group by a preset distance, the crosstalk between adjacent signal lines is reduced, and the timing analysis result of the signal transmitted on the signal line is improved.

[0101] Figure 4 It is a schematic flowchart of arranging the signal line group in the chip according to the planned path of the signal line group provided by the embodiment of the present application, which may include steps 401 to 404, and these steps will be described in detail below.

[0102] 401. According to the planned path of the signal line group in the chip, determine the signal path of each signal line in the signal line group;

[0103] Among them, the planned path includes the path planned from the starting position to the ending position of the signal line group in the chip, and the arrangement positions of each signal line in the signal line group need to be consistent with the planned path.

[0104] Among them, for the multiple signal lines included in the signal line group, after determining the planned path, the signal path (path) of each signal line can be determined in sequence according to the number of signal lines.

[0105] The signal path of the signal line is the path planned from the starting position to the ending position of a signal line, and the signal paths of each signal line in the signal line group can form the planned path of the signal line group.

[0106] Figure 5It is another schematic diagram of the chip design provided by the embodiments of the present application. The schematic diagram of the chip design includes a planned path 501 of a signal line group. The signal line group contains multiple signal lines, and the planned path can be divided into signal paths corresponding to multiple signal lines. The Figure 5 Taking 5 signal paths as an example for illustration. From the starting position A to the ending position E of the signal line group, these 5 signal paths are arranged in parallel.

[0107] 402. In the signal path of each signal line, determine the setting positions of at least two inverters;

[0108] Among them, in the signal line group, multiple inverters need to be set on each signal line. After determining the signal path of the signal line, first determine the setting positions of the inverters on the signal path.

[0109] Among them, in order to ensure the stability of signal transmission, inverters can be set at the same interval distance on the signal path, and multiple inverters are set on the same signal line.

[0110] Moreover, for the inverters on any two adjacent signal lines, the setting positions are spaced apart by a preset distance along the direction of the planned path (which can also be said to be the signal path).

[0111] In a possible implementation, the number of inverters that can be set in a signal path can be determined in advance according to the total length of the signal line, and then the positions of the inverters are determined in the signal path.

[0112] In a possible implementation, the position of the first-stage inverter can also be determined first, and then the positions of each inverter are set in turn without considering the total length of the signal line.

[0113] In a possible implementation, since when bending occurs, the signal line will penetrate into the adjacent wiring layer, and the via between two adjacent wiring layers is used for penetration, and no inverter can be set in the via, the signal line can be divided into multiple segments. The starting position and the adjacent bending point, any two adjacent bending points, and the ending position and the adjacent bending point are respectively a segment of the signal line. Based on the starting point (starting position or bending point) and the ending point (bending point or ending position) of each segment of the signal line, the setting positions of the inverters are determined.

[0114] Figure 6It is a schematic diagram of signal paths of multiple signal lines provided in an embodiment of the present application. These multiple signal lines belong to the same signal line group, and each signal line corresponds to a signal path 601. Four signal lines are used for illustration in this schematic diagram. A plurality of inverters 602 are arranged on each signal path. In this schematic diagram, a section on the signal path is used for illustration. In this schematic diagram, only 5 inverters on each signal path are shown, and there is a preset distance d between the inverters of any two adjacent signal paths. This signal path is subsequently used for arranging signal lines.

[0115] Among them, since there is a preset distance between the inverters of adjacent signal lines, in the segments before and after the inverters in the signal lines serving as interfering lines, the signal interference on the signal lines being interfered is reversed in the opposite direction, alleviating to a certain extent the influence of the signal conversion speed increasing / decreasing.

[0116] 403. Set at least two inverters in the chip according to the set position.

[0117] Before laying signal lines (also called wire routing) in the chip, first set inverters in the chip.

[0118] Among them, the set position of the inverters can be determined in the signal path of each signal line, and the inverters are set accordingly. A plurality of inverters are set in the signal path of each signal line.

[0119] 404. Arrange each signal line in the signal line group on the chip in sequence according to the signal path of each signal line, and each signal line is connected in series with each inverter in the signal path.

[0120] Among them, after setting the inverters on the signal path, arrange the signal lines on the signal path, and the arranged signal lines are connected in series with each inverter in the signal path.

[0121] Among them, a wire routing rule can be preset, and according to this wire routing rule, the arrangement (wire routing) of the signal lines and the connection of each level of inverters are completed on the chip.

[0122] In a possible implementation, the wire routing rule may include the line width, line spacing, wiring layer, etc. of the signal lines. The specific content of this wire routing rule is not limited in the present application.

[0123] Among them, the inverters are connected in series by the signal lines. During the process of the signal lines transmitting signals, the signals are flipped by the inverters in sequence and finally transmitted to the end position.

[0124] In this embodiment, according to the planned path of the signal line group in the chip, the signal path of each signal line in the signal line group is determined; in the signal path of each signal line, the setting positions of at least two inverters are determined; according to the setting positions of the inverters, at least two inverters are set in the chip; according to the signal path of each signal line, each signal line in the signal line group is arranged on the chip in sequence, and each signal line is connected in series with each inverter in the signal path, realizing the arrangement of signal lines and inverters in the chip.

[0125] Figure 7 FIG. 4 is a schematic flowchart of determining the setting positions of at least two inverters in the signal path of each signal line provided by an embodiment of the present application, which may include steps 701 to 703, and these steps will be described in detail below.

[0126] 701. Determine the driving distance of the inverter;

[0127] Wherein, the driving distance of the inverter refers to the maximum distance at which the output signal of the inverter can maintain an effective logic level on the signal line.

[0128] Wherein, the driving distance of the inverter can be affected by inverter parameters, the signal source, and even the material of the signal line, etc.

[0129] Therefore, when determining the driving distance of the inverter, it can be determined according to inverter parameters, the signal frequency emitted by the signal source, the material of the signal line, etc.

[0130] In the present application, there is no limitation on the specific determination method of the driving distance of the inverter.

[0131] Wherein, in the same signal line, the interval between two adjacent inverters generally adopts this driving distance, so as to minimize the number of inverters on the premise of ensuring effective signal transmission, thereby reducing the complexity of the chip.

[0132] 702. Determine a preset distance according to the driving distance;

[0133] Wherein, determining a preset distance according to the driving distance, the preset distance is greater than zero and less than the driving distance.

[0134] In a possible implementation, half of the driving distance is determined as the preset distance.

[0135] Since the inverters on two adjacent signal lines are not aligned, interfering with the signal inversion before and after the inverter on the interfering signal line, partially offsetting the crosstalk effect. To maximize the offset effect, half of the driving distance is determined as the preset distance.

[0136] Among them, the inverters on two adjacent signal lines are staggered by 1 / 2 driving distance, so that the signals on the signal lines before and after any inverter are inverted in the opposite direction. When calculating SI, considering the factor of the logic inversion direction, the timing analysis result is improved.

[0137] 703. In the signal path of each signal line, determine the setting positions of the inverters in each signal line in the signal line group according to the preset distance.

[0138] Among them, after determining the preset distance, when determining the position of the inverter in the signal line in the signal path, according to the preset distance and the driving distance, determine the setting position of the inverter in each signal path.

[0139] Among them, the inverters in each signal path are spaced by the driving distance; the inverters in the signal paths of any two adjacent signal lines are spaced by the preset distance.

[0140] In a possible implementation, since when bending occurs, the signal line will penetrate into the adjacent wiring layer, and when penetrating the layer, it is through the via between two adjacent wiring layers, and no inverter can be set in the via. When determining the setting position of the inverter in the signal path of the signal line, the height difference at the via position can be ignored, and the sum of the position from the last inverter in the upper layer to the via and the position from the first inverter in the lower layer to the via is the driving distance, and the inverters in the signal paths of adjacent signal lines are spaced by the preset distance.

[0141] In a possible implementation, since no inverter can be set in the via, the signal line can be divided into multiple segments. The start position and the adjacent bending point, any two adjacent bending points, and the end position and the adjacent bending point are each a segment of the signal line. Determine the setting position of the inverter based on the start point and the end point of each segment of the signal line. Determine that the inverters in the signal line are spaced by the driving distance within the wiring layer, and the inverters in the signal paths of adjacent signal lines are spaced by the preset distance.

[0142] Reference Figure 6 In the schematic diagram of the signal line group in, the interval distance between the inverters on each signal line is the driving distance, and the interval d between the inverters on two signal lines is 1 / 2 driving distance.

[0143] Among them, the interval d between the inverters on the two adjacent signal lines is 1 / 2 driving distance, which is applicable to the wiring schemes of vertical, horizontal, medium and low speed, and long distance, and is not limited to the Figure 6 wiring scheme in.

[0144] Crosstalk between signal lines is generally quantified by net delay (Deltadelay). This net delay is the difference between an equivalent waveform that the EDA tool backtracks from the output waveform to the input and a waveform that is not affected by crosstalk, which can intuitively reflect the impact brought by crosstalk.

[0145] Table 1 below shows the net delays of signal lines for the scheme of aligning inverters on adjacent signal lines and the scheme of the present application.

[0146] Table 1

[0147]

[0148] As can be seen from the records in Table 1 above, for the scheme provided in the present application where the inverters in adjacent signal lines are spaced 1 / 2 driving distance apart, compared with the scheme of aligning inverters in adjacent signal lines, the net delay is reduced by about 1 / 2, greatly improving the timing analysis results.

[0149] In this embodiment, the driving distance of the inverter is determined; a preset distance is determined based on the driving distance; in the signal path of each signal line, the setting positions of each inverter in each signal line in the signal line group are determined according to the preset distance and the driving distance. According to the driving distance of the inverter, the preset distance is determined, and the setting positions of the inverters in each signal line in the signal line group are determined according to the driving distance and the preset distance, ensuring that the signals on the signal lines before and after any inverter flip in opposite directions. When calculating SI, the factor of the logic flip direction is considered, achieving the improvement of the timing analysis results, being able to save the overall power consumption of the chip, and enhancing the signal transmission frequency of the chip.

[0150] Figure 8 It is a schematic flowchart of determining the setting positions of each inverter in each signal line in the signal line group according to the preset distance and the driving distance in the signal path of each signal line provided by the embodiment of the present application, which may include steps 801 to 804. The following will describe these steps in detail.

[0151] 801. Determine the first setting position of the first-stage inverter in the signal path of each signal line in the signal line group according to the starting position of the signal line group in the chip and the signal path of each signal line;

[0152] Among them, when setting an inverter in the signal path of a signal line, a first-stage inverter can be set at the starting position of each signal path.

[0153] Correspondingly, according to the starting position of the signal line group in the chip and the signal path of each signal line, determine the starting position of each signal path, and use the starting position of the signal path as the first setting position, which is subsequently used to set the first-stage inverter.

[0154] Among them, in the signal path of each signal line, the starting position thereof is used as the first setting position of the first inverter.

[0155] 802. In the second signal path of the second signal line, according to the preset distance, determine the second setting position of the second inverter at a distance of the preset distance from the first inverter. The first signal line and the second signal line are adjacent.

[0156] Among them, in the first signal path of the first signal line, determine the setting positions of each subsequent inverter to be set.

[0157] Among them, taking the first setting position as a reference, according to the driving distance of the inverter, sequentially determine the setting positions of each subsequent inverter to be set until reaching the end position of the signal path.

[0158] Among them, the setting position of the inverter is not affected by whether the signal path is bent.

[0159] 803. In the second signal path of the second signal line, determine the position at a distance of the preset distance from the first inverter as the second setting position of the second inverter.

[0160] Among them, the second signal line and the first signal line are adjacent. When setting an inverter in the second signal path of the second signal line, the relative position relationship between it and the inverter in the first signal line needs to be considered. The relative position relationship is that the inverters of the two are spaced apart by a preset distance in the direction along the planned path.

[0161] Among them, when determining the setting position of the inverter in the second signal path, first determine the first setting position of the first inverter, then determine the second setting position of the second inverter, and finally determine the setting positions of the subsequent inverters after the second inverter.

[0162] Among them, in the second signal path, determine the position at a distance of the preset distance from the first inverter, and this position is used as the second setting position of the second inverter.

[0163] 804. According to the driving distance of the inverter, sequentially determine the setting positions of at least one inverter after the second setting position in the second signal path.

[0164] Among them, in the second signal path of the second signal line, the distance between the second inverter and the subsequent inverters uses the driving distance of the inverter.

[0165] Starting from the second inverter, the distance between any two inverters is the driving distance.

[0166] Among them, the first signal line and the second signal line are two adjacent signal lines. For example, in a signal line group, the first signal line is a single-sequence signal line and the second signal line is a double-sequence signal line; or in a signal line group, the first signal line is a double-sequence signal line and the second signal line is a single-sequence signal line.

[0167] Figure 9 is a schematic diagram of a signal line group provided by an embodiment of the present application. The signal line group includes multiple signal lines, and 8 signal lines are used for illustration in this schematic diagram. The signal lines are sorted from top to bottom as 1 to 8. A first-stage inverter is provided at the starting position of each signal line. Between any two inverters in the double-sequence signal lines, there is an inverter driving distance. In the single-sequence signal lines, the second-stage inverter is spaced 1 / 2 driving distance from the first-stage inverter. Starting from the second-stage inverter, between any two inverters, there is an inverter driving distance, achieving that between the inverters in any two adjacent signal lines, along the planned path direction of the signal line, they are spaced 1 / 2 driving distance. The arrow direction in the figure indicates the signal transmission direction.

[0168] In this embodiment, according to the starting position of the signal line group in the chip and the signal path of each signal line, the first setting position of the first-stage inverter in the signal path of each signal line in the signal line group is determined; in the first signal path of the first signal line, according to the driving distance of the inverter, at least one inverter setting position is sequentially determined after the first-stage inverter in the first signal path; in the second signal path of the second signal line, the position spaced a preset distance from the first-stage inverter is determined as the second setting position of the second-stage inverter; according to the driving distance of the inverter, at least one inverter setting position is sequentially determined after the second setting position in the second signal path; the first signal line and the second signal line are adjacent, realizing the process of setting inverters for a group of signal lines, and realizing that between the inverters in any two adjacent signal lines, along the planned path direction of the signal line, they are spaced 1 / 2 driving distance.

[0169] Figure 10 is another process schematic diagram for determining the setting positions of each inverter in each signal line in the signal line group according to a preset distance and a driving distance in the signal path of each signal line provided by an embodiment of the present application. It may include steps 901 to 902, which will be described in detail below.

[0170] 1001. According to the starting position of the signal line group in the chip, the third signal path of the third signal line, and the driving distance of the inverter, in the third signal path, determine a third setting position spaced the driving distance from the starting position, and this third setting position is used to set the first-stage inverter;

[0171] Among them, when an inverter is set in the signal path of the signal line, the inverter may not be set at the starting position of each signal path.

[0172] Among them, in the third signal path, a position that is spaced from the starting position of the third signal path in the chip by the driving distance is determined as the third setting position for setting the first-stage inverter.

[0173] 1002. According to the driving distance of the inverter, at least one setting position of the inverter is determined in sequence after the third setting position of the third signal path.

[0174] Among them, in the third signal path of the third signal line, the setting positions of each subsequent inverter to be set are determined.

[0175] Among them, taking the third setting position as a reference, according to the driving distance of the inverter, the setting positions of each subsequent inverter are determined in sequence until the end position of the signal path is reached.

[0176] Among them, the setting position of the inverter is not affected by whether the signal path is bent.

[0177] 1003. According to the starting position of the signal line group in the chip, the fourth signal path of the fourth signal line, and the preset distance, in the fourth signal path, a fourth setting position that is spaced from the starting position by the preset distance is determined, and the fourth setting position is used to set the first-stage inverter; the third signal line and the fourth signal line are adjacent.

[0178] Among them, the fourth signal line and the third signal line are adjacent. When an inverter is set in the fourth signal path of the fourth signal line, the relative position relationship between it and the inverter in the third signal line needs to be considered, and the relative position relationship is that the inverters of the two are spaced by a preset distance in the direction along the planned path.

[0179] Among them, when determining the setting position of the inverter in the third signal path, first determine the fourth setting position of the first-stage inverter, and then determine the setting positions of the subsequent stages of inverters after the first-stage inverter.

[0180] Among them, in the fourth signal path, the first-stage inverter is set at the fourth setting position that is spaced from the starting position in the chip by the preset distance.

[0181] 1004. According to the driving distance of the inverter, at least one setting position of the inverter is determined in sequence after the first-stage inverter in the fourth signal path.

[0182] Among them, in the fourth signal path of the fourth signal line, the distance between the first-stage inverter and the subsequent inverters adopts the driving distance of the inverter.

[0183] Starting from the first - stage inverter, the distance between any two inverters is the driving distance.

[0184] Among them, the third signal line and the fourth signal line are two adjacent signal lines. For example, in a signal - line group, the third signal line is a single - numbered signal line and the fourth signal line is a double - numbered signal line; or in a signal - line group, the third signal line is a double - numbered signal line and the fourth signal line is a single - numbered signal line.

[0185] Figure 11 It is another schematic diagram of the signal - line group provided by the embodiment of the present application. The signal - line group contains multiple signal lines, and 8 signal lines are used for illustration in this schematic diagram. The signal - line sorting from top to bottom is 1 - 8. The starting position of each signal line is not provided with an inverter. In the single - numbered signal lines, the first - stage inverter is spaced from the starting position by 1 / 2 of the driving distance. Starting from the second - stage inverter, the distance between any two inverters is the driving distance of the inverter. In the double - numbered signal lines, the first - stage inverter is spaced from the starting position by the driving distance. Starting from the second - stage inverter, the distance between any two inverters is the driving distance of the inverter. It realizes that the inverters in any two adjacent signal lines are spaced by 1 / 2 of the driving distance along the planned path direction of the signal line. The arrow direction in the figure represents the signal transmission direction.

[0186] In this embodiment, according to the starting position of the signal - line group in the chip, the third signal path of the third signal line, and the driving distance of the inverter, in the third signal path, a third setting position spaced from the starting position by the driving distance is determined, and the third setting position is used to set the first - stage inverter; according to the driving distance of the inverter, at least one setting position of the inverter is determined in turn after the third setting position of the third signal path; according to the starting position of the signal - line group in the chip, the fourth signal path of the fourth signal line, and a preset distance, in the fourth signal path, a fourth setting position spaced from the starting position by the preset distance is determined, and the fourth setting position is used to set the first - stage inverter; according to the driving distance of the inverter, at least one setting position of the inverter is determined in turn after the first - stage inverter of the fourth signal path; the third signal line and the fourth signal line are adjacent, and it realizes that the inverters in any two adjacent signal lines are spaced by 1 / 2 of the driving distance along the planned path direction of the signal line.

[0187] Figure 12 It is a schematic flow chart for arranging the signal - line group in the chip according to the planned path of the signal - line group provided by the embodiment of the present application, which may include steps 1201 to 1203, and the following will describe these steps in detail.

[0188] 1201. Stat the target length of the planned path of the signal - line group;

[0189] 1202. Determine the type of the signal - line group;

[0190] Among them, after determining the planned path of the signal line group, it is further determined whether the signal line group needs to be set in such a way that inverters are spaced at a preset distance between two adjacent signal lines.

[0191] Among them, when the parallel length of the signal lines is long enough and it is a high-speed bus, the crosstalk between the signal lines will be serious, and it is necessary to set inverters to reduce the influence of the crosstalk and ensure the signal transmission quality.

[0192] Therefore, the target length of the planned path of the signal line group is counted. The length of the planned path is the same as the length of the signal line group actually arranged on the chip later. Therefore, by counting the target length of the planned path, the length of the signal line group is determined, and the length of the signal line group represents the parallel length of each signal line in the signal line group.

[0193] In a possible implementation, the method for determining the type of the signal line group can be to determine it according to the type of the signal it transmits. For example, if the signal transmitted by the signal line group is a high-speed signal, the signal line group is a high-speed bus. For example, if the signal transmitted by the signal line group is a low-speed signal, the signal line group is a low-speed bus.

[0194] Among them, when the signals transmitted by the signal lines in the signal line group are low-speed signals, the crosstalk between the signal lines is small, and the chip wiring design method in this application may not be adopted; however, if the signals transmitted by the signal lines in the signal line group are high-speed signals, the crosstalk between the signal lines is serious, and it is necessary to set inverters to reduce the crosstalk.

[0195] It should be noted that the order of execution of counting the length of the planned path of the signal line group and determining the type of the signal line group can be determined simultaneously or in any order, and this application does not make any restrictions.

[0196] 1203. Based on the fact that the target length is greater than the length threshold and the type of the signal line group is a high-speed bus, arrange the signal line group on the chip according to the planned path of the signal line group.

[0197] Among them, if the target length of the planned path of the signal line group is greater than the length threshold, it indicates that the signal line group is long, and the type of the signal line group is a high-speed bus, and the crosstalk between each signal line in the signal line group is serious, and it is necessary to reduce the influence of the crosstalk.

[0198] Correspondingly, when arranging the signal line group on the chip according to the planned path of the signal line group, the setting positions of the inverters between any two adjacent signal lines in the signal line group are spaced at a preset distance along the direction of the planned path to reduce the influence of the crosstalk.

[0199] Among them, for the specific process of arranging the signal line group on the chip, please refer to the explanation in the foregoing embodiments, and details are not described herein again.

[0200] In this embodiment, the target length of the planned path of the signal line group is statistically calculated; the type of the signal line group is determined; based on the fact that the target length is greater than the length threshold and the type of the signal line group is a high-speed bus, the signal line group is arranged in the chip according to the planned path of the signal line group. For any two adjacent signal lines in the signal line group, the setting positions of the inverters are spaced apart by a preset distance along the direction of the planned path. According to the length of the planned path of the signal line group and the type of the signal line group, after determining that the signal line group is arranged in the chip, during the actual operation of the chip, whether there will be a serious crosstalk problem when the signal line group transmits signals is determined. And in the case of a serious crosstalk problem, the setting positions of the inverters in any two adjacent signal lines are set to be spaced apart by a preset distance to reduce the crosstalk problem.

[0201] Figure 13 FIG. is another flowchart showing the arrangement of the signal line group in the chip according to the planned path of the signal line group provided by the embodiment of the present application, which may include steps 1301 to 1304, and these steps will be described in detail below.

[0202] 1301. Determine the driving distance of the inverter;

[0203] 1302. Determine the preset distance according to the driving distance;

[0204] In a possible implementation, half of the driving distance is determined as the preset distance.

[0205] Among them, steps 1301 to 1302 are the same as Figure 7 steps 701 to 702 therein. For specific explanations, please refer to the explanations of steps 701 and 702, and details will not be elaborated here.

[0206] 1303. Determine the setting positions of the inverters in the fifth signal line, where the distance between the fifth signal line and the target signal line in the signal line group is less than the preset spacing threshold, the fifth signal line does not belong to the signal line group, and the target signal line is adjacent to the fifth signal line;

[0207] Among them, multiple signal line groups may be arranged in parallel in the chip. Since the distance between the signal lines at the edge positions of each signal line group is very close, crosstalk problems are also likely to occur between the signal lines at the edge positions.

[0208] Due to the integration characteristics of the chip, hundreds or thousands of signal lines can be arranged in a very small area on the chip, and the distance between any two signal lines can reach the nanometer level. Different signal line groups may also be arranged in parallel. In this embodiment, the parallel arrangement of different signal line groups is addressed.

[0209] Among them, the fifth signal line can be a signal line parallel to the target signal line in the signal line group, and the fifth signal does not belong to the signal line group and can be a signal line in other signal line groups.

[0210] Among them, when designing the chip wiring, the wiring design time of the fifth signal line is earlier than that of the signal line group.

[0211] Among them, the spacing threshold is the maximum distance that can cause crosstalk. When the spacing between the fifth signal line and the target signal line is less than the preset spacing threshold, crosstalk will occur between the fifth signal line and the target signal line. Therefore, when arranging the signal line group, the setting positions of the inverters in the fifth signal line need to be considered.

[0212] Therefore, it is necessary to determine the setting positions of the inverters in the fifth signal line.

[0213] During the wiring process on the chip, the fifth signal line can be wired earlier than the signal line group, later than the signal line group, or at the same time. In this application, the wiring time of the two is not restricted.

[0214] 1304. Determine the setting positions of the inverters in each signal line of the signal line group according to the setting positions of the inverters in the fifth signal line, the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance.

[0215] Among them, first determine the setting positions of the inverters of the target signal line in the signal line group; then, in combination with the setting positions of the inverters in the target signal line, determine the setting positions of the inverters in the remaining signal lines in the signal line group.

[0216] First, based on the setting positions of the inverters in the fifth signal line, determine the setting positions of the inverters of the target signal line in the signal line group according to the starting position of the signal line group in the chip, the planned path, the driving distance, and the preset distance.

[0217] Then, determine the setting positions of the inverters in the remaining signal lines according to the setting positions of the inverters in the remaining signal lines in the signal line group.

[0218] Among them, the setting positions of the inverters in the target signal line are spaced apart from the setting positions of the inverters in the fifth signal line by a preset distance, and the setting positions of the inverters in each signal line are set according to the driving distance and the preset distance.

[0219] The setting positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance in the direction along the planned path.

[0220] Refer to the foregoing Figure 8 and Figure 11The process of determining the setting positions of the inverters in each signal line in the signal line group shown in the figure. The target signal line can be used as the first signal line or the third signal line, and the setting positions of the inverters in the remaining signal lines are set accordingly.

[0221] In this embodiment, the driving distance of the inverter is determined; the preset distance is determined according to the driving distance; the setting positions of the inverters in the fifth signal line are determined. The distance between the fifth signal line and the target signal line in the signal line group is less than the preset distance threshold. The fifth signal line does not belong to the signal line group, and the target signal line is adjacent to the fifth signal line. According to the setting positions of the inverters in the fifth signal line, the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance, the setting positions of the inverters in each signal line in the signal line group are determined. When setting the inverters in each signal line of the signal line group, considering the influence of adjacent signals in the signal line group, the crosstalk problem between signals is reduced from the overall signal lines arranged in the chip, the overall power consumption of the chip is saved, and the signal transmission frequency of the chip is improved.

[0222] Figure 14 It is another flow chart of arranging the signal line group in the chip according to the planned path of the signal line group provided by the embodiment of the present application, which may include steps 1401 to 1403. These steps are described in detail below.

[0223] 1401. Determine the driving distance of the inverter;

[0224] 1402. Determine the preset distance according to the driving distance;

[0225] In a possible implementation, half of the driving distance is determined as the preset distance.

[0226] Among them, steps 1401 to 1402 are the same as Figure 7 steps 701 to 702 in. For specific explanations, please refer to the explanations of steps 701 and 702, and will not be repeated here.

[0227] 1403. According to the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance, determine the setting positions of the inverters in each signal line in the signal line sets located in different wiring layers in the signal line group. The signal line group includes at least two signal line sets located in different wiring layers. The setting positions of the inverters in any two adjacent signal lines in the same signal line set are spaced apart by a preset distance along the direction of the planned path.

[0228] Among them, the signal line group contains several signal lines. The signal line group is divided into at least two signal line sets, and different signal line sets are located in different wiring layers.

[0229] In a possible implementation, each signal line in the signal line group is set between the starting position and the ending position in the slave chip. Correspondingly, each signal line in each signal line set can be multiple signal lines from the starting position to the ending position.

[0230] As an example, from the starting position to the ending position of the signal line group on the chip, 120 signal lines can be set in one wiring layer, and the signal line group contains 128 signal lines. 120 signal lines in the signal line group are set in one wiring layer, and the remaining 8 signal lines are set in another wiring layer. The 120 signal lines set in the same wiring layer are used as one signal line set, and the 8 signal lines set in the same wiring layer are used as another signal line set. The wiring directions of the two wiring layers where the two signal line sets are arranged are the same, so that each line in the signal line group is parallel within the wiring layer, and the two signal line sets are parallel between the wiring layers.

[0231] As an example, from the starting position to the ending position of the signal line group on the chip, 50 signal lines can be set in one wiring layer, and the signal line group contains 200 signal lines. Every 50 adjacent signal lines in the signal line group are set in one wiring layer, and a total of 4 wiring layers are set. The 50 signal lines set in the same wiring layer are used as one signal line set. The wiring directions of the 4 wiring layers where the 4 signal line sets are arranged are the same, so that each line in the signal line group is parallel within the wiring layer, and the 4 signal line sets are parallel between the wiring layers.

[0232] As an example, the wiring layers are arranged from bottom to top in the order of 1-4. The first signal line set is arranged in wiring layer 1, and the second signal line set is arranged in wiring layer 3. When the signal line group is bent, the first signal line set penetrates into wiring layer 2, and the second signal line set penetrates into wiring layer 4. When the signal line group is bent again, the first signal line set penetrates back into wiring layer 1, and the second signal line set penetrates back into wiring layer 3. The wiring directions of wiring layer 1 and 3 are the same, and the wiring directions of wiring layer 2 and 4 are the same. The wiring direction of wiring layer 1 is perpendicular to the wiring direction of wiring layer 2.

[0233] In a possible implementation, since the wiring directions of any two adjacent wiring layers in the chip are perpendicular, then, a set composed of a group of adjacent signal line segments arranged in the same wiring layer can be used as one signal line set. The signal line group is bent N times. Correspondingly, the signal line group contains N + 1 signal line sets, where N is an integer greater than 0.

[0234] As an example, the wiring layers are arranged from bottom to top in the order of 1-2. The wiring direction of wiring layer 1 is perpendicular to the wiring direction of wiring layer 2. Refer to Figure 2, the signal line group is divided into 4 sets, namely signal line sets 1 - 4. Each signal line segment between point A and point B forms signal line set 1, each signal line segment between point B and point C forms signal line set 2, each signal line segment between point C and point D forms signal line set 3, and each signal line segment between point D and point E forms signal line set 4. Among them, signal line set 1 and signal line set 3 are arranged in wiring layer 1, and signal line set 2 and signal line set 4 are arranged in wiring layer 2.

[0235] Among them, since in the chip, the first - direction wiring layer and the second - direction wiring layer are arranged at intervals in turn, and the first direction and the second direction are perpendicular, therefore, there is a non - same - direction wiring layer between each two same - direction wiring layers in the chip, and the interval distance between two same - direction wiring layers is relatively far. The crosstalk between signal lines of two adjacent (with a non - same - direction wiring layer in between) same - direction wiring layers can be not considered. However, the crosstalk between signal lines within the same wiring layer is serious and needs to be reduced.

[0236] Correspondingly, in this embodiment, each signal line set is located in a different wiring layer, and the signal lines on each wiring layer are arranged in the same direction. When the signal line group is bent, each signal line penetrates into the wiring layer in the other direction in turn, and the signal lines on the other wiring layer are also arranged in the same direction.

[0237] Therefore, for the signal line set in the same wiring layer, regarding the setting positions of inverters in each signal line, the setting positions of adjacent signal lines need to be considered.

[0238] In a possible implementation, taking a signal line set as a small signal line group, referring to the process of determining the setting positions of each inverter in each signal line in the signal line group shown in the foregoing Figure 8 and Figure 11 , set the setting positions of each inverter in this signal line set.

[0239] In this embodiment, determine the driving distance of the inverter; determine the preset distance according to the driving distance; according to the starting position and planned path of the signal line group in the chip, the driving distance of the inverter, and the preset distance, determine the setting positions of each inverter in each signal line of the signal line sets located in different wiring layers in the signal line group. The signal line group includes at least two signal line sets located in different wiring layers. For any two adjacent signal lines in the same signal line set, the setting positions of the inverters are spaced apart by the preset distance along the direction of the planned path. The same signal line group includes multiple signal line sets, and different signal line sets are located in different wiring layers. Since the crosstalk between signal lines in the same wiring layer is serious, therefore, when setting inverters for each signal line in the signal line set in the same wiring layer, the setting positions of the inverters in any two adjacent signal lines need to be spaced apart by the preset distance along the direction of the planned path to reduce the crosstalk problem between signal lines.

[0240] The above describes a chip wiring design method provided by an embodiment of the present application. The following will introduce a chip for which wiring design is performed using the above chip wiring design method.

[0241] Please refer to Figure 15 , Figure 15 which is a schematic structural diagram of a chip provided by an embodiment of the present application. As Figure 15 shown, the chip 1500 includes:

[0242] at least two modules 1501;

[0243] a signal line group 1502, which contains several signal lines. The positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance in the direction along the planned path. The starting position of the signal line group is in the first module, and the ending position of the signal line group is in the second module. The first module and the second module belong to the at least two modules.

[0244] In a possible implementation, the signal line group is a high-speed bus, and the signal lines in the signal line group are used to transmit high-speed signals.

[0245] In a possible implementation, the length of the signal line group is greater than a length threshold.

[0246] Among them, multiple inverters are provided on each signal line in the signal line group.

[0247] In a possible implementation, when an inverter is provided at the starting position of the signal line group, a first-stage inverter is provided at the starting position of the first signal line; on the first signal line, at least one inverter is sequentially provided after the first-stage inverter at an interval of the driving distance of the inverter. A first-stage inverter is provided at the starting position of the second signal line; a second-stage inverter is provided on the second signal line at a preset distance from the first-stage inverter; at least one inverter is sequentially provided after the second-stage inverter at an interval of the driving distance of the inverter, and the first signal line and the second signal line are adjacent.

[0248] In a possible implementation, when no inverter is provided at the starting position of the signal line group, in the third signal line, a first-stage inverter is provided at a third setting position spaced apart from the starting position by the driving distance; on the third signal line, at least one inverter is sequentially provided after the first-stage inverter at an interval of the driving distance of the inverter. In the fourth signal line, a first-stage inverter is provided at a fourth setting position spaced apart from the starting position by a preset distance; at least one inverter is sequentially provided after the first-stage inverter at an interval of the driving distance of the inverter, and the third signal line and the fourth signal line are adjacent.

[0249] In a possible implementation, the preset distance can be half of the driving distance of the inverter.

[0250] It should be noted that for the explanations of the components in a chip provided in the embodiments of the present application, please refer to the corresponding explanations in the foregoing method embodiments, and details are not described herein again.

[0251] In this embodiment, the chip includes at least two modules; a signal line group including a plurality of signal lines. The positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance in the direction along the planned path. The starting position of the signal line group is in the first module, and the ending position of the signal line group is in the second module, and the first module and the second module belong to the at least two modules. The fact that the positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance can reduce the crosstalk between adjacent signal lines and improve the timing analysis result of the signals transmitted on the signal lines.

[0252] The above introduces a chip wiring design method provided in the embodiments of the present application. Next, a device for implementing the above chip wiring design method will be introduced.

[0253] Please refer to Figure 16 , Figure 16 which is a schematic structural diagram of a chip wiring design device provided in the embodiments of the present application. As Figure 16 shown, the chip wiring design device 1600 includes:

[0254] A determination module 1601, configured to determine the planned path of the signal line group in the chip according to the starting position and the ending position of the signal line group in the chip and the chip layout information;

[0255] An arrangement module 1602, configured to arrange the signal line group in the chip according to the planned path of the signal line group. The signal line group includes a plurality of signal lines; the positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance in the direction along the planned path.

[0256] In a possible implementation, the arrangement module includes:

[0257] A first determination unit, configured to determine the signal path of each signal line in the signal line group according to the planned path of the signal line group in the chip;

[0258] A second determination unit, configured to determine the positions of at least two inverters in the signal path of each signal line;

[0259] A setting unit, configured to set at least two inverters in the chip according to the setting positions;

[0260] The first layout unit is configured to sequentially layout each signal line in the signal line group on the chip according to the signal path of each signal line, and each signal line is connected in series with each inverter in the signal path.

[0261] In a possible implementation, the second determination unit includes:

[0262] The first determination subunit is configured to determine the driving distance of the inverter;

[0263] The second determination subunit is configured to determine a preset distance according to the driving distance;

[0264] The third determination subunit is configured to determine the setting positions of each inverter in each signal line in the signal line group according to the preset distance and the driving distance in the signal path of each signal line.

[0265] In a possible implementation, the third determination subunit is specifically configured to:

[0266] According to the starting position of the signal line group in the chip and the signal path of each signal line, determine the first setting position of the first-stage inverter in the signal path of each signal line in the signal line group;

[0267] In the first signal path of the first signal line, according to the driving distance of the inverter, sequentially determine the setting positions of at least one inverter after the first-stage inverter in the first signal path;

[0268] In the second signal path of the second signal line, determine the second setting position of the second-stage inverter at a position spaced from the first-stage inverter by the preset distance; according to the driving distance of the inverter, sequentially determine the setting positions of at least one inverter after the second setting position in the second signal path; the first signal line and the second signal line are adjacent.

[0269] In a possible implementation, the third determination subunit is specifically configured to:

[0270] According to the starting position of the signal line group in the chip, the third signal path of the third signal line, and the driving distance of the inverter, determine a third setting position spaced from the starting position by the driving distance in the third signal path, and the third setting position is used to set the first-stage inverter; according to the driving distance of the inverter, sequentially determine the setting positions of at least one inverter after the third setting position in the third signal path;

[0271] According to the starting position of the signal line group in the chip, the fourth signal path of the fourth signal line, and the preset distance, in the fourth signal path, determine a fourth setting position that is spaced from the starting position by the preset distance, and the fourth setting position is used to set the first-stage inverter; according to the driving distance of the inverter, successively determine the setting positions of at least one inverter after the first-stage inverter in the fourth signal path; the third signal line and the fourth signal line are adjacent.

[0272] In a possible implementation, the layout module includes:

[0273] A statistics unit for statistically calculating the target length of the planned path of the signal line group;

[0274] A third determination unit for determining the type of the signal line group;

[0275] A second layout unit for, based on the target length being greater than the length threshold and the type of the signal line group being a high-speed bus, layout the signal line group in the chip according to the planned path of the signal line group.

[0276] In a possible implementation, the layout module includes:

[0277] A fourth determination unit for determining the driving distance of the inverter;

[0278] A fifth determination unit for determining the preset distance according to the driving distance;

[0279] A sixth determination unit for determining the setting positions of each inverter in the fifth signal line, where the distance between the fifth signal line and the target signal line in the signal line group is less than a preset distance threshold, the fifth signal line does not belong to the signal line group, and the target signal line is adjacent to the fifth signal line;

[0280] A seventh determination unit for determining the setting positions of each inverter in each signal line in the signal line group according to the setting positions of each inverter in the fifth signal line, the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance.

[0281] In a possible implementation, the layout module includes:

[0282] An eighth determination unit for determining the driving distance of the inverter;

[0283] A ninth determination unit for determining the preset distance according to the driving distance;

[0284] A tenth determination unit, configured to determine the setting positions of inverters for each signal line in the signal line sets located in different wiring layers in the signal line group according to the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter, and the preset distance. The signal line group includes at least two signal line sets located in different wiring layers. The setting positions of the inverters in any two adjacent signal lines in the same signal line set are spaced apart by a preset distance along the direction of the planned path.

[0285] In a possible implementation, the second determination subunit is specifically configured to:

[0286] Determine half of the driving distance as the preset distance.

[0287] It should be noted that for the function explanations of the components in a chip wiring design device provided in the embodiments of the present application, please refer to the explanations in the foregoing method embodiments, and will not be elaborated in this embodiment.

[0288] In this embodiment, a determination module is configured to determine the planned path of the signal line group in the chip according to the starting position and the ending position of the signal line group in the chip and the chip layout information; an arrangement module is configured to arrange the signal line group in the chip according to the planned path of the signal line group. The signal line group includes several signal lines. The setting positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance along the direction of the planned path. By spacing the setting positions of the inverters in any two adjacent signal lines in the signal line group by a preset distance, the crosstalk between adjacent signal lines is reduced, and the timing analysis result of the signal transmitted on the signal line is improved.

[0289] An electronic device is further provided in the embodiments of the present application. Refer to Figure 17 As shown, it shows a schematic structural diagram of an electronic device suitable for implementing the chip wiring design method in the embodiments of the present application. The electronic device in the embodiments of the present application may include, but is not limited to, fixed terminals such as mobile phones, laptop computers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), desktop computers, and the like. Figure 17 The shown electronic device is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0290] Such as Figure 17As shown, the electronic device may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 1701, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1702 or a program loaded from a storage device 1708 into a random access memory (RAM) 1703. When the electronic device is powered on, various programs and data required for the operation of the electronic device are also stored in the RAM 1703. The processing device 1701, the ROM 1702, and the RAM 1703 are connected to each other through a bus 1704. An input / output (I / O) interface 1705 is also connected to the bus 1704.

[0291] Generally, the following devices may be connected to the I / O interface 1705: an input device 1706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1708 including, for example, a memory card, a hard disk, etc.; and a communication device 1709. The communication device 1709 may allow the electronic device to communicate with other devices wirelessly or wireline to exchange data. Although Figure 17 an electronic device with various devices is shown, it should be understood that it is not required to implement or include all the shown devices. Instead, more or fewer devices may be implemented or included.

[0292] An embodiment of the present application also provides a computer program product including computer-readable instructions, which, when running on an electronic device, enable the electronic device to implement any one of the chip wiring design methods provided by the embodiments of the present application.

[0293] An embodiment of the present application also provides a computer-readable storage medium carrying one or more computer programs, which, when executed by an electronic device, can enable the electronic device to implement any one of the chip wiring design methods provided by the embodiments of the present application.

[0294] In addition, it should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the device embodiments provided in the present application, the connection relationship between the modules indicates that they have a communication connection, which may be specifically implemented as one or more communication buses or signal lines.

[0295] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions accomplished by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be diverse, such as analog circuits, digital circuits, or dedicated circuits. However, for this application, software program implementation is a better embodiment in more cases. Based on such an understanding, the technical solution of this application, in essence or the part that makes contributions to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disc of a computer, and includes several instructions for causing a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods described in various embodiments of this application.

[0296] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0297] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, computer, training device, or data center to another website, computer, training device, or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can store, or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state drive (SSD)).

Claims

1. A chip wiring design method, comprising: Determining a planned path of the signal line group in the chip according to the starting position and the ending position of the signal line group in the chip and the chip layout information; The signal line group is arranged on a chip according to a planned path of the signal line group, wherein the signal line group includes a plurality of signal lines; the inverters in any two adjacent signal lines in the signal line group are arranged at positions spaced by a preset distance in a direction along the planned path.

2. The chip wiring design method according to claim 1, wherein the step of arranging the signal line group on the chip according to the planned path of the signal line group comprises: Determining a signal path of each signal line in the signal line group according to a planned path of the signal line group in the chip; In a signal path of each signal line, determining a setting position of at least two inverters; According to the setting position, at least two inverters are set in the chip; According to the signal path of each signal line, each signal line in the signal line group is arranged in sequence on the chip, and each signal line is connected in series with each inverter in the signal path.

3. The chip wiring design method according to claim 2, wherein determining the locations of at least two inverters in the signal path of each signal line comprises: Determine the drive distance of the inverter; determining a preset distance according to the driving distance; In the signal path of each signal line, the arrangement position of each inverter in each signal line in the signal line group is determined according to the preset distance and the driving distance.

4. The chip wiring design method according to claim 3, wherein in the signal path of each signal line, determining the setting position of each inverter in each signal line in the signal line group according to the preset distance and the driving distance comprises: Determining a first setting position of a first-stage inverter in the signal path of each signal line in the signal line group according to a starting position of the signal line group in the chip and a signal path of each signal line; In a first signal path of a first signal line, determining a setting position of at least one inverter after a first-stage inverter of the first signal path in sequence according to a driving distance of the inverter; In a second signal path of the second signal line, determining a position spaced apart from the first-stage inverter by the preset distance as a second setting position of the second-stage inverter; According to the driving distance of the inverter, the setting position of at least one inverter is determined after the second setting position in the second signal path in sequence; the first signal line and the second signal line are adjacent.

5. The chip wiring design method according to claim 3, wherein in the signal path of each signal line, determining the setting position of each inverter in each signal line in the signal line group according to the preset distance and the driving distance comprises: According to the starting position of the signal line group in the chip, the third signal path of the third signal line, and the driving distance of the inverter, in the third signal path, a third setting position spaced from the starting position by the driving distance is determined, and the third setting position is used to set the first-stage inverter; according to the driving distance of the inverter, the setting position of at least one inverter is determined sequentially after the third setting position of the third signal path; According to the starting position of the signal line group in the chip, the fourth signal path of the fourth signal line and the preset distance, in the fourth signal path, a fourth setting position spaced from the starting position by the preset distance is determined, and the fourth setting position is used to set the first-stage inverter; According to the driving distance of the inverter, the setting position of at least one inverter is determined sequentially after the first-stage inverter of the fourth signal path; the third signal line and the fourth signal line are adjacent.

6. The chip wiring design method according to claim 1, wherein the step of arranging the signal line group on the chip according to the planned path of the signal line group comprises: Counting the target length of the planned path of the signal line group; determining a type of the signal line group; Based on the target length being greater than a length threshold and the type of the signal line group being a high-speed bus, the signal line group is arranged on a chip according to a planned path of the signal line group.

7. The chip wiring design method according to claim 1, wherein the step of arranging the signal line group on the chip according to the planned path of the signal line group comprises: Determine the drive distance of the inverter; determining the preset distance according to the driving distance; Determine the location of each inverter in the fifth signal line, the distance between the fifth signal line and the target signal line in the signal line group is less than a preset distance threshold, the fifth signal line does not belong to the signal line group, and the target signal line is adjacent to the fifth signal line; The setting position of each inverter in each signal line in the signal line group is determined according to the setting position of each inverter in the fifth signal line, the starting position of the signal line group in the chip, the planned path, the driving distance of the inverter and the preset distance.

8. The chip wiring design method according to claim 1, wherein the step of arranging the signal line group on the chip according to the planned path of the signal line group comprises: Determine the drive distance of the inverter; determining the preset distance according to the driving distance; Based on the starting position of the signal line group in the chip and the planned path, the driving distance of the inverter and the preset distance, the setting position of each inverter of each signal line in the signal line set located in different wiring layers in the signal line group is determined, the signal line group includes at least two signal line sets located in different wiring layers, and the setting positions of the inverters in any two adjacent signal lines in the same signal line set are spaced apart by a preset distance in the direction along the planned path.

9. The chip wiring design method according to any one of claims 3 to 8, wherein determining the preset distance according to the driving distance comprises: Half of the driving distance is determined as the preset distance.

10. A chip, comprising: At least two modules; A signal line group, wherein the signal line group comprises a plurality of signal lines, wherein the setting positions of the inverters in any two adjacent signal lines in the signal line group are spaced apart by a preset distance in the direction of the planned path, wherein the starting position of the signal line group is in a first module, and the ending position of the signal line group is in a second module, and the first module and the second module belong to the at least two modules.

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