SiC epitaxial wafer and preparation method thereof

Abstract

The invention provides a SiC epitaxial wafer and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to reduce the defect density of the SiC epitaxial wafer, and the SiC epitaxial wafer comprises a SiC substrate and an epitaxial layer arranged on one side of the SiC substrate. The epitaxial layer comprises a C surface and a Si surface which are oppositely arranged, any one of the C surface and the Si surface is close to the SiC substrate, the thickness range of the epitaxial layer is 50-500 microns, and the defect density range of the epitaxial layer is 0.02 / cm < 2 >-1 / cm < 2 >.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and particularly to a SiC epitaxial wafer and a method for preparing the same. Background Art

[0002] The breakdown voltage level of a silicon carbide device is proportional to the thickness of the epitaxial layer on the silicon carbide substrate. For high-voltage silicon carbide devices with a breakdown voltage specification of several thousand volts to several tens of thousand volts, the thickness of the SiC epitaxial wafer needs to be between several tens of micrometers and several hundreds of micrometers. A large number of defects (such as triangular defects, carrot defects, large pits, stacking faults, basal plane dislocations, through defects) will cause local high electric field aggregation in the SiC epitaxial wafer, resulting in a lower breakdown voltage, an increased leakage current, and a reduced thermal stability of the silicon carbide device, thereby reducing the overall reliability and performance of the silicon carbide device. Therefore, a SiC epitaxial wafer with a low defect density is the key to high-voltage silicon carbide devices. Summary of the Invention

[0003] Embodiments of the present disclosure provide a SiC epitaxial wafer and a method for preparing the same, aiming to reduce the defect density of the SiC epitaxial wafer.

[0004] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a SiC epitaxial wafer is provided. The SiC epitaxial wafer includes: a SiC substrate and an epitaxial layer disposed on one side of the SiC substrate. The epitaxial layer includes: a C plane and a Si plane that are oppositely arranged. Either the C plane or the Si plane is close to the SiC substrate. The thickness range of the epitaxial layer is 50 μm to 500 μm.

[0005] Wherein, the defect density range of the epitaxial layer is 0.02 / cm 2 ~1 / cm 2 .

[0006] The thickness range of the epitaxial layer of the SiC epitaxial wafer provided by the above embodiments of the present disclosure is 50 μm to 500 μm, enabling the SiC epitaxial wafer to withstand a relatively high electric field strength, thereby reducing the risk of breakdown caused by local electric field concentration, and enabling the silicon carbide device fabricated from the SiC epitaxial wafer to have a relatively high breakdown voltage. At the same time, the epitaxial layer has two crystal plane structures, namely the C plane and the Si plane. The selection of the SiC epitaxial wafer with the Si plane epitaxy and the SiC epitaxial wafer with the C plane epitaxy will affect the manufacturing process of the silicon carbide device and the performance of the silicon carbide device, making the SiC epitaxial wafer suitable for different application scenarios. Among them, the SiC epitaxial wafer with the C plane away from the SiC substrate is applied to the silicon carbide device, making the silicon carbide device have advantages in performance. For example, when the SiC epitaxial wafer with the C plane away from the SiC substrate is applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the channel mobility of the MOSFET can be improved.

[0007] Moreover, the defect density range of the epitaxial layer is 0.02 / cm 2 ~1 / cm 2 , indicating that the SiC epitaxial wafer has fewer defects. Fewer defects (such as triangular defects, carrot defects, large pits, stacking faults, basal plane dislocations, through defects) can reduce the local high electric field aggregation in the silicon carbide device, improve the breakdown voltage, reduce the leakage current, and improve the thermal stability of the silicon carbide device, ensuring the quality of the SiC epitaxial wafer, thereby improving the overall reliability and performance of the silicon carbide device.

[0008] In some embodiments, the material of the epitaxial layer includes: nitrogen atoms. In the epitaxial layer, the doping concentration range of nitrogen atoms is 1×10 14 cm -3 ~1×10 17 cm -3 .

[0009] In some embodiments, the surface roughness range of the epitaxial layer is 0.1 nm to 1 nm.

[0010] In some embodiments, the thickness range of the epitaxial layer is 100 μm to 200 μm.

[0011] On the other hand, a method for fabricating a SiC epitaxial wafer is provided. The method for fabricating the SiC epitaxial wafer includes: First epitaxy, forming an epitaxial sublayer on one side of a first SiC substrate.

[0012] First bonding, bonding a second SiC substrate on the side of the epitaxial sublayer away from the first SiC substrate.

[0013] First peeling, peeling off the first SiC substrate.

[0014] In the first cycle, the first epitaxy is repeated to obtain a second epitaxial sublayer connected to the first SiC substrate.

[0015] In the second bonding, the second epitaxial sublayer connected to the first SiC substrate is bonded to the epitaxial sublayer connected to the second SiC substrate to obtain a first bonded epitaxial wafer.

[0016] In the second peeling, one of the second SiC substrate and the first SiC substrate in the first bonded epitaxial wafer is peeled off to obtain an initial SiC epitaxial wafer.

[0017] In heat treatment or laser treatment, under an inert gas condition, the initial SiC epitaxial wafer is recrystallized by heat treatment or laser treatment to obtain a SiC epitaxial wafer.

[0018] It can be understood that in the method for preparing a SiC epitaxial wafer provided by the above embodiments of the present disclosure, multiple single-layer epitaxial sublayers are bonded together. The bulk defect density and distribution of the bonded SiC epitaxial wafer can be obtained from the defect density and distribution of the single-layer epitaxial sublayers, and the defect distributions of different single-layer epitaxial sublayers are different, so that the through defects of the SiC epitaxial wafer prepared in the present disclosure are less. Through heat treatment or laser treatment, the bonding interface between adjacent epitaxial sublayers can be recrystallized to eliminate interface defects, and a SiC epitaxial wafer with a flat surface and a low defect density can be obtained to solve the problems of rough surface and many defects of the SiC epitaxial wafer directly grown on the SiC substrate, thereby improving the reliability of the silicon carbide device. Moreover, the doping concentration uniformity of the single-layer epitaxial sublayer before bonding in the present disclosure is good, that is, the doping concentration uniformity of each epitaxial sublayer in multiple single-layer epitaxial sublayers is good, so that the doping concentration uniformity of the bonded epitaxial layer is equivalent to the doping concentration uniformity of the single-layer epitaxial sublayer, and an epitaxial layer with good doping concentration uniformity is obtained, which is better than the doping uniformity of the directly grown epitaxial layer.

[0019] In some embodiments, in the second peeling, the second SiC substrate in the first bonded epitaxial wafer is peeled off; before heat treatment or laser treatment, it further includes: In the second cycle, the first epitaxy, the first bonding and the first peeling are repeated to obtain a second epitaxial sublayer connected to the second SiC substrate.

[0020] In the third bonding, the second epitaxial sublayer connected to the second SiC substrate is bonded to the epitaxial sublayer far from the first SiC substrate in the initial SiC epitaxial wafer to obtain a second bonded epitaxial wafer.

[0021] In the third peeling, the second SiC substrate in the second bonded epitaxial wafer is peeled off to obtain another initial SiC epitaxial wafer.

[0022] In some embodiments, before heat treatment or laser treatment, it further includes: Repeat the second cycle, the third bonding, and the third stripping n times, where n ranges from 1 to 20.

[0023] In some embodiments, in the second stripping, strip the first SiC substrate in the first bonded epitaxial wafer; before the heat treatment or laser treatment, further include: The third cycle, repeat the first epitaxy to obtain a third epitaxial sublayer connected to the first SiC substrate.

[0024] The fourth bonding, bond the third epitaxial sublayer connected to the first SiC substrate with the epitaxial sublayer far from the second SiC substrate in the initial SiC epitaxial wafer to obtain a third bonded epitaxial wafer.

[0025] The fourth stripping, strip the first SiC substrate in the third bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

[0026] In some embodiments, before the heat treatment or laser treatment, further include: Repeat the third cycle, the fourth bonding, and the fourth stripping n times, where n ranges from 1 to 20.

[0027] In some embodiments, the conditions for the heat treatment are: in an inert atmosphere, at a temperature range of 1400 °C to 2000 °C, and treat for 10 min to 120 min.

[0028] In some embodiments, the power range of the laser treatment is 10 4 W / cm 2 ~10 6 W / cm 2 .

[0029] In some embodiments, the time range of the laser treatment is 10 min to 120 min.

[0030] In some embodiments, the first epitaxy includes: Form a buffer layer on one side of the first SiC substrate.

[0031] Form an epitaxial sublayer on the side of the buffer layer far from the first SiC substrate.

[0032] In stripping the first SiC substrate, further include: removing the buffer layer.

[0033] In some embodiments, the thickness range of the epitaxial sublayer is 10 μm to 80 μm. Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the accompanying drawings required for use in some embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, etc.

[0035] Figure 1 FIG. is a schematic structural diagram of a SiC epitaxial wafer provided according to some embodiments of the present disclosure; Figure 2 FIG. is a schematic structural diagram of a SiC epitaxial wafer provided according to some other embodiments of the present disclosure; Figure 3 FIG. is a relationship diagram between the thickness of an epitaxial layer and the occurrence frequency of triangular defects provided according to some examples of the present disclosure; Figure 4 FIG. is a correlation diagram between the surface roughness of an epitaxial layer and the number of triangular defects provided according to some examples of the present disclosure; Figure 5 FIG. is a flowchart of a method for preparing a SiC epitaxial wafer provided according to some embodiments of the present disclosure; Figure 6 FIG. is a structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided according to some embodiments of the present disclosure; Figure 7 FIG. is another structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided according to some embodiments of the present disclosure; Figure 8 FIG. is yet another structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided according to some embodiments of the present disclosure; Figure 9 FIG. is yet another structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided according to some embodiments of the present disclosure; Figure 10 FIG. is a structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided according to Embodiment 1 of the present disclosure; Figure 11 FIG. is a structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided according to Embodiment 2 of the present disclosure; Figure 12 FIG. is a surface defect diagram of a SiC epitaxial wafer provided according to some embodiments of the present disclosure. Detailed Embodiments

[0036] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0037] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplary" or "some examples", etc., are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0038] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0039] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0040] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0041] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0042] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The materials added on the substrate can be patterned or can remain unpatterned. In addition, the substrate can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0043] In addition, in the present disclosure, orientation terms such as "upper" and "lower" are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and they can change accordingly with the change of the orientation in which the components in the drawings are placed.

[0044] The technical solutions of the present disclosure can be applied to electronic devices, which are different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices; the electronic devices can also be network devices such as base stations. The electronic device can also be a device such as a power amplifier used in the above-mentioned electronic devices. The specific form of the above-mentioned electronic devices is not particularly limited in the embodiments of the present disclosure.

[0045] It should be noted that, for example, 1 / 2 appearing in the drawings of the present disclosure means that both component 1 and component 2 can refer to this component. For example, Figure 2 10 / 10A in the drawings means that both the SiC epitaxial wafer 10 and the Si-face epitaxial SiC epitaxial wafer 10A can be represented by this component. Other similar reference numerals appearing in the drawings also follow the above description.

[0046] Silicon carbide (SiC) semiconductor material is an important third-generation semiconductor material, which has the advantages of large bandgap width, high breakdown field strength, and high thermal conductivity. SiC devices have currently been widely used in high-voltage power systems such as high-voltage power transmission, communication power supplies, and new energy electric vehicles. The thin film materials used for the manufacture of SiC devices need to have high crystal quality, good doping concentration uniformity, and low thin film defect density.

[0047] The breakdown voltage level of the SiC device is proportional to the thickness of the epitaxial layer 2 on the SiC substrate 1 (as Figure 1 shown). For high-voltage SiC devices with a breakdown voltage specification of several thousand volts to tens of thousands of volts, the thickness of the SiC epitaxial wafer 10 needs to be between dozens of microns and hundreds of microns. More defects (such as dislocations, gap defects, and through defects) will cause local high electric field aggregation in the SiC epitaxial wafer 10, resulting in a lower breakdown voltage, an increase in leakage current, and a decrease in the thermal stability of the SiC device in the SiC epitaxial wafer 10, thereby reducing the overall reliability and performance of the SiC device. Therefore, the SiC epitaxial wafer with a low defect density is the key to high-voltage SiC devices.

[0048] Moreover, the SiC epitaxial wafer 10 includes: a SiC epitaxial wafer 10A epitaxially grown on the Si face and a SiC epitaxial wafer 10B epitaxially grown on the C face. In the SiC epitaxial wafer 10A epitaxially grown on the Si face, the surface of the epitaxial layer 2 away from the SiC substrate 1 is the Si face; in the SiC epitaxial wafer 10B epitaxially grown on the C face, the surface of the epitaxial layer 2 away from the SiC substrate 1 is the C face. Among them, the C face refers to the (000-1) face of silicon carbide, and the termination atom of this surface is a carbon atom. The Si face refers to the (0001) crystal plane of the silicon carbide wafer, and the termination atom of this surface is a silicon atom. The selection of the SiC epitaxial wafer 10A epitaxially grown on the Si face and the SiC epitaxial wafer 10B epitaxially grown on the C face will affect the manufacturing process of silicon carbide devices and the performance of silicon carbide devices.

[0049] In some embodiments, the SiC epitaxial wafer 10 is a SiC epitaxial wafer 10A epitaxially grown on the Si face. However, the advantage of the SiC epitaxial wafer 10B epitaxially grown on the C face compared to the SiC epitaxial wafer 10A epitaxially grown on the Si face is that the channel mobility of the MOSFET fabricated with the SiC epitaxial wafer 10B epitaxially grown on the C face can be increased from 25 cm 2 / V·s to about 100 cm 2 / V·s. Therefore, the SiC epitaxial wafer 10B epitaxially grown on the C face with higher quality is one of the key technologies for improving the ultra-high voltage withstand silicon carbide MOSFET device.

[0050] In some implementation manners, the SiC epitaxial wafer 10 can be prepared by directly growing an epitaxial layer 2 with a preset thickness on the SiC substrate 1. However, affected by the stability of the growth reactor of the epitaxial layer 2 of the SiC epitaxial wafer 10 and the deposition layer of the graphite component, during the growth of the epitaxial layer 2, as the thickness of the epitaxial layer 2 increases, the number of fatal defects such as triangular defects and dropout defects will increase significantly. At the same time, as the thickness of the epitaxial layer 2 increases, the size of the fatal defects also gradually becomes larger, which will lead to a reduction in the yield of the SiC epitaxial wafer 10. The defects of the epitaxial layer 2 can be reduced by optimizing the growth conditions of the epitaxial layer 2, and at the same time, the cleanliness of the graphite fittings in the reaction chamber is ensured to improve the yield of the SiC epitaxial wafer 10.

[0051] In some examples, in a chemical vapor deposition (CVD) epitaxial device, the epitaxial layer 2 is directly grown on the SiC substrate 1, and the triangular defects on the surface of the epitaxial layer 2 are reduced by controlling the surface roughness of the epitaxial layer 2 (18 μm to 350 μm) to improve the yield of the SiC epitaxial wafer 10; as Figure 3 shown, Figure 3 is a relationship diagram of the thickness of an epitaxial layer and the occurrence frequency of triangular defects provided for some examples. It can be seen that if the thickness of the epitaxial layer 2 is above 18 μm, the occurrence frequency of triangular defects increases significantly. Figure 4Graph showing the correlation between the surface roughness of an epitaxial layer and the number of triangular defects for some examples Figure 4 The vertical axis of Figure 4 represents the number of triangular defects per wafer [defects / wf] seen on the surface of the epitaxial layer 2 when an epitaxial layer 2 with a thickness of 18 μm or more is formed on a 4-inch SiC substrate 1. Figure 4 The horizontal axis of Figure 4 represents the arithmetic mean roughness (Ra) of the entire surface of the epitaxial layer 2 of the SiC epitaxial wafer 10. It can be seen that if the arithmetic mean roughness (Ra) of the entire surface of the epitaxial layer 2 becomes larger, the triangular defects also increase significantly; moreover, the growth window of this method is small; there are differences in the optimal epitaxial conditions and rules for different types of epitaxial growth equipment.

[0052] At the same time, when growing the thickness of the epitaxial layer 2 of the SiC epitaxial wafer 10 (for example, thickness > 100 μm), the thickness of the epitaxial layer 2 and the thickness of the SiC substrate 1 are in the same order of magnitude, which will cause a large stress on the SiC substrate 1 during the growth of the epitaxial layer 2, resulting in warping of the epitaxial layer 2, making the temperature difference within the SiC epitaxial wafer 10 different, and making it difficult to control the doping uniformity of the epitaxial layer 2. At the same time, the growth of the epitaxial layer 2 of the SiC epitaxial wafer 10 is restricted by the equipment hardware and the stress and defect evolution during epitaxial growth. It is difficult to prepare a SiC epitaxial wafer 10 with high quality, and as the thickness of the epitaxial layer 2 increases, the preparation difficulty also increases exponentially.

[0053] Based on this, an embodiment of the present disclosure provides a method for preparing a SiC epitaxial wafer 10. As Figures 5 - 7 shown, the method for preparing the SiC epitaxial wafer includes: S1: First epitaxy, forming an epitaxial sub-layer 21 on one side of the first SiC substrate 11.

[0054] Exemplarily, the first SiC substrate 11 can be any one of a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, and a polycrystalline SiC substrate.

[0055] Exemplarily, when forming the epitaxial sub-layer 21 on one side of the first SiC substrate 11, the surface of the epitaxial sub-layer 21 away from the first SiC substrate 11 is the Si face, and an epitaxial sub-layer 21 epitaxially grown on the Si face can be formed.

[0056] Exemplarily, the thickness range of the epitaxial sub-layer 21 is 10 μm to 80 μm.

[0057] Exemplarily, the thickness of the epitaxial sub-layer 21 can be 10 μm, 30 μm, 50 μm, 70 μm, or 80 μm, and there is no limitation here.

[0058] In some embodiments, in combination with Figure 2 , as Figure 6 and Figure 7As shown, the first epitaxy S1 includes the following steps (1) and (2).

[0059] (1) Form a buffer layer 3 on one side of the first SiC substrate 11.

[0060] (2) Form an epitaxial sublayer 21 on the side of the buffer layer 3 away from the first SiC substrate 11.

[0061] Exemplarily, SiHCl3, C3H8, and N2 are introduced within the range of 1550 °C to 1700 °C to grow a buffer layer 3 with a thickness range of 1 μm to 20 μm and a doping concentration range of 1×10 17 cm -3 ~2×10 19 cm -3 This can make the first SiC substrate 11 and the epitaxial layer 2 more matched, help form a transition zone between the first SiC substrate 11 and the epitaxial layer 2, thereby reducing the stress caused by lattice mismatch and reducing the defects during the growth of the epitaxial layer 2; meanwhile, controlling the doping concentration range of the buffer layer 3 to be 1×10 17 cm -3 ~2×10 19 cm -3 can reduce the mismatch stress between the first SiC substrate 11 and the epitaxial layer 2 caused by the huge change in doping concentration, thereby reducing the defect density of the epitaxial layer 2.

[0062] S2: The first bonding. Bond a second SiC substrate 12 on the side of the epitaxial sublayer 21 away from the first SiC substrate 11.

[0063] Exemplarily, the second SiC substrate 12 can be any one of a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, and a polycrystalline SiC substrate.

[0064] Here, the materials of the first SiC substrate 11 and the second SiC substrate 12 can be the same or different.

[0065] S3: The first peeling. Peel off the first SiC substrate 11.

[0066] Exemplarily, for the first peeling in S3, laser peeling or mechanical grinding chemistry can be selected, and chemical mechanical polishing is used to remove peeling defects at the same time.

[0067] When forming a buffer layer 3 on one side of the first SiC substrate 11, during the peeling of the first SiC substrate 11, it further includes: removing the buffer layer 3.

[0068] Exemplarily, the method for removing the buffer layer 3 can be laser peeling or a grinding process.

[0069] S4: The first cycle, repeat the first epitaxy S1 to obtain a second epitaxial sublayer 21 connected to the first SiC substrate 11.

[0070] S5: The second bonding, bond the second epitaxial sublayer 21 connected to the first SiC substrate 11 with the epitaxial sublayer 21 connected to the second SiC substrate 12 to obtain the first bonded epitaxial wafer 101.

[0071] Exemplarily, in the first bonded epitaxial wafer 101, for the epitaxial sublayer 21 on the side close to the first SiC substrate 11, the surface of this epitaxial sublayer 21 close to the first SiC substrate 11 is the C plane; for the epitaxial sublayer 21 on the side close to the second SiC substrate 12, the surface of this epitaxial sublayer 21 close to the second SiC substrate 12 is the Si plane.

[0072] S6: The second peeling, peel off one of the second SiC substrate 12 (as shown in Figure 6 shown) and the first SiC substrate 11 (as shown in Figure 6 shown) in the first bonded epitaxial wafer 101 to obtain the initial SiC epitaxial wafer 102.

[0073] Exemplarily, the method of the second peeling can select laser peeling or mechanical grinding chemistry, and at the same time use chemical mechanical polishing to remove peeling defects.

[0074] Exemplarily, peeling off the second SiC substrate 12 in the first bonded epitaxial wafer 101 can obtain the initial SiC epitaxial wafer 102. At this time, the initial SiC epitaxial wafer 102 is the initial SiC epitaxial wafer 102A with Si-plane epitaxy.

[0075] Exemplarily, peeling off the first SiC substrate 11 in the first bonded epitaxial wafer 101 can obtain the initial SiC epitaxial wafer 102. At this time, the initial SiC epitaxial wafer 102 is the initial SiC epitaxial wafer 102B with C-plane epitaxy.

[0076] S7: Heat treatment or laser treatment, under the condition of inert gas, use heat treatment or laser treatment to recrystallize the initial SiC epitaxial wafer 102 to obtain the SiC epitaxial wafer 10.

[0077] Exemplarily, the conditions of the heat treatment are: in an inert atmosphere, the temperature range is 1400°C to 2000°C, and the treatment time is 10 min to 120 min.

[0078] Exemplarily, the temperature of the heat treatment can be 1400°C, 1600°C, 1800°C or 2000°C, etc., and there is no limit here.

[0079] Exemplarily, the time of the heat treatment can be 10 min, 50 min, 90 min or 120 min, etc., and there is no limit here.

[0080] Exemplarily, the inert atmosphere can be any one of argon and nitrogen.

[0081] It can be understood that after heat treatment, the interface defect Q formed by the bonding of the epitaxial sub-layers 21 in the initial SiC epitaxial wafer 102 disappears after recrystallization by heat treatment or laser treatment.

[0082] Exemplarily, the power range of the laser treatment is 10 4 W / cm 2 ~10 6 W / cm 2 .

[0083] Exemplarily, the power of the laser treatment can be 5×10 4 W / cm 2 , 10 5 W / cm 2 , 2×10 5 W / cm 2 , or 10 6 W / cm 2 etc., and there is no limitation here.

[0084] Exemplarily, the time range of the laser treatment is 10 min to 120 min.

[0085] Exemplarily, the time of the laser treatment can be 10 min, 30 min, 50 min, 70 min, 100 min, 120 min, etc., and there is no limitation here.

[0086] Exemplarily, subjecting the initial SiC epitaxial wafer 102A with Si-face epitaxy to S7 heat treatment or laser treatment can obtain a SiC epitaxial wafer 10A with Si-face epitaxy.

[0087] Exemplarily, subjecting the initial SiC epitaxial wafer 102B with C-face epitaxy to S7 heat treatment or laser treatment can obtain a SiC epitaxial wafer 10B with C-face epitaxy.

[0088] It can be understood that by bonding multiple single-layer epitaxial sub-layers 21 together, the bulk defect density and distribution of the obtained SiC epitaxial wafer 10 can be obtained from the defect density and distribution of the single-layer epitaxial sub-layers 21, and the defect distributions of different single-layer epitaxial sub-layers 21 are different, so that the through defects in the epitaxial layer 2 of the SiC epitaxial wafer 10 prepared in the present disclosure are less, and the bonding interface between adjacent epitaxial sub-layers 21 can be recrystallized by heat treatment or laser treatment to eliminate the interface defect Q, obtaining a SiC epitaxial wafer 10 with a flat surface and a low defect density, solving the problems of large surface roughness and increased defects of the SiC epitaxial wafer 10 caused by directly growing the epitaxial layer 2 on the SiC substrate 1, thereby improving the reliability of the silicon carbide device.

[0089] Moreover, the doping concentration uniformity of the epitaxial sub-layer 21 of the single layer before bonding is relatively good, that is, the doping concentration uniformity of each epitaxial sub-layer 21 in multiple single-layer epitaxial sub-layers 21 is relatively good, so that the doping concentration uniformity of the obtained epitaxial layer 2 after bonding is equivalent to that of the single-layer epitaxial sub-layer 21, and an epitaxial layer 2 with relatively good doping concentration uniformity is obtained, which is better than the doping uniformity of directly growing a relatively thick epitaxial layer 2.

[0090] In some embodiments, in the second stripping of S6, the second SiC substrate 12 in the first bonded epitaxial wafer 101 is stripped; before the heat treatment or laser treatment in S7, as Figure 8 shown, steps S4.1 to S6.1 are further included.

[0091] S4.1: Second cycle, repeating the first epitaxy S1, the first bonding S2, and the first stripping S3 to obtain a second epitaxial sub-layer 21 connected to the second SiC substrate 12.

[0092] S5.1: Third bonding, bonding the second epitaxial sub-layer 21 connected to the second SiC substrate 12 to the epitaxial sub-layer 21 far from the first SiC substrate 11 in the initial SiC epitaxial wafer 102 to obtain a second bonded epitaxial wafer 101A.

[0093] S6.1: Third stripping, stripping the second SiC substrate 12 in the second bonded epitaxial wafer 101A to obtain another initial SiC epitaxial wafer 102A with Si-face epitaxy.

[0094] In some embodiments, before the heat treatment or laser treatment in S7, it further includes: repeating the second cycle S4.1, the third bonding S5.1, and the third stripping S6.1 n times, where the value range of n is 1 to 20.

[0095] Exemplarily, the value of n can be 1, 3, 5, 7, 10, 15, or 20, etc., and there is no limitation here.

[0096] It can be understood that through the above n cycles, an initial SiC epitaxial wafer 102A with Si-face epitaxy in which n + 3 epitaxial sub-layers 21 are overlapped can be obtained. After the heat treatment or laser treatment in S7, the interfacial defect Q between the epitaxial sub-layers 21 is eliminated, and a SiC epitaxial wafer 10A with Si-face epitaxy and an expected thickness can be obtained as needed.

[0097] In some embodiments, in the second stripping of S6, the first SiC substrate 11 in the first bonded epitaxial wafer 101 is stripped; before the heat treatment or laser treatment in S7, as Figure 9 shown, steps S4.2 to S6.2 are further included.

[0098] S4.2: The third cycle, repeating the first epitaxy S1, to obtain the third epitaxial sub-layer 21 connecting the first SiC substrate 11.

[0099] S5.2: The fourth bonding, bonding the third epitaxial sub-layer 21 connecting the first SiC substrate 11 with the epitaxial sub-layer 21 far from the second SiC substrate 12 in the initial SiC epitaxial wafer 102, to obtain the third bonded epitaxial wafer 101B.

[0100] S6.2: The fourth stripping, stripping the first SiC substrate 11 in the third bonded epitaxial wafer 101B, to obtain another initial SiC epitaxial wafer 102B with C-plane epitaxy.

[0101] In some embodiments, before the S7 heat treatment or laser treatment, it further includes: repeating the third cycle of S4.2, the fourth bonding of S5.2 and the fourth stripping of S6.2 for n times, where n ranges from 1 to 20.

[0102] Exemplarily, the value of n can be 1, 3, 5, 7, 10, 15 or 20, etc., and there is no limitation here.

[0103] It can be understood that through the above n cycles, an initial SiC epitaxial wafer 102B with C-plane epitaxy having n + 3 epitaxial sub-layers 21 overlapping can be obtained. After the S7 heat treatment or laser treatment, the interface defect Q between the epitaxial sub-layers 21 is eliminated, and a SiC epitaxial wafer 10B with the desired thickness and C-plane epitaxy can be obtained as needed.

[0104] Embodiments of the present disclosure provide a SiC epitaxial wafer 10. As Figure 1 and Figure 2 shown, the SiC epitaxial wafer 10 includes: a SiC substrate 1 and an epitaxial layer 2 provided on one side of the SiC substrate 1. The epitaxial layer 2 includes: a C-plane and a Si-plane arranged oppositely. Either the C-plane or the Si-plane is close to the SiC substrate 1. The thickness D of the epitaxial layer 2 ranges from 50 μm to 500 μm.

[0105] Exemplarily, as Figure 1 shown, the epitaxial layer 2 is an epitaxial layer 2 with C-plane epitaxy.

[0106] Exemplarily, as Figure 2 shown, the epitaxial layer 2 is an epitaxial layer 2 with Si-plane epitaxy.

[0107] Exemplarily, the thickness D of the epitaxial layer 2 can range from 50 μm, 150 μm, 250 μm, 350 μm, 450 μm or 500 μm, etc., and there is no limitation here.

[0108] Among them, the defect density of the epitaxial layer 2 ranges from 0.02 / cm 2 ~1 / cm 2 .

[0109] Exemplarily, the defects of the epitaxial layer 2 can be triangular defects, carrot defects, large pits, stacking faults, basal plane dislocations, without limitation here.

[0110] Exemplarily, the defect density of the epitaxial layer 2 can be 0.02 / cm 2 、0.1 / cm 2 、0.3 / cm 2 、0.5 / cm 2 、0.7 / cm 2 or 1 / cm 2 etc., without limitation here.

[0111] It can be understood that the SiC substrate is the basis for epitaxial growth, and the SiC substrate provides mechanical support and electrical properties.

[0112] The thickness range of the epitaxial layer 2 is from 50 μm to 500 μm, enabling the silicon carbide device to withstand a higher electric field strength, thereby reducing the risk of breakdown caused by local electric field concentration, and enabling the silicon carbide device fabricated from the SiC epitaxial wafer 10 to have a higher breakdown voltage. At the same time, the epitaxial layer 2 has two crystal plane structures, namely the C plane and the Si plane. The selection of the SiC epitaxial wafer 10A with Si plane epitaxy and the SiC epitaxial wafer 10B with C plane epitaxy will affect the manufacturing process of the silicon carbide device and the performance of the silicon carbide device, making the SiC epitaxial wafer 10 suitable for different application scenarios. Among them, the SiC epitaxial wafer 10B with C plane epitaxy is applied to the silicon carbide device, making the silicon carbide device have advantages in performance. For example, when the SiC epitaxial wafer 10B with C plane epitaxy is applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the channel mobility of the MOSFET can be improved.

[0113] Moreover, the defect density range of the epitaxial layer 2 is from 0.02 / cm 2 ~1 / cm 2 , indicating that the SiC epitaxial wafer 10 has fewer defects (such as triangular defects, carrot defects, large pits, stacking faults, basal plane dislocations, through defects), which can reduce the local high electric field aggregation of the silicon carbide device, improve the breakdown voltage, reduce the leakage current, and improve the thermal stability of the silicon carbide device, ensuring the quality of the SiC epitaxial wafer 10, thereby improving the overall reliability and performance of the silicon carbide device.

[0114] Here, the defect density can be obtained by testing with Lasertec SIGA 88 or KLA 8520.

[0115] In some embodiments, the material of the epitaxial layer 2 includes: nitrogen atoms. In the epitaxial layer 2, the doping concentration range of nitrogen atoms is 1×10 14 cm -3 ~1×10 17 cm -3 .

[0116] Among them, the material of the epitaxial layer 2 epitaxially grown on the SiC substrate 1 includes SiC, and the epitaxial layer 2 is also doped with nitrogen atoms. The radius of nitrogen atoms is close to that of carbon atoms, and it is easy to replace the carbon sites in the lattice, providing free electrons, thereby reducing the resistivity and improving the conductivity of the epitaxial layer 2.

[0117] Exemplarily, the doping concentration of nitrogen atoms can be 1×10 14 cm -3 、1×10 15 cm -3 、1×10 16 cm -3 or 1×10 17 cm -3 etc., and there is no limitation here.

[0118] It can be understood that nitrogen atoms, as n-type dopants, can provide extra free electrons to improve the conductivity of the SiC epitaxial wafer 10; that is, by controlling the doping concentration of nitrogen atoms within the range of 1×10 14 cm -3 ~1×10 17 cm -3 range, the conductive performance of the SiC epitaxial wafer 10 can be optimized, the efficiency of current passing through the SiC epitaxial wafer 10 and the thermal stability can be balanced, the recombination loss of carriers and the formation of defects can be reduced, the defect density of the epitaxial layer 2 can be further reduced, and thus the defect density of the SiC epitaxial wafer 10 can be reduced.

[0119] Here, the doping concentration of nitrogen atoms can be obtained by testing the voltage-current (IV) characteristics of a mercury (Hg) probe.

[0120] In some embodiments, the surface roughness Ra of the epitaxial layer 2 ranges from 0.1 nm to 1 nm.

[0121] Exemplarily, the surface roughness Ra of the epitaxial layer 2 can be 0.1 nm, 0.3 nm, 0.5 nm, 0.7 nm or 1 nm, etc., and there is no limitation here.

[0122] It can be understood that controlling the surface roughness Ra of the epitaxial layer 2 within the range of 0.1 nm to 1 nm (scanning range 5 μm × 5 μm) indicates that the roughness Ra of the SiC epitaxial wafer 10 is small, which helps to reduce the formation and propagation of crystal defects (such as dislocations and gap defects), improves the crystal structure quality of the epitaxial layer 2, and thus reduces the defect density.

[0123] Here, the surface roughness Ra can be obtained by testing with an atomic force microscope.

[0124] In some embodiments, the thickness range of the epitaxial layer 2 is 100 μm to 200 μm.

[0125] Exemplarily, the thickness of the epitaxial layer 2 can be 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, etc., and there is no limitation here.

[0126] It can be understood that controlling the thickness of the epitaxial layer 2 within the range of 100 μm to 200 μm can enable the silicon carbide device to have a high breakdown voltage capability, can effectively disperse the electric field, and reduce the possibility of local electric field concentration caused by defects, thereby improving the stability of the silicon carbide device.

[0127] Example 1: Example 1 provides a SiC epitaxial wafer 10, as Figure 10 shown, the preparation method of the SiC epitaxial wafer 10 includes the following steps (1A) to (8A).

[0128] (1A) Put the first SiC substrate 11 into high-temperature CVD, and process it for 15 minutes at 1630 °C in a hydrogen atmosphere to obtain a SiC surface with a clean surface and atomic steps.

[0129] For example, the first SiC substrate 11 is an 8-inch Si-face SiC substrate with high crystal quality.

[0130] (2A) Heat the first SiC substrate 11 to 1650 °C, and then introduce SiHCl3, C3H8, and N2 into the reaction chamber to grow a buffer layer 3 with a thickness of 10 μm and a doping concentration of 2×10 18 cm -3 , and then adjust the N2 flow rate to continue growing to obtain an epitaxial sublayer 21 with a thickness of 45 μm and a doping concentration of 5×10 14 cm -3 .

[0131] (3A) Bond the second SiC substrate 12 on the side of the epitaxial sublayer 21 away from the first SiC substrate 11.

[0132] For example, the second SiC substrate 12 is a conductive polycrystalline SiC substrate.

[0133] (4A) Use laser lift-off to remove the first SiC substrate 11, with a laser wavelength of 1050 nm and a power of 10 W. When removing the first SiC substrate 11, simultaneously use chemical mechanical polishing to remove the buffer layer 3 and peeling defects; clean to remove surface impurities and contaminants.

[0134] (5A) Bond another epitaxial sublayer 21 connecting the first SiC substrate 11 to the epitaxial sublayer 21 connected to the second SiC substrate 12 obtained in the previous step [step (4A)] to obtain a first bonded epitaxial wafer 101.

[0135] (6A) Remove the second SiC substrate 12 by laser lift-off process, and remove the surface defects of the peeled surface by chemical mechanical polishing to obtain an initial SiC epitaxial wafer 102A with Si-face epitaxy of two epitaxial sublayers 21. The total thickness of the two epitaxial sublayers is about 85 μm.

[0136] (7A) Repeat step (5A) and step (6A) three times to obtain an initial SiC epitaxial wafer 102A with Si-face epitaxy of five epitaxial sublayers 21. The total thickness of the five epitaxial sublayers 21 is about 200 μm.

[0137] (8A) Put the initial SiC epitaxial wafer 102A obtained in step (7A) into a high-temperature furnace for heat treatment to eliminate the bonding interface defects Q between the epitaxial sublayers 21. The heat treatment conditions are: in an argon atmosphere, at a temperature of 1750 °C for 30 minutes to obtain a SiC epitaxial wafer 10A with Si-face epitaxy.

[0138] As Figure 12 shown, Figure 12 in (a) is the surface defect (defect density 0.1 / cm 2 ) of the 8-inch SiC epitaxial wafer 10 in Example 1, Figure 12 in (b) is the surface defect (defect density 2 / cm 2 ) of directly growing an epitaxial layer 2 (the thickness of the epitaxial layer 2 is 200 μm) on an 8-inch SiC substrate 1. It can be seen that the surface defects of the SiC epitaxial wafer 10 obtained by using the SiC epitaxial wafer 10 preparation method of the present disclosure are significantly reduced.

[0139] Example 2: Example 2 provides a SiC epitaxial wafer 10. As Figure 11 shown, the preparation method of the SiC epitaxial wafer 10 includes the following steps (1B) to (8B).

[0140] (1B) Put the first SiC substrate 11 into high-temperature CVD, and treat it at 1650 °C in a hydrogen atmosphere for 10 minutes to obtain a SiC surface with a clean surface and atomic steps.

[0141] For example, the first SiC substrate 11 is an 8-inch Si-face 4-HSiC substrate with high crystal quality.

[0142] (2B) Heat the first SiC substrate 11 to 1650 °C, and then introduce SiHCl3, C3H8, and N2 into the reaction chamber to grow a buffer layer 3 with a thickness of 10 μm and a doping concentration of 2×10 18 cm -3 . Then adjust the N2 flow rate and continue to grow to obtain an epitaxial sublayer 21 with a thickness of 35 μm and a doping concentration of 5×10 14 cm -3 .

[0143] (3B) Bond a second SiC substrate 12 to the side of the epitaxial sublayer 21 away from the first SiC substrate 11.

[0144] For example, the second SiC substrate 12 is a high-conductivity 6H-SiC substrate.

[0145] (4B) Remove the first SiC substrate 11 by mechanical grinding, and at the same time remove the buffer layer 3 and peeling defects by chemical mechanical polishing; clean to remove surface impurities and contaminants.

[0146] (5B) Bond the epitaxial sublayer 21 connected to the first SiC substrate 11 to the epitaxial sublayer 21 connected to the second SiC substrate 12 obtained in the previous step [step (4B)] to obtain a first bonded epitaxial wafer 101.

[0147] (6B) Remove the first SiC substrate 11 by laser mechanical grinding process, and remove the peeling surface defects and buffer layer 3 by chemical mechanical polishing to obtain an initial SiC epitaxial wafer 102B with C-plane epitaxy of 2 epitaxial sublayers 21. The total thickness of the 2 epitaxial sublayers is about 65 μm.

[0148] (7B) Repeat step (5B) and step (6B) three times to obtain an initial SiC epitaxial wafer 102B with C-plane epitaxy of 5 epitaxial sublayers 21. The total thickness of the 5 epitaxial sublayers 21 is about 150 μm.

[0149] (8B) Put the initial SiC epitaxial wafer 102B obtained in step (7B) into a high-temperature furnace for heat treatment to eliminate the bonding interface defects Q of different epitaxial sublayers 21; the high-temperature treatment conditions are: in an argon atmosphere, at a temperature of 1650 °C, treat for 50 min to obtain a SiC epitaxial wafer 10B with C-plane epitaxy.

[0150] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims described above.

Claims

1. A SiC epitaxial wafer, characterized in that: include: A SiC substrate and an epitaxial layer provided on one side of the SiC substrate; The epitaxial layer comprises: a C surface and a Si surface arranged opposite to each other; either the C surface or the Si surface is close to the SiC substrate; the thickness of the epitaxial layer is in the range of 50 μm to 500 μm; The defect density of the epitaxial layer is in the range of 0.02 / cm 2 ~1 / cm 2 .

2. The SiC epitaxial wafer according to claim 1, characterized in that: The material of the epitaxial layer includes: nitrogen atoms; In the epitaxial layer, the doping concentration of the nitrogen atoms is in the range of 1×10 14 cm -3 ~1×10 17 cm -3 .

3. The SiC epitaxial wafer according to claim 1, characterized in that: The surface roughness of the epitaxial layer is in the range of 0.1 nm to 1 nm.

4. The SiC epitaxial wafer according to claim 1, characterized in that: The thickness of the epitaxial layer ranges from 100 μm to 200 μm.

5. A method for preparing a SiC epitaxial wafer, characterized in that: include: First epitaxy, forming an epitaxial sublayer on one side of a first SiC substrate; First bonding, bonding a second SiC substrate on a side of the epitaxial sublayer away from the first SiC substrate; first peeling, peeling off the first SiC substrate; In a first cycle, the first epitaxy is repeated to obtain a second epitaxial sublayer connected to the first SiC substrate; second bonding, bonding the second epitaxial sublayer connected to the first SiC substrate to the epitaxial sublayer connected to the second SiC substrate to obtain a first bonded epitaxial wafer; Second peeling, peeling off one of the second SiC substrate and the first SiC substrate in the first bonded epitaxial wafer to obtain an initial SiC epitaxial wafer; Heat treatment or laser treatment: Under inert gas conditions, heat treatment or laser treatment is used to recrystallize the initial SiC epitaxial wafer to obtain the SiC epitaxial wafer.

6. The method for preparing a SiC epitaxial wafer according to claim 5, characterized in that: In the second stripping, the second SiC substrate in the first bonded epitaxial wafer is stripped; Before the heat treatment or laser treatment, the method further comprises: In a second cycle, the first epitaxy, the first bonding and the first peeling are repeated to obtain a second epitaxial sublayer connected to a second SiC substrate; The third bonding step is to bond the second epitaxial sublayer connected to the second SiC substrate to the epitaxial sublayer in the initial SiC epitaxial wafer away from the first SiC substrate to obtain a second bonded epitaxial wafer; The third stripping step is to strip the second SiC substrate in the second bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

7. The method for preparing a SiC epitaxial wafer according to claim 6, characterized in that: Before the heat treatment or laser treatment, the method further comprises: The second cycle, the third bonding and the third peeling are repeated n times, where n is in the range of 1 to 20.

8. The method for preparing a SiC epitaxial wafer according to claim 5, characterized in that: In the second stripping, the first SiC substrate in the first bonded epitaxial wafer is stripped; Before the heat treatment or laser treatment, the method further comprises: In a third cycle, the first epitaxy is repeated to obtain a third epitaxial sublayer connected to the first SiC substrate; Fourth bonding, bonding the third epitaxial sublayer connected to the first SiC substrate to the epitaxial sublayer in the initial SiC epitaxial wafer away from the second SiC substrate to obtain a third bonded epitaxial wafer; The fourth peeling step is to peel off the first SiC substrate in the third bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

9. The method for preparing a SiC epitaxial wafer according to claim 8, characterized in that: Before the heat treatment or laser treatment, the method further comprises: The third cycle, the fourth bonding and the fourth peeling are repeated n times, where n is in the range of 1 to 20.

10. The method for preparing a SiC epitaxial wafer according to claim 5, characterized in that: The heat treatment conditions are: in an inert atmosphere, at a temperature range of 1400° C. to 2000° C., and for 10 min to 120 min.

11. The method for preparing a SiC epitaxial wafer according to claim 5, characterized in that: The laser processing power range is 10 4 W / cm 2 ~10 6 W / cm 2 and / or, The time range of the laser treatment is 10 min to 120 min.

12. The method for preparing a SiC epitaxial wafer according to claim 5, characterized in that: The first extension comprises: forming a buffer layer on one side of the first SiC substrate; forming an epitaxial sublayer on a side of the buffer layer away from the first SiC substrate; The step of stripping the first SiC substrate further includes: removing the buffer layer.

13. The method for preparing a SiC epitaxial wafer according to any one of claims 5 to 12, characterized in that: The thickness of the epitaxial sublayer ranges from 10 μm to 80 μm.

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