Wafer bonding method and repairing device

Abstract

The invention relates to a wafer bonding method and a repairing device, and relates to the technical field of semiconductors. The wafer bonding method comprises the following steps: bonding a first wafer and a second wafer to form an initial bonding wafer; carrying out hole detection on the initial bonding wafer, and obtaining the position of a hole as a target area; vacuumizing and exhausting the cavity until the gas in the cavity is completely exhausted; and heating the target area to form interatomic covalent bond interconnection in the target area to obtain the bonded wafer. According to the wafer bonding method, the cavities generated after wafer bonding are repaired, so that the product yield is improved, and the loss is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a wafer bonding method and a repair device. Background Art

[0002] With the development of the post-Moore era, the development of multi-layer wafer bonding technology is particularly important.

[0003] However, during the wafer bonding process, void defects may form at the bonding interface, which can cause the devices disposed on the two wafers to be unable to connect and result in the failure of the bonded wafers.

[0004] Therefore, how to repair the voids generated after wafer bonding and thereby improve the product yield is an urgent problem to be solved. Summary of the Invention

[0005] Based on this, it is necessary to provide a wafer bonding method and a repair device to repair the voids generated after wafer bonding and thereby improve the product yield.

[0006] On the one hand, an embodiment of the present disclosure provides a wafer bonding method, including the following steps:

[0007] Bond a first wafer and a second wafer to form an initial bonded wafer;

[0008] Perform void detection on the initial bonded wafer to obtain the position of the void as the target area;

[0009] Perform vacuum evacuation on the void until the gas in the void is completely exhausted;

[0010] Heat the target area so that covalent bonds between atoms are formed within the target area to obtain a bonded wafer.

[0011] In some embodiments of the present disclosure, heating the target area so that covalent bonds between atoms are formed within the target area includes the following steps:

[0012] Heat the target area using a secondary sintering process so that silicon-oxygen bonds are formed within the target area to achieve covalent bond interconnection between atoms.

[0013] In some embodiments of the present disclosure, performing vacuum evacuation on the void until the gas in the void is completely exhausted includes the following steps:

[0014] Form an exhaust channel communicating with the void within the first wafer;

[0015] Perform vacuum evacuation on the void based on the exhaust channel until the gas in the void is completely exhausted;

[0016] Wherein, the first wafer is the wafer to be subsequently thinned.

[0017] In some embodiments of the present disclosure, forming an exhaust channel communicating with the cavity in the first wafer includes the following steps:

[0018] Using at least one of a drill bit, laser etching, and plasma etching process to form an exhaust channel communicating with the cavity in the first wafer.

[0019] In some embodiments of the present disclosure, using a drill bit to form an exhaust channel communicating with the cavity in the first wafer includes the following steps:

[0020] Moving the initial bonded wafer above the drill bit of the machine; wherein, the non-bonded surface of the first wafer is in contact with the drill bit of the machine;

[0021] The drill bit of the machine drills upward based on the non-bonded surface of the first wafer to form an exhaust channel communicating with the cavity in the first wafer.

[0022] In some embodiments of the present disclosure, evacuating the cavity based on the exhaust channel includes the following steps:

[0023] Aligning and placing the first chuck above the exhaust channel;

[0024] The first chuck evacuates the cavity based on the exhaust channel. Wherein, the opening of the exhaust channel faces upward.

[0025] In some embodiments of the present disclosure, heating the target area to form an interatomic covalent bond interconnect in the target area includes the following steps: Using the second chuck to heat the target area to form an interatomic covalent bond interconnect in the target area.

[0026] In some embodiments of the present disclosure, the heating temperature of the second chuck is: 100°C to 400°C, and the heat preservation time is: 1 hour to 4 hours.

[0027] On the other hand, embodiments of the present disclosure provide a repair device, including: a first chuck disposed on the non-bonded surface of the first wafer and a second chuck disposed on the non-bonded surface of the second wafer.

[0028] The first chuck is used to evacuate the cavity until the gas in the cavity is completely exhausted; wherein, the cavity is generated after the first wafer and the second wafer are bonded.

[0029] The second chuck is used to heat the target area; wherein, the target area is the area where the cavity is generated.

[0030] In some embodiments of the present disclosure, the first chuck and the second chuck are disposed opposite to each other. The first chuck is further used for: after the gas in the cavity is completely exhausted, heating the target area synchronously with the second chuck.

[0031] The wafer bonding method and repair device provided by the present application can / at least have the following advantages:

[0032] In the embodiments of the present application, first, the bonded wafer is subjected to void detection. If voids exist in the bonded wafer, the position information of the voids is obtained, and then the voids are evacuated until the gas is completely exhausted; finally, the evacuated void area is heated so that covalent bonds are re-formed in the void area, realizing covalent bond interconnection between atoms to obtain a bonded wafer without voids. That is, when voids are generated during wafer bonding, the present application first evacuates the voids, and then heats the evacuated void area so that covalent bonds are re-formed in the void area, and finally obtains a bonded wafer without voids. In this way, the present application improves the product yield by repairing the voids generated after wafer bonding, thereby reducing losses.

[0033] In addition, in the embodiments of the present application, after obtaining a bonded wafer without voids, the bonded wafer can continue to complete the remaining process flow. In particular, after the bonded wafer is subjected to planarization treatment, wafer-to-wafer hybrid heterogeneous wafer bonding can be performed again.

[0034] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 is a flowchart of a wafer bonding method provided in some embodiments;

[0037] Figure 2 is a flowchart of evacuating voids;

[0038] Figure 3 is a flowchart of evacuating voids based on an exhaust channel in some embodiments;

[0039] Figure 4 is a schematic structural diagram of the structure obtained in step S200 of a wafer bonding method provided in some embodiments;

[0040] Figure 5 is a schematic structural diagram of a structure obtained in step S310 of a wafer bonding method provided in some embodiments;

[0041] Figure 6 Schematic diagram of another structure obtained in step S310 of a wafer bonding method provided in some embodiments;

[0042] Figure 7 Schematic diagram of the structure obtained when cleaning the drilled wafer in a wafer bonding method provided in some embodiments;

[0043] Figure 8 Schematic diagram of the structure obtained in step S320 of a wafer bonding method provided in some embodiments;

[0044] Figure 9 Schematic diagram of the structure obtained in step S400 of a wafer bonding method provided in some embodiments.

[0045] Description of reference numerals:

[0046] 1 - First wafer; 2 - Second wafer; 3 - Void; 4 - Exhaust channel; 5 - Machine drill bit; 6 - First chuck; 7 - Second chuck. Detailed implementation manners

[0047] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0050] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under", "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0051] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be identified, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] As used herein, the "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0053] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular will generally have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0054] With the development of the post-Moore era, the development of the multi-wafer hybrid bonding process is particularly important. The wafer bonding method is used to bond different wafers to improve the integration degree. In the wafer bonding process, usually two wafers are bonded face to face, and certain pressure, temperature, voltage, etc. are applied to the two wafers, so that covalent bonds, metal bonds, molecular bonds, etc. are generated at the interface of the two wafers, and the two wafers are combined into one body to form a bonded wafer.

[0055] During the wafer bonding process, void defects may be formed at the bonding interface. Although wafer bonding, as a new process technology, breaks through the von Neumann architecture and replaces the traditional micro-bumps (μ-Bump), shortening the interconnect length by dozens of times and reducing the power consumption, due to its process conditions of normal temperature and pressure, new problems are also introduced: void defects, that is, void regions where the wafers are not in contact and no covalent bonds are formed between the wafers. This void defect will cause the devices disposed on the two wafers to be unable to be connected, resulting in the failure of the bonded wafer.

[0056] The reasons for the generation of void defects are diverse, but the voids caused by the introduction of large foreign particles in the previous layer are extremely harmful, and their size is usually greater than 1 cm. These large-sized voids will rupture when the back of the wafer is thinned during subsequent wafer processes. For example, large broken pieces will cause a large number of scratches to other regions, resulting in wafer scrapping, and will also affect other normal wafers; in addition, steps will be left in the rupture region and there will be metal exposure. When the subsequent plasma process is carried out, abnormal arcs will occur, resulting in the generation of a large number of molten foreign substances, which will lead to the scrapping of all wafers and will also affect other normal wafers.

[0057] Therefore, how to repair the voids generated after wafer bonding and thus improve the product yield is an urgent problem to be solved.

[0058] Based on this, it is necessary to provide a wafer bonding method and a repair device to repair the voids generated after wafer bonding, thereby improving the product yield.

[0059] Please refer to Figure 1 , an embodiment of the present disclosure provides a wafer bonding method, including steps S100 to S400.

[0060] S100, bond a first wafer and a second wafer to form an initial bonded wafer.

[0061] S200, perform void detection on the initial bonded wafer to obtain the position of the void as the target area.

[0062] S300, evacuate the void until all the gas in the void is exhausted.

[0063] S400, heat the target area so that covalent bonds between atoms are formed in the target area to obtain a bonded wafer.

[0064] In the embodiment of the present application, first, void detection is performed on the bonded wafer. If there are voids in the bonded wafer, the position information of the voids is obtained, and then the voids are evacuated until all the gas is exhausted; finally, the evacuated void area is heated so that covalent bonds are re-formed in the void area, realizing covalent bond interconnection between atoms to obtain a bonded wafer without voids. That is, when voids are generated during wafer bonding, the present application first evacuates the voids and then heats the evacuated void area so that covalent bonds are re-formed in the void area, ultimately obtaining a bonded wafer without voids. In this way, the present application improves the product yield by repairing the voids generated after wafer bonding, thereby reducing losses.

[0065] In addition, in the embodiment of the present application, after obtaining a bonded wafer without voids, the bonded wafer can continue to complete the remaining process flow. In particular, after the bonded wafer is subjected to planarization treatment, wafer-to-wafer hybrid heterogeneous wafer bonding can be performed again.

[0066] In some embodiments, step S400 heats the target area so that covalent bonds between atoms are formed in the target area, including the following steps:

[0067] Heat the target area using a secondary sintering process so that silicon-oxygen bonds are formed in the target area to achieve covalent bond interconnection between atoms.

[0068] In some embodiments, please refer to Figure 2 , step S300 evacuates the void until all the gas in the void is exhausted, including steps S310 to S320.

[0069] S310, form an exhaust channel communicating with the void in the first wafer.

[0070] S320, evacuate the cavity through the exhaust channel until all the gas in the cavity is exhausted.

[0071] Wherein, the first wafer is the wafer on which the thinning process is to be subsequently performed.

[0072] In some embodiments, step S310 of forming an exhaust channel communicating with the cavity in the first wafer includes:

[0073] Use at least one of the processes of drill bit, laser etching, and plasma etching to form an exhaust channel communicating with the cavity in the first wafer.

[0074] In some embodiments, step S310 of using a drill bit to form an exhaust channel communicating with the cavity in the first wafer includes the following steps:

[0075] Move the initially bonded wafer above the drill bit of the machine; wherein, the non-bonded surface of the first wafer is in contact with the drill bit of the machine;

[0076] The drill bit of the machine drills upward based on the non-bonded surface of the first wafer to form an exhaust channel communicating with the cavity in the first wafer.

[0077] In some embodiments, please refer to Figure 3 , step S320 of evacuating the cavity through the exhaust channel includes steps S321 to S322.

[0078] S321, align and place the first chuck above the exhaust channel;

[0079] S322, the first chuck evacuates the cavity through the exhaust channel. Wherein, the opening of the exhaust channel faces upward.

[0080] In some embodiments, step S400 of heating the target area to form covalent bonds between atoms in the target area includes the following steps: use the second chuck to heat the target area to form covalent bonds between atoms in the target area.

[0081] In some embodiments, the heating temperature of the second chuck is: 100°C to 400°C. For example: the heating temperature of the second chuck can be: 100°C, 150°C, 200°C, 250°C, 300°C, 350°C or 400°C, etc. The heat preservation time is: 1 hour to 4 hours. For example: the heat preservation time of the second chuck can be: 1 hour, 1.5 hours, 2 hours, 2.5 hours, 3 hours, 3.5 hours or 4 hours, etc.

[0082] It should be noted that in the above embodiments, the execution of each step in the method has no strict order limit. These steps do not necessarily need to be executed in the described order and can be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be completed at the same moment but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps. The method is limited to being able to achieve the preparation of the corresponding bonded wafers.

[0083] To more clearly illustrate the wafer bonding method provided in the above embodiments, the following Figures 4 - 8 details this wafer bonding method.

[0084] In step S100, please refer to Figure 1 step S100 in Figure 4 , and bond the first wafer 1 and the second wafer 2 to form an initial bonded wafer.

[0085] In some examples, both the first wafer 1 and the second wafer 2 can be any suitable substrate materials well-known in the art. For example, they can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also include multi-layer structures composed of these semiconductors, etc. Or they can be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Or they can also be double-sided polished wafers (DSP for short), or ceramic substrates such as alumina, quartz or glass substrates, etc. This embodiment does not limit here.

[0086] In some examples, the first wafer 1 and the second wafer 2 are attached and a preset pressure is applied for bonding to obtain an initial bonded wafer.

[0087] In step S200, please refer to Figure 1 step S200 in Figure 4 , perform void detection on the initial bonded wafer, and obtain the position of the void 3 as the target area.

[0088] In some examples, performing void detection on the initial bonded wafer and obtaining the position of void 3 as the target area includes: performing void detection on the initial bonded wafer and recording the coordinates of void 3.

[0089] In some examples, void detection on the initial bonded wafer can be performed using acoustic wave detection, infrared imaging detection, optical microscope detection, X-ray imaging detection, electrical testing, ultraviolet light detection, and so on.

[0090] In step S310, please refer to Figure 2 step S310 in Figure 5 and form an exhaust channel 4 communicating with void 3 in the first wafer 1.

[0091] In some embodiments, step S310 of forming an exhaust channel 4 communicating with void 3 in the first wafer 1 includes:

[0092] Using at least one of a drill bit, laser etching, and plasma etching process to form an exhaust channel 4 communicating with void 3 in the first wafer 1.

[0093] In some embodiments, please refer to Figure 6 where step S310 of using a drill bit to form an exhaust channel 4 communicating with void 3 in the first wafer 1 includes the following steps:

[0094] Moving the initial bonded wafer above the machine drill bit 5; wherein, the non-bonded surface of the first wafer 1 is in contact with the machine drill bit 5;

[0095] In some examples, the first wafer to be subsequently thinned faces downwards, and the void is moved above the machine drill bit 5.

[0096] The machine drill bit 5 drills upwards based on the non-bonded surface of the first wafer 1 to form an exhaust channel 4 communicating with void 3 in the first wafer 1.

[0097] In some examples, the depth of the machine drill bit 5 drilling upwards based on the non-bonded surface of the first wafer 1 is: 700 μm to 850 μm. For example, the depth of the machine drill bit 5 drilling upwards based on the non-bonded surface of the first wafer 1 can be: 700 μm, 720 μm, 740 μm, 760 μm, 780 μm, 800 μm, 820 μm, or 850 μm, and so on.

[0098] In some embodiments, please refer to Figure 7 after forming an exhaust channel 4 communicating with void 3 in the first wafer 1, it further includes: keeping the outlet of the exhaust channel 4 facing downwards and cleaning the drilled wafer, especially various particulate matters in the holes, to ensure the smoothness of the exhaust channel 4 for void exhaust.

[0099] In step S320, please refer toFigure 2 Step S320 in Figure 8 , evacuate the cavity 3 through the exhaust passage 4 until all the gas in the cavity 3 is exhausted.

[0100] Among them, the first wafer 1 is the wafer to be thinned in the subsequent process.

[0101] In some embodiments, step S320 of evacuating the cavity through the exhaust passage includes steps S321 - S322.

[0102] In step S321, refer to Figure 2 Step S320 in Figure 8 , align and place the first chuck 6 above the exhaust passage 4.

[0103] In step S322, refer to Figure 2 Step S320 in Figure 8 , the first chuck 6 evacuates the cavity 3 through the exhaust passage 4. Among them, the opening of the exhaust passage 4 faces upward.

[0104] Here, it should be particularly noted that the first chuck 6 has the ability to maintain vacuum, and the vacuum can cause the cavity 3 to shrink, thereby causing the bonding surfaces of the first wafer 1 and the second wafer 2 in the target area to come into contact again.

[0105] In some examples, the first chuck 6 has functions of alignment, evacuation, and local heating. The first chuck 6 is aligned and placed above the exhaust passage 4, and starts to evacuate, forcing the gas in the cavity 3 to be discharged, reducing the size of the cavity 3 and the height difference between the upper and lower interfaces of the cavity 3.

[0106] In step S400, refer to Figure 1 Step S400 in Figure 9 , heat the target area so that covalent bonds between atoms are formed within the target area to obtain a bonded wafer.

[0107] In some embodiments, step S400 of heating the target area so that covalent bonds between atoms are formed within the target area includes the following steps:

[0108] Use a secondary sintering process to heat the target area so that silicon - oxygen bonds are formed within the target area to achieve covalent bond interconnection between atoms.

[0109] In some embodiments, step S400 of heating the target area so that covalent bonds between atoms are formed within the target area includes the following steps: heat the target area with the second chuck 7 so that covalent bonds between atoms are formed within the target area.

[0110] Here, it should be specifically noted that when the second chuck 7 is used to heat the target area, in addition to having a heating function, the second chuck 7 can also approach the first chuck 6 to apply an appropriate force to the first wafer 1 and the second wafer 2 in the target area, so as to prompt the bonding surfaces of the first wafer 1 and the second wafer 2 in the target area to come into contact again.

[0111] In some embodiments, the heating temperature of the second chuck 7 is: 100°C to 400°C. For example: the heating temperature of the second chuck can be: 100°C, 150°C, 200°C, 250°C, 300°C, 350°C or 400°C, etc. The heat preservation time is: 1 hour to 4 hours. For example: the heat preservation time of the second chuck 7 can be: 1 hour, 1.5 hours, 2 hours, 2.5 hours, 3 hours, 3.5 hours or 4 hours, etc.

[0112] In the embodiments of the present application, first, void detection is performed on the bonded wafers. If voids exist in the bonded wafers, the position information of the voids is obtained, and then the voids are evacuated until the gas is completely exhausted; finally, the evacuated void area is heated so that covalent bonds are re-formed in the void area to achieve covalent bond interconnection between atoms, so as to obtain a bonded wafer without voids. That is, when voids are generated during wafer bonding, the present application first evacuates the voids, and then heats the evacuated void area so that covalent bonds are re-formed in the void area, and finally obtains a bonded wafer without voids. In this way, the present application repairs the voids generated after wafer bonding, improves the product yield, and thus reduces losses.

[0113] In some embodiments, obtaining a bonded wafer without voids further includes the following steps:

[0114] Performing a thinning process on the first wafer 1;

[0115] Forming a silicon oxide layer and performing lithography etching for the Through-Silicon Via (TSV) technology;

[0116] Electroplating of metallic copper;

[0117] Chemical mechanical polishing of copper.

[0118] In the embodiments of the present application, after obtaining a bonded wafer without voids, the bonded wafer can continue to complete the remaining process flows. The subsequent process returns to the normal multi-layer wafer bonding process, thereby eliminating the interference of voids on multi-layer wafer bonding. In particular, after the bonded wafer is planarized, wafer-to-wafer hybrid heterogeneous wafer bonding can be performed again.

[0119] Please refer to Figure 8, embodiments of the present disclosure provide a repair device for repairing voids after wafer bonding. The repair device includes: a first chuck 6 disposed on the non-bonding surface of the first wafer 1 and a second chuck 7 disposed on the non-bonding surface of the second wafer 2.

[0120] The first chuck 6 is used to evacuate the void 3 until all the gas in the void 3 is exhausted; wherein, the void 3 is generated after the bonding of the first wafer 1 and the second wafer 2.

[0121] The second chuck 7 is used to heat the target area; wherein, the target area is the area where the void 3 is generated.

[0122] In the embodiments of the present application, first, void detection is performed on the bonded wafers. If there are voids in the bonded wafers, the position information of the voids is obtained, and then the voids are evacuated until the gas is completely exhausted; finally, the evacuated void area is heated so that covalent bonds are re-formed in the void area, realizing covalent bond interconnection between atoms to obtain a bonded wafer without voids. That is, when voids are generated during wafer bonding, the present application first evacuates the voids, and then heats the evacuated void area so that covalent bonds are re-formed in the void area, and finally obtains a bonded wafer without voids. In this way, the present application improves the product yield by repairing the voids generated after wafer bonding, thereby reducing losses.

[0123] In addition, in the embodiments of the present application, after obtaining a bonded wafer without voids, the bonded wafer can continue to complete the remaining process flows. In particular, after the bonded wafer is subjected to planarization treatment, wafer-to-wafer hybrid heterogeneous wafer bonding can be performed again.

[0124] In some examples, the first chuck 6 has functions of alignment, evacuation, and local heating. The first chuck 6 is aligned and placed above the exhaust channel 4, and evacuation starts to force the gas in the void 3 to be discharged, reducing the size of the void 3 and lowering the height difference between the upper and lower interfaces of the void 3.

[0125] In some embodiments, the heating temperature of the second chuck 7 is: 100°C to 400°C. For example: the heating temperature of the second chuck can be: 100°C, 150°C, 200°C, 250°C, 300°C, 350°C, or 400°C, etc. The heat preservation time is: 1 hour to 4 hours. For example: the heat preservation time of the second chuck 7 can be: 1 hour, 1.5 hours, 2 hours, 2.5 hours, 3 hours, 3.5 hours, or 4 hours, etc.

[0126] In some embodiments of the present disclosure, the first chuck 6 and the second chuck 7 are disposed opposite to each other. The first chuck 6 is further used for: after all the gas in the void 3 is exhausted, heating the target area synchronously with the second chuck 7.

[0127] In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0128] The above-mentioned embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A wafer bonding method, characterized in that, Including: Bonding a first wafer and a second wafer to form an initial bonded wafer; Performing void detection on the initial bonded wafer to obtain the position of the void as the target area; Performing vacuum evacuation on the void until the gas in the void is completely exhausted; Heating the target area so that an interatomic covalent bond interconnection is formed within the target area to obtain a bonded wafer.

2. The wafer bonding method according to claim 1, characterized in that, The heating the target area so that an interatomic covalent bond interconnection is formed within the target area includes: Heating the target area using a secondary sintering process so that a silicon-oxygen bond is formed within the target area to achieve an interatomic covalent bond interconnection.

3. The wafer bonding method according to claim 1, characterized in that, Performing vacuum evacuation on the void until the gas in the void is completely exhausted includes: Forming an exhaust channel communicating with the void within the first wafer; Performing vacuum evacuation on the void based on the exhaust channel until the gas in the void is completely exhausted; Wherein, the first wafer is the wafer on which a thinning process is subsequently performed.

4. The wafer bonding method according to claim 3, characterized in that, The forming an exhaust channel communicating with the void within the first wafer includes: Using at least one of a drill bit, laser etching, and plasma etching process to form an exhaust channel communicating with the void within the first wafer.

5. The wafer bonding method according to claim 4, characterized in that, The forming an exhaust channel communicating with the void within the first wafer using a drill bit includes: Moving the initial bonded wafer above the machine table drill bit; wherein, the non-bonded surface of the first wafer is in contact with the machine table drill bit; The machine table drill bit drills upward based on the non-bonded surface of the first wafer to form an exhaust channel communicating with the void within the first wafer.

6. The wafer bonding method according to claim 3, characterized in that, The performing vacuum evacuation on the void based on the exhaust channel includes: Aligning and placing a first chuck above the exhaust channel; The first chuck performs vacuum evacuation on the void based on the exhaust channel; Wherein, the opening of the exhaust channel faces upward.

7. The wafer bonding method according to claim 1, characterized in that, The heating the target area so that an interatomic covalent bond interconnection is formed within the target area includes: Using a second chuck to heat the target area so that an interatomic covalent bond interconnection is formed within the target area.

8. The wafer bonding method according to claim 7, characterized in that, The heating temperature of the second chuck is: 100°C to 400°C, and the heat preservation time is: 1 hour to 4 hours.

9. A repair device, characterized in that, Including: A first chuck disposed on the non-bonded surface of the first wafer and a second chuck disposed on the non-bonded surface of the second wafer; The first chuck is used to perform vacuum evacuation on the void until the gas in the void is completely exhausted; wherein, the void is generated after the bonding of the first wafer and the second wafer; The second chuck is used to heat the target area; wherein, the target area is the area where the void is generated.

10. The repair device according to claim 9, characterized in that, The first chuck and the second chuck are disposed opposite to each other; the first chuck is further used for: after the gas in the void is completely exhausted, heating the target area synchronously with the second chuck.

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