Wafer alignment method and wafer bonding method

Abstract

The invention relates to a wafer alignment method and a wafer bonding method. The wafer alignment method comprises the following steps: respectively taking a first wafer and a second wafer as target wafers; selecting at least two first target marks on one side of the first reference line on the target wafer; the at least two second target marks are positioned on the other side of the first reference line; the at least two first target marks and the at least two second target marks are located on the two sides of the second datum line respectively. Acquiring first angle data of each first target mark and second angle data of each second target mark; and determining a first angle offset according to the first angle data, and determining a second angle offset according to the second angle data. And determining the average angle offset of the corresponding target wafer according to the first angle offset and the second angle offset. And performing wafer angle alignment according to the average angle offset of the first wafer and the average angle offset of the second wafer. The method can be matched with the central symmetry effect of the wafer manufacturing process, and the accuracy of angle offset measurement is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and particularly to a wafer alignment method and a wafer bonding method. Background Art

[0002] With the development of the post-Moore era, the development of multi-wafer on-wafer hybrid bonding structures in the field of semiconductor manufacturing is particularly important. The multi-wafer bonding structure can break through the von Neumann architecture, shorten the size of the interconnect structure to about 1 μm, and increase the number of interconnect structures per square millimeter on the wafer to millions, thus significantly improving the wafer integration and effectively reducing the power consumption.

[0003] Since the size of the hybrid bonding interconnect structure (such as bonding pads) in the multi-wafer bonding structure further tends to be miniaturized, the requirement for the alignment accuracy between wafers during the wafer bonding process in related technologies is also getting higher and higher. Summary of the Invention

[0004] Based on this, some embodiments of the present application provide a wafer alignment method and a wafer bonding method, which can match the central symmetry effect in the wafer production process, improve the accuracy of angle offset measurement, and thus improve the wafer alignment accuracy.

[0005] To achieve the above object, on the one hand, some embodiments of the present application provide a wafer alignment method. The wafer alignment method is used to align a first wafer and a second wafer; the wafer alignment method includes the following steps.

[0006] Respectively use the first wafer and the second wafer as target wafers.

[0007] Select at least two wafer alignment marks on one side of a first reference line on the target wafer as first target marks, and select at least two wafer alignment marks on the other side of the first reference line on the target wafer as second target marks; wherein, at least two first target marks are respectively located on both sides of a second reference line, and at least two second target marks are respectively located on both sides of the second reference line; the second reference line is orthogonal to the first reference line.

[0008] Respectively obtain first angle data of at least two first target marks and second angle data of at least two second target marks.

[0009] Determine a first angle offset of the first target mark according to the first angle data, and determine a second angle offset of the second target mark according to the second angle data.

[0010] Determine an average angle offset of the corresponding target wafer relative to the wafer machine stage according to the first angle offset and the second angle offset.

[0011] Perform angular alignment between the first wafer and the second wafer based on the average angular offset of the first wafer and the average angular offset of the second wafer.

[0012] In some embodiments, obtaining first angular data of at least two first target marks and second angular data of at least two second target marks respectively includes the following steps.

[0013] Determine the intersection point of the first reference line and the second reference line as the reference point.

[0014] Determine the first angular data based on the angle between the straight line connecting the geometric center of at least two first target marks and the reference point and the first reference line, and determine the second angular data based on the angle between the straight line connecting the geometric center of at least two second target marks and the reference point and the first reference line.

[0015] In some embodiments, the reference point is located at the geometric center of the target wafer.

[0016] In some embodiments, both the first wafer and the second wafer include a plurality of chips arranged in an array, and each chip has a wafer alignment mark; select at least two wafer alignment marks on the target wafer located on one side of the first reference line as the first target marks, and select at least two wafer alignment marks on the target wafer located on the other side of the first reference line as the second target marks, including the following steps.

[0017] Select a first chip and a second chip on the target wafer located on both sides of the first reference line respectively, use the wafer alignment mark on the first chip as the first target mark, and use the wafer alignment mark on the second chip as the second target mark; wherein, the number of chips separated by the first chip and the second chip from the first reference line in the direction parallel to the second reference line is equal, and the number of chips separated by the first chip and the second chip from the second reference line in the direction parallel to the first reference line is equal.

[0018] In some embodiments, the rows and columns of each first chip of the first wafer and each first chip of the second wafer in the chip array are the same, and the rows and columns of each second chip of the first wafer and each second chip of the second wafer in the chip array are the same.

[0019] In some embodiments, after selecting at least two wafer alignment marks on the target wafer located on one side of the first reference line as the first target marks and selecting at least two wafer alignment marks on the target wafer located on the other side of the first reference line as the second target marks, the wafer alignment method further includes the following steps.

[0020] Obtain the first position data of at least two first target marks and the second position data of at least two second target marks respectively.

[0021] Determine the first position offset of the first target mark according to the first position data, and determine the second position offset of the second target mark according to the second position data.

[0022] Determine the average position offset of the corresponding target wafer relative to the wafer stage according to the first position offset and the second position offset.

[0023] Perform position alignment between the first wafer and the second wafer according to the average position offset of the first wafer and the average position offset of the second wafer.

[0024] In some embodiments, the first position offset includes a first lateral position offset in a direction parallel to the first reference line and a first longitudinal position offset in a direction parallel to the second reference line; the second position offset includes a second lateral position offset in a direction parallel to the first reference line and a second longitudinal position offset in a direction parallel to the second reference line.

[0025] In some embodiments, the first angle data of at least two first target marks is obtained by synchronous measurement with the first position data, and the second angle data of at least two second target marks is obtained by synchronous measurement with the second position data.

[0026] In some embodiments, the wafer alignment method further includes the following steps.

[0027] According to the process sequence, compensate for the angle alignment of the current group of first wafers and second wafers according to the average angle offset of the previous group of first wafers and second wafers.

[0028] On the other hand, according to some embodiments of the present application, a wafer bonding method is provided; the wafer bonding method includes: providing a first wafer and a second wafer; aligning the second wafer and the first wafer by using the wafer alignment method described in the foregoing some embodiments of the present application; bonding the aligned second wafer and first wafer.

[0029] The embodiments of the present application can / at least have the following advantages:

[0030] In the embodiments of the present application, at least two first target marks located on both sides of the second reference line are selected on one side of the first reference line, and at least two second target marks located on both sides of the second reference line are selected on the other side of the first reference line, so as to sample the angular data at different positions on both sides of the first reference line and on both sides of the second reference line, and measure the angular offsets at different positions multiple times. By determining the average angular offset of the corresponding target wafer relative to the wafer stage according to the first angular offset of the first target mark and the second angular offset of the second target mark, the determined average angular offset has global representativeness on the corresponding target wafer, and can exclude the adverse effects of environmental factors (such as optical signal interference, measurement noise interference, instantaneous environmental fluctuations, etc.) at local positions of the wafer on the angular data measurement, thereby improving the accuracy of angular offset measurement. According to the average angular offset of the first wafer and the average angular offset of the second wafer, angular alignment between the two is performed, which can match the central symmetry effect in the wafer production process, align the wafers based on the global deviation, effectively improve the wafer alignment accuracy, and is beneficial to improving the product yield of the wafer bonding process. In summary, under the combined action of the above technical features, the embodiments of the present application perform global measurement on the angular data of the wafer to match the central symmetry effect in the wafer production process, determine the average angular offset with global representativeness, improve the accuracy of angular offset measurement, and thus are beneficial to improving the wafer alignment accuracy.

[0031] Details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0033] Figure 1 It is a flowchart of a wafer alignment method provided in some embodiments;

[0034] Figure 2 It is a flowchart of another wafer alignment method provided in some embodiments;

[0035] Figure 3 It is a flowchart of yet another wafer alignment method provided in some embodiments;

[0036] Figure 4Flowchart of yet another wafer alignment method provided in some embodiments;

[0037] Figure 5 Schematic structural diagram of a wafer provided in some embodiments; wherein, Figure 5 Figure (a) therein is a schematic structural diagram of a first wafer, Figure 5 Figure (b) therein is a schematic structural diagram of a second wafer;

[0038] Figure 6 Schematic structural diagram of a combined pattern formed by a first wafer alignment mark and a second wafer alignment mark provided in some embodiments;

[0039] Figure 7 Schematic structural diagram of a target wafer provided in some embodiments.

[0040] Explanation of reference numerals:

[0041] w1 - first wafer, w2 - second wafer, W - target wafer, S1 - first wafer alignment mark, S2 - second wafer alignment mark, A1 - first target mark, A2 - second target mark, o - reference point, C - chip, C1 - first chip, C2 - second chip. Detailed implementation manners

[0042] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] It should be understood that when an element or layer is referred to as "on", "adjacent to", or "connected to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0045] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the described features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0047] In the field of semiconductor manufacturing, manufacturing processes in the wafer production process (such as wafer spin cleaning process, photoresist spin coating process, etc.) and wafer characteristics itself (such as wafer crystal orientation, wafer warpage, etc.) usually have a central symmetry effect.

[0048] Based on this, embodiments of the present application provide a wafer alignment method and a wafer bonding method, which can match the central symmetry effect in the wafer production process, improve the accuracy of angle offset measurement, and thus improve the wafer alignment accuracy.

[0049] In some embodiments, please refer to Figure 1 , the wafer alignment method is used to align a first wafer and a second wafer; the wafer alignment method includes the following steps S100 to S600.

[0050] S100, using the first wafer and the second wafer as target wafers respectively.

[0051] S200, selecting at least two wafer alignment marks on one side of the first reference line on the target wafer as the first target marks, and selecting at least two wafer alignment marks on the other side of the first reference line on the target wafer as the second target marks; wherein, at least two of the first target marks are respectively on both sides of the second reference line, and at least two of the second target marks are respectively on both sides of the second reference line; the second reference line is orthogonal to the first reference line.

[0052] S300, obtaining the first angle data of at least two first target marks and the second angle data of at least two second target marks respectively.

[0053] S400, determining the first angle offset of the first target marks according to the first angle data, and determining the second angle offset of the second target marks according to the second angle data.

[0054] S500, determining the average angle offset of the corresponding target wafer relative to the wafer machine according to the first angle offset and the second angle offset.

[0055] S600, performing angle alignment between the first wafer and the second wafer according to the average angle offset of the first wafer and the average angle offset of the second wafer.

[0056] In the embodiments of the present application, at least two first target marks located on both sides of the second reference line are selected on one side of the first reference line, and at least two second target marks located on both sides of the second reference line are selected on the other side of the first reference line, so as to sample the angular data at different positions on both sides of the first reference line and both sides of the second reference line, and measure the angular offset at different positions multiple times. By determining the average angular offset of the corresponding target wafer relative to the wafer stage according to the first angular offset of the first target mark and the second angular offset of the second target mark, the determined average angular offset has global representativeness on the corresponding target wafer, and can exclude the adverse effects of environmental factors (such as optical signal interference, measurement noise interference, instantaneous environmental fluctuations, etc.) at local positions of the wafer on the measurement of angular data, thereby improving the accuracy of angular offset measurement. According to the average angular offset of the first wafer and the average angular offset of the second wafer, the angular alignment between the two is performed, which can match the central symmetry effect in the wafer production process, and the alignment between wafers is performed based on the global deviation, effectively improving the wafer alignment accuracy and being beneficial to improving the product yield of the wafer bonding process. In summary, under the combined action of the above technical features, the embodiments of the present application perform global measurement on the angular data of the wafer to match the central symmetry effect in the wafer production process, determine the average angular offset with global representativeness, improve the accuracy of angular offset measurement, and thus are beneficial to improving the wafer alignment accuracy.

[0057] In some embodiments, please refer to Figure 2 , step S300 includes the following steps S310 to S320.

[0058] S310, determine the intersection point of the first reference line and the second reference line as the reference point.

[0059] S320, determine the first angular data according to the angle between the straight line connecting the geometric center of at least two first target marks and the reference point and the first reference line, and determine the second angular data according to the angle between the straight line connecting the geometric center of at least two second target marks and the reference point and the first reference line.

[0060] In the embodiments of the present application, by determining the intersection point of the first reference line and the second reference line as the reference point, and making both the first angular data and the second angular data be determined based on this reference point, all angular data are determined with reference to the same fixed position, enhancing the unity of the determined angular data to facilitate subsequent data processing steps, and at the same time can also improve the data acquisition efficiency.

[0061] In some embodiments, the reference point is located at the geometric center of the target wafer.

[0062] In the embodiment of the present application, the reference point is located at the geometric center of the target wafer, that is, the first reference line and the second reference line are orthogonal to the geometric center of the target wafer, which can match the central symmetry effect in the wafer production process, so that the first reference line and the second reference line evenly divide the target wafer into multiple wafer areas of the same area. In this way, the first angle data and the second angle data are located in different wafer areas, which can match the central symmetry effect in the wafer production process, improve the sampling uniformity of the angle data and make the obtained average angle offset globally representative, thereby improving the accuracy of the angle offset measurement.

[0063] In some embodiments, the first wafer and the second wafer each include a plurality of chips arranged in an array, and each chip has a wafer alignment mark. Figure 3 , step S200 includes the following step S210.

[0064] S210, select the first chip and the second chip on the target wafer respectively located on both sides of the first baseline, use the wafer alignment mark on the first chip as the first target mark, and use the wafer alignment mark on the second chip as the second target mark; wherein, the number of chips between the first chip and the second chip in a direction parallel to the second baseline and the first baseline is equal, and the number of chips between the first chip and the second chip in a direction parallel to the first baseline and the second baseline is equal.

[0065] In the embodiment of the present application, wafer alignment marks on the first chip and the second chip that are symmetrically positioned on both sides of the first reference line are respectively selected as the first target mark and the second target mark, which can match the central symmetry effect in the wafer production process, so that the positions of the first target mark and the second target mark on the target wafer also have a certain symmetry, thereby improving the sampling uniformity of the angle data and making the angle offset globally representative, thereby improving the accuracy of the angle offset measurement.

[0066] In some embodiments, each first chip of the first wafer and each first chip of the second wafer are located in the same number of rows and columns in the chip array, and each second chip of the first wafer and each second chip of the second wafer are located in the same number of rows and columns in the chip array.

[0067] In the embodiment of the present application, measurement is performed based on the alignment marks on the chips at the same position on the first wafer and the second wafer, so that the data acquisition between the first wafer and the second wafer can be consistent, which is beneficial to improving the accuracy of offset determination.

[0068] In some embodiments, see Figure 4 , after step S200, the wafer alignment method further includes the following steps S710~S740.

[0069] S710. Obtain the first position data of at least two first target marks and the second position data of at least two second target marks respectively.

[0070] S720. Determine the first position offset of the first target mark according to the first position data, and determine the second position offset of the second target mark according to the second position data.

[0071] S730. Determine the average position offset of the corresponding target wafer relative to the wafer stage according to the first position offset and the second position offset.

[0072] S740. Perform position alignment between the first wafer and the second wafer according to the average position offset of the first wafer and the average position offset of the second wafer.

[0073] In some embodiments, the first angle data of at least two first target marks is obtained by synchronous measurement with the first position data, and the second angle data of at least two second target marks is obtained by synchronous measurement with the second position data.

[0074] In the embodiments of the present application, it is possible to exclude the adverse effects of environmental factors (such as optical signal interference, measurement noise interference, instantaneous environmental fluctuations, etc.) at local positions of the wafer on the measurement of position data, and to make the determined average position offset globally representative on the corresponding target wafer to match the central symmetry effect in the wafer production process, improving the accuracy of position offset measurement, and thus being beneficial to improving the wafer alignment accuracy.

[0075] In some embodiments, the first position offset includes a first lateral position offset in a direction parallel to the first reference line (such as the X direction) and a first longitudinal position offset in a direction parallel to the second reference line (such as the Y direction); the second position offset includes a second lateral position offset in a direction parallel to the first reference line (such as the X direction) and a second longitudinal position offset in a direction parallel to the second reference line (such as the Y direction).

[0076] In the embodiments of the present application, obtaining the position offsets in two directions (such as including the X direction and the Y direction) respectively can improve the accuracy and comprehensiveness of position offset measurement, and is beneficial to improving the wafer alignment accuracy.

[0077] In some embodiments, the wafer alignment method further includes the following step S800.

[0078] S800. According to the process sequence, compensate for the angle alignment of the current group of first wafers and second wafers according to the average angle offset of the previous group of first wafers and second wafers.

[0079] In some embodiments, the wafer alignment method further includes the following step S900.

[0080] S900. According to the process sequence, compensate for the position alignment of the current group of the first wafer and the second wafer based on the average position offset of the previous group of the first wafers and the average position offset of the second wafers.

[0081] In the embodiments of the present application, performing the alignment compensation for the current group based on the globally representative average offset determined in the previous group of wafer alignment steps can effectively improve the wafer alignment accuracy in the entire process, thereby improving the yield of wafer products.

[0082] It should be understood that although Figures 1 to 4 the steps in the flowchart of Figures 1 to 4 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover,

[0083] at least a part of the steps in Figures 5 to 7 may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of the steps or stages in other steps or other steps.

[0083] To more clearly illustrate the wafer alignment method in the above-mentioned some embodiments, the following some embodiments are to be understood in conjunction with Figures 5 to 7 herein.

[0084] In some embodiments, the wafer alignment method is used to align the first wafer w1 and the second wafer w2.

[0085] In some examples, referring to Figure 5 Figure (a) in Figure 5 Figure (b) in

[0086] it should be noted that, referring to Figure 6 in the process of aligning the first wafer w1 and the second wafer w2, it is necessary to make the first wafer alignment marks S1 and the second wafer alignment marks S2 form a combined pattern, and measure the alignment offset between the first wafer w1 and the second wafer w2 based on this combined pattern.

[0087] Exemplarily, the alignment offset includes but is not limited to the angular offset and the position offset, etc.

[0088] In some embodiments, a wafer alignment method is used to align a first wafer w1 and a second wafer w2; the wafer alignment method includes steps S100 to S600 as follows.

[0089] In step S100, the first wafer w1 and the second wafer w2 are respectively used as the target wafer W.

[0090] It should be noted that in some of the following embodiments, the first wafer w1 and the second wafer w2 need to be respectively used as the target wafer W, and steps S200 to S500 are respectively executed on the target wafer W. Figure 7 The case where the first wafer w1 is used as the target wafer W and the wafer alignment mark is the first wafer alignment mark S1 is exemplified, but it can be understood that in the case where the second wafer w2 is used as the target wafer W and the wafer alignment mark is the second wafer alignment mark S2, the steps exemplified in some of the following embodiments also need to be executed, which will not be elaborated here. Figure 7 The steps for exemplification will not be elaborated here.

[0091] In step S200, at least two wafer alignment marks on one side of the first reference line (e.g., the x-axis) of the target wafer W are selected as the first target marks A1, and at least two wafer alignment marks on the other side of the first reference line (e.g., the x-axis) of the target wafer W are selected as the second target marks A2; wherein, at least two of the first target marks A1 are respectively on both sides of the second reference line (e.g., the y-axis), and at least two of the second target marks A2 are respectively on both sides of the second reference line (e.g., the y-axis); the second reference line (e.g., the y-axis) is orthogonal to the first reference line (e.g., the x-axis).

[0092] In some embodiments, please refer to Figure 5 , both the first wafer w1 and the second wafer w2 include a plurality of chips C arranged in an array, and each chip C has a wafer alignment mark. Step S200 includes the following step S210.

[0093] In step S210, a first chip C1 and a second chip C2 respectively located on both sides of the first reference line (e.g., the x-axis) of the target wafer W are selected, the wafer alignment mark on the first chip C1 is used as the first target mark A1, and the wafer alignment mark on the second chip C2 is used as the second target mark A2; wherein, the number of chips C spaced between the first chip C1 and the second chip C2 and the first reference line (e.g., the x-axis) in the direction parallel to the second reference line (e.g., the y-axis) is equal or as close as possible, and the number of chips C spaced between the first chip C1 and the second chip C2 and the second reference line (e.g., the y-axis) in the direction parallel to the first reference line (e.g., the x-axis) is equal or as close as possible.

[0094] It should be explained that the "number of spaced chips" refers to the number of complete chips C in the interval distance between the target mark and the reference line.

[0095] It should be noted that Figure 7 in the example, the number of chips C spaced between the first chip C1 and the second chip C2 in the direction parallel to the second reference line (e.g., the y-axis) and the first reference line (e.g., the x-axis) is 1, and the number of chips C spaced between the first chip C1 and the second chip C2 in the direction parallel to the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) is 1; however, it can be understood that the number of spaced chips C can also take other values, and the present application does not limit this.

[0096] It should be noted that, please continue to refer to Figure 7 , the number of the first chips C1 can be at least two, and the number of the second chips C2 can be at least two.

[0097] It should be supplemented that, in some examples, please continue to refer to Figure 7 , at least two first target marks A1 located on the same side of the first reference line (e.g., the x-axis) and on both sides of the second reference line (e.g., the y-axis) satisfy the following conditions: the number of chips C spaced between at least two first target marks A1 in the direction parallel to the second reference line (e.g., the y-axis) and the first reference line (e.g., the x-axis) is equal or as close as possible; the number of chips C spaced between at least two first target marks A1 in the direction parallel to the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) is equal or as close as possible.

[0098] In some examples, please continue to refer to Figure 7 , at least two second target marks A2 located on the same side of the first reference line (e.g., the x-axis) and on both sides of the second reference line (e.g., the y-axis) satisfy the following conditions: the number of chips C spaced between at least two second target marks A2 in the direction parallel to the second reference line (e.g., the y-axis) and the first reference line (e.g., the x-axis) is equal or as close as possible; the number of chips C spaced between at least two second target marks A2 in the direction parallel to the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) is equal or as close as possible.

[0099] In some embodiments, the rows and columns in which each first chip C1 in the first wafer w1 and each first chip C1 in the second wafer w2 are located in the chip array are the same or as close as possible, and the rows and columns in which each second chip C2 in the first wafer w1 and each second chip C2 in the second wafer w2 are located in the chip array are the same or as close as possible.

[0100] In step S300, first angle data of at least two first target marks A1 and second angle data of at least two second target marks A2 are respectively obtained.

[0101] In some embodiments, step S300 includes the following steps S310 to S320.

[0102] In step S310, determine the intersection point of the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) as the reference point o.

[0103] In step S320, determine the first angle data according to the angle between the straight-line connection between the geometric centers of at least two first target markers A1 and the reference point o and the first reference line (e.g., the x-axis), and determine the second angle data according to the angle between the straight-line connection between the geometric centers of at least two second target markers A2 and the reference point o and the first reference line (e.g., the x-axis).

[0104] Exemplarily, the first angle data can be the angle between the straight-line connection between the geometric center of the first target marker A1 and the reference point o and the positive direction of the first reference line (e.g., the positive x-axis), or the angle between the straight-line connection between the geometric center of the first target marker A1 and the reference point o and the negative direction of the first reference line (e.g., the negative x-axis), and this application does not limit this.

[0105] Exemplarily, the second angle data can be the angle between the straight-line connection between the geometric center of the second target marker A2 and the reference point o and the positive direction of the first reference line (e.g., the positive x-axis), or the angle between the straight-line connection between the geometric center of the second target marker A2 and the reference point o and the negative direction of the first reference line (e.g., the negative x-axis), and this application does not limit this.

[0106] It should be noted that the first angle data is the angle between the straight-line connection between the geometric centers of at least two first target markers A1 and the reference point o and the first reference line (e.g., the x-axis) in the same direction. The second angle data is the angle between the straight-line connection between the geometric centers of at least two second target markers A2 and the reference point o and the first reference line (e.g., the x-axis) in the same direction.

[0107] In some embodiments, the reference point o is located at the geometric center of the target wafer W.

[0108] It should be noted that in the above embodiments, the first reference line and the second reference line are orthogonal to the reference point o, and the reference point o is located at the geometric center of the target wafer W; then the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) can evenly divide the target wafer W into multiple fan-shaped regions with equal areas. Among them, please continue to refer to Figure 7 , each first target marker A1 and each second target marker A2 can be respectively located in different fan-shaped regions evenly divided by the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis).

[0109] In step S400, a first angular offset of the first target mark A1 is determined according to the first angular data, and a second angular offset of the second target mark A2 is determined according to the second angular data.

[0110] In step S500, an average angular offset of the corresponding target wafer W relative to the wafer stage is determined according to the first angular offset and the second angular offset.

[0111] Exemplarily, the average angular offset may be the arithmetic mean between the first angular offset and the second angular offset.

[0112] In step S600, angular alignment between the first wafer w1 and the second wafer w2 is performed according to the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2.

[0113] It should be noted that the relationship between the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2 can be used to characterize the rotational deviation caused by relative rotation between the second wafer w2 and the first wafer w1. The specific manner of performing angular alignment in step S600 may be: keeping the angle of the first wafer w1 fixed, and relatively rotating the second wafer w2 according to the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2 to compensate for the angular deviation.

[0114] Exemplarily, when the average angular offset of the first wafer w1 is equal to the average angular offset of the second wafer w2, angular alignment is achieved between the first wafer w1 and the second wafer w2.

[0115] In some embodiments, after step S200, the wafer alignment method further includes the following steps S710 to S740.

[0116] It should be noted that in some of the following embodiments, the first wafer w1 and the second wafer w2 need to be used as the target wafer W respectively, and steps S710 to S740 are performed on the target wafer W respectively. Moreover, the first target mark A1 and the second target mark A2 in the determination process of the position offset can be selected in step S200 in some of the above embodiments, which will not be elaborated here.

[0117] In step S710, first position data of at least two first target marks A1 and second position data of at least two second target marks A2 are obtained respectively.

[0118] It should be noted that the first position data and the second position data can be determined based on a rectangular coordinate system established with the first reference line as the x-axis, the second reference line as the y-axis, and the reference point o as the origin.

[0119] Exemplarily, the first position data includes the abscissa value of the first target mark A1 on the x-axis and the ordinate value on the y-axis. The first position data can be, for example, (Tx1, Ty1).

[0120] Exemplarily, the second position data includes the abscissa value of the second target mark A2 on the x-axis and the ordinate value on the y-axis. The second position data can be, for example, (Tx2, Ty2).

[0121] In some embodiments, the first angle data of at least two first target marks A1 is obtained by synchronous measurement with the first position data, and the second angle data of at least two second target marks A2 is obtained by synchronous measurement with the second position data.

[0122] In step S720, the first position offset of the first target mark A1 is determined according to the first position data, and the second position offset of the second target mark A2 is determined according to the second position data.

[0123] In some embodiments, the first position offset includes a first lateral position offset in a direction parallel to the first reference line (e.g., the x-axis) (e.g., the X direction) and a first longitudinal position offset in a direction parallel to the second reference line (e.g., the y-axis) (e.g., the Y direction); the second position offset includes a second lateral position offset in a direction parallel to the first reference line (e.g., the x-axis) (e.g., the X direction) and a second longitudinal position offset in a direction parallel to the second reference line (e.g., the y-axis) (e.g., the Y direction).

[0124] In step S730, the average position offset of the corresponding target wafer W relative to the wafer stage is determined according to the first position offset and the second position offset.

[0125] Exemplarily, the average position offset can be the arithmetic mean between the first position offset and the second position offset.

[0126] Exemplarily, the average position offset includes an average lateral position offset and an average longitudinal position offset. Among them, the average lateral position offset can be the arithmetic mean between the first lateral position offset and the second lateral position offset; the average longitudinal position offset can be the arithmetic mean between the first longitudinal position offset and the second longitudinal position offset.

[0127] In step S740, the position alignment between the first wafer w1 and the second wafer w2 is performed according to the average position offset of the first wafer w1 and the average position offset of the second wafer w2.

[0128] It should be noted that the relationship between the average position offset of the first wafer w1 and the average position offset of the second wafer w2 can be used to characterize the displacement deviation caused by the relative displacement between the second wafer w2 and the first wafer w1. The specific manner of performing position alignment in step S740 may be: keeping the position of the first wafer w1 fixed, and relatively translating the second wafer w2 according to the average position offset of the first wafer w1 and the average position offset of the second wafer w2 to compensate for the position deviation.

[0129] Exemplarily, when the average position offset of the first wafer w1 is equal to the average position offset of the second wafer w2, position alignment is achieved between the first wafer w1 and the second wafer w2.

[0130] In some embodiments, the wafer alignment method further includes the following step S800.

[0131] In step S800, according to the process sequence, the angular alignment of the current group of the first wafer w1 and the second wafer w2 is compensated based on the average angular offset of the previous group of the first wafer w1 and the average angular offset of the second wafer w2.

[0132] In some embodiments, the wafer alignment method further includes the following step S900.

[0133] In step S900, according to the process sequence, the position alignment of the current group of the first wafer w1 and the second wafer w2 is compensated based on the average position offset of the previous group of the first wafer w1 and the average position offset of the second wafer w2.

[0134] In some examples, the compensation processes in the above step S800 and step S900 can both be achieved by feeding back the offset to an Advanced Process Control (APC) system, and the APC system compensates for the wafer alignment based on the offset.

[0135] This application also provides a wafer bonding method according to some embodiments, and this wafer bonding method includes the wafer alignment method in the above - mentioned some embodiments. The technical advantages of the foregoing wafer alignment method are also possessed by this wafer bonding method. It should be noted that for the same or corresponding parts as the above - mentioned embodiments, reference can be made to the corresponding descriptions of the foregoing embodiments, and details will not be elaborated hereinafter.

[0136] In some embodiments, the wafer bonding method includes the following steps S001 - S003.

[0137] S001, Provide a first wafer and a second wafer.

[0138] In some examples, step S001 includes: fixing a first wafer to a first chuck of a wafer bonding machine platform; fixing a second wafer to a second chuck of the wafer bonding machine platform; wherein, the front sides of the first wafer and the second wafer are relatively close to each other.

[0139] Exemplarily, the front side of the first wafer is vertically upward, and the front side of the second wafer is vertically downward.

[0140] S002, align the second wafer and the first wafer by using the wafer alignment method in some of the foregoing embodiments of the present application.

[0141] S003, bond the aligned second wafer and the first wafer.

[0142] The wafer bonding method in the embodiments of the present application can match the central symmetry effect in the wafer production process during the wafer alignment process, determine at least two sets of offsets with global representativeness, which is beneficial to improving the wafer alignment accuracy, and thus is beneficial to achieving high-precision bonding of wafers, effectively improving the product yield of the wafer bonding process.

[0143] In the description of this specification, the descriptions with reference to terms such as "some embodiments", "some examples", "exemplarily", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0144] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0145] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application.

Claims

1. A wafer alignment method, characterized in that, For aligning a first wafer and a second wafer; The wafer alignment method includes: Using the first wafer and the second wafer as target wafers respectively; Selecting at least two wafer alignment marks on one side of a first reference line on the target wafer as first target marks, and selecting at least two wafer alignment marks on the other side of the first reference line on the target wafer as second target marks; wherein, at least two of the first target marks are respectively on both sides of a second reference line, and at least two of the second target marks are respectively on both sides of the second reference line; the second reference line is orthogonal to the first reference line; Obtaining first angle data of at least two of the first target marks and second angle data of at least two of the second target marks respectively; Determining a first angle offset of the first target marks according to the first angle data, and determining a second angle offset of the second target marks according to the second angle data; Determining an average angle offset of the corresponding target wafer relative to the wafer stage according to the first angle offset and the second angle offset; Performing angle alignment between the first wafer and the second wafer according to the average angle offset of the first wafer and the average angle offset of the second wafer.

2. The wafer alignment method according to claim 1, characterized in that, The obtaining first angle data of at least two of the first target marks and second angle data of at least two of the second target marks respectively includes: Determining the intersection point of the first reference line and the second reference line as a reference point; Determining the first angle data according to the angle between the straight line connecting the geometric centers of at least two of the first target marks and the reference point and the first reference line, and determining the second angle data according to the angle between the straight line connecting the geometric centers of at least two of the second target marks and the reference point and the first reference line.

3. The wafer alignment method according to claim 2, characterized in that, The reference point is located at the geometric center of the target wafer.

4. The wafer alignment method according to claim 1, characterized in that, Both the first wafer and the second wafer include a plurality of chips arranged in an array, and each chip has the wafer alignment mark; the selecting at least two wafer alignment marks on one side of a first reference line on the target wafer as first target marks, and selecting at least two wafer alignment marks on the other side of the first reference line on the target wafer as second target marks includes: Selecting a first chip and a second chip on both sides of the first reference line on the target wafer, using the wafer alignment mark on the first chip as the first target mark, and using the wafer alignment mark on the second chip as the second target mark; wherein, the number of chips spaced between the first chip and the second chip and the first reference line in the direction parallel to the second reference line is equal, and the number of chips spaced between the first chip and the second chip and the second reference line in the direction parallel to the first reference line is equal.

5. The wafer alignment method according to claim 4, characterized in that, Each of the first chips on the first wafer and each of the first chips on the second wafer are in the same row and column in the chip array, and each of the second chips on the first wafer and each of the second chips on the second wafer are in the same row and column in the chip array.

6. The wafer alignment method according to claim 1, characterized in that, After selecting at least two wafer alignment marks on one side of the first reference line on the target wafer as the first target marks and selecting at least two wafer alignment marks on the other side of the first reference line on the target wafer as the second target marks, the wafer alignment method further includes: Obtaining first position data of at least two of the first target marks and second position data of at least two of the second target marks respectively; Determining a first position offset of the first target marks according to the first position data, and determining a second position offset of the second target marks according to the second position data; Determining an average position offset of the corresponding target wafer relative to the wafer stage according to the first position offset and the second position offset; Performing position alignment between the first wafer and the second wafer according to the average position offset of the first wafer and the average position offset of the second wafer.

7. The wafer alignment method according to claim 6, characterized in that, The first position offset includes a first lateral position offset in a direction parallel to the first reference line and a first longitudinal position offset in a direction parallel to the second reference line; the second position offset includes a second lateral position offset in a direction parallel to the first reference line and a second longitudinal position offset in a direction parallel to the second reference line.

8. The wafer alignment method according to claim 6, characterized in that, The first angle data of at least two of the first target marks are obtained by synchronous measurement with the first position data, and the second angle data of at least two of the second target marks are obtained by synchronous measurement with the second position data.

9. The wafer alignment method according to claim 1, characterized in that, It further includes: According to the process sequence, compensating for the angle alignment of the current group of the first wafer and the second wafer according to the average angle offset of the previous group of the first wafer and the average angle offset of the second wafer.

10. A wafer bonding method, characterized in that, It includes: Providing a first wafer and a second wafer; Aligning the second wafer and the first wafer by using the wafer alignment method according to any one of claims 1 to 9; Bonding the aligned second wafer and the first wafer.

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