Time-interleaved analog-to-digital converter and error calibration method thereof

Abstract

The invention discloses a time-interleaved analog-to-digital converter and an error calibration method thereof, the time-interleaved analog-to-digital converter comprises a first digital calibration unit and a plurality of sub-ADCs, the first digital calibration unit calibrates a to-be-processed digital signal output by the to-be-calibrated sub-ADC according to a target gain trimming coefficient corresponding to the to-be-calibrated sub-ADC, and the to-be-processed digital signal is output by the to-be-calibrated sub-ADC. Obtaining a first target digital signal; the target gain trimming coefficient is determined by the first digital calibration unit based on a plurality of first digital signals output by the to-be-calibrated sub-ADC and a plurality of second digital signals output by the reference sub-ADC. The target gain trimming coefficient is determined through the digital signals output by the to-be-calibrated sub-ADC and the reference sub-ADC, and error calibration is performed on the to-be-processed digital signals by using the target gain trimming coefficient, so that the influence of mismatch errors on the conversion precision of the time-interleaved analog-to-digital converter is weakened, the conversion precision of the time-interleaved analog-to-digital converter is improved, and the time-interleaved analog-to-digital converter is improved. The performance of the time-interleaved analog-to-digital converter is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and particularly to a time-interleaved analog-to-digital converter and an error calibration method thereof. Background Art

[0002] With the rapid development of communication technologies, modern communication systems have increasingly high performance requirements for analog-to-digital converters (ADCs). To meet the performance requirements of communication systems, it is usually required that the analog-to-digital converter can receive broadband, high-frequency, and large-dynamic signals, which also requires the analog-to-digital converter to have a high data conversion rate and high sampling accuracy.

[0003] A time-interleaved analog-to-digital converter (TI ADC) is a multi-channel parallel sampling analog-to-digital converter, which has the characteristics of high conversion rate and high sampling accuracy. However, due to the influence of environmental factors such as mismatches between electronic components and unstable voltages, the operating conditions between the channels of the time-interleaved analog-to-digital converter cannot be kept completely consistent, resulting in mismatch errors, reducing the conversion accuracy of the time-interleaved analog-to-digital converter, and affecting the performance of the time-interleaved analog-to-digital converter. Summary of the Invention

[0004] The present invention provides a time-interleaved analog-to-digital converter and an error calibration method thereof to solve the problem of reduced conversion accuracy caused by the existing time-interleaved analog-to-digital converter due to the existence of mismatch errors.

[0005] In a first aspect, an embodiment of the present invention provides a time-interleaved analog-to-digital converter, including a first digital calibration unit and a plurality of sub-ADCs arranged in parallel, where:

[0006] The first digital calibration unit is electrically connected to a to-be-calibrated sub-ADC and a reference sub-ADC respectively, where the reference sub-ADC is a specified one of the plurality of sub-ADCs, and the to-be-calibrated sub-ADC is any one of the plurality of sub-ADCs;

[0007] The first digital calibration unit is configured to perform the following operations:

[0008] Calibrate the to-be-processed digital signal output by the to-be-calibrated sub-ADC according to a target gain trimming coefficient corresponding to the to-be-calibrated sub-ADC to obtain a first target digital signal;

[0009] Wherein, the target gain trimming coefficient is determined by the first digital calibration unit based on a plurality of first digital signals output by the to-be-calibrated sub-ADC and a plurality of second digital signals output by the reference sub-ADC.

[0010] In the time-interleaved analog-to-digital converter provided by the embodiment of the present invention, the first digital calibration unit determines a target gain trimming coefficient based on the first digital signal output by the sub-ADC to be calibrated and the second digital signal output by the reference sub-ADC, and uses the target gain trimming coefficient to calibrate the gain mismatch error in the digital signal to be processed, so as to obtain a first target digital signal, thereby reducing the influence of the gain mismatch error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter; in addition, through the first digital calibration unit, the calibration of the gain mismatch error of multiple sub-ADCs can be realized, reducing the hardware cost and improving the calibration efficiency.

[0011] In an alternative embodiment, the first digital calibration unit is specifically configured to perform the following operations:

[0012] Calculate the product of the target gain trimming coefficient and the digital signal to be processed to obtain a digital increment signal;

[0013] Use the sum of the digital increment signal and the digital signal to be processed as the first target digital signal.

[0014] The above analog-to-digital converter determines a digital increment signal through the product of the target gain trimming coefficient and the digital signal to be processed, and uses the sum of the digital increment signal and the digital signal to be processed as the first target digital signal, thereby realizing the calibration of the gain mismatch error in the digital signal to be processed, reducing the influence of the gain mismatch error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter.

[0015] In an alternative embodiment, the first digital calibration unit determines the target gain trimming coefficient in the following manner:

[0016] Process the multiple first digital signals and the multiple second digital signals through an iterative method until a preset number of iterations is satisfied, and use the gain trimming coefficient determined in the last round as the target gain trimming coefficient;

[0017] Wherein, in the process of one round of iteration, the gain trimming coefficient is determined in the following manner:

[0018] Calibrate the multiple first digital signals according to the gain trimming coefficient determined in the previous round of iteration to obtain multiple first calibrated digital signals;

[0019] Calculate the absolute value of the difference between any one of the multiple first calibration digital signals and the first delay signal to obtain a first absolute difference value, and calculate the absolute value of the difference between any one of the multiple second digital signals and the second delay signal to obtain a second absolute difference value;

[0020] Wherein, the first delay signal is obtained by delaying the first calibration digital signal, and the second delay signal is obtained by delaying the second digital signal;

[0021] Calculate the sum of multiple first absolute difference values, and use the average value of the obtained sum as the first gain value, and calculate the sum of multiple second absolute difference values, and use the average value of the obtained sum as the second gain value;

[0022] Calculate the difference between the second gain value and the first gain value, and process the obtained difference based on the least mean square algorithm, and use the processed difference as the gain adjustment coefficient determined in this round of iteration.

[0023] The above analog-to-digital converter adjusts the gain adjustment coefficient through multiple rounds of iteration, and uses the gain adjustment coefficient determined in the last round as the target gain adjustment coefficient to increase the accuracy of the target gain adjustment coefficient, and further increase the accuracy of error calibration for gain mismatch error.

[0024] In an alternative embodiment, the time-interleaved analog-to-digital converter further includes a second digital calibration unit;

[0025] The second digital calibration unit is electrically connected to the sub-ADC to be calibrated, the reference sub-ADC, and the first digital calibration unit respectively;

[0026] The second digital calibration unit is configured to perform the following operations:

[0027] Calibrate the to-be-processed digital signal output by the sub-ADC to be calibrated according to the target offset amount corresponding to the sub-ADC to be calibrated to obtain a second target digital signal;

[0028] The first digital calibration unit is configured to perform the following operations:

[0029] Calibrate the second target digital signal according to the target gain adjustment coefficient to obtain the first target digital signal;

[0030] Wherein, the target offset amount is determined by the second digital calibration unit based on multiple third digital signals output by the sub-ADC to be calibrated and multiple fourth digital signals output by the reference sub-ADC.

[0031] For the above analog-to-digital converter, the second digital calibration unit determines a target offset amount based on the digital signals output by the sub-ADC to be calibrated and the digital signals output by the reference sub-ADC, and uses the target offset amount to calibrate the offset error in the digital signal to be processed to obtain a second target digital signal. Then, the target gain trimming coefficient is used to calibrate the gain mismatch error in the second target digital signal to obtain a first target digital signal, thereby reducing the influence of the offset error and the gain mismatch error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter.

[0032] In an alternative embodiment, the second digital calibration unit is specifically configured to perform the following operations:

[0033] Calculate the difference between the digital signal to be processed and the target offset amount, and use the difference as the second target digital signal.

[0034] For the above analog-to-digital converter, by calculating the difference between the digital signal to be processed and the target offset amount, the second target digital signal is determined to eliminate the influence of the offset error and improve the performance of the time-interleaved analog-to-digital converter.

[0035] In an alternative embodiment, the second digital calibration unit determines the target offset amount in the following manner:

[0036] Accumulate the multiple third digital signals, and use the average value of the accumulation result as the first offset amount, and accumulate the multiple fourth digital signals, and use the average value of the accumulation result as the second offset amount;

[0037] Use the difference between the second offset amount and the first offset amount as the target offset amount.

[0038] For the above analog-to-digital converter, the first offset amount corresponding to the sub-ADC to be calibrated is determined through the digital signal output by the sub-ADC to be calibrated, and the second offset amount corresponding to the reference sub-ADC is determined through the digital signal output by the reference sub-ADC, and the difference between the second offset amount and the first offset amount is used as the target offset amount. Therefore, this target offset amount can be used to characterize the mismatch deviation between the sub-ADC to be calibrated and the reference sub-ADC.

[0039] In an alternative embodiment, the time-interleaved analog-to-digital converter further includes a third digital calibration unit and a plurality of clock-adjustable delay modules, where:

[0040] The third digital calibration unit is electrically connected to the plurality of sub-ADCs and the plurality of clock-adjustable delay modules respectively, and the plurality of clock-adjustable delay modules are also electrically connected to the plurality of sub-ADCs correspondingly;

[0041] The third digital calibration unit is configured to perform the following operations:

[0042] Adjust the sampling clock signal output by the clock adjustable delay module electrically connected to the sub-ADC to be calibrated according to the time skew corresponding to the sub-ADC to be calibrated, so that the sub-ADC to be calibrated outputs the digital signal to be processed under the control of the adjusted sampling clock signal;

[0043] Wherein, the time skew is determined by the third digital calibration unit based on the fifth digital signal output by the sub-ADC to be calibrated, the sixth digital signal output by the previous sub-ADC of the sub-ADC to be calibrated, and the target amplitude mean value, and the target amplitude mean value is determined by the third digital calibration unit based on the digital signals output by the multiple sub-ADCs.

[0044] For the above analog-to-digital converter, the third digital calibration unit determines the time skew according to the amplitude value of the digital signal output by the sub-ADC to be calibrated and the target amplitude mean value, and uses the time skew to adjust the sampling clock signal input to the sub-ADC to be calibrated, so as to eliminate the sampling time skew error problem in the digital signal to be processed caused by the time skew of the sampling clock signal, thereby reducing the influence of the sampling time skew error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter.

[0045] In an alternative embodiment, the third digital calibration unit determines the time skew in the following manner:

[0046] Calculate the difference between the amplitude value of the fifth digital signal and the amplitude value of the sixth digital signal to obtain an amplitude difference;

[0047] Calculate the difference between the amplitude difference and the target amplitude mean value to obtain a target amplitude difference;

[0048] Calculate the product of the target amplitude difference and the first coefficient, and use the sum of the product and the second coefficient as the time skew corresponding to the sub-ADC to be calibrated;

[0049] Wherein, the first coefficient and the second coefficient are determined according to the sampling frequency of the time-interleaved analog-to-digital converter.

[0050] For the above analog-to-digital converter, the amplitude difference corresponding to the sub-ADC to be calibrated is determined by the difference between the amplitude value of the fifth digital signal and the target amplitude mean value. Since there is a linear relationship between the amplitude difference and the time skew, the time skew corresponding to the sub-ADC to be calibrated is determined accordingly, thereby realizing the calibration of the sampling time skew and improving the performance of the time-interleaved analog-to-digital converter.

[0051] In an alternative embodiment, the third digital calibration unit determines the target amplitude mean in the following manner:

[0052] Calculate the absolute value of the difference between the multiple digital signals output by the second sub-ADC and the multiple digital signals output by the first sub-ADC, and perform an accumulation process on the obtained multiple absolute values, and take the average value of the accumulation result as the amplitude mean;

[0053] Wherein, the first sub-ADC is any one of the multiple sub-ADCs. If the first sub-ADC is not the last sub-ADC, the second sub-ADC is the next sub-ADC after the first sub-ADC. If the first sub-ADC is the last sub-ADC, the second sub-ADC is the first sub-ADC;

[0054] Take the average value of all the obtained amplitude means as the target amplitude mean.

[0055] The above analog-to-digital converter determines the amplitude mean according to the multiple digital signals output by two adjacent sub-ADCs, takes the average value of the determined multiple amplitude means as the target amplitude mean, and determines the time skew amount for sampling time skew calibration according to the target amplitude mean, thereby realizing the calibration of the sampling time skew and improving the performance of the time-interleaved analog-to-digital converter.

[0056] In a second aspect, an error calibration method for a time-interleaved analog-to-digital converter provided by an embodiment of the present invention is applied to the time-interleaved analog-to-digital converter described in any one of the embodiments in the first aspect above. The method includes:

[0057] Pass the digital signal to be processed output by the sub-ADC to be calibrated;

[0058] Wherein, the sub-ADC to be calibrated is any one of the multiple sub-ADCs arranged in parallel included in the time-interleaved analog-to-digital converter except the reference sub-ADC, and the reference sub-ADC is a specified one of the multiple sub-ADCs;

[0059] Pass the first digital calibration unit to calibrate the digital signal to be processed according to the target gain trimming coefficient corresponding to the sub-ADC to be calibrated to obtain the first target digital signal;

[0060] Wherein, the target gain trimming coefficient is determined by the first digital calibration unit based on the multiple first digital signals output by the sub-ADC to be calibrated and the multiple second digital signals output by the reference sub-ADC.

[0061] In an alternative embodiment, calibrating the to-be-processed digital signal by the first digital calibration unit according to the target gain trimming coefficient corresponding to the to-be-calibrated sub-ADC to obtain the first target digital signal includes:

[0062] Calculating, by the first digital calibration unit, the product of the target gain trimming coefficient and the to-be-processed digital signal to obtain a digital increment signal;

[0063] Taking, by the first digital calibration unit, the sum value of the digital increment signal and the to-be-processed digital signal as the first target digital signal.

[0064] In an alternative embodiment, the target gain trimming coefficient is obtained by the following method:

[0065] Processing, by the first digital calibration unit, the multiple first digital signals and the multiple second digital signals in a sampling and iterative manner until a preset number of iterations is satisfied, and taking the gain trimming coefficient determined in the last round as the target gain trimming coefficient;

[0066] Wherein, in the process of one round of iteration, the gain trimming coefficient is determined by the following method:

[0067] Calibrating, according to the gain trimming coefficient determined in the previous round of iteration, the multiple first digital signals to obtain multiple first calibrated digital signals;

[0068] Calculating the absolute value of the difference between any one of the multiple first calibrated digital signals and the first delay signal to obtain a first absolute difference value, and calculating the absolute value of the difference between any one of the multiple second digital signals and the second delay signal to obtain a second absolute difference value;

[0069] Wherein, the first delay signal is obtained by delaying the first calibrated digital signal, and the second delay signal is obtained by delaying the second digital signal;

[0070] Calculating the sum value of the multiple first absolute difference values and taking the average value of the obtained sum value as a first gain value, and calculating the sum value of the multiple second absolute difference values and taking the average value of the obtained sum value as a second gain value;

[0071] Calculating the difference between the second gain value and the first gain value, and processing the obtained difference based on the least mean square algorithm, and taking the processed difference as the gain trimming coefficient determined in the current round of iteration.

[0072] In an alternative embodiment, after the digital signal to be processed output by the sub-ADC to be calibrated, the following steps are further included:

[0073] The second digital calibration unit calibrates the digital signal to be processed according to the target offset corresponding to the sub-ADC to be calibrated, and obtains a second target digital signal;

[0074] Wherein, the target offset is determined by the second digital calibration unit based on a plurality of third digital signals output by the sub-ADC to be calibrated and a plurality of fourth digital signals output by the reference sub-ADC;

[0075] The first digital calibration unit calibrates the second target digital signal according to the target gain trimming coefficient to obtain the first target digital signal.

[0076] In an alternative embodiment, the step of calibrating the digital signal to be processed by the second digital calibration unit according to the target offset corresponding to the sub-ADC to be calibrated to obtain a second target digital signal includes:

[0077] The second digital calibration unit calculates the difference between the digital signal to be processed and the target offset, and uses the difference as the second target digital signal.

[0078] In an alternative embodiment, the target offset is determined by the following method:

[0079] The second digital calibration unit accumulates the plurality of third digital signals, and uses the average value of the accumulation result as the first offset, and accumulates the plurality of fourth digital signals, and uses the average value of the accumulation result as the second offset;

[0080] The second digital calibration unit uses the difference between the second offset and the first offset as the target offset.

[0081] In an alternative embodiment, the method further includes:

[0082] The third digital calibration unit adjusts the sampling clock signal according to the time skew corresponding to the sub-ADC to be calibrated;

[0083] Wherein, the sampling clock is output by a clock adjustable delay module electrically connected to the sub-ADC to be calibrated;

[0084] Under the control of the adjusted sampling clock signal, the sub-ADC to be calibrated outputs the digital signal to be processed;

[0085] Wherein, the time skew amount is determined by the third digital calibration unit based on the fifth digital signal output by the to-be-calibrated sub-ADC, the sixth digital signal output by the previous sub-ADC of the to-be-calibrated sub-ADC, and the target amplitude mean value, and the target amplitude mean value is determined by the third digital calibration unit based on the digital signals output by the multiple sub-ADCs.

[0086] In an alternative embodiment, the time skew amount is determined in the following manner:

[0087] The third digital calibration unit calculates the difference between the amplitude value of the fifth digital signal and the amplitude value of the sixth digital signal to obtain an amplitude difference.

[0088] The third digital calibration unit calculates the difference between the amplitude difference and the target amplitude mean value to obtain a target amplitude difference.

[0089] The third digital calibration unit calculates the product of the target amplitude difference and the first coefficient, and takes the sum value of the product and the second coefficient as the time skew amount corresponding to the to-be-calibrated sub-ADC.

[0090] Wherein, the first coefficient and the second coefficient are determined according to the sampling frequency of the time-interleaved analog-to-digital converter.

[0091] In an alternative embodiment, the target amplitude mean value is determined in the following manner:

[0092] The third digital calibration unit calculates the absolute value of the difference between the multiple digital signals output by the second sub-ADC and the multiple digital signals output by the first sub-ADC, accumulates the obtained multiple absolute values, and takes the average value of the accumulation result as the amplitude mean value.

[0093] Wherein, the first sub-ADC is any one of the multiple sub-ADCs. If the first sub-ADC is not the last sub-ADC, the second sub-ADC is the next sub-ADC of the first sub-ADC. If the first sub-ADC is the last sub-ADC, the second sub-ADC is the first sub-ADC.

[0094] The third digital calibration unit takes the average value of all the obtained amplitude mean values as the target amplitude mean value.

[0095] In addition, for the technical effects brought by any implementation manner in the second aspect, reference may be made to the technical effects brought by different implementation manners in the first aspect, which will not be elaborated herein. Description of the Drawings

[0096] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0097] Figure 1 Structural schematic diagram of a time-interleaved analog-to-digital converter provided by the related art;

[0098] Figure 2 Waveform schematic diagram of a sampling clock signal provided by the related art;

[0099] Figure 3 Structural schematic diagram of a time-interleaved analog-to-digital converter provided by an embodiment of the present invention;

[0100] Figure 4 Internal structural schematic diagram of a first digital calibration unit provided by an embodiment of the present invention;

[0101] Figure 5 Internal structural schematic diagram of a least mean square algorithm engine provided by an embodiment of the present invention;

[0102] Figure 6 Schematic diagram of the working process for a first digital calibration unit to determine a gain adjustment coefficient provided by an embodiment of the present invention;

[0103] Figure 7 Schematic diagram of the working process for a first digital calibration unit to calibrate a digital signal to be processed provided by an embodiment of the present invention;

[0104] Figure 8 Structural schematic diagram of another time-interleaved analog-to-digital converter provided by an embodiment of the present invention;

[0105] Figure 9 Internal structural schematic diagram of a second digital calibration unit provided by an embodiment of the present invention;

[0106] Figure 10 Schematic diagram of the working process for a second digital calibration unit to determine a target offset provided by an embodiment of the present invention;

[0107] Figure 11 Structural schematic diagram of another time-interleaved analog-to-digital converter provided by an embodiment of the present invention;

[0108] Figure 12 Internal structural schematic diagram of a third digital calibration unit provided by an embodiment of the present invention;

[0109] Figure 13Schematic diagram of the working process for a third digital calibration unit to determine the target amplitude mean provided by an embodiment of the present invention;

[0110] Figure 14 Schematic diagram of the working process for a third digital calibration unit to determine the time skew provided by an embodiment of the present invention;

[0111] Figure 15 Schematic diagram of the structure of another time-interleaved analog-to-digital converter provided by an embodiment of the present invention;

[0112] Figure 16 Schematic diagram of the flow of an error calibration method for a time-interleaved analog-to-digital converter provided by an embodiment of the present invention. Detailed implementation manners

[0113] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0114] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present invention. On the contrary, they are only examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0115] In recent years, with the rapid development of communication technologies, modern communication systems have increasingly higher requirements for the performance of analog-to-digital converters. To meet the performance requirements of communication systems, it is usually required that analog-to-digital converters can receive broadband, high-frequency, and large-dynamic signals, which also requires analog-to-digital converters to have a high data conversion rate and a high sampling accuracy.

[0116] However, due to the limitations of manufacturing processes, it is difficult for a single-chip analog-to-digital converter to simultaneously meet the requirements of high conversion rate and high sampling accuracy. Therefore, time-interleaved analog-to-digital converters have been proposed. As a multi-channel parallel sampling analog-to-digital converter, time-interleaved analog-to-digital converters have the characteristics of both high conversion rate and high sampling accuracy. Time-interleaved analog-to-digital converters can increase the overall sampling rate of the system to more than gigasamples per second (Gsps), and are the mainstream architecture in the research of analog-to-digital converters in recent years.

[0117] However, due to the influence of environmental factors such as mismatches in electronic components and unstable voltages in a time-interleaved analog-to-digital converter, the operating conditions between channels cannot be kept completely consistent, resulting in mismatch errors between channels. Among them, the mismatch errors in a time-interleaved analog-to-digital converter mainly include offset error, gain mismatch error, and sampling time skew error. The existence of the aforementioned errors will introduce additional spurs and noise in the output spectrum, reducing the conversion accuracy of the time-interleaved analog-to-digital converter and seriously affecting the system performance of the time-interleaved analog-to-digital converter.

[0118] Based on this, the embodiments of the present invention provide a time-interleaved analog-to-digital converter and an error calibration method thereof to calibrate the offset error, gain error, and sampling time skew error in the time-interleaved analog-to-digital converter, improve the conversion accuracy of the time-interleaved analog-to-digital converter, and improve the performance of the time-interleaved analog-to-digital converter.

[0119] The time-interleaved analog-to-digital converter provided by the present invention will be specifically introduced below with reference to the accompanying drawings:

[0120] Figure 1 A schematic structural diagram of a time-interleaved analog-to-digital converter is shown. As Figure 1 shown, the time-interleaved analog-to-digital converter 100 includes an analog-to-digital conversion module 110 and a data multiplexing module 120. Among them, the analog-to-digital conversion module 110 includes a plurality of parallel analog-to-digital conversion channels (1101 to 110M), and the data multiplexing module 120 includes a multiplexer MUX01;

[0121] The input ends of the plurality of analog-to-digital conversion channels (1101 to 110M) are all used to input an analog input signal x(t), and the output ends of the plurality of analog-to-digital conversion channels (1101 to 110M) are respectively electrically connected to the plurality of input ends of the MUX 01;

[0122] The MUX 01 is used to alternately output the digital signals output by the plurality of analog-to-digital conversion channels (1101 to 110M) in sequence to obtain the output signal y(n) of the time-interleaved analog-to-digital converter 100.

[0123] As Figure 1 shown, the analog-to-digital conversion channel 1101 includes a sample and hold circuit S / H1 and a sub-ADC (sub-ADC1) connected electrically, and the sampling clock signal of the analog-to-digital conversion channel 1101 is clk1;

[0124] The analog-to-digital conversion channel 1102 includes a sample-and-hold circuit S / H2 and a sub-ADC (sub-ADC2) that are electrically connected. The sampling clock signal of the analog-to-digital conversion channel 1102 is clk2;

[0125] The analog-to-digital conversion channel 1103 includes a sample-and-hold circuit S / H3 and a sub-ADC (sub-ADC3) that are electrically connected. The sampling clock signal of the analog-to-digital conversion channel 1103 is clk3;

[0126] And so on, the analog-to-digital conversion channel 110M includes a sample-and-hold circuit S / H M and a sub-ADC (sub-ADC M ), and the sampling clock signal of the analog-to-digital conversion channel 110M is clk M .

[0127] Figure 2 Fig. shows a schematic diagram of the sampling clock signal of a time-interleaved analog-to-digital converter 100. As Figure 2 shown, clk is the reference clock signal, and the period of the reference clock signal clk is T S , and the frequency is After the reference clock signal clk is divided by M through a frequency divider, sampling clock signals clk1, clk2, clk3,..., clk M are generated, and the sampling clock signals are transmitted to the corresponding analog-to-digital conversion channels. Among them, the phase difference between the sampling clock signals corresponding to adjacent two channels is the same.

[0128] In a specific implementation, the sampling rate of the time-interleaved analog-to-digital converter 100 including M parallel analog-to-digital conversion channels is M times higher than that of a single-chip analog-to-digital converter, and the conversion accuracy of the time-interleaved analog-to-digital converter 100 is the same as that of each sub-ADC.

[0129] Figure 3 Fig. shows a schematic structural diagram of a time-interleaved analog-to-digital converter provided by an embodiment of the present invention. As Figure 3 shown, the time-interleaved analog-to-digital converter 300 includes a first digital calibration unit 310 and a plurality of sub-ADCs 320 arranged in parallel;

[0130] In one or more embodiments, the time-interleaved analog-to-digital converter 300 can be a time-interleaved successive approximation register ADC (TI SAR ADC), or can be other types of time-interleaved analog-to-digital converters, and the embodiments of the present invention do not make any restrictions on this.

[0131] The first digital calibration unit 310 is electrically connected to the sub-ADC to be calibrated and the reference sub-ADC respectively. Among them, the reference sub-ADC is a specified one of the multiple sub-ADCs 320, and the sub-ADC to be calibrated is any one of the multiple sub-ADCs 320;

[0132] Exemplarily, as Figure 3 shown, for the time-interleaved analog-to-digital converter 300 including N sub-ADCs (sub-ADC1 to sub-ADC N ), the first sub-ADC, that is, sub-ADC1, is used as the reference sub-ADC, and sub-ADC2 to sub-ADC N are sequentially used as the sub-ADCs to be calibrated.

[0133] Among them, sub-ADC1 can also be used as the sub-ADC to be calibrated ( Figure 3 not shown in the figure). At this time, the determined target gain trimming coefficient corresponding to the sub-ADC to be calibrated is 0.

[0134] The first digital calibration unit 310 is used to perform the following operations:

[0135] Calibrate the to-be-processed digital signal output by the sub-ADC to be calibrated according to the target gain trimming coefficient corresponding to the sub-ADC to be calibrated to obtain the first target digital signal;

[0136] Among them, the target gain trimming coefficient is determined by the first digital calibration unit 310 based on multiple first digital signals output by the sub-ADC to be calibrated and multiple second digital signals output by the reference sub-ADC.

[0137] Exemplarily, as Figure 3 shown, d a1 is the first target digital signal output by sub-ADC1, d a2 is the first target digital signal output by sub-ADC2, d a3 is the first target digital signal output by sub-ADC3, and so on, d aN is the first target digital signal output by sub-ADC N .

[0138] In the time-interleaved analog-to-digital converter provided by the embodiment of the present invention, the first digital calibration unit determines the target gain trimming coefficient through the first digital signal output by the sub-ADC to be calibrated and the second digital signal output by the reference sub-ADC, and uses the target gain trimming coefficient to calibrate the gain error in the to-be-processed digital signal to obtain the first target digital signal, thereby reducing the influence of the gain error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter;

[0139] In addition, through the first digital calibration unit, the gain errors of multiple sub-ADCs can be calibrated, reducing the hardware overhead and improving the calibration efficiency.

[0140] In an optional embodiment, the first digital calibration unit 310 determines the target gain trimming coefficient in the following manner:

[0141] Process multiple first digital signals and multiple second digital signals through an iterative manner until the preset number of iterations is satisfied, and use the gain trimming coefficient determined in the last round as the target gain trimming coefficient;

[0142] In one or more embodiments, the number of iterations is an empirical value and can be flexibly set according to actual service requirements. For example, the number of iterations can be set to 6.

[0143] In one or more embodiments, Figure 4 shows a schematic internal structure diagram of a first digital calibration unit 310, as Figure 4 shown, the first digital calibration unit 310 includes a delay element (Z -1 ) D1, an adder ADD1, an absolute value unit (ABS1), and an accumulation and averaging unit (ACC&AVG 1) that are electrically connected in sequence;

[0144] Among them, the input end of the delay element D1 and the positive input end of the adder ADD1 are both used to input the digital signal output by the reference sub-ADC;

[0145] The first digital calibration unit 310 further includes a multiplier MUL1 and an adder ADD2, a delay element (Z -1 ) D2, an adder ADD3, an absolute value unit (ABS2), and an accumulation and averaging unit (ACC&AVG 2) that are electrically connected in sequence;

[0146] Among them, the first positive input end of the adder ADD2 is used to input the digital signal output by the sub-ADC to be calibrated, and the second positive input end of the adder ADD2 is electrically connected to the output end of the multiplier MUL1;

[0147] The first input end of the multiplier MUL1 is used to input the target gain trimming coefficient corresponding to the sub-ADC to be calibrated, and the second input end of the multiplier MUL1 is used to input the digital signal output by the sub-ADC to be calibrated;

[0148] The output end of the adder ADD2 is also electrically connected to the reverse input end of the adder ADD3;

[0149] The first digital calibration unit 310 further includes an adder ADD4 and a Least Mean Square Algorithm engine (LMS engine 1);

[0150] Among them, the forward input terminal of the adder ADD4 is electrically connected to the output terminal of ACC&AVG 1, and the reverse input terminal of the adder ADD4 is electrically connected to the output terminal of ACC&AVG 2; the output terminal of the adder ADD4 is electrically connected to the input terminal of LMS engine 1;

[0151] The output terminal of LMS engine 1 is electrically connected to the first input terminal of the multiplier MUL1.

[0152] Figure 5 The internal structure schematic diagram of a least mean square algorithm engine LMS engine 1 is shown. As Figure 5 shown, LMS engine 1 includes an adjustment unit M1, an adder ADD5, and a delay element (Z -1 ) D3 that are electrically connected in sequence. Among them, after receiving the difference signal output by the adder ADD4, the adjustment unit M1 uses the trimming strength coefficient U G for adjustment and then transmits the adjusted signal to one input terminal of the adder ADD5; the output terminal of the delay element D3 is electrically connected to the other input terminal of the adder ADD5 and serves as the output terminal of LMS engine 1;

[0153] Among them, the trimming strength coefficient U G is stored in a register (GM Register).

[0154] During one round of iteration, as Figure 6 shown, the gain trimming coefficient is determined through steps S601 to S604:

[0155] Step S601: Calibrate a plurality of first digital signals according to the gain trimming coefficient determined in the previous round of iteration to obtain a plurality of first calibrated digital signals;

[0156] In one or more embodiments, if this round of iteration is the first round of iteration, then the plurality of first calibrated digital signals in step S501 are the plurality of first digital signals output by the sub-ADC to be calibrated.

[0157] In a specific implementation, based on Figure 4 the first digital calibration unit 310 shown, taking sub-ADC1 as the reference sub-ADC, the second digital signal output by sub-ADC1 is d1[n], and taking sub-ADC2 as the sub-ADC to be calibrated, the first digital signal output by sub-ADC2 is d2[n];

[0158] During the first-round iteration, the first digital signal d2[n] is directly used as the first calibrated digital signal;

[0159] During the non-first-round iteration, the first digital signal d2[n] is calibrated according to the gain trimming coefficient determined in the previous round, and the calibrated signal is used as the first calibrated digital signal.

[0160] Step S602: Calculate the absolute value of the difference between any one of the multiple first calibrated digital signals and the first delay signal to obtain the first absolute difference value, and calculate the absolute value of the difference between any one of the multiple second digital signals and the second delay signal to obtain the second absolute difference value;

[0161] Among them, the first delay signal is obtained by delaying the first calibrated digital signal, and the second delay signal is obtained by delaying the second digital signal;

[0162] In a specific implementation, both sub-ADC1 and sub-ADC2 quantify a preset duration to obtain multiple second digital signals and multiple first digital signals. Among them, the preset duration is an empirical value and can be flexibly set according to actual service requirements.

[0163] Based on Figure 4 As shown in the first digital calibration unit 310, during the first-round iteration, the second digital signal d1[n] is delayed by the delay unit D1 to obtain the second delay signal d1[n - 1]; after the second digital signal d1[n] and the second delay signal d1[n - 1] pass through the adder ADD1, the obtained difference is: F1 = d1[n] - d1[n - 1]; the difference F1 passes through the absolute value unit (ABS1) to obtain the second absolute difference value: |F1| = |d1[n] - d1[n - 1]|;

[0164] At the same time, the first digital signal d2[n] is delayed by the delay unit D2 to obtain the first delay signal d2[n - 1]; after the first digital signal d2[n] and the first delay signal d2[n - 1] pass through the adder ADD3, the obtained difference is: F2 = d2[n] - d2[n - 1]; the difference F2 passes through the absolute value unit (ABS2) to obtain the first absolute difference value: |F2| = |d2[n] - d2[n - 1]|.

[0165] Based on Figure 4 As shown in the first digital calibration unit 310, during the non-first-round iteration, taking the second-round iteration as an example:

[0166] Assume that based on the gain trimming coefficient determined in the first round of iteration, after trimming the first digital signal d2[n] through the multiplier MUL1 and the adder ADD2, the obtained first calibrated digital signal is d2[n]’, then:

[0167] The second digital signal d1[n] undergoes a delay process by the delay element D1 to obtain a second delayed signal d1[n - 1]; after the second digital signal d1[n] and the second delayed signal d1[n - 1] pass through the adder ADD1, the obtained difference is: F1 = d1[n] - d1[n - 1]; after the difference F1 passes through the absolute value unit (ABS1), the obtained second absolute difference value is: |F1| = |d1[n] - d1[n - 1]|;

[0168] Meanwhile, the first calibrated digital signal d2[n]’ undergoes a delay process by the delay element D2 to obtain a first delayed signal d2[n - 1]’; after the first calibrated digital signal d2[n]’ and the first delayed signal d2[n - 1]’ pass through the adder ADD3, the obtained difference is: F2’ = d2[n]’ - d2[n - 1]’; after the difference F2’ passes through the absolute value unit (ABS2), the obtained first absolute difference value is: |F2’| = |d2[n]’ - d2[n - 1]’|.

[0169] Step S603, calculate the sum value of multiple first absolute difference values, and use the average value of the obtained sum value as the first gain value, and calculate the sum value of multiple second absolute difference values, and use the average value of the obtained sum value as the second gain value;

[0170] In a specific implementation, within a preset time duration, the sub - ADC1 outputs K1 second digital signals d1[n], and the sub - ADC2 outputs K1 first digital signals d2[n], then according to step S502, K1 second absolute difference values and K1 first absolute difference values can be obtained.

[0171] Based on Figure 4 the first digital calibration unit 310 shown, taking the second round of iteration as an example:

[0172] Pass multiple second absolute difference values |F1| = |d1[n] - d1[n - 1]| through ACC&AVG 1 to obtain the second gain value S1 = ∑|F1| = ∑|d1[n] - d1[n - 1]|;

[0173] Meanwhile, pass multiple first absolute difference values |F2’| = |d2[n]’ - d2[n - 1]’| through ACC&AVG 2 to obtain the first gain value S2 = ∑|F2’| = ∑|d2[n]’ - d2[n - 1]’|.

[0174] In one or more embodiments, it can be determined through step S503 that:

[0175] The gain value corresponding to sub-ADC1 is: S1 = ∑|F1| = ∑|d1[n] - d1[n - 1]|;

[0176] The gain value corresponding to sub-ADC2 is: S2 = ∑|F2| = ∑|d2[n] - d2[n - 1]|;

[0177] The gain value corresponding to sub-ADC3 is: S3 = ∑|F3| = ∑|d3[n] - d3[n - 1]|;

[0178] ……

[0179] The gain value corresponding to sub-ADC N is: S N = ∑|F N | = ∑|d N [n] - d N [n - 1]|.

[0180] Step S604, calculate the difference between the second gain value and the first gain value, and process the obtained difference based on the least mean square algorithm, and use the processed difference as the gain adjustment coefficient determined in the current round of iteration.

[0181] Based on Figure 4 the first digital calibration unit 310 shown, taking the second round of iteration as an example:

[0182] The second gain value S1 = ∑|F1| = ∑|d1[n] - d1[n - 1]|, and the first gain value S2 = ∑|F2'| = ∑|d2[n]' - d2[n - 1]'|, after passing through the adder ADD4, the obtained difference is:

[0183] S1 - S2 = ∑|F1| - ∑|F2'|

[0184] = ∑|d1[n] - d1[n - 1]| - ∑|d2[n]' - d2[n - 1]'|;

[0185] Then, the difference S1 - S2 is processed by the least mean square algorithm through the LMS engine 1, and the processed data is used as the gain adjustment coefficient determined in the current round of iteration.

[0186] In one or more embodiments, the LMS engine 1 processes the difference S1 - S2 based on the adjustment strength coefficient U G where the adjustment strength coefficient U G is stored in the GM Register.

[0187] In a specific implementation, the adjustment strength coefficient U G is an empirical value and corresponds one-to-one with the number of iterations, and can be flexibly set according to actual business requirements. For example, for 6 iterations, the adjustment strengths corresponding to the 6 iterations are set as: [±12, ±6, ±3, ±2, ±2, ±1, ±1], then the adjustment strength coefficients U for the 6 iterations G are respectively:

[0188] where 27 = 12 + 6 + 3 + 2 + 2 + 1 + 1.

[0189] In a specific implementation, the adjustment strength coefficient stored in the GM Register can be adjusted, and different ranges of adjustment for the difference between the second gain value and the first gain value can be achieved.

[0190] In a specific implementation, if the sub-ADC1 is used as the reference ADC and the sub-ADCs 2 to sub-ADC N are used as the sub-ADCs to be calibrated in sequence, then through steps S501 to S504, it can be determined that:

[0191] The gain adjustment coefficient corresponding to the sub-ADC1 is 0;

[0192] The gain adjustment coefficient corresponding to the sub-ADC2 is

[0193] The gain adjustment coefficient corresponding to the sub-ADC3 is

[0194] ……

[0195] The gain adjustment coefficient corresponding to the sub-ADC N is

[0196] By means of multiple rounds of iteration, the gain adjustment coefficient is adjusted, and the gain adjustment coefficient determined in the last round is used as the target gain adjustment coefficient to increase the accuracy of the target gain adjustment coefficient, and further increase the accuracy of error calibration for the gain error.

[0197] In an alternative embodiment, as Figure 7 shown, the first digital calibration unit 310 specifically determines the first target digital signal through steps S701 to S702:

[0198] Step S701, calculate the product of the target gain adjustment coefficient and the digital signal to be processed to obtain a digital increment signal;

[0199] Based on Figure 4 the first digital calibration unit 310 shown, the digital signal d to be processeda [n] and the target gain trimming coefficient After passing through the multiplier MUL1, the obtained digital increment signal is:

[0200] Step S702: Use the sum value of the digital increment signal and the digital signal to be processed as the first target digital signal.

[0201] Based on Figure 4 As shown in the first digital calibration unit 310, the digital increment signal and the digital signal d a [n] After passing through the adder ADD2, the obtained first target digital signal is

[0202]

[0203] Determine the digital increment signal through the product of the target gain trimming coefficient and the digital signal to be processed, and use the sum value of the digital increment signal and the digital signal to be processed as the first target digital signal, thereby realizing the calibration of the gain error in the digital signal to be processed, weakening the influence of the gain error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter.

[0204] In an alternative embodiment, as Figure 8 shown, the time-interleaved analog-to-digital converter 300 further includes a second digital calibration unit 330;

[0205] The second digital calibration unit 330 is electrically connected to the sub-ADC to be calibrated, the reference sub-ADC, and the first digital calibration unit 310 respectively;

[0206] The second digital calibration unit 330 is used to perform the following operations:

[0207] Calibrate the digital signal to be processed output by the sub-ADC to be calibrated according to the target offset corresponding to the sub-ADC to be calibrated to obtain a second target digital signal;

[0208] Among them, the target offset is determined by the second digital calibration unit based on a plurality of third digital signals output by the sub-ADC to be calibrated and a plurality of fourth digital signals output by the reference sub-ADC.

[0209] In a specific implementation, after completing the calibration of the capacitor mismatch error of the sub-ADC of the time-interleaved analog-to-digital converter 300, start the calibration operation of the offset error.

[0210] In one or more embodiments, Figure 9 shows a schematic internal structure diagram of a second digital calibration unit 330, as Figure 9As shown, the second digital calibration unit 330 includes an accumulation and averaging unit (ACC&AVG 3), an accumulation and averaging unit (ACC&AVG 4), an adder ADD6, and an adder ADD7, where:

[0211] The input terminal of ACC&AVG 3 is used to input the digital signal d 01 [n] output by the reference sub-ADC, and the output terminal of ACC&AVG 3 is electrically connected to the positive input terminal of adder ADD6;

[0212] The input terminal of ACC&AVG 4 is used to input the digital signal d 02 [n] output by the sub-ADC to be calibrated, and the output terminal of ACC&AVG 4 is electrically connected to the negative input terminal of adder ADD6;

[0213] The output terminal of adder ADD6 is electrically connected to the negative input terminal of adder ADD7, and is used to output the target offset ΔS corresponding to the sub-ADC to be calibrated;

[0214] The positive input terminal of adder ADD7 is used to input the digital signal d 02 [n] output by the sub-ADC to be calibrated, and the output terminal of adder ADD7 is used to output the second target signal d a02 [n].

[0215] In an alternative embodiment, as Figure 10 shown, the second digital calibration unit 330 determines the target offset through steps S1001 to S1002:

[0216] Step S1001: Accumulate multiple third digital signals, and use the average value of the accumulation result as the first offset, and accumulate multiple fourth digital signals, and use the average value of the accumulation result as the second offset;

[0217] In a specific implementation, based on the second digital calibration unit 330 as Figure 9 shown, taking sub-ADC1 as the reference sub-ADC, the fourth digital signal output by sub-ADC1 is d 01 [n], taking sub-ADC2 as the sub-ADC to be calibrated, and the third digital signal output by sub-ADC2 is d 02 [n];

[0218] After passing multiple third digital signals d 02 [n] through ACC&AVG 4, the obtained first offset is: S 02 = avg(∑d 02 [n]); at the same time, after passing multiple fourth digital signals d 01 [n] through ACC&AVG 3, the obtained second offset is: S01 = avg(∑d 01 [n]).

[0219] Step S1002: Use the difference between the second offset amount and the first offset amount as the target offset amount.

[0220] In a specific implementation, based on the second digital calibration unit 330 as shown in Figure 9 , after adding the first offset amount S 02 and the second offset amount S 01 through the adder ADD6, the obtained target offset amount is:

[0221] ΔS 02 = S 01 - S 02 = avg(∑d 01 [n]) - avg(∑d 02 [n]);

[0222] In one or more embodiments, take sub - ADC1 as the reference ADC, and take sub - ADC2 to sub - ADC N in sequence as the sub - ADCs to be calibrated. Then, through steps S1001 - S1002, it can be determined that:

[0223] The target offset amount corresponding to sub - ADC1 is 0;

[0224] The target offset amount corresponding to sub - ADC2 is ΔS 02 ;

[0225] ……

[0226] The target offset amount corresponding to sub - ADC N is ΔS 0N .

[0227] Determine the first offset amount corresponding to the sub - ADC to be calibrated through the digital signal output by the sub - ADC to be calibrated, and determine the second offset amount corresponding to the reference sub - ADC through the digital signal output by the reference sub - ADC. Then, use the difference between the second offset amount and the first offset amount as the target offset amount. Therefore, this target offset amount can be used to characterize the mismatch deviation between the sub - ADC to be calibrated and the reference sub - ADC.

[0228] In an alternative embodiment, the second digital calibration unit 330 is specifically configured to perform the following operations:

[0229] Calculate the difference between the digital signal to be processed and the target offset amount, and use the difference as the second target digital signal.

[0230] In a specific implementation, based on the second digital calibration unit 330 as shown in Figure 9 , for the digital signal d to be processeda After [n] and the target offset ΔS pass through the adder ADD7, the second target digital signal obtained is: d a02 [n] = d a [n] - ΔS.

[0231] By calculating the difference between the digital signal to be processed and the target offset, the second target digital signal is determined to eliminate the influence of the offset error and improve the performance of the time-interleaved analog-to-digital converter.

[0232] In one or more embodiments, after the offset error calibration is completed by the second digital calibration unit 330, the second target digital signal output by the second digital calibration unit 330 is further transmitted to the first digital calibration unit 310 to continue the gain error calibration operation;

[0233] Among them, the first digital calibration unit 310 is used to perform the following operations:

[0234] Calibrate the second target digital signal according to the target gain trimming coefficient to obtain the first target digital signal.

[0235] The second digital calibration unit 330 determines the target offset through the digital signal output by the sub-ADC to be calibrated and the digital signal output by the reference sub-ADC, and uses the target offset to calibrate the offset error in the digital signal to be processed to obtain the second target digital signal, and then uses the target gain trimming coefficient to calibrate the gain error in the second target digital signal to obtain the first target digital signal, thereby weakening the influence of the offset error and the gain error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter.

[0236] In a specific implementation, first, the second digital calibration unit 330 calibrates the mismatch error in the digital signal to be processed, then, the first digital calibration unit 310 calibrates the gain error in the digital signal to be processed after the mismatch error calibration is completed, and finally, the sampling clock signal of the sub-ADC to be calibrated is calibrated in the following manner:

[0237] In an alternative embodiment, as Figure 11 shown, the time-interleaved analog-to-digital converter 300 further includes a third digital calibration unit 340 and a plurality of clock-adjustable delay modules 350, where:

[0238] The third digital calibration unit 340 is electrically connected to a plurality of sub-ADCs 310 and a plurality of clock-adjustable delay modules 350 respectively, and the plurality of clock-adjustable delay modules 350 are also electrically connected to the plurality of sub-ADCs 310 correspondingly;

[0239] The third digital calibration unit 340 is used to perform the following operations:

[0240] According to the time skew corresponding to the sub-ADC to be calibrated, adjust the sampling clock signal output by the clock adjustable delay module electrically connected to the sub-ADC to be calibrated, so that the sub-ADC to be calibrated outputs a digital signal to be processed under the control of the adjusted sampling clock signal;

[0241] Among them, the time skew is determined by the third digital calibration unit based on the fifth digital signal output by the sub-ADC to be calibrated, the sixth digital signal output by the previous sub-ADC of the sub-ADC to be calibrated, and the target amplitude mean value, and the target amplitude mean value is determined by the third digital calibration unit based on the digital signals output by multiple sub-ADCs.

[0242] In one or more embodiments, after the third digital calibration unit 340 enables the sampling time skew calibration operation, the time-interleaved analog-to-digital converter 300 performs sampling and quantization operations on a single-tone sine wave with an amplitude of A and an angular frequency of ω. Among them, the digital signals output by multiple sub-ADCs 310 in the time-interleaved analog-to-digital converter 300 can be expressed as:

[0243] The digital signal corresponding to sub-ADC1 is:

[0244] Among them, f s is the overall sampling rate of the time-interleaved analog-to-digital converter 300, and Δt0 is the time skew corresponding to sub-ADC1;

[0245] The digital signal corresponding to sub-ADC2 is:

[0246] Among them, Δt1 is the time skew corresponding to sub-ADC2;

[0247] The digital signal corresponding to sub-ADC3 is:

[0248] Among them, Δt2 is the time skew corresponding to sub-ADC3;

[0249] ……

[0250] The digital signal corresponding to sub-ADC N is:

[0251] Among them, Δt N-1 is the time skew corresponding to sub-ADC N ;

[0252] Then, calculate the difference between the digital signals corresponding to two adjacent sub-ADCs. Taking sub-ADC1 and sub-ADC2 as an example, the difference between the obtained digital signals is:

[0253]

[0254] As can be seen from the above formula, the difference between the digital signals corresponding to sub-ADC1 and sub-ADC2 can be expressed as a sine wave whose amplitude is related to the time skew, and the amplitude of this difference is:

[0255]

[0256] Since Δt1 and Δt0 in the above formula are in the order of picoseconds, it can be simplified to:

[0257]

[0258] It can be seen therefrom that the amplitude of the difference signal is linearly related to the time skew, that is, the sampling time delay link can be feedback-controlled through the amplitude.

[0259] In one or more embodiments, taking the time-interleaved analog-to-digital converter 300 including 4 sub-ADCs, namely sub-ADC1, sub-ADC2, sub-ADC3, and sub-ADC4, as an example, the internal structure of the third digital calibration unit 340 will be described:

[0260] As Figure 12 shown, the third digital calibration unit 340 includes 4 processing channels corresponding to 4 sub-ADCs, an average value determination unit (AVG1), an adder ADD12, an adder ADD13, and a least mean square algorithm engine (LMS engine 2);

[0261] Among them, the processing channel corresponding to sub-ADC1 includes a delay element (Z -1 ) D4, an adder ADD8, an absolute value unit (ABS 3), and an accumulative average value unit (ACC&AVG 5) connected in series; the input end of the delay element D4 is used to input the digital signal output by sub-ADC1, and the output end of the ACC&AVG 5 is electrically connected to one input end of the AVG1;

[0262] The processing channel corresponding to sub-ADC2 includes a delay element (Z -1 ) D5, an adder ADD9, an absolute value unit (ABS 4), and an accumulative average value unit (ACC&AVG 6) connected in series; the input end of the delay element D5 is used to input the digital signal output by sub-ADC2, the output end of the delay element D5 is also electrically connected to one input end of the adder ADD8, and the output end of the ACC&AVG 6 is electrically connected to the other input end of the AVG1;

[0263] The processing channel corresponding to sub-ADC3 includes a delay element (Z -1) D6, adder ADD10, absolute value unit (ABS 5), and accumulative mean unit (ACC&AVG 7); the input end of delay unit D6 is used to input the digital signal output by sub-ADC3, and the output end of delay unit D6 is also electrically connected to one input end of adder ADD9, and the output end of ACC&AVG 7 is electrically connected to the other input end of AVG1;

[0264] The processing channel corresponding to sub-ADC4 includes a delay unit (Z -1 ) D7, adder ADD11, absolute value unit (ABS 6), and accumulative mean unit (ACC&AVG 8); the input end of delay unit D7 is used to input the digital signal output by sub-ADC4, and the output end of delay unit D7 is also electrically connected to one input end of adder ADD10, and the output end of ACC&AVG 8 is electrically connected to the other input end of AVG1;

[0265] One input end of adder ADD11 is also electrically connected to the input end of delay unit D4;

[0266] The output end of AVG1 is electrically connected to one input end of ADD12, the other input end of ADD12 is electrically connected to the output end of adder ADD13, the output end of ADD12 is electrically connected to the input end of LMS engine 2, and the output end of LMS engine 2 is used to output the time skew (Δt1~Δt4) for adjusting the clock adjustable delay module corresponding to each sub-ADC;

[0267] The positive input end of adder ADD13 is used to receive the digital signal output by the sub-ADC ( Figure 12 sub-ADC2 in it), and the negative input end of adder ADD13 is used to receive the digital signal output by the previous sub-ADC of the sub-ADC to be calibrated ( Figure 12 sub-ADC1 in it).

[0268] The third digital calibration unit 340 further includes a register (TM Register) storing the adjustment coefficient U T , and the output end of TMRegister is electrically connected to the controlled end of LMS engine 2;

[0269] LMS engine 2 is based on the least mean square algorithm and, according to the adjustment coefficient U T , adjusts the output result of ADD12 to generate the time skew (Δt1~Δt4) for adjusting the clock adjustable delay module corresponding to each sub-ADC;

[0270] In addition, since the internal structure of the LMS engine 2 is similar to that of the LMS engine 1, the internal structure of the LMS engine 2 can be referred to Figure 5 the internal structure of the LMS engine 1 shown, which will not be elaborated here.

[0271] It should be noted that for the time-interleaved analog-to-digital converter 300 including other numbers of sub-ADCs, the internal structure diagram of the third digital calibration unit 340 can be referred to Figure 12 , but Figure 12 it should not limit the embodiments of the present invention.

[0272] In an alternative embodiment, as Figure 13 shown, the third digital calibration unit 340 determines the target amplitude mean value through steps S1301 to S1302:

[0273] Step S1301, calculate the absolute value of the difference between the multiple digital signals output by the second sub-ADC and the multiple digital signals output by the first sub-ADC, and perform an accumulation process on the obtained multiple absolute values, and use the average value of the accumulation result as the amplitude mean value;

[0274] Among them, the first sub-ADC is any one of the multiple sub-ADCs. If the first sub-ADC is not the last sub-ADC, the second sub-ADC is the next sub-ADC of the first sub-ADC. If the first sub-ADC is the last sub-ADC, the second sub-ADC is the first sub-ADC;

[0275] In a specific implementation, the time-interleaved analog-to-digital converter 300 includes N sub-ADCs, and the digital signals output by each sub-ADC are respectively: d1[n], d2[n],.., d N [n];

[0276] Among them, if sub-ADC1 is used as the first sub-ADC, sub-ADC2 is used as the second sub-ADC. If sub-ADC2 is used as the first sub-ADC, sub-ADC3 is used as the second sub-ADC, and so on. If sub-ADC N is used as the first sub-ADC, sub-ADC1 is used as the second sub-ADC

[0277] Taking sub-ADC1 as the first sub-ADC and sub-ADC2 as the second sub-ADC as an example:

[0278] As Figure 12As shown, after delaying the digital signal d1[n] output by the sub-ADC1 through the delay unit D4, and delaying the d2[n] output by the sub-ADC2 through the delay unit D5, and then passing them through the adder ADD8, the obtained difference is: d2[n] - d1[n]; after passing this difference through the ABS3, the obtained absolute value is: |d2[n] - d1[n]|; after passing this absolute value through the ACC&AVG 5, the obtained amplitude average value is: avg(∑|d2[n] - d1[n]|);

[0279] By the same method, N amplitude average values can be obtained, which are respectively:

[0280] avg(∑|d2[n] - d1[n]|), avg(∑|d3[n] - d2[n]|),..., avg(∑|d N [n] - d N-1 [n]|), avg(∑|d1[n + 1] - d N [n]|).

[0281] Step S1302: Use the average value of all the obtained amplitude average values as the target amplitude average value.

[0282] In a specific implementation, AVG1 calculates the average value of the N amplitude average values obtained through step S1301 to obtain the target amplitude average value, that is:

[0283]

[0284] According to multiple digital signals output by adjacent sub-ADCs, determine the amplitude average value, use the average value of the determined multiple amplitude average values as the target amplitude average value, and determine the time skew amount for sampling time skew calibration according to this target amplitude average value, so as to realize the calibration of sampling time skew and improve the performance of the time-interleaved analog-to-digital converter.

[0285] In a specific implementation, after the third digital calibration unit 340 determines the target amplitude average value, it determines the time skew amount corresponding to each sub-ADC according to this target amplitude average value:

[0286] In an alternative embodiment, as Figure 14 shown, the third digital calibration unit 340 determines the time skew amount through steps S1401 - S1402:

[0287] Step S1401: Calculate the difference between the amplitude value of the fifth digital signal and the amplitude value of the sixth digital signal to obtain the amplitude difference;

[0288] In a specific implementation, as Figure 12As shown, taking the sub-ADC2 as the sub-ADC to be calibrated and the sub-ADC1 as the previous sub-ADC of the sub-ADC to be calibrated as an example, after the fifth digital signal output by the sub-ADC2 and the sixth digital signal output by the sub-ADC1 pass through the adder ADD13, the determined amplitude difference is Δamp.

[0289] Step S1402: Calculate the difference between the amplitude difference and the target amplitude mean value to obtain the target amplitude difference;

[0290] In a specific implementation, as Figure 12 shown, the target amplitude mean value Amp t and the amplitude difference Δamp pass through the adder ADD12 to perform an amplitude subtraction operation to obtain the target amplitude difference ΔAmp t = Δamp - Amp t .

[0291] Step S1403: Calculate the product of the target amplitude difference and the first coefficient, and use the sum value of the product and the second coefficient as the time skew amount corresponding to the sub-ADC to be calibrated;

[0292] Among them, the first coefficient and the second coefficient are determined according to the sampling frequency of the time-interleaved analog-to-digital converter.

[0293] Among them, according to the formula: it can be known that:

[0294]

[0295] Among them, is the first coefficient, is the second coefficient, and Δt is the time skew amount corresponding to the sub-ADC to be calibrated.

[0296] In one or more embodiments, the LMS engine 2 is used to gradually approximate the time skew amount Δt to improve the accuracy of the determined time skew amount Δt.

[0297] Determine the amplitude difference corresponding to the sub-ADC to be calibrated through the difference between the amplitude value of the fifth digital signal and the target amplitude mean value. Since there is a linear relationship between the amplitude difference and the time skew amount, the time skew amount corresponding to the sub-ADC to be calibrated is determined accordingly, thereby realizing the calibration of the sampling time skew and improving the performance of the time-interleaved analog-to-digital converter.

[0298] In a specific implementation, the time skew amount Δt corresponding to the sub-ADC to be calibrated is output to the clock adjustable delay module corresponding to the sub-ADC to be calibrated to adjust the phase of the clock signal output by the clock adjustable delay module.

[0299] The third digital calibration unit 340 determines a time skew amount according to the amplitude value of the digital signal output by the sub-ADC to be calibrated and the target amplitude mean value, and uses the time skew amount to adjust the sampling clock signal input to the sub-ADC to be calibrated, so as to eliminate the sampling time skew error problem in the digital signal to be processed caused by the time skew of the sampling clock signal, thereby reducing the influence of the sampling time skew error on the conversion accuracy of the time-interleaved analog-to-digital converter, improving the conversion accuracy of the time-interleaved analog-to-digital converter, and improving the performance of the time-interleaved analog-to-digital converter.

[0300] In one or more embodiments, as Figure 15 shown, the first digital calibration unit 310, the second digital calibration unit 330, and the third digital calibration unit 340 may be integrated in a digital processing module (LOGIC), and the digital processing module (LOGIC) is connected to N sub-ADCs, facilitating the integration of the time-interleaved analog-to-digital converter chip;

[0301] Among them, the input ends of the N sub-ADCs are respectively electrically connected to the differential input ends (VIP, VIN), the reference voltage ends (Vref_P, Vref_N), and the sampling clock end; the phases of the sampling clock signals of different sub-ADCs are different. For example, the phase of the sampling clock signal corresponding to the first sub-ADC is φ1, the phase of the sampling clock signal corresponding to the second sub-ADC is φ2, and so on. The phase of the sampling clock signal corresponding to the Nth sub-ADC is φN.

[0302] Based on the same concept, the embodiment of the present invention further provides an error calibration method for a time-interleaved analog-to-digital converter. Since this method is the method executed by the time-interleaved analog-to-digital converter in the embodiment of the present invention, and the principle of solving the problem of this method is similar to that of the time-interleaved analog-to-digital converter, the implementation of this method can refer to the implementation of the time-interleaved analog-to-digital converter, and the repeated parts will not be elaborated.

[0303] As Figure 16 shown, the above method includes the following steps:

[0304] Step S1601, output the digital signal to be processed through the sub-ADC to be calibrated;

[0305] Among them, the sub-ADC to be calibrated is any one of the multiple sub-ADCs arranged in parallel included in the time-interleaved analog-to-digital converter except the reference sub-ADC, and the reference sub-ADC is a specified one of the multiple sub-ADCs;

[0306] Step S1602, calibrate the digital signal to be processed through the first digital calibration unit according to the target gain trimming coefficient corresponding to the sub-ADC to be calibrated to obtain the first target digital signal;

[0307] Among them, the target gain trimming coefficient is determined by the first digital calibration unit based on a plurality of first digital signals output by the sub-ADC to be calibrated and a plurality of second digital signals output by the reference sub-ADC.

[0308] In an alternative embodiment, the first digital calibration unit calibrates the digital signal to be processed according to the target gain trimming coefficient corresponding to the sub-ADC to be calibrated, and obtains a first target digital signal, including:

[0309] The first digital calibration unit calculates the product of the target gain trimming coefficient and the digital signal to be processed to obtain a digital increment signal;

[0310] The first digital calibration unit uses the sum value of the digital increment signal and the digital signal to be processed as the first target digital signal.

[0311] In an alternative embodiment, the target gain trimming coefficient is obtained by the following method:

[0312] The first digital calibration unit processes a plurality of first digital signals and a plurality of second digital signals in an iterative sampling manner until a preset number of iterations is satisfied, and uses the gain trimming coefficient determined in the last round as the target gain trimming coefficient;

[0313] Among them, in the process of one round of iteration, the gain trimming coefficient is determined by the following method:

[0314] According to the gain trimming coefficient determined in the previous round of iteration, a plurality of first digital signals are calibrated to obtain a plurality of first calibrated digital signals;

[0315] Calculate the absolute value of the difference between any one of the first calibrated digital signals in the plurality of first calibrated digital signals and the first time-delay signal to obtain a first absolute difference value, and calculate the absolute value of the difference between any one of the second digital signals in the plurality of second digital signals and the second time-delay signal to obtain a second absolute difference value;

[0316] Among them, the first time-delay signal is obtained by delaying the first calibrated digital signal, and the second time-delay signal is obtained by delaying the second digital signal;

[0317] Calculate the sum value of the plurality of first absolute difference values, and use the average value of the obtained sum value as the first gain value, and calculate the sum value of the plurality of second absolute difference values, and use the average value of the obtained sum value as the second gain value;

[0318] Calculate the difference between the second gain value and the first gain value, and process the obtained difference based on the least mean square algorithm, and use the processed difference as the gain trimming coefficient determined in this round of iteration.

[0319] In an alternative embodiment, after the digital signal to be processed output by the sub-ADC to be calibrated, the following is further included:

[0320] The second digital calibration unit calibrates the digital signal to be processed according to the target offset amount corresponding to the sub-ADC to be calibrated, and obtains a second target digital signal;

[0321] Wherein, the target offset amount is determined by the second digital calibration unit based on a plurality of third digital signals output by the sub-ADC to be calibrated and a plurality of fourth digital signals output by the reference sub-ADC;

[0322] The first digital calibration unit calibrates the second target digital signal according to the target gain trimming coefficient, and obtains a first target digital signal.

[0323] In an alternative embodiment, the second digital calibration unit calibrates the digital signal to be processed according to the target offset amount corresponding to the sub-ADC to be calibrated, and obtains a second target digital signal, including:

[0324] The second digital calibration unit calculates the difference between the digital signal to be processed and the target offset amount, and uses the difference as the second target digital signal.

[0325] In an alternative embodiment, the target offset amount is determined by the following method:

[0326] The second digital calibration unit accumulates a plurality of third digital signals, and uses the average value of the accumulation result as the first offset amount, and accumulates a plurality of fourth digital signals, and uses the average value of the accumulation result as the second offset amount;

[0327] The second digital calibration unit uses the difference between the second offset amount and the first offset amount as the target offset amount.

[0328] In an alternative embodiment, the method further includes:

[0329] The third digital calibration unit adjusts the sampling clock signal according to the time skew amount corresponding to the sub-ADC to be calibrated;

[0330] Wherein, the sampling clock is output by a clock adjustable delay module electrically connected to the sub-ADC to be calibrated;

[0331] Under the control of the adjusted sampling clock signal, the sub-ADC to be calibrated outputs a digital signal to be processed;

[0332] Among them, the time skew is determined by a third digital calibration unit based on a fifth digital signal output by a sub-ADC to be calibrated, a sixth digital signal output by the previous sub-ADC of the sub-ADC to be calibrated, and a target amplitude mean value. The target amplitude mean value is determined by the third digital calibration unit based on digital signals output by multiple sub-ADCs.

[0333] In an alternative embodiment, the time skew is determined in the following manner:

[0334] The third digital calibration unit calculates the difference between the amplitude value of the fifth digital signal and the amplitude value of the sixth digital signal to obtain an amplitude difference.

[0335] The third digital calibration unit calculates the difference between the amplitude difference and the target amplitude mean value to obtain a target amplitude difference.

[0336] The third digital calibration unit calculates the product of the target amplitude difference and a first coefficient, and takes the sum value of the product and a second coefficient as the time skew corresponding to the sub-ADC to be calibrated.

[0337] Among them, the first coefficient and the second coefficient are determined according to the sampling frequency of the time-interleaved analog-to-digital converter.

[0338] In an alternative embodiment, the target amplitude mean value is determined in the following manner:

[0339] The third digital calibration unit calculates the absolute value of the difference between multiple digital signals output by a second sub-ADC and multiple digital signals output by a first sub-ADC, and performs an accumulation process on the obtained multiple absolute values, and takes the average value of the accumulation result as the amplitude mean value.

[0340] Among them, the first sub-ADC is any one of the multiple sub-ADCs. If the first sub-ADC is not the last sub-ADC, the second sub-ADC is the next sub-ADC of the first sub-ADC. If the first sub-ADC is the last sub-ADC, the second sub-ADC is the first sub-ADC.

[0341] The third digital calibration unit takes the average value of all obtained amplitude mean values as the target amplitude mean value.

[0342] Those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A time-interleaved analog-to-digital converter, characterized in that, It includes a first digital calibration unit and a plurality of sub-analog-to-digital converters (ADCs) arranged in parallel, where: The first digital calibration unit is electrically connected to the sub-ADC to be calibrated and the reference sub-ADC respectively. Among them, the reference sub-ADC is a specified sub-ADC among the plurality of sub-ADCs, and the sub-ADC to be calibrated is any one of the plurality of sub-ADCs; The first digital calibration unit is used to perform the following operations: Calibrate the digital signal to be processed output by the sub-ADC to be calibrated according to the target gain trimming coefficient corresponding to the sub-ADC to be calibrated to obtain a first target digital signal; Among them, the target gain trimming coefficient is determined by the first digital calibration unit based on a plurality of first digital signals output by the sub-ADC to be calibrated and a plurality of second digital signals output by the reference sub-ADC.

2. The analog-to-digital converter according to claim 1, characterized in that, The first digital calibration unit is specifically used to perform the following operations: Calculate the product of the target gain trimming coefficient and the digital signal to be processed to obtain a digital increment signal; Use the sum value of the digital increment signal and the digital signal to be processed as the first target digital signal.

3. The analog-to-digital converter according to claim 1, characterized in that, The first digital calibration unit determines the target gain trimming coefficient in the following manner: Process the plurality of first digital signals and the plurality of second digital signals in an iterative manner until a preset number of iterations is satisfied, and use the gain trimming coefficient determined in the last round as the target gain trimming coefficient; Among them, in the process of one round of iteration, the gain trimming coefficient is determined in the following manner: Calibrate the plurality of first digital signals according to the gain trimming coefficient determined in the previous round of iteration to obtain a plurality of first calibrated digital signals; Calculate the absolute value of the difference between any one of the plurality of first calibrated digital signals and the first delay signal to obtain a first absolute difference value, and calculate the absolute value of the difference between any one of the plurality of second digital signals and the second delay signal to obtain a second absolute difference value; Among them, the first delay signal is obtained by delaying the first calibrated digital signal, and the second delay signal is obtained by delaying the second digital signal; Calculate the sum value of the plurality of first absolute difference values and use the average value of the obtained sum value as the first gain value, and calculate the sum value of the plurality of second absolute difference values and use the average value of the obtained sum value as the second gain value; Calculate the difference between the second gain value and the first gain value, and process the obtained difference based on the least mean square algorithm, and use the processed difference as the gain trimming coefficient determined in the current round of iteration.

4. The analog-to-digital converter according to claim 1, characterized in that, It further includes a second digital calibration unit; The second digital calibration unit is electrically connected to the sub-ADC to be calibrated, the reference sub-ADC, and the first digital calibration unit respectively; The second digital calibration unit is used to perform the following operations: Calibrate the digital signal to be processed output by the sub-ADC to be calibrated according to the target offset corresponding to the sub-ADC to be calibrated to obtain a second target digital signal; The first digital calibration unit is used to perform the following operations: Calibrate the second target digital signal according to the target gain trimming coefficient to obtain the first target digital signal; Wherein, the target offset amount is determined by the second digital calibration unit based on a plurality of third digital signals output by the sub-ADC to be calibrated and a plurality of fourth digital signals output by the reference sub-ADC.

5. The analog-to-digital converter according to claim 4, characterized in that, The second digital calibration unit is specifically used to perform the following operations: Calculate the difference between the digital signal to be processed and the target offset amount, and use the difference as the second target digital signal.

6. The analog-to-digital converter according to claim 4, characterized in that, The second digital calibration unit determines the target offset amount in the following manner: Accumulate the plurality of third digital signals, and use the average value of the accumulation result as the first offset amount, and accumulate the plurality of fourth digital signals, and use the average value of the accumulation result as the second offset amount; Use the difference between the second offset amount and the first offset amount as the target offset amount.

7. The analog-to-digital converter according to claim 1 or 4, characterized in that, It further includes a third digital calibration unit and a plurality of clock-adjustable delay modules, wherein: The third digital calibration unit is electrically connected to the plurality of sub-ADCs and the plurality of clock-adjustable delay modules respectively, and the plurality of clock-adjustable delay modules are also correspondingly electrically connected to the plurality of sub-ADCs; The third digital calibration unit is used to perform the following operations: Adjust the sampling clock signal output by the clock-adjustable delay module electrically connected to the sub-ADC to be calibrated according to the time skew amount corresponding to the sub-ADC to be calibrated, so that the sub-ADC to be calibrated outputs the digital signal to be processed under the control of the adjusted sampling clock signal; Wherein, the time skew amount is determined by the third digital calibration unit based on a fifth digital signal output by the sub-ADC to be calibrated, a sixth digital signal output by the previous sub-ADC of the sub-ADC to be calibrated, and a target amplitude mean value, and the target amplitude mean value is determined by the third digital calibration unit based on digital signals output by the plurality of sub-ADCs.

8. The analog-to-digital converter according to claim 7, wherein, The third digital calibration unit determines the time skew amount in the following manner: Calculate the difference between the amplitude value of the fifth digital signal and the amplitude value of the sixth digital signal to obtain an amplitude difference; Calculate the difference between the amplitude difference and the target amplitude mean value to obtain a target amplitude difference; Calculate the product of the target amplitude difference and a first coefficient, and use the sum value of the product and a second coefficient as the time skew amount corresponding to the sub-ADC to be calibrated; Wherein, the first coefficient and the second coefficient are determined according to the sampling frequency of the time-interleaved analog-to-digital converter.

9. The analog-to-digital converter according to claim 7, wherein, The third digital calibration unit determines the target amplitude mean value in the following manner: Calculate the absolute value of the difference between a plurality of digital signals output by the second sub-ADC and a plurality of digital signals output by the first sub-ADC, and perform an accumulation process on the obtained plurality of absolute values, and use the average value of the accumulation result as the amplitude mean value; Among them, the first sub-ADC is any one of the multiple sub-ADCs. If the first sub-ADC is not the last sub-ADC, the second sub-ADC is the next sub-ADC of the first sub-ADC. If the first sub-ADC is the last sub-ADC, the second sub-ADC is the first sub-ADC; The average value of all the obtained amplitude means is used as the target amplitude mean.

10. An error calibration method for a time-interleaved analog-to-digital converter, wherein, Applied to the time-interleaved analog-to-digital converter according to any one of claims 1 to 9, the method includes: Obtain a to-be-processed digital signal output by a to-be-calibrated sub-analog-to-digital converter (ADC) through a first digital calibration unit in the time-interleaved analog-to-digital converter; Among them, the to-be-calibrated sub-ADC is any one of the multiple sub-ADCs arranged in parallel included in the time-interleaved analog-to-digital converter, except for a reference sub-ADC, and the reference sub-ADC is a specified one of the multiple sub-ADCs; Calibrate the to-be-processed digital signal according to a target gain trimming coefficient corresponding to the to-be-calibrated sub-ADC through the first digital calibration unit to obtain the first target digital signal; Among them, the target gain trimming coefficient is determined by the first digital calibration unit based on multiple first digital signals output by the to-be-calibrated sub-ADC and multiple second digital signals output by the reference sub-ADC.

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