Silicon carbide semiconductor device

Abstract

The present application relates to a silicon carbide semiconductor device comprising: a silicon carbide substrate formed of silicon carbide of a first conductivity type; a drift layer formed on a first surface of the silicon carbide substrate from a first conductivity type silicon carbide, and a plurality of body layers formed on the drift layer from a second conductivity type silicon carbide; and a plurality of source layers formed of silicon carbide of the first conductivity type over each of the body layers. In addition, the semiconductor device further comprises a gate insulating film formed in contact with the main body layer and the source electrode layer, a gate electrode, an interlayer insulating film for covering the gate electrode and the gate insulating film, and a conductive barrier layer arranged between the side part of the interlayer insulating film and the source electrode and used for preventing hydrogen ions from passing through, therefore, hydrogen ions can be prevented from entering the semiconductor device, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to semiconductor technology, and particularly to a silicon carbide semiconductor device. Background Art

[0002] Compared with semiconductor devices using silicon (Si) as a substrate, semiconductor devices using silicon carbide (SiC) as a substrate and a drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed, and are thus used in, for example, power semiconductor devices.

[0003] For example, in the silicon carbide semiconductor device (SiC-MOSFET) described in Patent Document [Japanese Unexamined Patent Application Publication No. 2021-93496], as an interlayer insulating film between an insulating gate electrode and a source wiring, a TEOS (Tetra Ethy OrthoSilicate) oxide film is deposited, and a BPSG (Boro-phospho-silicate Glass) film is deposited on the TEOS oxide film, and further a TEOS oxide film is deposited on the BPSG film to form a three-layer insulating film. In other non-patent literature [DOI 10.1109 / JEDS.2021.3109347, Journal of the Institute of Electrical and Electronics Engineers, Inc. Electron Devices Society], it is pointed out that in a trench-type power SiC-MOSFET, when hydrogen ions (H+) penetrate into the device, the reliability of HTRB (High Temperature Reverse Bias Test) is reduced. To solve this problem, by using a material with a high phosphorus concentration as the interlayer insulating film, hydrogen ions are adsorbed to prevent hydrogen ions from entering the interior of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0004] However, silicon carbide semiconductor devices such as SiC-MOSFETs are usually resin-encapsulated, and hydrogen ions precipitated from the resin can pass through the source wiring electrode, the gate, and the gate insulating film to reach the channel region of the body layer, thereby reducing the reliability of the HTRB test and causing fluctuations in the gate threshold voltage (Vth) and an increase in leakage current of the semiconductor device. Therefore, it is necessary to prevent hydrogen ions from passing through the interlayer insulating film. Summary of the Invention

[0005] This application is made to overcome the above problems. The object of this application is to provide a silicon carbide semiconductor device that can prevent hydrogen ions from reaching the gate electrode and the gate insulating film from the source wiring electrode and can improve the reliability of the silicon carbide semiconductor device.

[0006] In a first aspect, an embodiment of this application provides a silicon carbide semiconductor device, including: A silicon carbide substrate formed of silicon carbide of a first conductivity type; A drift layer formed of silicon carbide of a first conductivity type on a first surface of the silicon carbide substrate; A plurality of body layers formed of silicon carbide of a second conductivity type above the drift layer; A plurality of source layers formed of silicon carbide of a first conductivity type and having an impurity concentration higher than that of the drift layer on each of the plurality of body layers; A gate insulating film formed by connecting with the body layer and the source layer; A gate formed on the gate insulating film; An interlayer insulating film covering the gate and the gate insulating film; And a conductive blocking layer provided between a side surface of the interlayer insulating film and a source electrode for preventing hydrogen ions from passing through.

[0007] According to an embodiment of the present application, since a conductive blocking layer for preventing hydrogen ions from passing through is provided between a side portion of the interlayer insulating film of the silicon carbide semiconductor device and the source electrode, the interlayer insulating film and the source electrode are blocked by the conductive blocking layer, and hydrogen ions can be prevented from entering the channel region through the gate insulating film and the gate electrode. Therefore, it is possible to prevent a decrease in reliability, a change in gate threshold voltage (Vth), and an increase in leakage current in the HTRB (High Temperature Reverse Bias) test caused by hydrogen ions reaching the channel region, thereby improving the reliability of the silicon carbide semiconductor device.

[0008] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more concise and understandable. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments and descriptions thereof of the present application are used to explain the present application and do not constitute an improper limitation of the present application.

[0010] Figure 1 is a cross-sectional view of the silicon carbide semiconductor device according to an embodiment of the present application; Figure 2 is Figure 1 a partial cross-sectional view of the manufacturing process of the silicon carbide semiconductor device shown; Figure 3 is Figure 1 a partial cross-sectional view of the manufacturing process of the silicon carbide semiconductor device shown; Figure 4 is Figure 1 a partial cross-sectional view of the manufacturing process of the silicon carbide semiconductor device shown; Figure 5 is Figure 1 a partial cross-sectional view of the manufacturing process of the silicon carbide semiconductor device shown; Figure 6 is Figure 1 A partial cross-sectional view of the manufacturing process of the silicon carbide semiconductor device shown in the figure.

[0011] 1 - Semiconductor device; 2 - Silicon carbide substrate; 3 - Drift layer; 4 - Body layer; 5 - Source layer; 6 - Body contact layer; 7 - Gate insulating film; 8 - Gate electrode; 9 - Interlayer insulating film; 10 - Source electrode; 10a - End portion on the side of the interlayer insulating film; 11 - Source wiring electrode; 12 - Drain electrode; 13 - Wiring; 13a - Ball bonding; 14 - Molding resin; 15 - Conductive barrier layer; 15d - Conductive film; 30 - First surface; 31 - Second surface; 41 - Upper corner portion; 42 - Side portion of the interlayer insulating film; 43 - Lower end of the side portion of the interlayer insulating film. Detailed implementation manners

[0012] To more clearly understand the purpose, technical solution, and advantages of the present application, the present application will be described and explained below with reference to the accompanying drawings and embodiments.

[0013] Unless otherwise defined, the technical terms or scientific terms involved in the present application shall have the general meaning understood by those with ordinary skills in the technical field to which the present application belongs. In the present application, words such as "a", "one", "a kind of", "the", "these", etc. do not indicate a limitation in quantity, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in the present application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products, or devices. The terms "connect", "be connected", "couple" and other similar words involved in the present application are not limited to physical or mechanical connections, but may include electrical connections, whether directly connected or indirectly connected. The term "a plurality of" involved in the present application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in the present application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0014] In the embodiments described below, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type can also be set to p-type and the second conductivity type can be set to n-type.

[0015] In addition, with regard to terms indicating directions such as up, down, left, right, side, inner, and outer, explanations are provided based on Figure 1 this, so they may be different from the directions of the actual product. In addition, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the thickness ratio of each layer, etc. may be different from the actual situation. In addition, there may also be differences in the dimensional relationships and ratios between the drawings.

[0016] Next, embodiments of the silicon carbide semiconductor device of the present application will be described. Figure 1 A cross-sectional view of the silicon carbide semiconductor device 1 as the minimum unit structure of a planar SiC-MOSFET. Multiple silicon carbide semiconductor devices identical to the Figure 1 shown silicon carbide semiconductor device 1 are provided inside a semiconductor chip (not shown).

[0017] As Figure 1 shown, the silicon carbide semiconductor device 1 includes: a silicon carbide substrate 2, a drift layer 3, two body layers 4, two source layers 5, two body contact layers 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, two source electrodes 10, a source wiring electrode 11, a drain electrode 12, and a conductive blocking layer 15.

[0018] As Figure 1 shown, a planar MOSFET is formed on the silicon carbide substrate 2 of n+-type conductivity type. The main surface of the silicon carbide substrate 2 above the Figure 1 drawing is the first surface 30, and the main surface below is the second surface 31. The impurity concentration of the n+-type silicon carbide substrate 2 is higher than that of the n-type drift layer 3 described later.

[0019] Two spaced-apart p-type conductivity type body layers 4 are formed inside the side where the upper surface of the n-type drift layer 3 is located (opposite to the silicon carbide substrate 2). The thickness of the body layer 4 is approximately 1 μm, and the p-type body layer 4 is formed by, for example, aluminum ion implantation.

[0020] Inside each p-type body layer 4 near the upper surface of the drift layer 3, a high-impurity-concentration n+-type source layer 5 is provided. The impurity concentration of the n+-type source layer 5 is higher than that of the n-type drift layer 3, and the thickness is about 0.3 - 0.4 μm. A p+-type body contact layer 6 is provided outside the n+-type source layer 5 near the upper surface of the drift layer 3 inside the p-type body layer 4. The impurity concentration of the p+-type body contact layer 6 is higher than that of the p-type body layer 4.

[0021] In addition, the body layer 4 is located between the n+-type source layer 5 and the drift layer 3, and contacts the gate insulating film 7 during formation. The gate insulating film 7 covers the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided on its upper surface. To improve conductivity, the gate electrode 8 is made of polysilicon doped with n-type impurities [such as phosphorus (P)]. The gate electrode 8 is electrically connected to the external wiring and the gate pad of the semiconductor chip (not shown) through a contact hole (not shown in the cross-sectional view of Figure 2 ).

[0022] The interlayer insulating film 9 covers a part of the gate electrode 8 and the gate insulating film 7. One of the functions of the interlayer insulating film 9 is to isolate the gate electrode 8 from other conductive components such as the source wiring electrode 11. The interlayer insulating film 9 can be composed of one or more layers of different types of structures. In this embodiment, specifically, it is a double-layer structure of a BPSG film covering the gate electrode 8 and a TEOS oxide film covering the BPSG film. The interlayer insulating film 9 covers the upper part of the gate electrode 8 and the upper part of the gate insulating film 7. Due to the low hydrogen ion permeability of the interlayer insulating film 9, it can prevent hydrogen ions from reaching the channel region from the source wiring electrode 11 through the gate insulating film 7.

[0023] A conductive barrier layer 15 is provided between the side portion of the interlayer insulating film and the source electrode 10. The material of the conductive barrier layer 15 is preferably tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or amorphous silicon carbide. However, as long as the material has conductivity and a hydrogen permeability lower than that of aluminum (hydrogen permeability is 1×10^-12 [m-1·s-1·Pa-0.5]) used for the source electrode 10, it can exert its effect. Therefore, the resistivity of the material of the conductive barrier layer 15 should be between "1.6 [μΩ·cm] and 100 [μΩ·cm], and the hydrogen permeability should be between 1×10^-20 [m-1·s-1·Pa-0.5] and 1×10^-12 [m-1·s-1·Pa-0.5]". Other materials can also be used in addition to the above materials).

[0024] As Figure 1 shown, the conductive barrier layer 15 is provided between the side portion 42 of the interlayer insulating film 9 and a part of the source electrode 10. In addition, the upper surface 9a of the interlayer insulating film 9 is not covered by the conductive barrier layer 15. Here, the "upper surface 9a of the interlayer insulating film 9" includes at least the highest part and the flat part of the interlayer insulating film 9. Therefore, the conductive barrier layer 15 is provided separately on the left and right sides.

[0025] The conductive barrier layer 15 is disposed between the lower side portion 43 of the interlayer insulating film 9 and the interlayer insulating film side end portion 10a at the upper part of the source electrode 10, and covers therebetween without covering the upper corner portion 41 of the interlayer insulating film 9. That is, the height of the upper end 15a of the conductive barrier layer 15 only reaches a part of the side portion 42 of the interlayer insulating film 9 and does not cover the upper corner portion 41.

[0026] In a plan view, the lower outer end portion 15b of the conductive barrier layer 15 is located inside (on the side closer to the interlayer insulating film 9) the outer end portion 5a of the source layer 5. In the range where the source electrode 10 overlaps with the source layer 5 in a plan view, the upper surface of the source electrode 10 includes a region covered by the conductive barrier layer 15 and a region not covered by the conductive barrier layer 15. That is, in a plan view, between the lower outer end portion 15b of the conductive barrier layer 15 and the outer end portion 5a of the source layer 5, the upper surface of the source electrode 10 is a region not covered by the conductive barrier layer 15. In addition, in a plan view, the distance between the lower outer end portion 15b of the conductive barrier layer 15 and the outer end portion 5a of the source layer 5 is about 100 nm, and the distance between the lower outer end portion 15b of the conductive barrier layer 15 and the interlayer insulating film side end portion 10a at the upper part of the source electrode 10 is also about 100 nm.

[0027] The source electrode 10 is formed above the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 11 is in contact with and electrically connected to the source electrode 10 and is provided on the source electrode 10 and the interlayer insulating film 9 (the first layer 9a). The material of the source wiring electrode 11 is, for example, aluminum (Al), or may be an aluminum-copper alloy or an aluminum-silicon alloy (Al-Si).

[0028] A wiring 13 is connected to the source wiring electrode 11 by a ball bond 13a. The material of the wiring 13 can be, for example, aluminum or an aluminum-copper alloy (Al-Cu).

[0029] As described above, in the silicon carbide semiconductor device 1 which is a planar SiC-MOSFET, in the body layer 4, the region near the region in contact with the gate insulating film 7 is the channel region. This channel region serves as a current path and allows an electron current to flow from the source electrode 10 via the source layer 5 and the drift layer 3 to the drain electrode 12. In addition, by controlling the voltage applied to the gate electrode 8, the width of the depletion layer formed in the channel region can be controlled, thereby controlling the current flowing through the channel region and further controlling the current between the source electrode 10 and the drain electrode 12.

[0030] By disposing the conductive barrier layer 15 between the side portion 42 of the interlayer insulating film 9 and the source electrode 10, the gap between the interlayer insulating film 9 and the source electrode 10 is filled with the conductive barrier layer 15, so that hydrogen ions can be prevented from infiltrating into the channel region through the gate insulating film 7 and the gate electrode 8. Thus, the conductive barrier layer 15 can effectively prevent hydrogen ions from entering the channel region, thereby improving the reliability of the silicon carbide semiconductor device 1.

[0031] If the conductive barrier layer 15 covers the entire surface of the interlayer insulating film 9, during the manufacturing process or operation, when the temperature of the silicon carbide semiconductor device 1 increases, due to the different thermal expansion rates of different materials, thermal stress will be generated, which may cause damage to the conductive barrier layer 15 or the interlayer insulating film 9. Based on this problem, in the silicon carbide semiconductor device 1 of the present embodiment, as described above, the design of the conductive barrier layer 15 avoids covering the upper surface 9a of the interlayer insulating film 9. Therefore, the conductive barrier layer 15 is separately provided on the left and right sides, and even when the temperature increases, damage to the conductive barrier layer 15 due to lateral thermal stress can be avoided.

[0032] If the conductive barrier layer 15 covers the entire surface of the interlayer insulating film 9, problems may also occur due to thermal stress in the up and down directions. However, in the silicon carbide semiconductor device 1 of the present embodiment, as described above, the conductive barrier layer 15 does not cover the upper corner portion 41 of the interlayer insulating film 9. That is, the height of the upper end 15a of the conductive barrier layer 15 only reaches a part of the side portion 42 of the interlayer insulating film 9 and does not cover the upper corner portion 41. Therefore, the conductive barrier layer 15 will not generate thermal stress due to the expansion of components in the up and down directions, thereby avoiding damage to the conductive barrier layer 15.

[0033] In addition, since the resistivity of the conductive barrier layer 15 is higher than that of the source wiring electrode 11, if the conductive barrier layer 15 covers the entire upper surface of the source electrode 10, the resistance value will increase significantly. Based on this problem, as described above, within the range where the source electrode 10 overlaps with the source layer 5, the upper surface of the source electrode 10 includes a region covered by the conductive barrier layer 15 and a region not covered by the conductive barrier layer 15. Therefore, hydrogen ions can be effectively prevented from entering the channel region without significantly increasing the resistance, thereby realizing a highly reliable silicon carbide semiconductor device.

[0034] In the present embodiment, the structure in which the lower end of the interlayer insulating film 9 only contacts the upper surface of the gate insulating film 7 and does not cover the source electrode 10 has been described, but the lower end of the interlayer insulating film 9 can also be designed to be wider to cover a part of the source electrode 10. In addition, although the side portion 42 of the interlayer insulating film 9 perpendicular to the silicon carbide substrate 2 has been described, its side portion can also be inclined.

[0035] Next, refer toFigures 2 to 5 , explain the manufacturing process of the silicon carbide semiconductor device 1 of this embodiment. Figure 2 As shown in (A), first, prepare an n+-type silicon carbide substrate 2 as the first conductive type material. Next, on the first surface 30 ( Figure 1 the upper surface in the figure) of the silicon carbide substrate 2, an n-type drift layer 3 is formed by epitaxial growth.

[0036] Next, a mask such as silicon dioxide (SiO2) is deposited on the surface of the n-type drift layer 3, and a mask 20 is formed by photolithography, exposing the upper part of the formation region of the p-type body layer 4. Then, a p-type body layer 4 is formed by implanting aluminum (Al) ions on the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In this embodiment, aluminum (Al) is used as the p-type dopant, but boron (B) or boron difluoride (BF2) can also be used.

[0037] Then, as Figure 2 shown in (B), a layer of the same material as the mask 20 (such as SiO2) is deposited on the main surface of the silicon carbide substrate 2, and then a mask 21 is formed by anisotropic etching. This mask 21 is formed wider than the mask 20, exposing the upper part of the formation region of the n-type source layer 5. Next, an n-type source layer 5 is formed by implanting nitrogen (N) ions from the mask 21. In this embodiment, nitrogen (N) is used as the n-type dopant, but phosphorus (P) can also be used.

[0038] Then, as Figure 2 shown in (C), after removing the mask 21, a mask 23 of a material such as SiO2 is deposited, and a mask 23 is formed by photolithography, exposing the formation region of the p+-type body contact layer 6. Subsequently, a p+-type body contact layer 6 is formed by implanting aluminum (Al) ions on the formation region of the body contact layer 6.

[0039] Next, after removing the mask 23, an annealing treatment at 1600 °C is performed. Through this annealing treatment, the p-type body layer 4, the n+-type source layer 5, and the p+-type body contact layer 6 are activated.

[0040] Then, as Figure 3 shown in (A), a gate insulating film 7 such as SiO2 is formed. Specifically, by heating the region including the body layer 4, the n+-type source layer 5, and the p+-type body contact layer 6 to 900 - 1350 °C, it is thermally oxidized to form SiO2, and it is patterned by photolithography and etching processes to form the gate insulating film 7.

[0041] Next, as Figure 3As shown in (B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, the conductivity is improved by depositing a polysilicon layer doped with n-type impurities, and then it is patterned by photolithography and etching processes to form the gate electrode 8.

[0042] Then, as Figure 3 shown in (C), an interlayer insulating film 9 covering the gate electrode 8 is formed. The interlayer insulating film 9 can be a single-layer structure made of any one of BPSG (borophosphosilicate glass), TEOS oxide film, or PSG (phosphosilicate glass), or a multi-layer structure. For example, when the interlayer insulating film 9 is a two-layer structure composed of BPSG and TEOS, first a BPSG film is deposited on the gate electrode 8, and then a TEOS film is deposited on the BPSG film. In this case, a BPSG film covering the entire wafer surface can be deposited on the gate electrode 8, and the BPSG film is patterned by photolithography and etching processes to form the first interlayer insulating film. Then a TEOS film is deposited on the BPSG film, and the TEOS film is patterned by photolithography and etching processes to form the second interlayer insulating film. The BPSG film is subjected to a planarization process so that the corners of the interlayer insulating film 9 are rounded, preventing the electric field from concentrating at the corners of the interlayer insulating film 9.

[0043] Next, as Figure 4 shown in (A), a source electrode 10 such as nickel silicide (NiSi) is formed. Specifically, first nickel (Ni) is deposited on the main surface of the silicon carbide substrate 2 including the source layer 5 and the body contact layer 6 by sputtering. Then an alloying annealing process is performed. Specifically, by laser heating for example, the silicon carbide substrate 2 on which nickel has been deposited is heated to 900 °C to 1100 °C. In this way, a part of the source electrode 10 (the nickel film part in contact with the source layer 5 and the body contact layer 6) is silicided to form nickel silicide. Then, the unsilicided nickel part is removed to complete the manufacture of the source electrode 10.

[0044] Next, as Figure 4 shown in (B), the interlayer insulating film 9 covering the entire wafer main surface is covered, and a conductive film 15d is deposited by sputtering. The material of the conductive film 15d is the material of the above-mentioned conductivity barrier layer 15, such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or amorphous silicon carbide.

[0045] Then, as Figure 4 shown in (C), anisotropic etching is performed by, for example, RIE (reactive ion etching) to remove the conductive film 15d with the same thickness on the surface layer, thereby forming the conductivity barrier layer 15. As Figure 1As shown, the conductive barrier layer 15 covers the region between the lower end 43 of the side portion 42 of the interlayer insulating film 9 and the upper interlayer insulating film side end portion 10a of the source electrode 10. By performing anisotropic etching on the conductive film 15d covering the main surface of the wafer, the conductive barrier layer 15 can be directly formed without using a mask.

[0046] Next, as Figure 5 (A) shows, the source wiring electrode 11 is formed. Specifically, the source wiring electrode 11 is formed by covering the source electrode 10, the interlayer insulating film 9, and the conductive barrier layer 15 by sputtering. The material of the source wiring electrode 11 is, for example, aluminum (Al), and it can also be an aluminum-copper alloy (Al-Cu) or an aluminum-silicon compound (Al-Si). The thickness of the source wiring electrode 11 is about 5 μm. Next, as Figure 5 (A) shows, a drain electrode 12 made of nickel silicide (NiSi) is formed on the second surface 31 of the silicon carbide substrate 2. The drain electrode 12 is formed by depositing nickel by sputtering, and then heating the nickel by, for example, laser annealing to partially nickel-silicide. Subsequently, the unsilicided nickel portion is removed to complete the formation of the drain electrode 12.

[0047] Next, as Figure 5 (B) shows, the wiring 13 is mounted on the source wiring electrode 11 by ball bonding 13a. The material of the wiring 13 can be, for example, aluminum (Al) or an aluminum-copper alloy (Al-Cu).

[0048] Finally, as Figure 6 shown, the silicon carbide semiconductor device 1 and the wiring 13 are encapsulated using a molding resin 14. Specifically, the molding resin 14 covers one side of the source wiring electrode 11 to form an encapsulation on the main surface.

[0049] In the above embodiment, an example of applying the silicon carbide semiconductor device of the present invention to a planar SiC-MOSFET has been explained, but it can also be applied to an IGBT (insulated gate bipolar transistor).

[0050] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of patent protection. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: a silicon carbide substrate formed of first conductivity type silicon carbide; a drift layer formed of first conductive type silicon carbide on the first surface of the silicon carbide substrate; a plurality of bulk layers formed of second conductivity type silicon carbide on the drift layer; A plurality of source layers formed of silicon carbide of the first conductivity type and having a higher impurity concentration than the drift layer on each of the plurality of body layers; a gate insulating film formed in connection with the body layer and the source layer; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode and the gate insulating film; And a conductive barrier layer is provided between the side surface of the interlayer insulating film and the source electrode for preventing hydrogen ions from passing through.

2. The silicon carbide semiconductor device according to claim 1, wherein: The conductive barrier layer is made of tantalum, tantalum nitride, titanium nitride or amorphous silicon carbide.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that: The material of the conductive barrier layer has a resistivity between 1.6 [μΩ·cm] and 100 [μΩ·cm], and a hydrogen permeability between 1×10^-20 [m-1·s-1·Pa-0.5] and 1×10^-12 [m-1·s-1·Pa-0.5].

4. The silicon carbide semiconductor device according to claim 1, wherein: The conductive barrier layer is provided to cover the side surfaces of the interlayer insulating film and a portion of the source electrode, and the upper surface of the interlayer insulating film is not covered by the conductive barrier layer.

5. The silicon carbide semiconductor device according to claim 1, wherein: The conductive barrier layer covers the lower end of the side surface of the interlayer insulating film, the upper portion of the source electrode, and the end portion in contact with the interlayer insulating film, and the upper corner of the interlayer insulating film is not covered.

6. The silicon carbide semiconductor device according to claim 1, wherein: In the plan view, the lower outer end of the conductive barrier layer is located inside the outer end of the source layer, and in the plan view, within the range where the source electrode overlaps with the source layer, the upper surface of the source electrode includes an area covered by the conductive barrier layer and an area not covered by the conductive barrier layer.

7. The silicon carbide semiconductor device according to claim 6, wherein: In a plan view, a distance between a lower outer end portion of the conductive barrier layer and an outer portion of the source layer is 100 nm.

8. The silicon carbide semiconductor device according to claim 6, wherein: In a plan view, the distance between the lower outer end of the conductive barrier layer and the side end of the upper interlayer insulating film of the source electrode is 100 nm.

9. The silicon carbide semiconductor device according to claim 1, wherein: The side portion of the interlayer insulating film is provided obliquely with respect to the silicon carbide substrate.

10. The silicon carbide semiconductor device according to claim 1, wherein: The interlayer insulating film includes a double-layer structure of a BPSG film covering the gate electrode and a TEOS oxide film covering the BPSG film.

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