Integrated circuit device, integrated circuit layout, and method of generating integrated circuit layout

Abstract

An integrated circuit device includes a plurality of rows of semiconductor devices. A plurality of rows elongate along a first axis and are arranged side-by-side along a second axis transverse to the first axis. The plurality of rows includes a first row having a first height along the second axis and a second row having a second height along the second axis. The second height is less than the first height. Each row includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type. The second active region is spaced apart from the first active region along the second axis. Along the second axis, a first width of the first or second active region in the first row is greater than a second width of the first or second active region in the second row. The embodiment of the invention also discloses an integrated circuit layout and a method for generating the integrated circuit layout.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices, integrated circuit layouts, and methods for generating integrated circuit layouts. Background Art

[0002] Integrated circuit (“IC”) devices include one or more semiconductor devices represented in an IC layout diagram (also referred to as an “IC design layout diagram”, “layout diagram”, or “IC layout”). The layout diagram is hierarchical and includes modules that perform higher-level functions according to the design specifications of the semiconductor devices. These modules are typically constructed from a combination of multiple cells, each cell representing one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layout diagrams, sometimes referred to as standard cells, are stored in a standard cell library (hereinafter simply referred to as a “library” or “cell library”) and can be accessed by various tools (such as electronic design automation (EDA) tools) to generate, optimize, and verify the design of the IC. Power, performance, and area (PPA) are design considerations for IC devices. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, there is provided an integrated circuit device, including: a plurality of rows of semiconductor devices, the plurality of rows extending along a first axis and arranged side by side along a second axis transverse to the first axis, wherein the plurality of rows include: a first row having a first height along the second axis, and a second row having a second height along the second axis, the second height being less than the first height, each row of the plurality of rows including: a first active region of a first conductivity type, and a second active region of a second conductivity type different from the first conductivity type, the second active region being spaced apart from the first active region along the second axis, and along the second axis, a first width of the first active region or the second active region in the first row being greater than a second width of the first active region or the second active region in the second row.

[0004] According to another aspect of an embodiment of the present application, there is provided an integrated circuit layout stored on a non-transitory computer-readable storage medium, the integrated circuit layout including: a first circuit region; and a second circuit region, wherein each of the first circuit region and the second circuit region includes: a first cell having a first cell height in a cell height direction, a second cell having a second cell height in the cell height direction, the height of the second cell being less than the height of the first cell, and an equivalent cell height corresponding to the first cell height, the second cell height, the number of rows of the first cell, and the number of rows of the second cell, and the equivalent cell height of the first circuit region being different from the equivalent cell height of the second circuit region.

[0005] According to another aspect of embodiments of the present application, a method for generating an integrated circuit layout for a circuit region is provided. The method is at least partially executed by a processor and includes: determining an equivalent cell height based on an application to be executed by the circuit region; determining a cell row configuration based on the determined equivalent cell height, the cell row configuration including at least one first row of a first height and at least one second row of a second height different from the first height; generating a cell array according to the determined cell row configuration; and performing a placement and routing operation to generate an integrated circuit layout for the circuit region, the placement and routing operation including performing the following operations based on the circuit region: placing one or more first cells of the first height in one or more first rows of the first height in the generated cell array, and placing one or more second cells of the second height in one or more second rows of the second height in the generated cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a block diagram of an IC device according to some embodiments.

[0008] Figure 1B is a perspective view of a portion of an IC device according to some embodiments.

[0009] Figure 1C is according to some embodiments Figure 1B a cross-sectional view of a portion of an IC device.

[0010] Figure 2A is a schematic diagram of an IC layout of a circuit region of an IC device according to some embodiments.

[0011] Figure 2B is according to some embodiments Figure 2A a simplified schematic diagram of an IC layout.

[0012] Figure 2C includes schematic diagrams of various cell row configurations in one or more IC layouts according to some embodiments.

[0013] Figure 3 includes schematic diagrams of various cells that can be placed in an IC layout according to some embodiments.

[0014] Figure 4A is a schematic diagram of an IC layout of a circuit region of an IC device according to some embodiments.

[0015] Figure 4B and Figure 4C is a schematic diagram of various cell rows in one or more IC layouts according to some embodiments.

[0016] Figure 5A is a block diagram of an IC device according to some embodiments.

[0017] Figure 5B and Figure 5C is a schematic diagram of the IC layout of various circuit regions of one or more IC devices according to some embodiments.

[0018] Figure 6 is a schematic diagram of the IC layout of the circuit region of an IC device according to some embodiments.

[0019] Figure 7A includes a schematic circuit diagram and a cross-sectional view of the circuit region of an IC device according to some embodiments.

[0020] Figure 7B and Figure 7C is according to some embodiments Figure 7A schematic diagrams of the respective layers of the IC layout of the circuit region of

[0021] Figure 7D includes a schematic circuit diagram and a cross-sectional view of the circuit region of an IC device according to some embodiments.

[0022] Figure 7E and Figure 7F is according to some embodiments Figure 7D schematic diagrams of the respective layers of the IC layout of the circuit region of

[0023] Figure 8A is a schematic circuit diagram of the circuit region of an IC device according to some embodiments.

[0024] Figure 8B is according to some embodiments Figure 8A schematic diagram of the IC layout of the circuit region of

[0025] Figure 9A and Figure 9B is a schematic diagram of the IC layout of various circuit regions of one or more IC devices according to some embodiments.

[0026] Figure 10 is a table showing the wiring characteristics of various cells that can be placed in an IC layout according to some embodiments.

[0027] Figure 11 and Figure 12 are flowcharts of various methods according to some embodiments.

[0028] Figure 13is a block diagram of an electronic design automation (EDA) system in accordance with some embodiments.

[0029] Figure 14 is a block diagram of an IC device manufacturing system and its associated IC manufacturing process in accordance with some embodiments. DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments or examples for implementing the features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. A source / drain may refer to a source or a drain individually or collectively, depending on the context.

[0031] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0032] In some embodiments, cells of different cell heights are read from one or more cell libraries, for example, by an automatic placement and routing (APR) tool or system, and placed in an IC layout. Cells with a cell height greater than the unit cell height of a unit cell are sometimes referred to as tall cells and are configured to improve (i.e., increase) the performance or speed of one or more regions of an IC device fabricated according to the IC layout. Cells with a cell height less than the unit cell height of a unit cell are sometimes referred to as short cells and are configured to improve (i.e., reduce) power consumption and / or chip area (hereinafter referred to as "power and area") in one or more other regions of the fabricated IC device. In at least one embodiment, the IC layout also includes unit cells. In some embodiments, the active regions of adjacent cells are merged to configure merged cells with improved performance or speed. In at least one embodiment, the active region widths of one or more short cells, unit cells, and / or tall cells are reduced to improve power and area. Thus, in one or more embodiments, the IC layout can be optimized and / or customized according to the purpose and / or application to be performed by the IC device fabricated based on the IC layout, to increase the speed of one or more regions while improving the power and area of one or more other regions. These are improvements over other methods in which all cells in the IC layout have the same cell height. Other features and corresponding advantages according to various embodiments are also described herein.

[0033] Figure 1A is a block diagram of an IC device 100A according to some embodiments.

[0034] In Figure 1AIn [the figure], the IC device 100A includes a macro 101 and the like. In some embodiments, the macro 101 includes a memory, a power grid, one or more cells, an inverter, a latch, a buffer, and / or any other type of circuit arrangement that can be numerically represented in a cell library. In some embodiments, the macro 101 is understood to be similar to the architectural hierarchy of modular programming, where subprocesses / programs are called by a main program (or other subroutines) to perform a given computing function. In this context, the IC device 100A uses the macro 101 to perform one or more given functions. Thus, in this case, in terms of the architectural hierarchy, the IC device 100A is similar to the main program, and the macro 101 is similar to the subprocess / program. In some embodiments, the macro 101 is a soft macro. In some embodiments, the macro 101 is a hard macro. In some embodiments, the macro 101 is a soft macro described numerically in register transfer level (RTL) code. In some embodiments, synthesis, placement, and routing have not been performed on the macro 101 so that the soft macro can be synthesized, placed, and routed for various process nodes. In some embodiments, the macro 101 is a hard macro described numerically in a binary file format (e.g., Graphic Database System II (GDSII) stream format), where the binary file format represents the planar geometry, text labels, other information, etc. of one or more layout diagrams of the macro 101 in a hierarchical form. In some embodiments, synthesis, placement, and routing have been performed on the macro 101 such that the hard macro is dedicated to a specific process node.

[0035] The macro 101 includes a region 103, and the region 103 includes cells having different cell heights as described herein. In some embodiments, the region 103 includes a substrate on which circuits are formed in front-end-of-line (FEOL) manufacturing. Further, above and / or below the substrate, the region 103 includes various metal layers that are stacked above and / or below an insulating layer in back-end-of-line (BEOL) manufacturing. The BEOL provides wiring for the circuits of the IC device 100A including the macro 101 and the region 103.

[0036] Figure 1B is a perspective view of a part of an IC device 100B according to some embodiments. In at least one embodiment, the IC device 100B corresponds to the IC device 100A.

[0037] The IC device 100B includes a substrate 110, and a plurality of semiconductor devices are formed above the substrate 110. In Figure 1B Two semiconductor devices 111, 121 of the IC device 100B are indicated. In Figure 1BIn the example configuration, semiconductor devices 111, 121 include nanosheet field-effect transistors (FETs), sometimes referred to as nanosheet devices. Nanosheet devices are examples of gate-all-around (GAA) devices. Other GAA configurations, such as nanowire FETs, sometimes referred to as nanowire devices, are also within the scope of various embodiments.

[0038] Substrate 110 includes a substrate portion 112 corresponding to semiconductor device 111, a substrate portion 122 corresponding to semiconductor device 121, and an isolation region 114 located between and surrounding substrate portions 112 and 122. Substrate portions 112, 122 extend or elongate along the X-axis. In some embodiments, substrate portions 112, 122 are part of the same wafer (not shown). During the fabrication of IC device 100B, the wafer has been partially removed, leaving substrate portions 112, 122. In some embodiments, the wafer is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which is doped (e.g., with P-type or N-type dopants) or undoped. Generally, an SOI substrate includes a semiconductor material layer formed on an insulator layer. Example materials for the insulator layer include, but are not limited to, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a silicon substrate, a glass substrate, a multi-layer substrate, or a gradient substrate. In some embodiments, substrate portions 112, 122 include semiconductor materials, including but not limited to: elemental semiconductors, including silicon or germanium in crystalline, polycrystalline, or amorphous structures; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. Isolation region 114 is formed in a trench between substrate portions 112, 122. Isolation region 114 has an upper surface flush with the upper surfaces of substrate portions 112, 122. Example materials for isolation region 114 include, but are not limited to, insulating materials, such as dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc.

[0039] IC device 100B also includes gate electrodes 116, 118 and nanosheet stacks 124, 134. Gate electrode 116 and nanosheet stack 124 form semiconductor device 111. Gate electrode 116 and nanosheet stack 134 form semiconductor device 121. Gate electrodes 116, 118 are formed on substrate portions 112, 122 and isolation region 114. Gate electrodes 116, 118 extend along the Y-axis that is transverse to the X-axis. In at least one embodiment, the Y-axis is perpendicular to the X-axis. In some embodiments, gate electrodes 116, 118 include one or more layers of conductive materials, including but not limited to doped polysilicon, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, their alloys, their combinations, etc. In some embodiments, gate electrodes 116, 118 also include other work function adjusting metals, diffusion barrier materials, glue layers, etc.

[0040] Each of nanosheet stacks 124, 134 includes a plurality of separated nanosheets stacked correspondingly on substrate portions 112, 122 along the Z-axis, where the Z-axis is the thickness direction of substrate 110. Nanosheet stacks 124, 134 extend along the X-axis, and substrate portions 112, 122 extend along this X-axis. In other words, nanosheet stacks 124, 134 extend transversely to gate electrodes 116, 118. A portion of each nanosheet of nanosheet stacks 124, 134 is surrounded by at least one of gate electrodes 116, 118. In some embodiments, the nanosheets in nanosheet stacks 124, 134 are generally two-dimensional semiconductor plates, whose length (along the X-axis) or width (along the Y-axis) is greater than about 110 nm, and thickness (along the Z-axis) is less than about 20 nm. Other nanosheet or nanowire configurations are within the scope of various embodiments. In Figure 1B the example configuration shown, each of nanosheet stacks 124, 134 includes four nanosheets. Other numbers of nanosheets in the nanosheet stack are within the scope of various embodiments.

[0041] In some embodiments, nanosheet stacks 124, 134 and substrate portions 112, 122 are formed from the same wafer by performing lithography and etching operations on the wafer. In at least one embodiment, nanosheet stack 124 or nanosheet stack 134 is doped with N-type impurities such as arsenic, phosphorus, etc. to form an N-type nanosheet FET, or doped with P-type impurities such as boron, etc. to form a P-type nanosheet FET. For example, nanosheet stack 124 is configured to be an N-type nanosheet that configures semiconductor device 111 as an N-type semiconductor device (e.g., an N-type transistor), while nanosheet stack 134 is configured to be a P-type nanosheet that configures semiconductor device 121 as a P-type semiconductor device (e.g., a P-type transistor). N-type is an example of one of the first and second conductive types, and P-type is an example of the other of the first and second conductive types.

[0042] Stacked nanosheets of the same nanosheet stack 124 or 134 are configured to form a combined channel region and / or a combined source / drain region of a corresponding semiconductor device. For example, a portion of each nanosheet of the nanosheet stack 124 that overlaps with the gate electrode 116 is configured as a combined channel region of the semiconductor device 111, while other portions of each nanosheet of the nanosheet stack 123 that are located on opposite sides of the channel region are configured as source / drain regions of the semiconductor device 111. Similarly, a portion of each nanosheet of the nanosheet stack 134 that overlaps with the gate electrode 116 is configured as a combined channel region of the semiconductor device 121, while other portions of each nanosheet of the nanosheet stack 134 that are located on opposite sides of the channel region are configured as source / drain regions of the transistor device 121.

[0043] Figure 1C is a cross-sectional view of a part of the IC device 100B according to some embodiments. Figure 1C The cross-sectional view in Figure 1B is taken along line C-C through the gate electrode 116 in

[0044] As Figure 1C shown, the semiconductor devices 111, 121 further include corresponding gate dielectric layers 126, 136 located between the gate electrode 116 and each nanosheet of the corresponding nanosheet stacks 124, 134. In some embodiments, the gate dielectric layers 126, 136 include one or more dielectric materials, including but not limited to oxides, nitrides, oxynitrides, high-k dielectric materials such as Al2O3, HfO2, ZrO2, HfO x N y 、ZrO x N y ,HfSi x O y 、ZrSi x O y 、HfSi x O y N z 、ZrSi x O y N z ,TiO2, Ta2O5, La2O3, CeO2, Bi4Si2O 12 、WO3, Y2O3, LaAlO3, Ba 1-xSrxTiO3, PbTiO3, BaTiO3 (BTO), SrTiO3 (STO), BaSrTiO3 (BST), PbZrO3, lead strontium titanate (PST), lead zinc niobate (PZN), lead zirconate titanate (PZT), lead magnesium niobate (PMN), yttria-stabilized zirconia (YSZ), ZnO / Ag / ZnO (ZAZ), combinations thereof, and the like. In some embodiments, the IC device 100B further includes a work function adjustment layer (not shown) located between the gate electrode 116 and each of the gate dielectric layers 126, 136. In Figure 1C In an example configuration, the nanosheets in each of the nanosheet stacks 124, 134 have a substantially the same width w along the Y-axis. Other configurations are within the scope of various embodiments.

[0045] Figure 2A is a schematic diagram of an IC layout 200 of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of the IC devices 100A, 100B. In some embodiments, the IC layout 200 and the IC layouts described herein with respect to various embodiments are generated by an EDA system (such as an APR system) and / or stored in a non-transitory computer-readable storage medium.

[0046] The IC layout 200 includes multiple rows 210, 220, 230 of semiconductor devices. The rows 210, 220, 230 extend along the X-axis and are arranged side by side along the Y-axis. The X-axis is an example of a first axis, and the Y-axis is an example of a second axis transverse to the first axis. In at least one embodiment, the semiconductor devices in the rows 210, 220, 230 correspond to the semiconductor devices 111, 121 and / or include GAA devices.

[0047] Each of the rows 210, 220, 230 has a pair of boundary lines spaced apart from each other along the Y-axis by a distance corresponding to the height of the row. For example, row 210 has a pair of boundary lines 201, 202 and a corresponding height H between the boundary lines 201 and 202 T , row 220 has a pair of boundary lines 202, 203 and a corresponding height H between the boundary lines 202 and 203 S , row 230 has a pair of boundary lines 203, 204 and a corresponding height H between the boundary lines 203 and 204 S . Row 210 is an example of a first row, and H T is an example of a first height of the first row along the Y-axis. Row 220 is an example of a second row, and H S is an example of a second height of the second row along the Y-axis. As described herein, in one or more embodiments, H S is less than H Tto achieve one or more advantages. Row 230 is an example of the third row, and H S is an example of the third height of the third row along the Y-axis. In some embodiments, as described herein, at least one of the boundary lines 201-204 corresponds to the center line of a power rail.

[0048] In Figure 2A the example configuration shown, rows 210, 220, 230 are in contact with each other and share a common boundary line. For example, rows 210, 220 are in contact with each other and share a common boundary line at common boundary line 202, and rows 220, 230 are in contact with each other and share a common boundary line at common boundary line 203. Other configurations are within the scope of various embodiments. For example, in at least one embodiment (not shown), two adjacent rows do not share a common boundary line and are spaced apart from each other along the Y-axis by a blank space that does not contain semiconductor devices. These two rows are sometimes referred to as adjacent non-contact rows. In some embodiments, when two rows share a common boundary line (e.g., rows 210, 220), or when two rows are adjacent non-contact rows, the two rows are considered adjacent to each other.

[0049] Each of rows 210, 220, 230 includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type, wherein the second active region is separated from the first active region. For example, row 210 includes a first active region 251 and a second active region 252. The first active region 251 includes portions 231, 237 having different active region widths as described herein, and the second active region 252 includes portions 232, 238 having different active region widths as described herein. One of the active regions 251, 252 is an N-type active region and the other is a P-type active region. For example, the active region 251 is a P-type active region and the active region 252 is an N-type active region. In some embodiments, the N-type active region corresponds to the nanosheet stack 124, and the P-type active region corresponds to the nanosheet stack 134.

[0050] The active regions 251, 252 of row 210 are spaced apart from each other along the Y-axis by at least a spacing S. For example, portions 231, 232 of the active regions 251, 252 are spaced apart from each other along the Y-axis by the spacing S, while portions 237, 238 of the active regions 251, 252 are spaced apart from each other along the Y-axis by a spacing greater than the spacing S. In some embodiments, the spacing S is a predetermined minimum active region spacing along the Y-axis between adjacent active regions. When there are no other active regions between two active regions, the two active regions are directly adjacent. The spacing S is a design rule to be satisfied to ensure the manufacturability and / or operability of the IC device corresponding to the IC layout 200.

[0051] Each of the active regions 251, 252 is disposed in a region of a corresponding conductivity type, such as a substrate region, a doped region, or a well region. For example, the active region 251 is a P-type active region and is disposed in the N-type well region 221, and the active region 252 is an N-type active region and is disposed in the P-type substrate region having portions 222, 226. For simplicity, the reference numeral 222 herein represents the P-type substrate region including the active region 252. The P-type substrate region 222 continuously extends through the boundary line 202 into the row 220. In some embodiments, the N-type well region 221 continuously extends through the boundary line 201( Figure 2A upward) into another row of semiconductor devices (not shown).

[0052] The row 220 includes a first active region 254 including portions 234, 240 and a second active region 253 including portions 233, 239. The active regions 253, 254 of the row 220 are spaced apart from each other along the Y-axis by at least a pitch S. For example, the portions 233, 234 of the active regions 253 and 254 are spaced apart from each other along the Y-axis by the pitch S, while the portions 239, 240 of the active region 253 or 254 are spaced apart from each other along the Y-axis by an interval greater than the pitch S. In Figure 2A the example configuration, the active region 253 is an N-type active region disposed in the P-type substrate region 222, and the active region 254 is a P-type active region disposed in the N-type well region having portions 223, 227. For simplicity, the reference numeral 223 herein represents the N-type well region including the active region 254. The N-type well region 223 continuously extends through the boundary line 203 into the row 230.

[0053] The row 230 includes a first active region 255 including portions 235, 241 and a second active region 256 including portions 236, 242. The active regions 255, 256 of the row 230 are spaced apart from each other along the Y-axis by at least a pitch S. For example, the portions 235, 236 of the active regions 255 and 256 are spaced apart from each other along the Y-axis by the pitch S, while the portions 241, 242 of the active region 255 or 256 are spaced apart from each other along the Y-axis by a pitch greater than the pitch S. The portions 231 to 242 are sometimes referred to as the active regions 231 to 242.

[0054] In Figure 2A the example configuration, the active region 255 is a P-type active region disposed in the N-type well region 223, and the active region 256 is an N-type active region disposed in the P-type substrate region having portions 224, 228. For simplicity, the reference numeral 224 herein represents the P-type substrate region including the active region 256. In some embodiments, the P-type substrate region 224 continuously extends through the boundary line 204 (in Figure 2A downward) into another row of semiconductor devices (not shown). The active region 240 and the active region 241 are continuous with each other and are combined into a combined active region, sometimes referred to as 240 / 241.

[0055] The active regions 231-242 are functional active regions that, together with the functional gate regions described herein, configure multiple semiconductor devices in rows 210, 220, 230. The IC layout 200 also includes non-functional or pseudo-active regions 245, 246, 247 that are not configured to form semiconductor devices, and / or one or more semiconductor devices formed by the pseudo-active regions are not electrically coupled to other circuits in the IC device corresponding to the IC layout 200. In some embodiments, the pseudo-active regions have the same configuration as the functional active regions and / or are fabricated by the same process. In Figure 2A an example configuration, the pseudo-active region 245 is disposed in the P-type substrate region 222 and is continuous with the active regions 233, 239, the pseudo-active region 246 is disposed in the N-type well region 223 and is continuous with the active regions 234, 235, 240, 241, and the pseudo-active region 247 is disposed in the P-type substrate region 224 and is continuous with the active regions 236, 242. In some embodiments, the pseudo-active regions are configured to isolate and demarcate active regions of different active region widths in the same well region, substrate region, or doped region. For example, in the same N-type well region 223, the pseudo-active region 246 is configured to isolate and demarcate the active regions 234, 235 on one side and the combined active regions 240 / 241 on the other side. In some embodiments, one or more pseudo-active regions are omitted.

[0056] The IC layout 200 also includes gate regions 211-217 that extend along the Y-axis through the active regions 231-242. Each of the gate regions 211-212, 214-216 extends through all of the rows 210, 220, 230. The gate region 213 extends through row 210 and is aligned along the Y-axis with the gate region 217 that extends through rows 220, 230. For simplicity, Figure 2A the widths of the gate regions 211-217 are not shown in Figure 2A an example configuration. In Figures 1B - 1C the example configuration, the gate regions 212, 213, 215 are functional gate regions that, together with the active regions 231-242, configure multiple semiconductor devices. For example, the gate regions 212, 213 and the active regions 231, 232 configure a number of semiconductor devices corresponding to the semiconductor devices shown in Figures 1B - 1C The gate regions 212 and 215 also configure other semiconductor devices together with the corresponding active regions 233-236 and 237-242. The IC layout 200 includes a plurality of cut gate region markers (sometimes referred to as "CPO"), typically denoted by the reference numeral 250, to indicate the locations where the gate regions are divided into segments. For example, the gate region 212 is cut into three segments by four cut gate region markers 250. In at least one embodiment, the centerline of the cut gate region marker 250 coincides with the boundary line 201-204 that overlaps the cut gate region marker 250.

[0057] The gate regions 211, 214, 217 are non-functional gate regions or dummy gate regions. A dummy gate region is not configured to form a semiconductor device together with the underlying active region, and / or one or more semiconductor devices formed by the dummy gate region and the underlying active region are not electrically coupled to other circuits in the IC device corresponding to the IC layout 200. In at least one embodiment, in a fabricated IC device, the non-functional gate region or dummy gate region comprises a dielectric material. Other configurations are within the scope of various embodiments. In some embodiments, as Figure 2B described, the dummy gate region defines a cell boundary.

[0058] Figure 2B is a simplified schematic diagram of an IC layout 200 according to some embodiments.

[0059] Figure 2B shows the cell boundaries of the various cells C1-C5 included in the IC layout 200. As referred to Figure 2A described, each of the cells C1-C5 comprises semiconductor devices configured by at least one corresponding gate region and at least one corresponding active region. Figure 2BThe gate region and the active region are omitted. Cell C1 is located in row 210 and has a cell boundary defined by the centerlines of boundary lines 201, 202 and pseudo-gate regions 211, 214. Cell C2 is located in row 210 and has a cell boundary defined by the centerlines of boundary lines 201, 202 and pseudo-gate regions 214, 216. Cell C3 is located in row 220 and has a cell boundary defined by the centerlines of boundary lines 202, 203 and pseudo-gate regions 211, 217. Cell C4 is located in row 230 and has a cell boundary defined by the centerlines of boundary lines 203, 204 and pseudo-gate regions 211, 217. Cell C5 is arranged across rows 220, 230 and has a cell boundary defined by the centerlines of boundary lines 202, 204 and pseudo-gate regions 214, 216. In a placement and routing operation, such as performed by an APR system, the cells are placed in the IC layout adjacent to each other at their respective cell boundaries. For example, along the X-axis, cell C1 is placed adjacent to cell C2 along a common cell boundary defined by pseudo-gate region 214. Along the Y-axis, cell C1 is placed adjacent to cell C3 along a common cell boundary defined by boundary line 202, which in one or more embodiments is defined by a power rail as described herein. The described cell arrangement is an example. Other cell arrangements are within the scope of various embodiments. Examples of cells C1-C5 include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-INV (OAI), multiplexer (MUX), flip-flop, buffer (BUFF), latch, delay, clock, memory such as static random access memory (SRAM), decoupling capacitor, analog amplifier, logic driver, digital driver, etc.

[0060] As Figure 2B shown, the heights of rows 210, 220, 230 correspond to the cell heights of the respective cells in the rows along the Y-axis. The Y-axis is sometimes referred to as the cell height direction. For example, the cell height H of cells C1, C2 T corresponds to the height of row 210, and the cell height H of cells C3, C4 S corresponds to the heights of rows 220, 230, and the cell height 2H of cell C5 S corresponds to the sum of the cell heights of rows 220, 230 through which cell C5 extends.

[0061] Rows (or cells) with a height (or cell height) greater than the unit height of a unit row (or the unit cell height of a unit cell) H are sometimes referred to as tall rows (or tall cells). Rows (or cells) with a height (or cell height) less than the unit height (or unit cell height) H are sometimes referred to as short rows (or short cells). In Figure 2B the example configuration of T> H, and the corresponding rows 210 and cells C1, C2 are sometimes referred to as high rows and high cells accordingly. On the other hand, H > H S , the corresponding rows 220, 230 and cells C3, C4 are sometimes referred to as low rows and low cells accordingly. As described herein, cell C5 is sometimes referred to as a merged cell. Regarding Figure 3 , Figure 4A Examples of unit rows and unit cells contained therein are described.

[0062] Returning to Figure 2A , cells C1 - C5 are represented by the active regions included in the cells. For example, cell C1 includes active regions 231, 232 and is indicated by them. Cell C2 includes active regions 237, 238 and is indicated by them. Cell C3 includes active regions 233, 234 and is indicated by them. Cell C4 includes active regions 235, 236 and is indicated by them. Cell C5 includes active regions 239, 242 and the merged active region 240 / 241 and is indicated by them. The merged active region 240 / 241 is arranged between the active regions 239, 242 and has a conduction type (e.g., P-type) different from the conduction type (e.g., N-type) of the active regions 239 and 242. Cell C5 is an example of a merged cell that extends along the Y-axis through two rows of semiconductor devices and includes a merged active region. In Figures 2A - 2B the example configuration in, cell C5 is a merged cell that spans two low rows 220, 230. Other merged cell configurations are within the scope of various embodiments. For example, in one or more embodiments, the merged cell extends through any two contact rows, e.g., two low rows, two high rows, two unit rows, one low row and one high row, one low row and one unit row, one high row and one unit row.

[0063] Each of the active regions 231 - 242 has a width along the Y-axis, sometimes referred to as the "active region width". For example, the active regions 231, 232 in row 210 or cell C1 have an active region width W T . In some embodiments, the active region width W T is predetermined and depends on the corresponding cell height (or row height) H T as well as one or more design rules. As described herein, an example design rule is the spacing S between active regions in the same row. Another example design rule is the predetermined minimum spacing Sx along the Y-axis between the active region and the nearest boundary line. For example, as Figure 2A shown, the spacing between the active region 231 and the nearest boundary line 201 is at least Sx. In some embodiments, S = 2Sx. Other design rules are within the scope of various embodiments. In some embodiments, given a cell height H T , W Tis the maximum active region width of active regions 231, 232 when all design rules are satisfied. In some embodiments, the corresponding values of W T and H T are predetermined, for example, for a set of design rules, materials, manufacturing processes, etc., and are stored, for example, in or associated with a cell library.

[0064] The active regions 233-236 in rows 220, 230 or cells C3, C4 have an active region width W S . In some embodiments, the active region width W S is predetermined and depends on the corresponding cell height (or row height) H S and one or more design rules. In at least one embodiment, the same set of design rules applicable to cell C1 or row 210 also applies to cells C3, C4 and rows 220, 230. In some embodiments, for a given cell height H S , W S is the maximum active region width of active regions 233-236 when all design rules are satisfied. In some embodiments, the corresponding values of W S and H S are predetermined, for example, for a set of design rules, materials, manufacturing processes, etc., and are stored, for example, in or associated with a cell library.

[0065] As described herein, H S <H < H T , where H is the cell height of the cell. As Figure 3 , Figure 4A shown, the active region in the cell has a unit active region width W. In some embodiments, W S < W < W T . In some embodiments, the unit active region width W is predetermined and depends on the corresponding unit cell height H and one or more design rules. In at least one embodiment, the same set of design rules applicable to tall cell C1, short cells C3, C4 and rows 210, 220, 230 also applies to the unit cell. In some embodiments, for a given cell height H, W is the maximum active region width of the active region in the unit cell when all design rules are satisfied. In some embodiments, the corresponding values of W and H are predetermined, for example, for a set of design rules, materials, manufacturing processes, etc., and are stored, for example, in or associated with a cell library.

[0066] The active region width W T of the tall row 210 or tall cell C1 is greater than the active region width W SAs a result, the semiconductor devices in the tall cells C1 are configured to provide stronger performance or faster speed than those in the short cells C3, C4. In W T >W, the semiconductor devices in the tall cells C1 are also configured to provide stronger performance than those in the unit cells. In other words, the tall cells C1 are configured for performance improvement. On the other hand, the semiconductor devices in the short cells C3, C4 occupy a smaller chip area due to their smaller size (e.g., smaller cell height and / or smaller active region width), and are configured to consume less power during operation than the semiconductor devices in the tall cells C1. In W S <W, the semiconductor devices in the short cells C3, C4 also occupy a smaller chip area and are configured to consume less power during operation than the semiconductor devices in the unit cells. In other words, the short cells C3, C4 are configured for power and area improvement. The arrangement of the rows of semiconductor devices with various cell heights and / or active region widths in the IC layout is an example of a mixed row height configuration (also referred to herein as a "mixed row configuration"). In at least one embodiment, the IC layout with a mixed row configuration enables improvements in all PPA aspects, e.g., as described for the tall cells C1 and the short cells C3, C4.

[0067] In contrast, in other methods where the rows of semiconductor devices in the IC layout have the same cell height and active region width, it is difficult to achieve improvements in all PPA aspects. For example, to increase (i.e., improve) performance according to other methods, the cell height of all cells is increased, which will have an adverse impact on power and area (i.e., increase them). As another example, to reduce (i.e., improve) power and area according to other methods, the cell height of all cells is decreased, which will have an adverse impact on performance. The mixed row configuration according to some embodiments overcomes these difficulties experienced by other methods and provides optimizability and / or customizability for different IC layouts and / or different circuit regions of an IC layout to adapt to one or more specific applications and / or functions.

[0068] In some embodiments, the tall cells C1 (or the tall row 210) and / or the short cells C3 or C4 (or the short rows 220 or 230) satisfy one or more or all of the following relationships (1)-(5):

[0069] 1.2H ≤ H T ≤ 1.6H (1)

[0070] 0.6H ≤ H S ≤ 0.8H (2)

[0071] 1.2W ≤ W T ≤ 2W (3)

[0072] 0.3W ≤ W S ≤ 0.8W (4)

[0073] 1.5 ≤ W T / W S ≤ 2 (5)

[0074] In some cases, when one of the relationships (1)-(5) is not satisfied, the expected improvements in performance, power, and area may not be achieved.

[0075] In some embodiments, all of the high cells in a high row have the same active region width, e.g., W T However, in at least one embodiment of the high row, the active region width of at least one high cell is less than W T For example, in Figure 2A the active regions 237, 238 of the high cell C2 have a reduced active region width W SM The active regions 237, 238 having a reduced active region width are sometimes referred to as "small OD". In some embodiments, high cells having small OD, such as cell C2, are configured to consume less power than conventional high cells (such as cell C1) and are placed at positions in the high row where performance improvement is not required. As a result, according to some embodiments, along the high row, performance improvement can be provided by placing high cells (such as high cell C1) where needed, and power consumption reduction can be achieved by placing high cells with small OD (such as cell C2) where performance improvement is not required. In at least one embodiment, such an arrangement further enhances the optimizability and / or customizability of the IC layout or its circuit region.

[0076] In some embodiments, different high cells having small OD have different reduced active region widths, i.e., different W SM values. In at least one embodiment, such an arrangement further enhances the optimizability and / or customizability of the IC layout or its circuit region, wherein a balance between performance and power consumption can be achieved by selecting and placing high cells with small OD having appropriate W SM values at positions along the high row. In some embodiments, for a given H T , various values of W SM for high cells having small OD are predetermined and stored, and stored, for example, in a cell library or associated with a cell library.

[0077] In some embodiments, a high cell having small OD (such as cell C2) satisfies the following relationship (6):

[0078] 0.3W ≤ W SM ≤ 0.8W (6)

[0079] In some cases, when the high cells with a small OD do not satisfy the relation (6), the expected improvements in performance, power, and area may not be achieved.

[0080] In some embodiments, the small OD configuration is applicable to the short cells or unit cells. For example, a short cell with a small OD has a reduced active region width W SM , where W SM <W S . In some embodiments, the short cells with a small OD satisfy the relation (6). In some embodiments, for a given H S , various values of W SM of the short cells with a small OD are pre-determined and stored, for example, within or associated with a cell library. In the Figure 2A example configuration, in one or more embodiments, at least one of the short cells C3, C4 can be a short cell with a small OD. In at least one embodiment, both of the cells C3, C4 are short cells with a small OD, where the W SM value of cell C3 is different from the W SM value of cell C4.

[0081] A cell with a small OD has a reduced active region width W SM , where W SM <W. In some embodiments, the unit cells with a small OD satisfy the relation (6). In some embodiments, for a given H, various values of W SM of the unit cells with a small OD are pre-determined and stored, for example, within or associated with a cell library. In at least one embodiment, one or more of the advantages described herein regarding the high cells with a small OD can be achieved by the short cells with a small OD and / or by the unit cells with a small OD. Regarding Figure 3 , Figure 4A , examples and further details of the short cells with a small OD and the cells with a small OD are described.

[0082] In at least one embodiment, the high cells (or high rows) can be optimized / customized independently of the short cells (or short rows) and / or independently of the unit cells (or unit rows), for example, by appropriate W SM values of the high cells with a small OD, the short cells with a small OD, the unit cells with a small OD and / or by the number and / or position of the high cells with a small OD, the short cells with a small OD, the unit cells with a small OD in the corresponding high rows, short rows, unit rows.

[0083] As described herein, the merged cell C5 includes a merged active region 240 / 241 of one conductivity type disposed between active regions 239, 242 of different conductivity types. In some embodiments, the active region width W of active region 239 M1 is the same as the active region width of active region 240, and the active region width W of active region 242 M2 is the same as the active region width of active region 241. As a result, the active region width W of the merged active region 240 / 241 M is the sum of W M1 and W M2 . In at least one embodiment, W M1 = W M2 and W M = 2W M1 = 2W M2 .

[0084] In at least one embodiment, by merging active regions 240, 241 into a merged active region 240 / 241, the active region width W of the merged active region 240 / 241 M is greater than the active region widths of those active regions initially included in the component cells (i.e., the first cell having active regions 239, 240 and the second cell having active regions 241, 242) before / without merging. In one or more embodiments, the increased active region width W M improves the performance of the merged cell C5. The described merged cell configuration according to some embodiments enables performance improvement (i.e., increased speed) to be provided even in regions with a limited active region width (e.g., in regions with short rows and / or unit rows). The performance improvement can also be achieved in regions with tall cells, because as described herein, in one or more embodiments, any two cells or rows (including two tall cells or two tall rows) can be merged to configure a merged cell.

[0085] In some embodiments, the merged cell (e.g., cell C5) satisfies the following relationship (7):

[0086] 1W ≤ W M ≤ 4W (7)

[0087] As can be seen from relationships (3) and (7), in some embodiments, the W of the merged active region M is greater than the maximum value (2W) of the active region width W of the tall cell T . In other words, in one or more embodiments, the merged cell may provide a greater speed improvement than the tall cell. In some cases, when the merged cell does not satisfy relationship (7), the expected or desired improvements in performance, power, and area may not be achieved.

[0088] Figure 2C A schematic diagram showing various unit row configurations 261-265 in one or more IC layouts according to some embodiments.

[0089] Each unit row configuration 261-265 includes a set of rows that includes at least one tall unit and at least one short unit. In at least one embodiment, the set of rows is repeatedly placed multiple times along the Y-axis to cover a planar view or a region of the IC layout. As a result, the IC layout includes a repeating pattern of the set of rows. Such a repeating pattern of the set of rows is sometimes referred to as a unit array. A unit array in which all rows have the same height is sometimes referred to as a single-height (SH) unit array (or a single row height unit array) having a single row height configuration. In some embodiments, all rows in the single-height unit array are unit rows, and the single-height unit array is a unit cell array. A unit array including rows of different heights (e.g., a unit array based on any of the unit row configurations 261-265) is sometimes referred to as a mixed row unit array. Refer to Figure 4B 、 Figure 4C for an example unit array having a repeating pattern of a set of rows.

[0090] In Figure 2C 's example configuration, the unit row configuration 261 includes a set of rows that includes three tall rows 271, 272, 273 and one short row 274. The unit row configuration 262 includes a set of rows that includes two tall rows and one short row. The unit row configuration 263 includes a set of rows that includes one tall row and one short row. The unit row configuration 264 includes a set of rows that includes one tall row and two short rows. The unit row configuration 265 includes a set of rows that includes one tall row 275 and three short rows 276, 277, 278. Other unit row configurations having other numbers of tall rows and / or short rows are within the scope of various embodiments. In at least one embodiment, each tall row, e.g., 271, 272, 273, 275 corresponds to the tall row 210, and / or each short row 274, 276, 277, 278 corresponds to the short row 220 or 230. Regarding Figure 2A 、 Figure 2B describes a specific example of the unit row configuration 264. In Figure 2C 's example configuration, all tall rows have the same height H T , and all short rows have the same height H S . Other configurations are within the scope of various embodiments. For example, in one or more embodiments, two tall rows in the same unit row configuration (e.g., tall rows 271, 272 in the unit row configuration 261) may have different heights greater than H, and / or two short rows in the same unit column configuration (e.g., short rows 276, 277 in the unit row configuration 265) may have different heights less than H.

[0091] As described herein, the tall rows containing tall cells are configured for performance, while the short rows containing short cells are configured for power and area. The number of tall rows, the number of short rows, and the corresponding heights H in each cell row configuration 261-265 T and H S determine the suitability of the cell row configuration for improving performance or improving power and area. In some embodiments, this suitability is represented by the equivalent cell height H E of the cell row configuration. In at least one embodiment, H E is determined by the mixed row ratio R mix as follows:

[0092] R mix = number of tall rows / number of short rows (8)

[0093] H E = (H T × R mix + H S ) / (R mix + 1) (9)

[0094] In one example, for cell row configuration 261, R mix = 3, H E = (3H T +H S ) / 4. In another example, for cell row configuration 265, R mix = 1 / 3, H E = (H T +3H S ) / 4. As Figure 2C shown, H E and R mix increase towards cell row configuration 261 and decrease towards cell row configuration 265. Cell row configuration 263 has R mix = 1. In at least one embodiment, H T +H S = 2H, resulting in cell row configuration 263 having H E = H. H E = H indicates that a cell array including a repeating pattern of cell row configuration 262 is equivalent in terms of performance, power, and area to a single-height cell array including a unit row of height H.

[0095] H E>H (e.g., for cell row configurations 261, 262) indicates that cell row configurations 261, 262 are configured to provide performance improvements superior to a single-height cell array and are suitable for speed-oriented applications or circuit regions. Among cell row configurations 261, 262, cell row configuration 262 is configured to provide a smaller performance improvement than cell row configuration 261 but has better power and area parameters. In at least one embodiment, cell row configuration 261 is suitable for or preferred for applications or circuit regions where speed is the highest priority, while cell row configuration 262 is suitable for or preferred for applications or circuit regions where the requirement for speed is less high and power and area are design considerations.

[0096] H E <H (e.g., for cell row configurations 264, 265) indicates that cell row configurations 264, 265 are configured to provide higher power and area improvements than a single-height cell array and are suitable for power- and area-oriented applications or circuit regions. Among cell row configurations 264, 265, cell row configuration 264 is configured to provide a smaller power and area improvement than cell row configuration 265 but has better performance (i.e., higher speed). In at least one embodiment, cell row configuration 265 is suitable for or preferred for applications or circuit regions where low power and area are the highest priorities, while cell row configuration 264 is suitable for or preferred for applications or circuit regions where the requirements for low power and area are not high and speed is a design consideration.

[0097] In some embodiments, cell row configurations 261 - 265 satisfy the following relation (10):

[0098] 0.8H ≤ H E ≤ 1.2H (10)

[0099] In at least one embodiment, H < H E ≤ 1.2H represents a performance improvement, while 0.8H ≤ H E < H represents an improvement in power and area. In some cases, when a cell row configuration does not satisfy relation (10), that cell row configuration may not achieve the expected or desired improvement in one of performance, power, and area.

[0100] In some embodiments, multiple applications and / or circuit regions are pre-associated with different H E values, e.g., in a lookup table. For example, high-speed applications are associated with high H E values, while low-power applications are associated with low H E values. In at least one embodiment, for a given H value, e.g., in the same or different lookup tables, different H E values are pre-associated with corresponding different cell row configurations, as e.g., with reference to Figure 2CAs described. In some embodiments, different H values (e.g., for different manufacturing processes, design rule sets, materials, etc.) result in different cell row configurations associated with the H E value.

[0101] In at least one embodiment, when developing an IC layout or its circuit region for an application, a look-up table is consulted to determine the corresponding H E , and then the corresponding cell row configuration is determined. A hybrid row cell array is generated as a repeating pattern of the determined cell row configuration. Tall cells and short cells are read from one or more cell libraries and placed in the corresponding tall rows and short rows of the hybrid row cell array according to the circuitry of the circuit region. Wiring is performed to couple the placed cells together and / or to other circuitry. Thus, an IC layout or its circuit region is generated for the application and expected improvements are made in one or more PPA aspects suitable for the application. In at least one embodiment, one or more of the advantages described herein can be achieved by the methods and / or cell row configurations described.

[0102] Figure 3 A schematic diagram showing various cells 310 - 360 that can be placed in an IC layout according to some embodiments. In some embodiments, the cells 310 - 360 are stored in a non-transitory computer-readable storage medium as part of one or more cell libraries (e.g., cell library 300 as shown Figure 3 ). In at least one embodiment, the cells 310 - 360 all meet and / or are configured for the same set of design rules, and / or manufacturing process and / or materials such that all cells 310 - 660 can be included in the same manufacturable IC layout.

[0103] As described herein, cell 310 is an example of a unit cell having a cell height H and an active region width W. A unit cell is sometimes referred to as a default cell. Cell 310 can be placed in a unit row of unit height H. Refer to Figure 4A for a description of an example unit row. With a spacing S between active regions, cell 310 has an optimal active region density (sometimes referred to as "OD density") in a cell having a cell height H. In at least one embodiment, the OD density of a cell is determined as the ratio of the sum of the active region widths in the cell to the cell height. The cell height of cell 310 is H = 2W + 2S (where 2Sx = S). The OD density of cell 310 is 2W / (2W + 2S) or W / (W + S).

[0104] As described herein, cell 320 is an example of a unit cell having a small OD. Cell 320 has a cell height H and a reduced active region width W SM , where W SM < W. In at least one embodiment, the W of cell 320 SMSatisfies the relationship (6). In at least one embodiment, the cell library 300 includes variants of the cell 320, i.e., multiple unit cells having the same small OD as the cell 320, configured for the same function / operation (e.g., a variant of a NAND gate cell is a NAND gate cell), but having different W SM values. The cell 320 can be placed in a unit row. In some embodiments, all the cells in the unit row are unit cells like the cell 310. In at least one embodiment, all the cells in the unit row are unit cells having a small OD like the cell 320, having the same W SM or different W SM values. In some embodiments, the cells in the unit row include one or more unit cells like the cell 310, and one or more unit cells having a small OD like the cell 320. In at least one embodiment, the cells in the unit row include a part of the merged cells, as described herein.

[0105] As described herein, the cell 330 is an example of a short cell having a cell height H S (where H S < H) and an active region width W S (where W S < W). In at least one embodiment, the cell library 300 includes variants of the cell 330, i.e., multiple short cells similar to the cell 330, configured for the same function / operation, but having different H S and W S values. In some embodiments. The cell 330 corresponds to the short cell C3 or C4. The cell 330 can be placed in a short row having a corresponding height H S . Refer to Figure 2A for a description of an exemplary short row. Through the spacing S between the active regions, the cell 330 has the best OD density among the cells having a cell height H S . In at least one embodiment, the OD density of the cell 330 is W S / (W S + S), and is less than the OD density of the cell 310.

[0106] As described herein, the cell 340 is an example of a short cell having a small OD. The cell 340 has a cell height H S and a reduced active region width W SM , where W SM < W S . In at least one embodiment, the W of the cell 340 SMSatisfies the relation (6). In at least one embodiment, the cell library 300 includes variants of cell 340, i.e., multiple short cells having the same small OD as cell 340, configured for the same function / operation but having different W SM values. Cell 340 can be placed in a short row. In some embodiments, all cells in the short row are short cells like cell 330. In at least one embodiment, all cells in the short row are short cells having the same small OD as cell 340 and having the same W SM or different W SM values. In some embodiments, the cells in the short row include one or more short cells like cell 330 and one or more short cells having the same small OD as cell 340. In at least one embodiment, the cells in the short row include a part of a merged cell, as described herein.

[0107] As described herein, cell 350 is an example of a tall cell having a cell height H T (where H T > H) and an active region width W T (where W T > W). In at least one embodiment, the cell library 300 includes variants of cell 350 (i.e., multiple tall cells like cell 350), configured for the same function / operation but having different H T and W T values. In some embodiments. Cell 350 corresponds to tall cell C1. Cell 350 can be placed in a tall row with a corresponding height H T . A sample tall row is described in reference Figure 2A . Through the spacing S between the active regions, cell 350 has the best OD density among cells having a cell height H T . In at least one embodiment, the OD density of cell 350 is W T / (W T + S), and is greater than the OD density of cell 310. The higher OD density of cell 350 indicates that cell 350 has better performance (e.g., higher speed) than cell 310.

[0108] As described herein, cell 360 is an example of a tall cell having a small OD. Cell 360 has a cell height H T and a reduced active region width W SM , where W SM < W T . In at least one embodiment, the W of cell 360 SMSatisfies the relation (6). In at least one embodiment, the cell library 300 includes variants of cell 360 (i.e., multiple tall cells having a small OD like cell 360), configured for the same function / operation but having different W SM values. Cell 360 can be placed in a tall row. In some embodiments, all cells in the tall row are tall cells like cell 350. In at least one embodiment, all cells in the tall row are tall cells having a small OD like cell 360, having the same W SM or different W SM values. In some embodiments, the cells in the tall row include one or more tall cells like cell 350, and one or more tall cells having a small OD like cell 360. In at least one embodiment, the cells in the tall row include a part of the merged cells, as described herein.

[0109] In some embodiments, in addition to cells 310 - 360 and the corresponding variants, the cell library 300 further includes one or more merged cells. In at least one embodiment, the merged cells are obtained by merging the active regions of any two cells selected from cells 310 - 360 and the corresponding variants. In some embodiments, the merged cells are not pre - stored in the cell library, but are generated by an EDA system by merging two cells read from the cell library (such as cell library 300).

[0110] In some embodiments, the cells read from the cell library 300 are placed in rows having corresponding heights in the generated cell array, for example, as Figure 2C , Figure 4B , Figure 4C described. In at least one embodiment, by selecting the cells to be placed in the IC layout from the cell library based on not only the function / operation that the cell is configured to perform, but also other considerations (such as cell height, active region width, whether the cell is to be placed in a circuit region to be optimized or improved for one or more of performance, power, and area), one or more of the advantages described herein can be achieved, including but not limited to PPA improvement, enhanced layout optimality, and / or customizability, etc.

[0111] Figure 4A is a schematic diagram of an IC layout 400A of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a part thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B.

[0112] Compared with the IC layout 200 including tall rows and short rows, the IC layout 400A includes tall rows, short rows, and unit rows. For example, in Figure 4AIn the circuit region shown, the IC layout 400A includes a first subset 401 of two unit rows 403, 405, and a second subset 402 of a tall row 404 and a short row 406. In Figure 4A , the unit rows 403, 405 are labeled "SH" (single height). The subsets 401 and 402 are arranged side by side for illustrative purposes and show that in the Figure 4A example configuration in, H S +H T = 2H. In at least one embodiment, the subsets 401 and 402 are not aligned along the X-axis, as shown; as Figure 4B , Figure 4C shown, one of the subsets 401, 402 is arranged above or below the other along the Y-axis.

[0113] A unit cell 410 including active regions 411, 412 is placed in the unit row 403. In at least one embodiment, the cell 410 corresponds to the cell 310. A unit cell 420 including active regions 421, 422 is placed in the unit row 405. In at least one embodiment, the cell 420 is a cell with a small OD and corresponds to the cell 320. A merged cell 470 including active regions 471, 473 located on opposite sides of the merged active region 472 is placed on the unit rows 403, 405. The active regions 471, 472, 473 of the merged cell 470 are isolated from the active regions 411, 412, 421, 422 of the cells 410, 420 by pseudo-active regions 475, 476, 477 in a manner similar to that described with respect to the pseudo-active regions 245, 246, 247. A short cell 440 including active regions 441, 442 is placed in the short row 406. In at least one embodiment, the cell 440 is a short cell with a small OD and corresponds to the cell 340. A tall cell 450 including active regions 451, 452 is placed in the tall row 404. In at least one embodiment, the tall cell 450 corresponds to the cell 350.

[0114] In the case of H S +H T = 2H and an equal number of tall rows and short rows, the IC layout 400A has R mix = 1 and H E= H, which indicates that overall, the IC layout 400A is comparable to a single-height cell array where all rows are unit rows. However, the arrangement of the tall and short rows in the IC layout 400A enables at least local optimization of one or more PPA aspects. For example, in at least one embodiment, the cells for performing functions or operations with speed as the highest priority are placed in the tall rows or are configured as merged cells. Other cells that consider speed on one hand and power and area on the other hand are placed in the cell rows. The remaining cells for functions or operations that are biased towards power and / or area relative to speed are placed in the short rows or are configured to have a reduced active region width. The described local PPA optimization / improvement is an example.

[0115] Figure 4B and Figure 4C are schematic diagrams of various cell row configurations 400B, 400C in one or more IC layouts according to some embodiments.

[0116] In Figure 4B , the cell row configuration 400B includes a repeating pattern of subset 401 and subset 402, where subset 401 and subset 402 are arranged alternately along the Y-axis. In Figure 4C , the cell row configuration 400C includes a repeating pattern of subset 401 in a part (e.g., the upper part of Figure 4C ) and a repeating pattern of subset 402 in another part (e.g., the lower part of Figure 4C ). Other cell row configurations including subset 401 and subset 402 are within the scope of various embodiments. As shown in Figure 4B , Figure 4C , a cell array including tall rows, short rows, and unit rows is sometimes referred to as an integrated cell array.

[0117] The described integrated cell array is an example. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, the relationship H S + H T = 2H and / or the row number relationship of two unit rows for each tall row and one short row may not necessarily be satisfied. In some embodiments, other numbers of unit rows, tall rows, and / or short rows are included in the integrated cell array. In at least one embodiment, an integrated cell array is obtained by including one or more cell rows in the cell row configuration of a mixed-row cell array. In some embodiments, the rows in subset 401 or subset 402 are adjacent and do not necessarily contact each other. In some embodiments, one or more of the advantages described herein can be achieved by using an IC layout of an integrated cell array (e.g., an integrated cell array based on cell row configuration 400B or 400C) and / or an IC device manufactured according to such an IC layout.

[0118] Figure 5AIt is a block diagram of an IC device 500A according to some embodiments. In at least one embodiment, the IC device 500A corresponds to the IC device 100A.

[0119] The IC device 500A includes a plurality of circuit regions 501-504. In at least one embodiment, the circuit regions 501-504 satisfy the same set of design rules, and / or are configured for the same manufacturing process and / or materials, such that all the circuit regions 501 to 504 can be manufactured together.

[0120] In Figure 5A the example configuration in, the circuit region 501 includes a hybrid row cell array, which includes tall cells and short cells placed in corresponding tall rows and short rows, and these tall rows and short rows are arranged in a cell row configuration, for example, as referred to in Figure 2C described. The circuit region 501 has an equivalent cell height H E1 and a hybrid row ratio R mix1 .

[0121] The circuit region 502 includes another hybrid row cell array, which includes tall cells and short cells placed in corresponding tall rows and short rows, and these cells are arranged in a cell row configuration, for example, as referred to in Figure 2C described. The circuit region 502 has an equivalent cell height H E2 and a hybrid row ratio R mix2 . In some embodiments, the circuit region 501 differs from the circuit region 502 in one or more of the number of tall rows, the number of short rows, the cell height of the tall cells, the cell height of the short cells, etc. In some embodiments, the circuit regions 501, 502 have the same H T , H S , W T , W S based on the same H and W, and the circuit regions 501 and 502 are different from each other in the number of tall rows and / or the number of short rows. Due to one or more of the said differences, the equivalent cell heights H E1 and H E2 are different from each other, and / or the hybrid row ratios R mix1 and R mix2 are different from each other. For example, H E1 >H E2 , and the circuit region 501 with the higher H E1 is configured for high-speed applications, while the circuit region 502 with the lower H E2 is configured for low-power applications.

[0122] The circuit region 503 includes an integrated cell array, which includes tall cells, short cells and unit cells placed in corresponding tall rows, short rows and unit rows, and these cells are arranged in a cell row configuration, as Figure 4B ,Figure 4C as shown. The circuit region 503 has an equivalent cell height H E3 and a mixed row ratio R mix3 . In some embodiments, the circuit region 503 is different from the circuit region 501 and / or the circuit region 502 in one or more aspects such as the number of tall rows, the number of short rows, the cell height of tall cells, the cell height of short cells, etc. In some embodiments, the circuit regions 501, 502, 503 have the same H T , H S , W T , W S , and the circuit region 503 is different from the circuit region 501 and / or the circuit region 502 in terms of the number of tall rows and / or the number of short rows. In at least one embodiment, the circuit region 503 has the same H T , H S , W T , W S , H, W, the number of tall rows, the number of short rows as the circuit regions 501 and 502, and is different from the circuit region 502 in that it additionally includes one or more unit rows. Due to one or more of the said differences, the equivalent cell height H E3 is different from at least one of H E1 or H E2 , and / or the mixed row ratio R mix3 is different from at least one of R mix1 or R mix2 . In at least one embodiment, H E3 and R mix3 are determined as described herein based on the application to be implemented in the circuit region 503 to implement the application while achieving one or more expected PPA improvements.

[0123] The circuit region 504 is a single-height cell array where all cells and all rows have the same cell height. In other words, all rows in the circuit region 504 are unit rows. In some embodiments, the unit cells in the circuit region 504 have the same H and W, and H and W are the basis for determining the H T , H S , W T , W S of one or more of the circuit regions 501 - 503. In at least one embodiment, the circuit region 504 includes unit cells, unit cells with small OD, and merged cells such that one or more PPA improvements can be locally achieved, as described with respect to Figure 4A subset 401. In some embodiments, one or more of the circuit regions 501 - 504 are omitted. The IC device 500A can achieve one or more of the advantages described herein.

[0124] Figure 5BSchematic diagram of IC layout 500B of the circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or 504, or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, 500A.

[0125] IC layout 500B includes a single-height cell array having various unit rows 505 - 510 arranged along the Y-axis. Each of the unit rows 505 - 510 has a height H. IC layout 500B includes a plurality of power rails configured to provide different power supply voltages, such as VDD and VSS. The power rail configured to provide VDD is sometimes referred to as the VDD rail. The power rail configured to carry VSS is sometimes referred to as the VSS rail. In Figure 5B the example configuration shown, the VDD rails and VSS rails are alternately arranged in IC layout 500B. The center line of each power rail coincides with the boundary line between two contact rows. For simplicity, Figure 5B the width of the power rails is not shown. The described power rail arrangement is an example. Other power rail arrangements are within the scope of various embodiments.

[0126] IC layout 500B includes three types of cells: unit cells, cells with small OD, and merged cells. For example, each of regions 511 - 516 includes one or more unit cells corresponding to, for example, cell 310. Each of regions 521 - 522 includes one or more unit cells with small OD corresponding to, for example, cell 320. Each of regions 531 - 535 includes one or more merged cells, each of which extends across two unit rows. For example, each merged cell in region 531 extends across two unit rows 509, 510 and corresponds to, for example, merged cell 470. In at least one embodiment, IC layout 500B enables at least local implementation of one or more PPA improvements. For example, the merged cells in regions 531 - 535 provide speed improvements, the unit cells with small OD in regions 521, 522 provide power and / or area improvements, and the unit cells in regions 511 - 516 provide a balance among various performance, power, and area considerations.

[0127] Figure 5C Schematic diagram of IC layout 500C of the circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103, 501 or 502, or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, 500A. In at least one embodiment, IC layout 500B and IC layout 500C correspond to various circuit regions of the same IC device.

[0128] The IC layout 500C includes a hybrid row cell array having rows 594 - 599 of various heights arranged along the Y-axis. Rows 594, 595, 598, 599 are short rows having a height H S and rows 596, 597 are tall rows having a height H T . The IC layout 500C includes a plurality of power rails, including alternating VDD rails and VSS rails, as Figure 5B shown.

[0129] The IC layout 500C includes five types of cells: tall cells, tall cells with small OD, short cells, short cells with small OD, and merged cells. For example, each of regions 541 - 544 includes one or more short cells corresponding to cell 330. Each of regions 551 - 552 includes one or more short cells with small OD, e.g., corresponding to cell 340. Each of regions 561 - 563 includes one or more tall cells, e.g., corresponding to cell 350. Each of regions 571 - 572 includes one or more tall cells with small OD, e.g., corresponding to cell 360. Each of regions 581 - 585 includes one or more merged cells, each merged cell extending across two contact rows. For example, each merged cell in regions 581, 584, or 585 extends across two short rows 594, 595 and corresponds to, e.g., merged cell C5. Each merged cell in regions 582 or 583 extends across one short row 595 or 598 and one tall row 596 or 597.

[0130] In some embodiments, based on the equivalent cell height H E of the IC layout 500C, e.g., as Figure 2C shown, one or more overall PPA improvements can be achieved across the entire IC layout 500C. In at least one embodiment, the IC layout 500C enables one or more PPA improvements to be further achieved locally. For example, even in regions having short rows for power and area, the merged cells in region 581 provide a speed improvement. The short cells with small OD in regions 551, 552 enhance the power and area improvements already provided by short rows 595, 599. The tall cells with small OD in regions 571, 572 provide power and area improvements even in regions having tall rows intended to increase speed. In some embodiments, one or more of the advantages described herein can be achieved by the IC layout 500C and / or an IC device fabricated according to the IC layout 500C.

[0131] Figure 6Schematic diagram of an IC layout 600 of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a part thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B.

[0132] IC layout 600 includes a subset 601 of two unit rows and a subset 602 of tall and short rows. In at least one embodiment, subset 601 corresponds to subset 401, and / or subset 602 corresponds to subset 402. IC layout 600 also includes a plurality of conductive patterns in the M0 layer. In some embodiments, the M0 layer is the metal layer closest to the active region in the IC layout or the IC device, and the metal layer M1 directly above the M0 layer is the second closest metal layer to the active region. Further details of the M0 layer and the M1 layer are described with reference to Figure 7A 、 Figure 7C 、 Figure 7D 、 Figure 7F 。The conductive patterns in the M0 layer or the M1 layer are sometimes correspondingly referred to as M0 conductive patterns or M1 conductive patterns. In Figure 6 , a first set of M0 conductive patterns 611 - 623 is for the unit rows in subset 601, and a second set of M0 conductive patterns 630 - 641 is for the tall and short rows in subset 602. For illustrative purposes, the M0 conductive patterns are shown on one side of the corresponding rows and cells. In an actual IC layout, the M0 conductive patterns extend along the X-axis over the rows and cells, as shown in Figure 7C 、 Figure 7F . The two sets of M0 conductive patterns of subsets 601, 602 are different from each other to achieve one or more PPA improvements, as described herein.

[0133] The first set of M0 conductive patterns 611 - 623 for the unit rows in subset 601 includes wider M0 conductive patterns 611, 617, 623 configured as power rails and having centerlines coinciding with the boundary lines of the unit rows, as with respect to Figure 5B 、 Figure 5CThe remaining M0 conductive patterns in the first group are configured for data or signals and are sometimes referred to as signal M0 conductive patterns. The signal M0 conductive patterns have the same width (sometimes referred to as "M0 metal width" or "metal width") M along the Y-axis. The metal width M is less than the width of the power rails 611, 617, 623 along the Y-axis. In at least one embodiment, the first group of M0 conductive patterns 611-623 includes two subsets, each corresponding to a separate mask and fabricated by a separate mask. The M0 conductive patterns of the two subsets are arranged alternately along the Y-axis. For example, the first subset includes M0 conductive patterns 611, 613, 615, 617, 619, 621, 623, while the second subset includes M0 conductor patterns 612, 614, 616, 618, 620, 622. The same number (e.g., five) of signal M0 conductive patterns are arranged on each unit row.

[0134] The second group of M0 conductive patterns 630-641 for the rows in subset 602 includes wider power rails 630, 636, 641. The remaining M0 conductive patterns in the second group are signal M0 conductive patterns and are narrower than the power rails 630, 636, 641. In at least one embodiment, the second group of M0 conductive patterns 630-641 includes two subsets, each corresponding to a separate mask and fabricated by a separate mask. The M0 conductive patterns of the two subsets are arranged alternately along the Y-axis. For example, the first subset includes M0 conductive patterns 631, 633, 635, 637, 639, 641, while the second subset includes M0 conductive patterns 630, 632, 634, 636, 638, 640. In some embodiments, the M0 conductive patterns 611, 613, 615, 617, 619, 621, 623 and 631, 633, 635, 637, 639, 641 correspond to the first mask and are fabricated by the first mask, while the M0 conductive patterns 612, 614, 616, 618, 620, 622 and 630, 632, 634, 636, 638, 640 correspond to the second mask and are fabricated through the second mask.

[0135] The signal M0 conductive patterns 631-635 on the high rows in subset 602 have a metal width M T , where M T > M. The reason is that the high cells in the high rows have a larger active region width W T , configured to handle a larger current than the unit cells with a smaller active region width W (to improve speed). The larger M of the signal M0 conductive patterns on the high rows TThis is to reduce the voltage drop (IR drop) associated with the larger current in high cell processing. In at least one embodiment, for similar reasons, the vias coupled to the signal M0 conductive patterns 631 - 635 on the high rows also have a larger size than the vias coupled to the signal M0 conductive patterns 612 - 616 on the unit rows.

[0136] The signal M0 conductive patterns 637 - 640 on the short rows in the subset 602 have a metal width M S , where M S < M. The reason is that the short cells in the short rows are not for speed improvement but have a smaller active region width W S or W SM , which is configured to handle a smaller current than the current handled by the unit cells with a larger active region width W. In one or more embodiments, the smaller metal width M of the signal M0 conductive patterns on the short rows S contributes to area reduction, i.e., improvement of the chip area. In Figure 6 the example configuration in, to further improve the area, the number (e.g., four) of the signal M0 conductive patterns 637 - 640 on the short rows is less than the number (e.g., five) of the signal M0 conductive patterns 631 - 635 on the high rows. In at least one embodiment, to achieve the expected area improvement, it is sufficient to reduce the number of the signal M0 conductive patterns on the short rows compared to the unit rows or the high rows, or to reduce the metal width of the signal M0 conductive patterns on the short rows compared to the unit rows or the high rows.

[0137] Figure 7A Includes a schematic circuit diagram and a cross - sectional view of the circuit region of the IC device 700A according to some embodiments. In some embodiments, the IC device 700A corresponds to one or more of the IC devices 100A, 100B, 500A.

[0138] In Figure 7A the example configuration in, the circuit region includes an inverter INV. As can be seen from Figure 7A the schematic circuit diagram in, the inverter INV includes a P - type device MP and an N - type device MN. The gates of the device MP and the device MN are connected to the input IN. The first source / drain of the device MP is connected to the first source / drain of the device MN and the output ZN. The second source / drain of the device MP is coupled to VDD, and the second source / drain of the device MN is coupled to VSS.

[0139] From Figure 7AAs can be seen from the cross-sectional view, the IC device 700A includes a first structure 701 and a second structure 702. The structure 701 is formed by FEOL manufacturing and is sometimes referred to as the FEOL structure 701. The structure 702 is formed on the FEOL structure 701 by BEOL manufacturing and is sometimes referred to as the BEOL structure 702.

[0140] The FEOL structure 701 includes a substrate (not numbered), which in one or more embodiments corresponds to the substrate 110. The active regions 761, 762 (schematically shown by the label "OD" in the figure) are located above the substrate and correspondingly configure the source / drain of the device MP and the device MN. In at least one embodiment, the active regions 761 and 762 correspond to the nanosheet stacks 134, 124 and / or various active regions described herein. The isolation region 704 is located between the active regions 761, 762 and, in one or more embodiments, corresponds to the isolation region 114. Figure 7A The gates of the device MP and the device MN are not shown in the figure. In some embodiments, the gates of the device MP and the device MN are continuous with each other and correspond to the gate electrodes 116 or 118. The source / drain contacts 763, 764 (schematically shown by the label "MD" in the figure) are correspondingly located above and in electrical contact with the active regions 761, 762. The isolation region 704 is also located between the source / drain contacts 763, 764. The dielectric layer 703 is located above the source / drain contacts 763, 764. The via-to-device (VD) vias 765, 766 are correspondingly located above and in electrical contact with the source / drain contacts 763, 764. Figure 7A The via-to-gate (VG) vias (not shown in the figure) are located above and in electrical contact with the gates of the device MP and the device MN. The VD vias 765, 766 and the VG vias are embedded in the dielectric layer 703. The upper surfaces of the dielectric layer 703, the VD vias 765, 766 and the VG vias correspond to the upper surface of the FEOL structure 701 on which the BEOL structure 702 is formed.

[0141] The BEOL structure 702 is sometimes referred to as a redistribution structure. The redistribution structure includes a plurality of metal layers and via layers that are arranged sequentially and alternately on the VD and VG vias. The redistribution structure also includes various interlayer dielectric (ILD) layers (commonly denoted as 705), in which the metal layers and via layers are embedded. The metal layers and via layers of the redistribution structure are configured to electrically couple various components or circuits of the IC device 700A to each other and to an external circuit. In the redistribution structure, the bottommost metal layer that is adjacent to and in electrical contact with the VD and VG vias is the M0 (metal zero) layer, the next metal layer adjacent to the M0 layer is the M1 layer, the next metal layer adjacent to the M1 layer is the M2 layer, and so on. The via layer Vn is arranged between the Mn layer and the Mn+1 layer and electrically couples them, where n is an integer equal to or greater than zero. For example, the via zero (V0) layer is the bottommost via layer that is arranged between the M0 layer and the M1 layer and electrically couples them. The other via layers are V1, V2, etc. The vias in the V0 layer are called V0 vias, the vias in the V1 layer are called V1 vias, and so on. For simplicity, Figure 7A the metal layers and via layers in the redistribution structure are not fully shown.

[0142] In Figure 7A the example configuration shown, the M0 conductive patterns 730 - 735 are located above the FEOL structure 701. The M0 conductive patterns 731, 735 are located above and in electrical contact with the VD vias 765, 766 respectively, and the M0 conductive pattern 733 is located above and in electrical contact with the VG. The V0 vias 741, 742 are located above and in electrical contact with the M0 conductive patterns 731, 735 respectively. Another V0 via ( Figure 7A not shown in the figure) is located above and in electrical contact with the M0 conductive pattern 733 to provide an electrical connection to the gates of the devices MP and MN. The M1 conductive pattern 740 is located above and in electrical contact with the V0 vias 741, 742 to electrically couple the source / drain of the device MP in the active region 761 to the source / drain of the device MN in the active region 762. The M1 conductive pattern 740 forms the output ZN. Another M1 conductive pattern ( Figure 7A not shown in the figure) is located above and in electrical contact with the via V0 that is coupled to the gates of the devices MP and MN to form the input IN.

[0143] Figure 7B and Figure 7C are schematic diagrams of the respective layers of the IC layout 700B of the circuit region according to some embodiments. Figure 7A The figure corresponds to a cross-section taken along the line A - A in Figure 7A and Figure 7B . Figure 7C The figure shows a part of the IC layout 700B corresponding to the FEOL structure 701. Figure 7B Figure 7C Figure 7CShows another part of the IC layout 700B corresponding to the BEOL structure 702. For simplicity, Figures 7A - 7C The corresponding components in are denoted by the same reference numerals.

[0144] Figure 7B The part of the IC layout 700B in is similar to the layout of the stub unit or unit cell described herein. The IC layout 700B includes gates G1, G2 of devices MP, MN. Gates G1, G2 are continuous with each other, and VG vias are located above gates G1, G2. The IC layout 700B includes cut MD masks CMD1, CMD2, and the cut MD masks CMD1, CMD2 indicate the positions where the source / drain contacts are divided into segments. Mask CMD2 corresponds to Figure 7A The isolation region 704 in that separates the source / drain contacts 763, 764. Mask CMD1 separates other source / drain contacts 767, 768 that are located above and in electrical contact with other source / drains corresponding to devices MP, MN in the active regions 761, 762 respectively. Extended VD vias VDR1, VDR2 are located above and in electrical contact with the source / drain contacts 767, 768 respectively, to electrically couple the source / drain contacts 767, 768 to the M0 conductive patterns 730, 736, and the M0 conductive patterns 730, 736 are the VDD rail and the VSS rail respectively.

[0145] Figure 7C The part of the IC layout 700B in includes M0 conductive patterns 730 - 736, V0 vias 741 - 743, and M1 conductive patterns 740, 744. V0 via 743 electrically couples the M0 conductive pattern 733 to the M1 conductive pattern 744 that constitutes the input IN. In some embodiments, the M0 conductive patterns 731 - 735 correspond to the signal M0 conductive patterns on the unit cell or stub unit, as Figure 6 shown.

[0146] As Figure 7A , Figure 7C shown, the source / drain of device MP and the source / drain of device MN are electrically coupled on the M1 conductive pattern 740. In one or more embodiments, this arrangement is applicable to cells with a not-too-high OD density, such as unit cells, stub units, or cells with a small OD. For cells with a high OD density, such as high cells, in one or more embodiments, additional conductors parallel to the M1 conductive pattern 740 are provided, as referenced Figures 7D - 7F described.

[0147] Figure 7DSchematic circuit diagrams and cross-sectional views of the circuit regions of IC device 700D according to some embodiments. In some embodiments, IC device 700D corresponds to one or more of IC devices 100A, 100B, 500A, 700A. For simplicity, Figure 7A , Figure 7D The corresponding components in are denoted by the same reference numerals.

[0148] Figure 7D The IC device 700D in is similar to the IC device 700A in Figure 7A but has the differences described herein. IC device 700D includes a FEOL structure 771 and a BEOL structure 702. The FEOL structure 771 differs from the FEOL structure 701 of IC device 700A in that the FEOL structure 771 includes extended source / drain contacts 773, which replace the source / drain contacts 763, 764 of IC device 700A. The extended source / drain contacts 773 extend continuously along the Y-axis between the active regions 761, 762. As a result, the active regions 761, 762 are electrically coupled to each other through a pair of parallel-coupled conductors (i.e., the extended source / drain contacts 773 and the M1 conductive pattern 740) to reduce the resistance (sometimes referred to as "drain side resistance"). In Figure 7D In the example configuration in, the extended source / drain contacts 773 also have a portion 774 that extends downward along the Z-axis. In some embodiments, the portion 774 of the extended source / drain contacts 773 further contacts the active regions 761, 762 along the Y-axis to further reduce the resistance. In at least one embodiment, the portion 774 is omitted.

[0149] Figure 7E and Figure 7F are schematic diagrams of the respective layers of the IC layout 700E of the circuit region of Figure 7D according to some embodiments. Figure 7D Corresponds to a cross-section taken along line A-A in Figure 7E , Figure 7F . Figure 7E Shows a portion of the IC layout 700E corresponding to the FEOL structure 771. Figure 7F Shows another portion of the IC layout 700E corresponding to the BEOL structure 702. For simplicity, Figures 7A - 7F The corresponding components in are denoted by the same reference numerals.

[0150] Figure 7F The portion of the layout 700E in is the same as the portion of the IC layout 700B in Figure 7C . Figure 7E The portion of the layout 700E in is similar to Figure 7Ba portion of layout 7000B, except that mask CMD2 of IC layout 700B is not included in IC layout 700E. As a result, the extended source / drain contact 773 in IC layout 700E is not divided into source / source contacts 763, 764 as in IC layout 700B, but extends continuously between active regions 761, 762 to configure, together with M1 conductive pattern 740, a pair of parallel-coupled conductors as described herein.

[0151] In at least one embodiment, the parallel-coupled arrangement described with reference to Figures 7D - 7F is applicable to cells with a high OD density, such as high cells. In one or more embodiments, this arrangement reduces the resistance between the source / drain (e.g., drain) of devices MP and MN, thereby increasing the current and improving the speed. The extended source / drain contact 773 may generate additional parasitic capacitance with adjacent conductive structures (such as gate electrodes). However, in at least one embodiment, the increased current outweighs any adverse effects associated with the potentially generated additional parasitic capacitance, and an increase in speed can be achieved through the extended source / drain contact 773.

[0152] Figure 8A is a schematic circuit diagram of circuit region 800A of an IC device according to some embodiments. In some embodiments, circuit region 800A corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, 500A, 700A, 700D.

[0153] Circuit region 800A includes a multi-stage circuit, such as buffers, AND gates, OR gates, etc. In Figure 8A the example configuration in, the multi-stage circuit includes two stages, each stage being an inverter. Specifically, the first stage includes inverter INV1, while the second stage includes inverter INV2. In at least one embodiment, inverters INV1, INV2 correspond to inverter INV described with reference to Figures 7A - 7F Other numbers of stages are within the scope of various embodiments. Other circuit configurations for each stage are also within the scope of various embodiments.

[0154] Inverter INV1 has an input IN1 and an output ZN1. Inverter INV2 has an input IN2 and an output ZN2. The input IN2 of inverter INV2 is coupled to the output ZN1 of inverter INV1. Inverter INV1 is configured to receive an input signal 821 at the input IN1. Inverter INV1 is configured to output an intermediate signal 822 at the output ZN1 based on the input signal 821. The intermediate signal 822 is input to inverter INV2 through the input IN2, and inverter INV2 is configured to output an output signal 823 at the output ZN2 based on the intermediate signal 822. In some embodiments, in order to achieve one or more PPA improvements in a multi-stage circuit, inverter INV1 as the first stage is configured to reduce the input impedance and / or capacitance, while inverter INV2 as the second stage is configured to provide a larger drive current than inverter INV1. As a result, in one or more embodiments, an improved stage ratio and performance of the multi-stage circuit can be achieved. Refer to Figure 8B An example layout of the multi-stage circuit is described.

[0155] Figure 8B is according to some embodiments Figure 8A A schematic diagram of the IC layout 800B of the circuit region 800A in

[0156] IC layout 800B includes a short cell 831 having a cell height H S and a tall cell 832 having a cell height H T The cells 831, 832 are arranged along the Y-axis in configuration 802, which in one or more embodiments corresponds to the configuration of subset 402 or 602. Cell 831 includes an active region 851 configuring an N-type device N1 and an active region 852 configuring a P-type device P1. Although Figure 8B not shown in Figure 7B , Figure 7C , Figure 7E , Figure 7F one or more of the conductive structures, vias, and patterns as described in

[0157] Cell 832 includes an active region 861 configuring a P-type device P2 and an active region 862 configuring an N-type device N2. Although Figure 8B not shown in Figure 7B , Figure 7C , Figure 7E , Figure 7FVarious conductive structures, vias, and patterns corresponding to one or more of the conductive structures, vias, and patterns therein. The various conductive structures, vias, and patterns couple the P-type device P2 and the N-type device N2 to an inverter corresponding to the inverter INV2.

[0158] As referred to Figure 8A above, the output of the inverter INV1 in the cell 831 is coupled to the input of the inverter INV2 in the cell 832. In one example, the cell 832 has a layout as Figure 7C shown, while the cell 831 has a layout that is horizontally flipped on the Y-axis as Figure 7A shown. A single M1 conductive pattern extends continuously from the cell 831 into the cell 832 and forms the output of the cell 831 and the input of the cell 832. As a result, as referred to Figure 8A above, the output of the inverter INV1 in the cell 831 is coupled to the input of the inverter INV2 in the cell 832 to form a multi-stage circuit.

[0159] In the IC layout 800B, the cell 831 is a short cell with a small OD, for example, as described with respect to the cell 340. In at least one embodiment, the cell 831 is a short cell, for example, as described with respect to the cell 330. Due to the reduction in the size of the cell 831 (such as the cell height and / or the active region width), the requirements of reducing the input impedance and / or capacitance of the first stage formed by the cell 831 can be achieved. On the other hand, the cell 832 is a tall cell, for example, as described with respect to the cell 350. As described herein, such a tall cell has a larger current than a short cell. As a result, the requirement of a high drive current for the second stage formed by the cell 832 can be achieved. In some embodiments, by configuring the first stage of the multi-stage circuit in a short cell and the second stage of the multi-stage circuit in a tall cell, one or more PPA improvements described herein can be achieved.

[0160] Figure 9A is a schematic diagram of an IC layout 900A of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to the region 103 or a part thereof. In at least one embodiment, the IC device corresponds to one or more of the IC devices 100A, 100B, 500A, 700A, 700D.

[0161] The IC layout 900A includes a hybrid row cell array having rows 901-912 of various heights arranged along the Y-axis. The rows 901-902, 905-906, 909-910 are tall rows having a height H T (not shown in Figure 9A ), while the rows 903-904, 907-908, 911-912 are short rows having a height H S (Figure 9B (not shown). In some embodiments, the IC layout 900A includes multiple power rails, and the power rails include VDD rails and VSS rails that alternate along the boundary lines between rows, as referenced Figure 5B as described.

[0162] During the design phase, critical path 950 is identified in the IC layout 900A. A critical path is a time-sensitive path through which signals propagate during operation. In one example, a critical path is a path with a time delay that does not meet (i.e., is greater than) the timing requirements. In another example, a critical path is a path in the circuit area of an IC device or the entire IC device that has a long time delay (in some cases, the longest time delay). A long time delay refers to a delay that may meet the timing requirements but is still greater than a predetermined threshold. The time delays of various paths in the IC design of an IC device are estimated during the design phase through one or more simulations performed, for example, before or after the APR operation. Based on the results of such simulations, one or more critical paths are identified. In some embodiments, reducing the time delay of a critical path is necessary to meet the timing requirements or is desirable to improve the performance of the IC device.

[0163] In Figure 9A the example configuration of, once the critical path, such as critical path 950, is identified, improvements are made to the IC design or the IC layout 900A to reduce the time delay of the critical path 950. To reduce the time delay of the critical path 950 in the IC layout 900A, in one or more embodiments, rerouting and / or reconfiguring one or more cells in the IC layout 900B is performed to route the critical path 950 through cells configured for speed or performance, such as through high cells and / or merged cells. For example, Figure 9AShows that after improving the IC layout 900A, the critical path 950 is routed through the tall cells 921, 922, 924, 925, 927 and the merged cells 923, 926, 928. In some embodiments, an operation of reconfiguring (e.g., merging) the cells in the short rows into one or more merged cells is performed to provide the merged cells 923, 926, 928. In at least one embodiment, the merged cells can be configured to provide better performance (e.g., higher speed, lower time delay) than the tall cells as described herein. The merged cells 923, 926, 928 enable high performance and reduced time delay to be provided even when the critical path 950 passes through the short rows that are not typically configured for high speed. In at least one embodiment, using one or the merged cells further shortens the critical path 950, thereby reducing the time delay of the critical path and / or reducing the drag effect observed when the critical path is too long and passes through unnecessary rows. In some embodiments, after the improvement, one or more simulations are re-executed to confirm that the path 950 is no longer the critical path. In at least one embodiment, when generating the IC layout from the IC design (IC schematic), the described routing and / or merged cell placement is performed in the first APR operation to reduce the time delay of the path, rather than as an improvement to an existing IC layout.

[0164] Figure 9B Is a schematic diagram of an IC layout 900B of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a part thereof. In at least one embodiment, the IC device corresponds to one or more of the IC devices 100A, 100B, 500A, 700A, 700D. In at least one embodiment, the IC layout 900A and the IC layout 900B are part of the same IC layout for the same IC device. For simplicity, Figure 9A 、 Figure 9B The corresponding components in are denoted by the same reference numerals.

[0165] Compared with the IC layout 900A showing examples of cells along the critical path (sometimes referred to as "critical cells"), the IC layout 900B shows examples of cells outside the critical path (sometimes also referred to as "non-critical cells"). In some embodiments, the non-critical cells do not need to provide high current or high speed, and are configured to have a small active region width to improve (e.g., reduce) power and / or area. In Figure 9B the example configuration in, the non-critical cells are configured by tall cells, short cells with small OD, or short cells with small OD. In Figure 9BTwo exemplary tall cells 941, 942 with small OD and two short cells 943, 944 are specified. In at least one embodiment, at least one of the cells 943, 944 is a short cell with small OD. In some embodiments, the tall cell with small OD, the short cell, and the short cell with small OD in the IC layout 900B correspond to cells 360, 330, 340. In at least one embodiment, using a tall cell with small OD for non-critical cells can at least improve power consumption, while using a short cell and / or a short cell with small OD for non-critical cells can improve power consumption and area.

[0166] Figure 10 Table 1000 shows the wiring characteristics of various cells that can be placed in an IC layout according to some embodiments. Regarding Figures 2A - 2C 、 Figure 3 、 Figures 4A - 4C 、 Figures 5A - 5B 、 Figure 6 、 Figures 7B - 7C 、 Figures 7E - 7F 、 Figure 8B 、 Figure 9A 、 Figure 9B One or more of them describe an example IC layout.

[0167] In some embodiments, the wiring characteristics include BEOL characteristics, such as metal layers, via layers, etc., as shown in Figure 6 、 Figure 7A 、 Figure 7D . In the example of Figure 10 , the wiring characteristics include M0 tracks, M2 tracks, M0PG width, M2 structure, VIA0, and VIA1 corresponding to rows 1001 - 1005 of Table 1000. The M0 tracks include the width and arrangement of the M0 conductive pattern, for example, as described with reference to Figure 6 . The M2 tracks include the width and arrangement of the M2 conductive pattern. The M0PG (power - ground) width represents the width of the M0 conductive pattern configured as the VDD rail (power) and the VSS rail (ground). The M2 structure includes further details of the M2 tracks. VIA0 includes the size of the V0 via. VIA1 includes the size of the V1 via. Other wiring characteristics are within the scope of various embodiments.

[0168] Figure 10 The wiring characteristics of three example cells are shown in Figures 5A - 5B , namely the unit cell in column 1010, the short cell in column 1030, and the tall cell in column 1050 of Table 1000. The unit cell shown in column 1010 can be placed in a single - height cell array configured with a single - row height, for example, as described inFigures 9A - 9B As shown. In some embodiments, the unit cells, short cells, and tall cells shown in Table 1000 can be placed in an integrated cell array, such as Figures 4A - 4C , Figure 5A , Figure 6 described. In at least one embodiment, the short cells and tall cells shown in Table 1000 can be placed in other hybrid row configurations, such as Figures 2A - 2C , Figure 8B described. In some embodiments, Figure 10 The wiring features for the unit cells shown in also apply to unit cells with a small OD and a part of the merged cells on the unit row. Figure 10 The wiring features of the short cells shown in also apply to short cells with a small OD and a part of the merged cells on the short row. Figure 10 The wiring features for the tall cells shown in also apply to tall cells with a small OD and a part of the merged cells on the tall row.

[0169] For the unit cells in row 1010 of Table 1000, the M0 tracks correspond to Figure 6 the tracks described for the unit cells. Five signal M0 conductive patterns with a width W1 (corresponding to the width M in Figure 6 ) are arranged along the Y-axis between two M0 conductive patterns configured as the VDD rail and the VSS rail respectively. The VDD rail and the VSS rail have the same width PG1, where PG1 > W1. For the M2 tracks, seven M2 conductive patterns are arranged on the cell, and all have the same width W2, where W2 > W1. The V0 vias and the V1 vias have the same size D1×D1.

[0170] For the short cells in row 1030 of Table 1000, the M0 tracks are similar to those of the unit cells in column 1010, except that the width PG3 of the VDD track is greater than the width PG1 of the VSS track. For the M2 tracks, four M2 conductive patterns that do not overlap with the VDD and VSS tracks and have a width W2 are arranged between the VDD track and the VSS track. One M2 conductive pattern overlaps with the VSS track and has a width W5. Another M2 conductive pattern overlaps with the VDD track and has a width W4, where W4 > W5 > W2. The V0 vias have the same size D1×D1 as the V0 vias of the unit cells, while the V1 vias have a larger size D2×D2, where D2 > D1.

[0171] For the tall cells in row 1050 of Table 1000, the VDD rail has the same width PG3 as the short cells in row 1030. The width PG4 of the VSS rail is larger, where PG4 > PG3. The two signal M0 conductive patterns 1052, 1054 have a width W2. The signal M0 conductive pattern 1053 between the signal M0 conductive patterns 1052, 1054 has a width W3, where W3 > W2. Correspondingly, the two signal M0 conductive patterns 1051, 1055 adjacent to the VDD rail and the VSS rail have a width W4, where W4 > W3. In some embodiments, the M0 conductive patterns 1051, 1053, 1055 correspond to one M0 mask, while the VDD rail, the VSS rail, and the M0 conductive patterns 1052, 1054 correspond to another M0 mask. For the M2 tracks, two M2 conductive patterns overlap with the VDD and VSS tracks correspondingly, and four M2 conductive patterns are arranged between the VDD and VSS tracks without overlapping with the VDD and VSS tracks. All six M2 conductive patterns have the same width W4. The V0 vias include a first V0 via with a size of D2×D2 and a second V0 via with a larger size of D3×D3, where D3 > D2 > D1. The first V0 via with the smaller size D2×D2 is used to couple with the M0 conductive patterns 1052, 1054 with the smaller width W2. The second V0 via with the larger size D3×D3 is used to couple with the M0 conductive patterns 1051, 1053, 1055 with the larger width W4 or W3. The size of the V1 via is D2×D2.

[0172] In Figure 10 the example configuration, compared with the unit cells in row 1010 and the short cells in row 1030, the tall cells in row 1050 have wider M0 conductive patterns and M2 conductive patterns, and larger V0 vias to achieve lower resistance and higher speed. The narrower signal M0 conductive patterns and M2 conductive patterns of the unit cells in row 1010 and the short cells in row 1030 are configured to improve power and / or area. In some embodiments, the hybrid row cell array with short cells and tall cells and the corresponding wiring features shown in rows 1030, 1050 provide performance improvements over the single-height cell array with unit cells in row 1010. In at least one embodiment, the performance improvement includes an increase in speed of about 4.5% at the maximum operating frequency of the cell array.

[0173] Figure 11 is a flowchart of a method 1100 for designing and / or manufacturing an IC device according to some embodiments. In some embodiments, the method 1100 can be used to design and / or manufacture one or more IC devices as described herein. According to some embodiments, for example, the method 1100 can be implemented using the EDA system discussed below and / or the manufacturing system discussed below.

[0174] In operation 1102, a layout diagram is generated, which includes one or more of the layouts of various circuits disclosed herein. According to some embodiments, operation 1102 can be implemented, for example, using the EDA system discussed below. Examples of the layout diagram obtained at operation 1102 include one or more of the layout diagrams described herein.

[0175] In operation 1104, based on the layout diagram, (A) one or more photolithographic exposures are performed, or (B) one or more semiconductor masks are fabricated, or (C) at least one of one or more components in the IC device layer is fabricated. According to some embodiments, operation 1104 can be implemented, for example, using the manufacturing system discussed below. Examples of the IC devices obtained at operation 1104 include one or more of the IC devices described herein. In some embodiments, operation 1104 is omitted.

[0176] Figure 12 is a flowchart of a method 1200 for generating an IC layout of a circuit region of an IC device according to some embodiments. In some embodiments, method 1200 is an example of at least a part of operation 1102. In at least one embodiment, method 1200 can be implemented at least partially using a processor, such as in the EDA system discussed below.

[0177] In operation 1205, a circuit region for which an IC layout is to be generated is received. In some embodiments, the circuit region includes all the circuits of the IC device. In at least one embodiment, the circuit region includes a part of the circuits of the IC device and corresponds to, for example, one or more circuit regions described with reference to Figure 5A In some embodiments, the circuit region is received in the form of an IC schematic diagram (i.e., an electrical diagram) of the circuit region. In some embodiments, the schematic diagram is generated or provided in the form of a schematic netlist (e.g., a simulation program with an integrated circuit emphasis (SPICE) netlist). Other data formats for describing the design, such as Verilog, are available in some embodiments.

[0178] In some embodiments, various groups of cells with different cell heights are obtained. For simplicity, a first cell with a first cell height and a second cell with a second cell height are obtained. In one example, the first cell is a tall cell and the second cell is a short cell. In some embodiments, as described with reference to Figure 3 one or more tall cells with different values of H T 、W T 、W SM are obtained from the cell library, and / or one or more tall cells with different values of H S 、W S 、W SMOne or more additional short cells with different values of one or more. In at least one embodiment, the EDA system derives at least one tall cell or short cell from a default cell. For example, as described herein, the H and W of the default cell are used in combination with one or more of the relationships (1)-(6) and a set of predetermined design rules to generate tall cells and / or short cells that satisfy the set of design rules and can be used to achieve one or more PPA improvements. In some embodiments, all or part of operation 1205 is omitted.

[0179] In operation 1210, based on the application to be executed in the circuit area, determine the equivalent cell height, such as H, of the IC layout to be generated. E . For example, as described herein, access a pre-prepared look-up table. The look-up table associates multiple applications and / or circuit areas with different H E values. For example, a high-speed application is associated with a high H E value, while a low-power application is associated with a low H E value. The application of the circuit area is input into the look-up table, and the look-up table returns the H E value that matches or is closest to the input application.

[0180] In operation 1215, based on the determined equivalent cell height, the cell row configuration includes at least a first row of a first height and at least a second row of a second height different from the first height. Refer to Figure 2C for a description of an example cell row configuration. In at least one embodiment, various cell row configurations are pre-developed and associated with the corresponding values of H E , for example, in the same or another look-up table, the determined H E is input into the look-up table and the corresponding cell row configuration is returned. In some embodiments, based on relationship (9), the determined H E and the H T and H S of the tall cells and short cells obtained in operation 1205 are used to calculate R mix . According to the calculated R mix and relationship (8), the number of tall rows and short rows in the cell row configuration to be used can be determined. For example, when the calculated R mix is 3, Figure 2C the cell row configuration 261 in

[0181] In operation 1220, a cell array is generated according to the determined cell row configuration. For example, assume that in operation 1215 it is determined to use a cell row configuration including two short rows and two tall rows (2 short 2 tall), then the determined cell row structure is repeatedly placed multiple times along the Y-axis to cover the floorplan of the IC layout. The resulting cell array includes a repeating pattern of 2 short rows, 2 tall rows, 2 short rows, 2 tall rows, etc. along the Y-axis, as Figure 5C shown. In at least one embodiment, at this stage, no cells have been placed in the generated cell array.

[0182] In operation 1225, one or more routing features are determined for the cells to be placed in the generated cell array. Examples of the routing features to be determined are described with respect to Figure 10 In at least one embodiment, the routing features are determined for each cell based on cell height, active region width, and / or various design rules. As described with reference to Figure 10 the routing features of short cells and tall cells are different in various aspects to optimize one or more of the PPA. In some embodiments, operation 1225 is omitted, and the routing features are determined by the APR tool when performing the APR operations as described herein.

[0183] In operation 1230, placement and routing operations are performed to generate the IC layout of the circuit region. In the placement and routing operations, one or more first cells of a first height are placed in the first row of the first height in the generated cell array, and one or more second cells of a second height are placed in the second row of the second height in the generated cell array. In at least one embodiment, the placement and routing operations include APR operations performed by an APR tool or system. For example, based on the IC schematic of the circuit region, the APR tool places cells of various functions corresponding to the IC schematic into the generated cell array. When a cell with a specific function (e.g., AND gate) is to be placed in the tall row of the cell array, then a tall cell with the specific function (i.e., AND gate) is placed. Similarly, when a cell with a specific function is to be placed in the short row of the cell array, then a short cell with that specific function is placed.

[0184] After the placement operation is completed, a routing operation is performed according to the IC schematic to couple the placed cells. In some embodiments, the routing operation is performed according to the routing features determined at operation 1225. In at least one embodiment, the routing operation is performed based on other routing features and / or design rules.

[0185] According to some embodiments, during the APR operation, one or more of operations 1235 - 1238 are performed to achieve further PPA improvements. In some embodiments, one or more of operations 1235 - 1238 are omitted.

[0186] In operation 1235, to configure a multi-stage circuit in a circuit region, one or more short cells are placed and routed to form an earlier or input stage, while tall cells are placed and routed to form a later or output stage, as referenced Figures 8A - 8B as described. As a result, in one or more embodiments, a low input impedance / capacitance and a high drive current can be achieved.

[0187] In operation 1236, for cells with a high OD density, such as tall cells, where the source / drain of a P-type device is coupled to the source / drain of an N-type device through an M1 conductive pattern, an extended source / drain contact (MD) is used to form a parallel conductor with the M1 conductive pattern, as Figures 7D - 7F shown. As a result, in one or more embodiments, the resistance can be reduced and the speed can be increased. In some embodiments, the changes required to create an extended MD in the existing layout of a cell are as simple as removing a cut MD mask.

[0188] In operations 1237 - 1238, when a critical path is identified in an IC layout, in one or more embodiments, at least one of the critical cells along the critical path or the non-critical cells outside the critical path can be optimized. In at least one embodiment, to optimize the critical cells along the critical path, cells configured for speed (such as merged cells, tall cells) are placed or created along the path to reduce the time delay and / or length of the path, as referenced Figure 9A as described. In some embodiments, to optimize the non-critical cells outside the critical path, cells configured for power and / or area (such as short cells, cells with a small OD) are placed to improve power and / or area, as Figure 9B shown.

[0189] After the layout and routing operations and before manufacturing, the generated IC layout is subjected to one or more validations and / or simulations and / or modifications. In at least one embodiment, one or more IC layouts generated by method 1200 and / or IC devices manufactured based on such IC layouts can achieve one or more of the advantages described herein.

[0190] The method includes exemplary operations, but does not necessarily need to be performed in the order shown. Operations can be appropriately added, replaced, reordered, and / or eliminated in accordance with the spirit and scope of the embodiments of the present disclosure. Embodiments combining different features and / or different embodiments are within the scope of the present disclosure, and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0191] In some embodiments, at least one of the above methods is performed in whole or in part by at least one EDA system. In some embodiments, the EDA system can be used as part of the design house of an IC manufacturing system discussed below.

[0192] Figure 13 is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0193] In some embodiments, the EDA system 1300 includes an APR system. According to one or more embodiments, the methods of designing layout diagrams described herein represent wiring arrangements, for example, and according to some embodiments, can be implemented using the EDA system 1300.

[0194] In some embodiments, the EDA system 1300 is a general computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Among other things, the storage medium 1304 is also encoded with computer program code 1306, that is, a set of executable instructions. The execution of the instructions 1306 by the hardware processor 1302 represents (at least in part) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to one or more embodiments.

[0195] The processor 1302 is electrically coupled to the computer-readable storage medium 1304 via a bus 1308. The processor 1302 is also electrically coupled to an I / O interface 1310 via the bus 1308. A network interface 1312 is also electrically connected to the processor 1302 via the bus 1308. The network interface 1312 is connected to a network 1314 such that the processor 1302 and the computer-readable storage medium 1304 can be connected to external components via the network 1314. The processor 1302 is configured to execute the computer program code 1306 encoded in the computer-readable storage medium 1304 to make the system 1300 available to perform part or all of the processes and / or methods. In one or more embodiments, the processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0196] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid state memories, magnetic tapes, removable computer disks, random access memories (RAMs), read-only memories (ROMs), rigid disks, and / or optical disks. In one or more embodiments using optical disks, the computer-readable storage medium 1304 includes compact disk read-only memories (CD-ROMs), compact disk read / write (CD-R / Ws), and / or digital video disks (DVDs).

[0197] In one or more embodiments, the storage medium 1304 stores computer program code 1306, which is configured to make the system 1300 (where such execution represents (at least in part) an EDA tool) available to perform some or all of the processes and / or methods described. In one or more embodiments, the storage medium 1304 also stores information that facilitates the performance of some or all of the processes and / or methods described. In one or more embodiments, the storage medium 1304 stores a standard cell library 1307 that includes the standard cells disclosed herein.

[0198] The EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to an external circuit. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for communicating information and commands to the processor 1302.

[0199] The EDA system 1300 also includes a network interface 1312 coupled to the processor 1302. The network interface 1312 allows the system 1300 to communicate with a network 1314 to which one or more other computer systems are connected. The network interface 1312 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods are implemented in two or more systems 1300.

[0200] The system 1300 is configured to receive information through the I / O interface 1310. The information received through the I / O interface 1310 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters for processing by the processor 1302. This information is transmitted to the processor 1302 via the bus 1308. The EDA system 1300 is configured to receive UI-related information through the I / O interface 1310. This information is stored as a user interface (UI) 1342 in the computer-readable storage medium 1304.

[0201] In some embodiments, part or all of the processes and / or methods are implemented as a stand-alone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in of a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 1300. In some embodiments, tools such as those available from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool are used to generate a layout diagram including standard cells.

[0202] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units such as optical discs (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROMs), RAMs, memory cards, etc.

[0203] Figure 14 is a block diagram of an integrated circuit (IC) manufacturing system 1400 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0204] In Figure 14 , the IC manufacturing system 1400 includes entities that interact in the design, development, and manufacturing cycle and / or services related to manufacturing the IC device 1460, such as a design house 1420, a mask house 1430, and an IC manufacturer / fabricator ("Fab") 1450. The entities in the system 1400 are connected by a communication network. In certain embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or fewer other entities. In some embodiments, two or more of the design house 1420, the mask house 1430, and the IC fabrication plant 1450 are owned by a single larger company. In some embodiments, two or more of the design house 1420, the mask house 1430, and the IC fabrication plant 1450 coexist in a common facility and use common resources.

[0205] The design house (or design team) 1420 generates an IC design layout 1422. The IC design layout 1422 includes various geometric patterns designed for the IC device 1460. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 1460 to be fabricated. The layers combine to form various IC features. For example, a portion of the IC design layout 1422 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal wires or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 1420 implements appropriate design procedures to form the IC design layout 1422. The design process includes one or more of logic design, physical design, or placement and routing operations. The IC design layout 1422 is presented in the form of one or more data files having geometric pattern information. For example, the IC design layout 1422 can be represented in the GDSII file format or the DFII file format.

[0206] The mask house 1430 includes data preparation 1432 and mask fabrication 1444. The mask house 1430 uses the IC design layout 1422 to fabricate one or more masks 1445 for use in fabricating the individual layers of the IC device 1460 according to the IC design layout 1422. The mask house 1430 performs mask data preparation 1432, in which the IC design layout 1422 is converted into a representative data file ("RDF"). The mask data preparation 1432 provides the RDF to the mask fabrication 1444. The mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1445 or a semiconductor wafer 1453. The design layout 1422 is manipulated by the mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 1450. In Figure 14 this, the mask data preparation 1432 and the mask fabrication 1444 are shown as separate elements. In some embodiments, the mask data preparation 1432 and the mask fabrication 1444 may be collectively referred to as mask data preparation.

[0207] In some embodiments, the mask data preparation 1432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 1422. In some embodiments, the mask data preparation 1432 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0208] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that uses a set of mask creation rules to inspect the IC design layout 1422 that has already been processed in OPC. The set of mask generation rules includes certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor manufacturing process and the like. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for the restrictions during mask fabrication 1444, which may undo some of the modifications performed by OPC to meet the mask creation rules.

[0209] In some embodiments, mask data preparation 1432 includes lithography process checking (LPC) that simulates the processes to be implemented by the IC foundry 1450 to fabricate the IC device 1460. The LPC simulates the processes based on the IC design layout 1422 to create a simulated fabricated device, such as the IC device 1460. The process parameters in the LPC simulation can include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used to fabricate the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the LPC creates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1422.

[0210] It should be understood that the above description of mask data preparation 1432 has been simplified for clarity. In some embodiments, data preparation 1432 includes additional features, such as a logic operation (LOP) that modifies the IC design layout 1422 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1422 during data preparation 1432 can be performed in various different orders.

[0211] After mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 is fabricated based on the modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithography exposures based on the IC design layout 1422. In some embodiments, based on the modified IC design layout 1422, a pattern is formed on the mask (photomask or reticle) 1445 using an electron beam (e-beam) or a mechanism of multiple electron beams. The mask 1445 can be formed using various techniques. In some embodiments, the mask 1445 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 1445 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1445 is formed using a phase-shift technique. In the phase-shift mask (PSM) version of the mask 1445, various features in the pattern formed on the phase-shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1444 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer 1453, in an etching process to form various etched regions in the semiconductor wafer 1453, and / or in other suitable processes.

[0212] IC foundry 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC foundry 1450 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) fabrication) for the interconnect and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0213] IC foundry 1450 includes manufacturing tools 1452 that are configured to perform various manufacturing operations on a semiconductor wafer 1453 to fabricate an IC device 1460 according to a mask (e.g., mask 1445). In various embodiments, the manufacturing tools 1452 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0214] IC manufacturer 1450 uses mask 1445 fabricated by mask chamber 1430 to fabricate IC device 1460. Thus, IC manufacturer 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC manufacturer 1450 using mask 1445 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 1453 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

[0215] In some embodiments, an integrated circuit (IC) device includes multiple rows of semiconductor devices. The multiple rows extend along a first axis and are arranged side by side along a second axis transverse to the first axis. The multiple rows include a first row having a first height along the second axis and a second row having a second height along the second axis. The second height is less than the first height. Each row of the multiple rows includes a first active region of a first conduction type and a second active region of a second conduction type different from the first conduction type. The second active region is spaced apart from the first active region along the second axis. Along the second axis, a first width of the first active region or the second active region in the first row is greater than a second width of the first active region or the second active region in the second row.

[0216] In some embodiments, the semiconductor device includes a gate-all-around (GAA) device.

[0217] In some embodiments, the multiple rows include a repeating pattern of a subset of the rows along the second axis, and the subset of the rows includes the first row and the second row.

[0218] In some embodiments, the subset of the rows includes at least one of the following: a first subset of the rows, each having a first height along the second axis, the first subset of the rows including the first row, or a second subset of the rows, each having a second height along the second axis, the second subset of the rows including the second row.

[0219] In some embodiments, in each of the first row and the second row, the spacing between the first active region and the second active region along the second axis is a predetermined minimum active region spacing.

[0220] In some embodiments, at least one of the following is satisfied: 1.2H ≤ H T ≤ 1.6H, 0.6H ≤ H S ≤ 0.8H, 1.2W ≤ W T ≤ 2W, 0.3W ≤ W S ≤ 0.8W, or 1.5 ≤ W T / W S≤2, where H is the unit height, H T is the first height, H S is the second height, W is the unit width, W T is the first width, and W S is the second width.

[0221] In some embodiments, H T +H S = 2H.

[0222] In some embodiments, the plurality of rows further includes a third row having a third height along a second axis, the third height being less than the first height and greater than the second height, and in the third row, the first active region or the second active region has a third width along the second axis, the third width being less than the first width and greater than the second width.

[0223] In some embodiments, the plurality of rows further includes a fourth row having a third height along a second axis, the first row and the second row are adjacent to each other and together form a first subset, the third row and the fourth row are adjacent to each other and together form a second subset, and along the second axis, the plurality of rows includes a repeating pattern of at least one of the first subset or the second subset.

[0224] In some embodiments, at least one of the following is satisfied: in the first row, the first active region or the second active region includes: a portion having a first width, and another portion having a reduced first width that is smaller than the first width, or in the second row, the first active region or the second active region includes: a portion having a second width, and another portion having a reduced second width that is smaller than the second width.

[0225] In some embodiments, at least one of the following is satisfied: 1.2H ≤ H T ≤ 1.6H, 0.6H ≤ H S ≤ 0.8H, 1.2W ≤ W T ≤ 2W, 0.3W ≤ W S ≤ 0.8W, 1.5 ≤ W T / W S ≤ 2, or 0.3W ≤ W SM ≤ 0.8W, where H is the unit height, H T is the first height, H S is the second height, W is the unit width, W T is the first width, W S is the second width, W SM is at least one of the reduced first width or the reduced second width.

[0226] In some embodiments, the plurality of rows further includes a third row, a first active region of the third row and a first active region of one of the first row and the second row are merged into a merged first active region, and the merged first active region is disposed along a second axis between a second active region of the third row and a second active region of one of the first row and the second row.

[0227] In some embodiments, the third row has the same height as one of the first row and the second row along the second axis.

[0228] In some embodiments, 1.2H ≤ H T ≤ 1.6H, 0.6H ≤ H S ≤ 0.8H, 1.2W ≤ W T ≤ 2W, 0.3W ≤ W S ≤ 0.8W, 1.5 ≤ W T / W S ≤ 2, and 1W ≤ W M ≤ 4W, where H is a unit height, H T is a first height, H S is a second height, W is a unit width, W T is a first width, W S is a second width, W M is the width of the merged first active region along the second axis.

[0229] In some embodiments, an integrated circuit (IC) layout is stored on a non-transitory computer-readable storage medium. The IC layout includes a first circuit region and a second circuit region. Each of the first circuit region and the second circuit region includes: a first cell having a first cell height along a cell height direction; a second cell having a second cell height along the cell height direction, the second cell height being less than the first cell height; an equivalent cell height corresponding to the first cell height, the second cell height, the number of rows of the first cell, and the number of rows of the second cell. The equivalent cell height of the first circuit region is different from the equivalent cell height of the second circuit region.

[0230] In some embodiments, the integrated circuit layout further includes: a third cell having a third cell height along the cell height direction, the third cell height being less than the first cell height and greater than the second cell height, where the third cell is included in at least one of: the first circuit region, the second circuit region, or a third circuit region of the integrated circuit layout, and all cells in the third circuit region are third cells.

[0231] In some embodiments, at least one of the following is satisfied. A first unit in at least one of the first circuit region or the second circuit region includes: a first unit having a first active region width along the unit height direction, the first active region width being greater than a third active region width, and another first unit having a reduced first active region width along the unit height direction, the reduced first active region width being less than the first active region width. A second unit in at least one of the first circuit region or the second circuit region includes: a second unit having a second active region width along the unit height direction, the second active region width being less than the third active region width, and another second unit having a reduced second active region width along the unit height direction, the reduced second active region width being less than the second active region width. Or a third unit in at least one of the first circuit region, the second circuit region, or the third circuit region includes: a third unit having a third active region width along the unit height direction, and another third unit having a reduced third active region width along the unit height direction, the reduced third active region width being less than the third active region width.

[0232] In some embodiments, the integrated circuit layout further includes a merged unit, where the merged unit includes two units, each of the two units being one of the first units, one of the second units, or one of the third units. The active regions of the two units are merged into a merged active region of the merged unit, and the unit height of the merged unit along the unit height direction is the sum of the unit heights of the two units along the unit height direction.

[0233] In some embodiments, a first unit among the first units includes: a first active region and a second active region having different conduction types and separated from each other along the unit height direction, an extended source / drain contact extending above the first active region and the second active region along the unit height direction and being electrically coupled to the first active region and the second active region, and in a metal layer that is the second closest to the first active region and the second active region among a plurality of metal layers of the integrated circuit layout, a conductive pattern extends above the extended source / drain contact along the unit height direction and is electrically coupled in parallel with the extended source / drain contact.

[0234] In some embodiments, a method for generating an integrated circuit layout for a circuit region is performed at least in part by a processor. The method includes: determining an equivalent cell height based on an application to be executed by the circuit region. The method further includes determining a cell row configuration based on the determined equivalent cell height, the cell row configuration including at least one first row of a first height and at least one second row of a second height different from the first height. The method further includes generating a cell array according to the determined cell row configuration. The method further includes performing a placement and routing operation to generate an integrated circuit layout for the circuit region. The placement and routing operation includes, based on the circuit region: placing one or more first cells of the first height in one or more first rows of the first height in the generated cell array, and placing one or more second cells of the second height in one or more second rows of the second height in the generated cell array.

[0235] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device comprising: a plurality of rows of semiconductor devices, the plurality of rows being elongated along a first axis and arranged side by side along a second axis transverse to the first axis, in, The plurality of rows include: a first row having a first height along the second axis, and a second row having a second height along the second axis, the second height being less than the first height, Each of the plurality of rows comprises: a first active region of a first conductivity type, and a second active region of a second conductivity type different from the first conductivity type, the second active region being spaced apart from the first active region along the second axis, and Along the second axis, a first width of the first active region or the second active region in the first row is greater than a second width of the first active region or the second active region in the second row.

2. The integrated circuit device according to claim 1, wherein: The plurality of rows comprises a repeating pattern of subsets of rows along the second axis, and The subset of rows includes the first row and the second row.

3. The integrated circuit device according to claim 2, wherein: The subset of rows includes at least one of: a first subset of rows, each having a first height along the second axis, the first subset of rows including the first row, or A second subset of rows each have a second height along the second axis, the second subset of rows including a second row.

4. The integrated circuit device according to claim 1, wherein: The plurality of rows further includes a third row having a third height along the second axis, the third height being less than the first height and greater than the second height, and In the third row, the first active region or the second active region has a third width along the second axis, the third width being smaller than the first width and larger than the second width.

5. The integrated circuit device according to claim 4, wherein: The plurality of rows further includes a fourth row having the third height along the second axis, The first row and the second row are adjacent to each other and together constitute a first subset, The third row and the fourth row are adjacent to each other and together constitute a second subset, and Along the second axis, the plurality of rows comprises a repeating pattern of at least one of the first subset or the second subset.

6. The integrated circuit device according to claim 1, wherein: Satisfy at least one of the following: In the first row, the first active region or the second active region includes: having a portion of said first width, and a further portion having a reduced first width, the reduced first width being less than the first width, or In the second row, the first active region or the second active region includes: having a portion of said second width, and A further portion has a reduced second width that is less than the second width.

7. The integrated circuit device according to claim 1, wherein: The plurality of rows also includes a third row, The first active region of the third row is merged with the first active region of one of the first row and the second row into a merged first active region, and The merged first active region is arranged along the second axis between the second active region of the third row and the second active region of the one of the first row and the second row.

8. An integrated circuit layout stored on a non-transitory computer readable storage medium, the integrated circuit layout comprising: First circuit area; as well as The second circuit area, in, Each of the first circuit area and the second circuit area includes: a first unit having a first unit height along a unit height direction, a second unit having a second unit height along the unit height direction, the second unit height being less than the first unit height, and an equivalent cell height corresponding to the first cell height, the second cell height, the number of rows of the first cell, and the number of rows of the second cell, and The equivalent cell height of the first circuit region is different from the equivalent cell height of the second circuit region.

9. The integrated circuit layout of claim 8, further comprising: a third unit having a third unit height along the unit height direction, wherein the third unit height is less than the first unit height and greater than the second unit height, Wherein, the third unit includes at least one of the following: the first circuit area, the second circuit area, or A third circuit region of the integrated circuit layout, wherein all cells in the third circuit region are the third cells.

10. A method of generating an integrated circuit layout for a circuit region, the method being performed at least in part by a processor and comprising: determining an equivalent cell height based on an application to be performed by the circuit area; determining a cell row configuration based on the determined equivalent cell heights, the cell row configuration comprising at least one first row having a first height and at least one second row having a second height different from the first height; generating a cell array according to the determined cell row configuration; as well as Performing a layout and routing operation to generate the integrated circuit layout for the circuit area, the layout and routing operation comprising performing the following operations based on the circuit area: placing one or more first cells having the first height in one or more first rows having the first height in the generated array of cells, and One or more second cells having the second height are placed in one or more second rows having the second height in the generated cell array.

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