Wafer-level infrared focal plane chip and manufacturing method thereof

Abstract

The invention provides a wafer-level infrared focal plane chip and a manufacturing method thereof, which are applied to the technical field of semiconductors, and the method comprises the steps: carrying out the low-temperature bonding of a detector wafer and a readout circuit wafer, forming a first heterogeneous integrated wafer, and forming a first electrode contact and a second electrode contact on the first surface of the readout circuit wafer; forming a first through hole and a second through hole which are arranged in an array on the surface of the detector wafer; etching the first region and the second region on the surface of the detector wafer to form a pixel mesa array and a common lower electrode region; a first electrode is formed on the pixel mesa array, a second electrode is formed on the common lower electrode area, and a target heterogeneous integrated wafer is obtained; the first electrode and the second electrode are used for enabling different layers in the detector wafer to form electric contact with the first electrode contact point and the second electrode contact point respectively; and scribing the target heterogeneous integrated wafer to obtain an infrared focal plane chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a wafer-level infrared focal plane chip and a manufacturing method thereof. Background Art

[0002] Infrared detectors are widely used in fields such as space communication, satellite remote sensing, night vision monitoring, medical diagnosis and treatment, and industrial inspection, and the requirements for the cost, volume, weight, and power consumption of semiconductor optoelectronic chips are becoming increasingly strict.

[0003] The traditional technical route for fabricating semiconductor optoelectronic chips is to separately process the infrared detector focal plane array and the silicon-based readout circuit to obtain a single detector chip and a readout circuit chip, and then bond the detector chip and the readout circuit chip through a flip-chip interconnection process to obtain an infrared focal plane optoelectronic chip, which has problems such as high operation difficulty, low production efficiency, and inability to quickly mass-produce. Summary of the Invention

[0004] (I) Technical Problems to be Solved

[0005] The present disclosure provides a wafer-level infrared focal plane chip and a manufacturing method thereof, which are used to at least partially solve one of the above technical problems.

[0006] (II) Technical Solutions

[0007] According to a first aspect of the present disclosure, there is provided a manufacturing method of a wafer-level infrared focal plane chip, including: performing low-temperature bonding on a detector wafer and a readout circuit wafer to form a first heterogeneous integrated wafer, wherein a bonding layer is formed between the detector wafer and the readout circuit wafer, and a first electrode contact and a second electrode contact are formed on a first surface of the readout circuit wafer in contact with the bonding layer; forming a first through hole and a second through hole arranged in an array on the surface of the detector wafer, and the first through hole and the second through hole penetrate the detector wafer and the bonding layer; etching a first region and a second region on the surface of the detector wafer to form a pixel mesa array and a common lower electrode region; respectively forming a first electrode on the pixel mesa array and a second electrode on the common lower electrode region to obtain a target heterogeneous integrated wafer; the first electrode and the second electrode are used to electrically connect different layers in the detector wafer to the first electrode contact point and the second electrode contact point respectively; dicing the target heterogeneous integrated wafer to obtain an infrared focal plane chip.

[0008] According to an embodiment of the present disclosure, the detector wafer sequentially includes a substrate, an etch stop layer, and an epitaxial layer, the epitaxial layer includes a first contact layer and a second contact layer, the first contact layer is in contact with the etch stop layer, and the second contact layer is in contact with the bonding layer; before forming the first through hole and the second through hole on the surface of the detector wafer where the epitaxial layer is in contact with the bonding layer, it further includes: removing the substrate and the etch stop layer of the detector wafer.

[0009] According to an embodiment of the present disclosure, forming first through-holes and second through-holes arranged in an array on the surface of a detector wafer includes: forming a patterned first mask layer on the surface of the epitaxial layer of the detector wafer, and the orthographic projections of the un-covered parts of the first mask layer coincide with the first electrode contact points and the second electrode contact points respectively; performing a first etching on the parts of the detector wafer and the bonding layer that are not covered by the first mask layer to form the first through-holes and the second through-holes, exposing partial areas of the first electrode contact points and the second electrode contact points.

[0010] According to an embodiment of the present disclosure, the method further includes: forming a first passivation layer on the sidewalls of the first through-holes, wherein the first passivation layer is in contact with partial areas of the surface of the epitaxial layer.

[0011] According to an embodiment of the present disclosure, etching a first area and a second area on the surface of the detector wafer to form a pixel mesa array and a common lower electrode area includes: forming a patterned second mask layer on the surface of the epitaxial layer of the detector wafer; performing a second etching on the first area and the second area on the surface of the detector wafer based on the second mask layer to form the pixel mesa array and the common lower electrode area, wherein the depth of the second etching is half of the distance from the surface of the detector wafer to the second contact layer.

[0012] According to an embodiment of the present disclosure, the method further includes: forming a second passivation layer on the sidewalls of the pixel mesa array; wherein the second passivation layer is in contact with partial areas of the surface of the epitaxial layer.

[0013] According to an embodiment of the present disclosure, forming a first electrode on the pixel mesa array and a second electrode on the common lower electrode area respectively includes: forming a patterned third mask layer on the surface of the epitaxial layer of the detector wafer, and the third mask layer is used to expose the sidewalls of the first through-holes, the first electrode contact points, partial first contact layers adjacent to the first through-holes, the sidewalls of the second through-holes, the second electrode contact points, and partial second contact layers adjacent to the second through-holes; forming a first electrode on the pixel mesa array and a second electrode on the common lower electrode area respectively, so that the first contact layer of the detector wafer is electrically connected to the first electrode contact points through the first through-holes, and the second contact layer is electrically connected to the second electrode contact points through the second through-holes.

[0014] According to an embodiment of the present disclosure, removing the substrate and the etch stop layer of the detector wafer includes: thinning the detector substrate to 50 μm - 100 μm by mechanical polishing; removing the thinned substrate and the etch stop layer based on a first chemical etchant and a second chemical etchant respectively to expose the epitaxial layer.

[0015] According to an embodiment of the present disclosure, a detector wafer and a readout circuit wafer are subjected to low-temperature bonding to form a heterogeneous integrated wafer, including: forming a first dielectric layer on the surface of the epitaxial layer of the detector wafer; forming a second dielectric layer on the surface of the readout circuit wafer including a first electrode contact and a second electrode contact; performing surface treatment on the first dielectric layer and the second dielectric layer; bonding the surface-treated first dielectric layer and the second dielectric layer to form a first heterogeneous integrated wafer; wherein, a bonding layer is formed after the low-temperature bonding of the first dielectric layer and the second dielectric layer.

[0016] According to a second aspect of the present disclosure, there is provided a wafer-level infrared focal plane chip, including: a detector wafer, which sequentially includes a first contact layer, a barrier layer, an absorption layer, and a second contact layer from top to bottom; a readout circuit wafer, on one side of the surface, including a first electrode contact and a second electrode contact; a bonding layer, disposed between the detector wafer and the readout circuit wafer, for bonding the detector wafer and the readout circuit wafer to form a first heterogeneous integrated wafer; a first electrode and a second electrode, the first electrode electrically connects the first contact layer and the first electrode contact, and the second electrode electrically connects the second contact layer and the second electrode contact; wherein, a pixel mesa array and a common lower electrode region are formed on the surface of the wafer-level infrared focal plane chip; the common lower electrode region is disposed around the pixel mesa array, a first through hole is provided at the center of the pixel mesa, a second through hole is provided at the center of the common lower electrode region, the first through hole and the second through hole penetrate the detector wafer and the bonding layer, the orthographic projection of the first through hole on the readout circuit wafer coincides with the first electrode contact, and the orthographic projection of the second through hole on the readout circuit wafer coincides with the second electrode contact; a first passivation layer is provided on the side wall of the first through hole, and a second passivation layer is provided on the side wall of the pixel mesa array; the first electrode starts from the part of the first contact layer not covered by the first passivation layer, extends through the first passivation layer to the bottom of the first through hole and covers the first electrode contact exposed in the first through hole; the second electrode starts from a part of the surface of the second contact layer, extends through the side wall of the second through hole to the bottom of the second through hole and covers the second electrode contact exposed in the second through hole.

[0017] (III) Beneficial Effects

[0018] The wafer-level infrared focal plane chip and its manufacturing method provided by the present disclosure at least include the following beneficial effects:

[0019] First, low-temperature wafer bonding of the detector wafer and the readout circuit wafer is performed to achieve heterogeneous integration, then a pixel mesa array is formed, and finally dicing and packaging are carried out. Thus, wafer-level mass production of the infrared focal plane array chip is effectively realized, the complexity and cost of the process are reduced, and the production efficiency is improved. Brief Description of the Drawings

[0020] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0021] Figure 1 Schematically shows a flowchart of a method for fabricating a wafer-level infrared focal plane chip according to an embodiment of the present disclosure;

[0022] Figures 2A to 2E Schematically shows a cross-sectional schematic diagram of a wafer-level infrared focal plane chip during fabrication according to an embodiment of the present disclosure;

[0023] Figure 3 Schematically shows a flowchart of low-temperature bonding of a detector wafer and a readout circuit wafer to form a heterogeneous integrated wafer according to an embodiment of the present disclosure;

[0024] Figure 4 Schematically shows a flowchart of removing the substrate and the etch stop layer of the detector wafer in the heterogeneous integrated wafer according to an embodiment of the present disclosure;

[0025] Figure 5 Schematically shows a flowchart of forming a first via hole and a second via hole arranged in an array on the surface of the detector wafer according to an embodiment of the present disclosure;

[0026] Figure 6 Schematically shows a flowchart of etching a first region and a second region on the surface of the detector wafer to form a pixel mesa array and a common lower electrode region according to an embodiment of the present disclosure;

[0027] Figure 7 Schematically shows a flowchart of forming a first electrode on the pixel mesa array and a second electrode on the common lower electrode region respectively according to an embodiment of the present disclosure;

[0028] Figure 8 Schematically shows a cross-sectional view of an infrared focal plane chip according to an embodiment of the present disclosure.

[0029]

Reference Numerals

[0030] 1 - Detector wafer; 2 - Readout circuit wafer; 31 - Bonding layer; 11 - Substrate; 12 - Etch stop layer; 13 - Epitaxial layer; 131 - First contact layer; 132 - Barrier layer; 133 - Absorption layer; 134 - Second contact layer; 141 - First via hole; 142 - Second via hole; 151 - First passivation layer; 152 - Second passivation layer; 161 - First region; 162 - Second region; 17 - Pixel mesa array; 18 - Common lower electrode region; 181 - First electrode; 182 - Second electrode; 21 - Readout circuit substrate; 221 - First electrode contact; 222 - Second electrode contact; 311 - First dielectric layer; 312 - Second dielectric layer. Detailed Embodiments

[0031] To make the objectives, technical solutions and advantages of the present disclosure more comprehensible, the following provides a further detailed description of the present disclosure with reference to specific embodiments and the accompanying drawings. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0032] The terms used herein are merely for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The terms such as "including" and "comprising" used herein indicate the presence of the described features, steps, operations, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

[0033] In the present disclosure, unless otherwise clearly defined and limited, the terms such as "mounted", "connected", "coupled", and "fixed" shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral one; it may be a mechanical connection, an electrical connection, or a connection capable of mutual communication; it may be a direct connection, or an indirect connection through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure may be understood according to specific circumstances.

[0034] In the description of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms such as "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inner", and "outer" are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the subsystems or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0035] Throughout the drawings, the same elements are denoted by the same or similar reference numerals. When it may cause confusion in the understanding of the present disclosure, the conventional structures or configurations will be omitted. Also, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships. Additionally, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claims.

[0036] Similarly, to streamline the present disclosure and assist in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. Descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0038] Embodiments of the present disclosure provide a wafer-level infrared focal plane chip and a manufacturing method thereof. Before introducing the technical solutions provided by the embodiments of the present disclosure, the related technologies involved in the present disclosure will be described first.

[0039] Infrared detectors are widely used in many fields, and currently, many new application scenarios of infrared detection systems are high-mobility platforms. Therefore, more stringent requirements are also imposed on semiconductor optoelectronic chips, such as lower cost, smaller volume, weight, power consumption, etc.

[0040] The inventors found during the research process that since the preparation route of traditional semiconductor optoelectronic chips is: separately processing the infrared detector focal plane array and the silicon-based readout circuit, after preparing patterned indium pillar arrays on the surfaces of the infrared detector wafer and the readout circuit wafer respectively, dicing to obtain individual detector chips and readout circuit chips, and obtaining an infrared focal plane optoelectronic chip through processes such as flip-chip interconnection, underfill, and substrate thinning. This results in problems such as relatively high operation difficulty in the preparation of optoelectronic chips, inability to quickly mass-produce, low production efficiency, and high process costs.

[0041] Specifically, the existing process requires the preparation of patterned indium column arrays on the surfaces of the infrared detector wafer and the readout circuit wafer, respectively. When flip-chip interconnection is performed, the indium column array on the surface of the detector chip needs to be finely aligned with the indium column array on the surface of the readout circuit chip. When filling the bottom with glue, the proportion of epoxy resin glue and the filling environment need to be accurately adjusted to allow the epoxy resin glue to fully flow and fill between the indium column arrays, resulting in a relatively difficult process. The existing technology requires first dicing the wafer into a single detector chip and a readout circuit chip, and then performing back-end processes on the detector chip and the readout circuit chip separately, resulting in low preparation efficiency of semiconductor optoelectronic chips and difficulty in mass production. In addition, metal indium is relatively expensive. The negative photoresist stripping process used in the existing process for preparing the indium column array will lose a large amount of metal indium, resulting in a high process cost.

[0042] The disclosed embodiment provides a method for manufacturing a wafer-level infrared focal plane chip, comprising: performing low-temperature bonding on a detector wafer and a readout circuit wafer to form a heterogeneous integrated wafer, wherein a bonding layer is formed between the detector wafer and the readout circuit wafer, and a first electrode contact and a second electrode contact are formed on a first surface of the readout circuit wafer in contact with the bonding layer; forming a first through hole and a second through hole arranged in an array on the surface of the detector wafer, the first through hole and the second through hole penetrating the detector wafer and the bonding layer; etching a first area and a second area on the surface of the detector wafer to form a pixel table array and a common lower electrode area; forming a first electrode on the pixel table array, and forming a second electrode on the common lower electrode area; the first electrode and the second electrode are used to make different layers in the detector wafer form electrical contact with the first electrode contact point and the second electrode contact point, respectively; and dicing the heterogeneous integrated wafer to obtain an infrared focal plane chip.

[0043] Figure 1 The flowchart of the method for manufacturing a wafer-level infrared focal plane chip according to an embodiment of the present disclosure is schematically shown.

[0044] Figures 2A to 2E The cross-sectional view of a wafer-level infrared focal plane chip during the manufacturing process according to an embodiment of the present disclosure is schematically shown.

[0045] like Figure 1 As shown, the method for manufacturing a wafer-level infrared focal plane chip of this embodiment includes operations S110 to S150. Figures 2A to 2E The manufacturing method of the wafer-level infrared focal plane chip of this embodiment is further introduced.

[0046] In operation S110, the detector wafer and the readout circuit wafer are low temperature bonded to form a first heterogeneous integrated wafer; wherein a bonding layer is formed between the detector wafer and the readout circuit wafer, and a first electrode contact and a second electrode contact are formed on a first surface of the readout circuit wafer in contact with the bonding layer.

[0047] In some embodiments, the detector wafer includes a substrate 11, an etch stop layer 12 disposed on the surface of the substrate 11, and an epitaxial layer 13 disposed on the surface of the etch stop layer. Among them, the epitaxial layer sequentially includes a first contact layer 131, a barrier layer 132, an absorption layer 133, and a second contact layer 134, and the first contact layer 131 is disposed on the surface of the etch stop layer 12. Optionally, the detector wafer 1 may include, for example, a Group-IV detector wafer, a Group-III-V detector wafer, a Group-II-VI detector wafer, etc. The material structures of the first contact layer 131, the barrier layer 132, the absorption layer 133, and the second contact layer 134 in the epitaxial layer 3 can be designed according to the material of the detector substrate 11 and the requirements of the target detection wavelength band, and the present disclosure does not limit this here.

[0048] In some embodiments, the readout circuit wafer 2 includes a readout circuit substrate 21, and a first electrode contact 221 and a second electrode contact 222 are disposed on the surface of the readout circuit substrate 21. Optionally, the readout circuit 2 may include, for example, a Group-IV detector wafer, etc.

[0049] In the specific implementation process, as Figure 2A shown, a first dielectric layer 311 is deposited on the surface of the second contact layer 134, a second dielectric layer 312 is deposited on the surface of the readout circuit wafer where the first electrode contact and the second electrode contact are disposed, the flipped detector wafer is aligned with the readout circuit wafer so that the first dielectric layer 311 and the second dielectric layer 112 are in contact with each other, and the first dielectric layer and the second dielectric layer are bonded by van der Waals forces through pressurization. The bonded wafers are placed in a bonding device, heated and pressurized to form a tight covalent bond between the first dielectric layer 311 and the second dielectric layer 312, obtaining a first hetero-integrated wafer, where the hetero-integrated wafer includes a bonding layer 31.

[0050] In some embodiments, the detector substrate 11 may be an N-type GaSb substrate in the (001) direction; the etch stop layer 12 may be InAs 0.91 Sb 0.09 lattice-matched to the GaSb substrate, with a thickness of 1 μm; the materials of the first contact layer 131 and the second contact layer 134 may be InAs 0.91 Sb 0.09 , an InAs / GaSb superlattice, or an InAs / InAsSb superlattice, with a thickness of 0.5 μm, the material of the barrier layer 132 may be AlAs 0.08 Sb 0.92 , an InAs / GaSb / AlSb / GaSb superlattice, or an AlAsSb / InAsSb superlattice, with a thickness of 0.2 μm; the material of the absorption layer 133 may be InAs 0.91 Sb 0.09, The InAs / GaSb superlattice, or the InAs / InAsSb superlattice, has a thickness of 2 μm. The doping polarities of the first contact layer 131 and the second contact layer 134 are opposite, that is, the first contact layer 131 is N-type doped and the second contact layer 134 is P-type doped, or the first contact layer 131 is P-type doped and the second contact layer 134 is N-type doped. The etch stop layer 12, the barrier layer 132, and the absorption layer 133 are unintentionally doped layers.

[0051] Operation S120: Form a first through hole and a second through hole arranged in an array on the surface of the detector wafer. The first through hole and the second through hole penetrate the detector wafer and the bonding layer.

[0052] In some embodiments, before performing operation S120, first remove the substrate 11 and the etch stop layer 12 of the detector wafer 1 in the heterogeneous integrated wafer, as Figure 2B shown. After removing the substrate 11 and the etch stop layer 12 of the detector wafer 1 in the heterogeneous integrated wafer, the upper surface of the heterogeneous integrated wafer is the first contact layer.

[0053] As Figure 2C shown, etch a specified area on the surface of the first contact layer to form a first through hole 141 and a second through hole 142 arranged in an array, where the first through hole 141 and the second through hole 142 penetrate the epitaxial layer 13 and the bonding layer 31, exposing partial areas of the first electrode contact and the second electrode contact.

[0054] In some embodiments, after forming the first through hole 141, form a first passivation layer 151 on the sidewall of the first through hole, where the first passivation layer 151 is in contact with a partial area on the surface of the first contact layer 131.

[0055] Operation S130: Etch the first area and the second area on the surface of the detector wafer to form a pixel mesa array and a common lower electrode area.

[0056] In some embodiments, refer to Figure 2D , etch the first area 161 and the second area 162 on the surface of the detector wafer to form a pixel mesa array 17 and a common lower electrode area. Among them, the first area 161 is arranged in an array on the detector wafer and is used to isolate the pixel mesa array 17, and the second area 162 is arranged around the pixel mesa array 17.

[0057] Operation S140: Form a first electrode on the pixel mesa array and a second electrode on the common lower electrode area to obtain the target heterogeneous integrated wafer; the first electrode and the second electrode are used to make different layers in the detector wafer form electrical contacts with the first electrode contact point and the second electrode contact point respectively.

[0058] In some embodiments, refer toFigure 2E A first electrode 181 is formed at a first through-hole 141 in each pixel mesa, and a second electrode 182 is formed at a second through-hole in each common lower electrode region.

[0059] The first electrode 181 starts from a portion of the first contact layer 131 that is not covered by the first passivation layer 151, extends through the first passivation layer 151 to the bottom of the first through-hole 141, and covers the first electrode contact 221 exposed in the first through-hole, thereby realizing the electrical connection between the first contact layer 131 and the first electrode contact 221.

[0060] The second electrode 181 starts from a partial surface of the second contact layer 134, extends through the sidewall of the second through-hole 142 to the bottom of the second through-hole 142, and covers the second electrode contact 222 exposed in the second through-hole.

[0061] Optionally, the materials of the first electrode 181 and the second electrode 182 can be metals, for example, a titanium-platinum-gold metal electrode (Ti / Pt / Au electrode). Among them, titanium (Ti) can enhance the adhesion between the metal electrode and the detector epitaxial layer 13, platinum (Pt) can prevent gold (Au) from diffusing into Ti and the detector epitaxial layer 13, and Au can achieve electrical connection.

[0062] In operation S150, the target heterogeneous integrated wafer is diced to obtain an infrared focal plane chip.

[0063] In some embodiments, the target heterogeneous integrated wafer formed by the detector wafer 1 and the readout circuit wafer 2 is diced to obtain a single infrared focal plane chip.

[0064] Figure 3 Schematically shows a flowchart of low-temperature bonding of a detector wafer and a readout circuit wafer to form a heterogeneous integrated wafer according to an embodiment of the present disclosure.

[0065] The method for fabricating a wafer-level infrared focal plane provided by the embodiments of the present disclosure first performs low-temperature wafer bonding on the detector wafer and the readout circuit wafer to achieve heterogeneous integration, then forms a pixel mesa array, and finally dices and packages. It can effectively improve the alignment accuracy, avoid the error superposition of multiple independent alignments in the existing process, thereby effectively realizing the wafer-level batch production of infrared focal plane array chips, reducing the process complexity and cost, and improving the production efficiency.

[0066] As Figure 3 shown, the low-temperature bonding of the detector wafer and the readout circuit wafer in this embodiment to form a heterogeneous integrated wafer includes operations S111 to S114.

[0067] In operation S111, a first dielectric layer is formed on the surface of the detector wafer epitaxial layer.

[0068] In some embodiments, a plasma enhanced chemical vapor deposition method or an atomic layer deposition method may be used to form a first dielectric layer 311 on the surface of the second contact layer 134 of the detector wafer 1.

[0069] In operation S112, a second dielectric layer is formed on the surface of the readout circuit wafer including the first electrode contact and the second electrode contact.

[0070] In some embodiments, a plasma enhanced chemical vapor deposition method or an atomic layer deposition method is used to form a second dielectric layer 312 on the surface of the readout circuit wafer 2 provided with the first electrode contact 221 and the second electrode contact 222, and a chemical mechanical planarization process is performed on the second dielectric layer 312 to make the surface of the second dielectric layer 312 flat and smooth.

[0071] In operation S113, surface treatment is performed on the first dielectric layer and the second dielectric layer.

[0072] In some embodiments, the materials of the first dielectric layer 311 and the second dielectric layer 312 may be silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3).

[0073] Performing surface treatment on the first dielectric layer 311 and the second dielectric layer 312 may include, for example, wet cleaning treatment and plasma activation treatment. Among them, the wet cleaning treatment is used to remove the residual contaminants on the surfaces of the first dielectric layer and the second dielectric layer, and the plasma activation treatment is used to break the chemical bonds on the surfaces of the first dielectric layer and the second dielectric layer to generate a large number of dangling bonds.

[0074] In operation S114, the surface-treated first dielectric layer and the second dielectric layer are bonded to form a heterogeneous integrated wafer.

[0075] In some embodiments, the detector wafer 1 and the readout circuit wafer 2 are aligned so that the first dielectric layer 311 and the second dielectric layer 312 are in contact, and pressure is applied to make the first dielectric layer and the second dielectric layer adhere through van der Waals forces. The bonded wafers are placed in a bonding device, heated and pressurized to form strong covalent bonds between the first dielectric layer 311 and the second dielectric layer 312, obtaining a bonding layer 31 and forming a heterogeneous integrated wafer.

[0076] Figure 4 A flowchart showing the removal of the substrate and the etch stop layer of the detector wafer in the heterogeneous integrated wafer according to an embodiment of the present disclosure is schematically shown.

[0077] As Figure 4 shown, removing the substrate and the etch stop layer of the detector wafer in the heterogeneous integrated wafer of this embodiment includes operation S410 to operation S420.

[0078] In operation S410, the detector substrate is thinned to 50 μm to 100 μm by mechanical grinding and polishing.

[0079] In operation S420, the thinned substrate and the etch stop layer are removed based on a first chemical etchant and a second chemical etchant respectively to expose the epitaxial layer.

[0080] In some embodiments, the substrate 11 of the detector wafer is completely removed using the first chemical etchant to expose the etch stop layer 12. Optionally, the first chemical etchant may be a solution of chromium trioxide (CrO3): hydrogen fluoride (HF): water (H2O) with a ratio of 10:1:20 to selectively etch the detector substrate 11 without etching the etch stop layer 12.

[0081] In some embodiments, the etch stop layer is completely removed using the second chemical etchant. Optionally, the second chemical etchant may be a solution of citric acid (C6H8O7): hydrogen peroxide (H2O2): water (H2O) with a ratio of 2:1:20 to selectively etch the etch stop layer 12 without etching the first contact layer 131.

[0082] Figure 5 A flowchart showing the formation of an array of first through-holes and second through-holes on the surface of a detector wafer according to an embodiment of the present disclosure is schematically shown.

[0083] As Figure 5 shown, the formation of an array of first through-holes and second through-holes on the surface of the detector wafer in this embodiment includes operations S121 to S122.

[0084] In operation S121, a patterned first mask layer is formed on the surface of the epitaxial layer of the detector wafer, and the orthographic projections of the unmasked parts of the first mask layer coincide with the first electrode contact point and the second electrode contact point respectively.

[0085] In some embodiments, the first mask layer is deposited on the first contact layer 131 by plasma enhanced chemical vapor deposition, and the first mask layer is etched to form a via pattern by ultraviolet lithography and reactive ion etching. Among them, the orthographic projections of the unmasked parts of the first mask layer coincide with the first electrode contact 221 and the second electrode contact 222 respectively. Optionally, the material of the first mask layer may be SiO2 or Si x N y 。

[0086] In operation S122, a first etching is performed on the parts of the detector wafer and the bonding layer that are not covered by the first mask layer to form a first through-hole and a second through-hole, exposing partial regions of the first electrode contact point and the second electrode contact point.

[0087] The first etching includes etching the epitaxial layer 13 of the detector wafer and etching the bonding layer 31.

[0088] In some embodiments, inductively coupled plasma etching can be used to etch the detector epitaxial layer 13 until the bottom of the second contact layer 134 is reached to expose the bonding layer 31. Then, reactive ion etching is used to continue etching the exposed bonding layer 31 until the bottom of the bonding layer 31 is reached to form a first through hole and a second through hole, exposing partial regions of the first electrode contact 221 and the second electrode contact 222.

[0089] After the etching of the first through hole and the second through hole is completed, the first mask layer on the surface of the epitaxial layer is removed, and a first passivation layer 151 is formed on the sidewall of the first through hole.

[0090] In some embodiments, reactive ion etching can be used to remove the first mask layer on the surface of the epitaxial layer.

[0091] Forming the first passivation layer on the sidewall of the first through hole includes: depositing the first passivation layer 151 on partial regions of the surface of the epitaxial layer by plasma enhanced chemical vapor deposition or atomic layer deposition, and etching the first passivation layer 151 by ultraviolet lithography and reactive ion etching to form an opening pattern. Among them, the first passivation layer 151 covers the sidewall of the first through hole and part of the first contact layer 131, and does not cover the sidewall of the second through hole, the surfaces of the first electrode contact 221 and the second electrode contact 222. Optionally, the material of the first passivation layer 151 can be any one or a combination of several materials such as SiO2, Si x N y , silicon oxynitride (SiON), Al2O3, zinc sulfide (ZnS), photoresist, epoxy resin, etc.

[0092] Figure 6 Schematically shows a flowchart of etching the first region and the second region on the surface of the detector wafer to form a pixel mesa array and a common lower electrode region according to an embodiment of the present disclosure.

[0093] As Figure 6 shown, etching the first region and the second region on the surface of the detector wafer in this embodiment to form a pixel mesa array and a common lower electrode region includes operations S131 to S132.

[0094] In operation S131, a patterned second mask layer is formed on the surface of the epitaxial layer of the detector wafer.

[0095] In some embodiments, a second mask layer is deposited on the epitaxial layer by plasma enhanced chemical vapor deposition, and the second mask layer is etched by ultraviolet lithography and reactive ion etching to form a mesa pattern.

[0096] Among them, the second mask layer covers the pixel mesa array 17 and does not cover the first region 161 and the second region 162. The material of the second mask layer can be SiO2 or Si x N y .

[0097] In operation S132, a second etching is performed on the first region and the second region of the detector wafer surface based on the second mask layer to form a pixel mesa array and a common lower electrode region, wherein the second etching depth is half of the distance from the detector wafer surface to the second contact layer.

[0098] In some embodiments, the second etching includes etching the first region and the second region. The inductively coupled plasma etching method can be used to etch the first region 161 and the second region 162 to half of the depth of the second contact layer 134. The first region 161 and the second region 162 are formed in an array. Among them, the part isolated by the first region 161 is the pixel mesa array 17, and the second region 162 is disposed around the pixel mesa array 17. When etching the second region 162, the epitaxial layer portion above the middle of the second contact layer in the second region is completely etched away to form a common lower electrode region. Optionally, the gas that can be used during the second etching can be a mixed gas of chlorine gas (Cl2), boron trichloride gas (BCl3), and argon gas (Ar).

[0099] After the second etching is completed, the second mask layer on the epitaxial layer surface is removed by reactive ion etching, and a second passivation layer 152 is formed on the sidewall of the pixel mesa array.

[0100] In some embodiments, the second passivation layer 152 is deposited on a partial region of the epitaxial layer surface by plasma enhanced chemical vapor deposition or atomic layer deposition, and the second passivation layer 152 is etched by ultraviolet lithography and reactive ion etching to form an opening pattern, so that the second passivation layer 152 covers the sidewall of the pixel mesa array 17 and a part of the first contact layer 131. Among them, the material of the second passivation layer 152 can be any one or a combination of several materials such as SiO2, Si x N y , SiON, Al2O3, ZnS, photoresist, epoxy resin, etc.

[0101] Figure 7 Schematically shows a flowchart of forming a first electrode on a pixel mesa array and a second electrode on a common lower electrode region according to an embodiment of the present disclosure.

[0102] As Figure 7 shown, forming a first electrode on a pixel mesa array and a second electrode on a common lower electrode region in this embodiment includes operations S141 to S142.

[0103] In operation S141, a patterned third mask layer is formed on the surface of the epitaxial layer of the detector wafer. The third mask layer is used to expose the sidewalls of the first through-holes, the first electrode contacts, and a portion of the first contact layer adjacent to the first through-holes, the sidewalls of the second through-holes, the second electrode contacts, and a portion of the second contact layer adjacent to the second through-holes.

[0104] In operation S142, a first electrode is formed on the pixel mesa array respectively, and a second electrode is formed on the common lower electrode region. The first contact layer of the detector wafer is electrically connected to the first electrode contact through the first through-hole, and the second contact layer is electrically connected to the second electrode contact through the second through-hole.

[0105] In some embodiments, based on the patterned third mask layer, the first electrode 181 and the second electrode 182 are formed by using a negative photoresist lithography, electron beam evaporation, and lift-off process. For the formation and removal of the third mask, please refer to Figure 5 、 Figure 6 the relevant content in the embodiments, which will not be elaborated here.

[0106] The formed first electrode 181 is located near the first through-hole 141 at the center of the pixel mesa array 17. Starting from the portion of the first contact layer 131 not covered by the first passivation layer 151, it extends through the first passivation layer 151 to the bottom of the first through-hole 141 and covers the first electrode contact 221, realizing the electrical connection between the first contact layer 131 and the first electrode contact 221.

[0107] The formed second electrode 182 is located near the second through-hole 142 in the second etching region 152. Starting from the surface of the second contact layer 134, it extends through the sidewall of the second through-hole 142 to the bottom of the second through-hole 142 and covers the second electrode contact 222. The materials of the first electrode 181 and the second electrode 182 can be metals. For example, they can be Ti / Pt / Au. Ti enhances the adhesion of the metal electrode to the detector epitaxial layer 13, Pt prevents the diffusion of Au to Ti and the detector epitaxial layer 13, and Au realizes the electrical connection.

[0108] Based on the above manufacturing method of the wafer-level infrared focal plane chip, the present disclosure also provides a wafer-level infrared focal plane chip. The following will be combined with Figure 8 to describe this wafer-level infrared focal plane chip in detail.

[0109] Figure 8 A cross-sectional view of an infrared focal plane chip according to an embodiment of the present disclosure is schematically shown.

[0110] As Figure 8As shown, the infrared focal plane chip includes a detector wafer, a readout circuit wafer, a bonding layer, a first electrode, and a second electrode. The infrared focal plane chip is obtained by slicing a target heterogeneous integrated wafer based on the manufacturing method of a wafer-level infrared focal plane chip.

[0111] The detector wafer sequentially includes a first contact layer 131, a barrier layer 132, an absorption layer 133, and a second contact layer 134 from top to bottom.

[0112] The readout circuit wafer includes a readout circuit substrate, and a first electrode contact 121 and a second electrode contact 122 are provided in the area where the readout circuit substrate is in contact with the bonding layer.

[0113] The bonding layer 31 is disposed between the detector wafer and the readout circuit wafer and is used to bond the detector wafer and the readout circuit wafer to form a first heterogeneous integrated wafer;

[0114] The first electrode 181 and the second electrode 182. The first electrode 181 electrically connects the first contact layer 131 and the first electrode contact 121, and the second electrode 182 electrically connects the second contact layer 134 and the second electrode contact 122.

[0115] In some embodiments, a pixel mesa array and a common lower electrode region are formed on the surface of the infrared focal plane chip. The common lower electrode region is disposed around the pixel mesa array. A first through hole is provided at the center of the pixel mesa, and a second through hole is provided at the center of the common lower electrode region. The first through hole and the second through hole penetrate the detector wafer and the bonding layer. The orthographic projection of the first through hole on the readout circuit wafer coincides with the first electrode contact, and the orthographic projection of the second through hole on the readout circuit wafer coincides with the second electrode contact.

[0116] Wherein, a first passivation layer is provided on the sidewall of the first through hole, and a second passivation layer is provided on the sidewall of the pixel mesa array. The first electrode 181 starts from the part of the first contact layer 131 not covered by the first passivation layer 151, extends through the first passivation layer 151 to the bottom of the first through hole 141 and covers the first electrode contact 221 exposed in the first through hole, realizing the electrical connection between the first contact layer 131 and the first electrode contact 221. The second electrode 181 starts from a part of the surface of the second contact layer 134, extends through the sidewall of the second through hole 142 to the bottom of the second through hole 142 and covers the second electrode contact 222 exposed in the second through hole.

[0117] Optionally, the detector wafer can be, for example, a Group-IV detector wafer, a Group-III-V detector wafer, a Group-II-VI detector wafer, etc. Among them, the material structures of the first contact layer 131, the barrier layer 132, the absorption layer 133, and the second contact layer 134 are all designed according to the material of the detector substrate 11 and the requirements of the target detection wavelength band.

[0118] Optionally, the materials of the first contact layer 131 and the second contact layer 134 can be InAs 0.91 Sb 0.09 , InAs / GaSb superlattice or InAs / InAsSb superlattice, and the thickness can be 0.5 μm. The material of the barrier layer 132 can be AlAs 0.08 Sb 0.92 , InAs / GaSb / AlSb / GaSb superlattice or AlAsSb / InAsSb superlattice, and the thickness is 0.2 μm. The material of the absorption layer 133 can be InAs 0.91 Sb 0.09 , InAs / GaSb superlattice or InAs / InAsSb superlattice, and the thickness is 2 μm. Among them, the doping polarities of the first contact layer 131 and the second contact layer 134 are opposite, that is, the first contact layer 131 is N-type doped and the second contact layer 134 is P-type doped, or the first contact layer 131 is P-type doped and the second contact layer 134 is N-type doped. The etch stop layer 12, the barrier layer 132, and the absorption layer 133 are all unintentionally doped layers.

[0119] A plurality of pixel mesa arrays are provided on the detector wafer 1, and each pixel mesa array includes pixel mesas 17 arranged in an array. Two adjacent pixels in the same array are isolated by a first region 161, and a common lower electrode region is provided around the pixel mesa array.

[0120] A first through hole 141 is provided at the center of each pixel mesa 17, and a second through hole 142 is provided in the common lower electrode region. The first through hole 141 and the second through hole 142 penetrate the detector wafer 1 and the bonding layer 31. The first electrode contacts 221 on the readout circuit wafer 2 correspond to the pixel mesas 17 one by one through the first through holes 141, and the second electrode contacts 222 correspond to the common lower electrode region one by one through the second through holes 142.

[0121] The excess materials in the first region 161 and the second region 162 are removed by etching to form the pixel mesas 17 and the common lower electrode region. The excess materials in the regions of the first through hole 141 and the second through hole 142 are removed from the epitaxial layer 13 and the bonding layer 31 by etching to form the first through hole 141 and the second through hole 142. When etching to remove the epitaxial materials in the first region 161 and the second region 162, the etching depth reaches half of the second contact layer 134, so that the pixel mesa 17 includes part of the first contact layer 131, the barrier layer 132, the absorption layer 133, and the second contact layer 134, and the common lower electrode region includes part of the second contact layer 134. When etching to remove the materials in the regions of the first through hole 141 and the second through hole 142, the etching depth penetrates the detector epitaxial layer 13 and the bonding layer 31, exposing partial regions of the first electrode contacts 221 and partial regions of the second electrode contacts 222 on the readout circuit wafer 2.

[0122] The side wall and the top part area of the pixel mesa 17 are covered with a first passivation layer 151 to electrically isolate two adjacent pixel mesas 17. The side wall of the first through hole 141 is covered with a second passivation layer 152 to electrically isolate the first electrode 181 from the detector epitaxial layer 13 other than the first contact layer 131.

[0123] According to an embodiment of the present invention, the materials of the first passivation layer 151 and the second passivation layer 152 can be one or a combination of several materials such as SiO2, Si x N y , SiON, Al2O3, ZnS, photoresist, epoxy resin and the like.

[0124] A first electrode 181 is provided on the pixel mesa 17, and a second electrode 182 is provided in the common lower electrode area. The first electrode 181 starts from the part of the first contact layer 131 of the pixel mesa 17 that is not covered by the first passivation layer 151, extends through the first passivation layer 151 to the bottom of the first through hole 141, and covers the first electrode contact 221 of the readout circuit wafer 2, realizing the electrical connection between the first contact layer 131 and the first electrode contact 221. The second electrode 182 starts from the second contact layer 134 in the common lower electrode area, extends through the side wall of the second through hole 142 to the bottom of the second through hole 142, and covers the second electrode contact 222 of the readout circuit wafer 2, realizing the electrical connection between the second contact layer 134 and the second electrode contact 222.

[0125] According to an embodiment of the present invention, the materials of the first electrode 181 and the second electrode 182 are metals. For example, they can be Ti / Pt / Au. Ti enhances the adhesion of the metal electrode to the detector epitaxial layer 13, Pt prevents Au from diffusing into Ti and the detector epitaxial layer 13, and Au realizes the electrical connection.

[0126] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should be included within the protection scope of the present disclosure.

Claims

1. A method for manufacturing a wafer-level infrared focal plane chip, characterized in that: The method comprises: Performing low temperature bonding on the detector wafer and the readout circuit wafer to form a first heterogeneous integrated wafer, wherein a bonding layer is formed between the detector wafer and the readout circuit wafer, and a first electrode contact and a second electrode contact are formed on a first surface of the readout circuit wafer in contact with the bonding layer; Forming a first through hole and a second through hole arranged in an array on the surface of the detector wafer, wherein the first through hole and the second through hole penetrate the detector wafer and the bonding layer; Etching the first area and the second area on the surface of the detector wafer to form a pixel table array and a common lower electrode area; Forming a first electrode on the pixel table array and a second electrode on the common lower electrode region respectively, to obtain a target heterogeneous integrated wafer; the first electrode and the second electrode are used to make different layers in the detector wafer form electrical contacts with the first electrode contact point and the second electrode contact point respectively; The target heterogeneous integrated wafer is diced to obtain an infrared focal plane chip.

2. The method for manufacturing a wafer-level infrared focal plane chip according to claim 1, characterized in that: The detector wafer comprises a substrate, an etching stop layer, and an epitaxial layer in sequence, wherein the epitaxial layer comprises a first contact layer and a second contact layer, wherein the first contact layer contacts the etching stop layer, and the second contact layer contacts the bonding layer; The epitaxial layer contacts the bonding layer, and before forming the first through hole and the second through hole on the surface of the detector wafer, the method further includes: The substrate and the etch stop layer of the detector wafer are removed.

3. The method for manufacturing a wafer-level infrared focal plane chip according to claim 2, characterized in that: The first through holes and the second through holes arranged in an array on the surface of the detector wafer include: forming a patterned first mask layer on the surface of the epitaxial layer of the detector wafer, wherein the orthographic projections of the uncovered portions of the first mask layer coincide with the first electrode contact points and the second electrode contact points respectively; A first etching is performed on the detector wafer and the bonding layer that are not covered by the first mask layer to form the first through hole and the second through hole, exposing a partial area of ​​the first electrode contact point and a partial area of ​​the second electrode contact point.

4. The method for manufacturing a wafer-level infrared focal plane chip according to claim 3, characterized in that: The method further comprises: A first passivation layer is formed on the sidewall of the first through hole, wherein the first passivation layer is in contact with a partial area of ​​the surface of the epitaxial layer.

5. The method for manufacturing a wafer-level infrared focal plane chip according to claim 2, characterized in that: The etching of the first area and the second area on the surface of the detector wafer to form a pixel table array and a common lower electrode area includes: forming a patterned second mask layer on the surface of the epitaxial layer of the detector wafer; Based on the second mask layer, the first area and the second area on the surface of the detector wafer are subjected to a second etching to form a pixel table array and a common lower electrode area, wherein the second etching depth is half of the distance from the surface of the detector wafer to the second contact layer.

6. The method for manufacturing a wafer-level infrared focal plane chip according to claim 2, characterized in that: The method further comprises: A second passivation layer is formed on the sidewalls of the pixel mesa array; wherein the second passivation layer is in contact with a partial area of ​​the surface of the epitaxial layer.

7. The method for manufacturing a wafer-level infrared focal plane chip according to claim 2, characterized in that: The forming of the first electrode on the pixel mesa array and the forming of the second electrode on the common lower electrode region respectively comprises: A patterned third mask layer is formed on the surface of the epitaxial layer of the detector wafer, wherein the third mask layer is used to expose the sidewall of the first through hole, the first electrode contact, a portion of the first contact layer adjacent to the first through hole, the sidewall of the second through hole, the second electrode contact, and a portion of the second contact layer adjacent to the second through hole; A first electrode is formed on the pixel table array, and a second electrode is formed on the common lower electrode region, so that the first contact layer of the detector wafer is electrically connected to the first electrode contact through the first through hole, and the second contact layer is electrically connected to the second electrode contact through the second through hole.

8. The method for manufacturing a wafer-level infrared focal plane chip according to claim 2, characterized in that: The removing the substrate and the etching stop layer of the detector wafer comprises: The detector substrate is thinned to 50 μm to 100 μm by mechanical grinding and polishing; The thinned substrate and the etching stop layer are removed based on a first chemical etching solution and a second chemical etching solution respectively to expose the epitaxial layer.

9. The method for manufacturing a wafer-level infrared focal plane chip according to claim 1, characterized in that: The method of low temperature bonding the detector wafer and the readout circuit wafer to form a heterogeneous integrated wafer comprises: Forming a first dielectric layer on the surface of the epitaxial layer of the detector wafer; forming a second dielectric layer on a surface of the readout circuit wafer including a first electrode contact and a second electrode contact; performing surface treatment on the first dielectric layer and the second dielectric layer; Bonding the surface-treated first dielectric layer to the second dielectric layer to form a first heterogeneous integrated wafer; The first dielectric layer and the second dielectric layer are bonded at low temperature to form the bonding layer.

10. A wafer-level infrared focal plane chip, made based on the manufacturing method according to any one of claims 1 to 9, characterized in that: include: The detector wafer includes, from top to bottom, a first contact layer, a barrier layer, an absorption layer, and a second contact layer; A readout circuit wafer, a surface side of which includes a first electrode contact and a second electrode contact; A bonding layer, disposed between the detector wafer and the readout circuit wafer, and used for bonding the detector wafer and the readout circuit wafer to form a heterogeneous integrated wafer; a first electrode and a second electrode, wherein the first electrode electrically connects the first contact layer to the first electrode contact, and the second electrode electrically connects the second contact layer to the second electrode contact; Wherein, a pixel table array and a common lower electrode area are formed on the surface of the wafer-level infrared focal plane chip; the common lower electrode area is arranged around the pixel table array, a first through hole is arranged at the center of the pixel table, and a second through hole is arranged at the center of the common lower electrode area, the first through hole and the second through hole penetrate the detector wafer and the bonding layer, the orthographic projection of the first through hole on the readout circuit wafer coincides with the first electrode contact, and the orthographic projection of the second through hole on the readout circuit wafer coincides with the second electrode contact; A first passivation layer is disposed on the sidewall of the first through hole, and a second passivation layer is disposed on the sidewall of the pixel mesa array; The first electrode starts from the portion of the first contact layer not covered by the first passivation layer, extends through the first passivation layer to the bottom of the first through hole and covers the first electrode contact exposed in the first through hole; The second electrode starts from a portion of the surface of the second contact layer, extends through the sidewall of the second through hole to the bottom of the second through hole and covers the second electrode contact exposed in the second through hole.

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