Display substrate

Abstract

The invention discloses a display substrate. The display substrate comprises a substrate, and a first electrode, a second electrode, a plurality of rows of first wires and a plurality of columns of second wires which are arranged on the substrate, the second electrode comprises a plurality of second electrode parts (PZ1, PZ2 and PZ3) which are arranged in an array; the orthographic projection of the second electrode and the orthographic projection of the first wiring area (AG1) on the substrate are mutually independent; the orthographic projection of the first electrode and the orthographic projection of the first wiring area (AG1) on the substrate are overlapped; the first electrode of at least one pixel region has an opening structure; along the second direction (Y), the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first wire arranged on the first side of the opening structure on the substrate is a first distance (L1), and the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first wire arranged on the second side of the opening structure on the substrate is a second distance (L2). The formation of an edge electric field of the grid line and the common electrode is avoided, so that the phenomenon of light leakage caused by liquid crystal deflection is improved.

Description

Display substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate. Background Art

[0002] In the related art, the output of small and medium-sized NBs (notebook computers) and car display screens has been steadily increasing, the technical specifications have been gradually tightened, and the demand for in-cell (embedded) touch has been gradually increasing. In the existing TDDI (display and display driver integration) products, the number of source drivers is large, and the price of source drivers is high, resulting in the high cost of current TDDI products. Based on this, a display substrate can be provided, in which the pixel electrodes are placed horizontally, that is, the extension direction of the pixel electrodes is roughly the same as the extension direction of the gate lines. In this way, the number of gate lines used is three times that of the relevant display products, and the number of data lines used is 1 / 3 of the relevant display products. While ensuring that the resolution of the display product remains unchanged, the number of data lines used is greatly reduced, thereby reducing the number of source drivers used and reducing costs. At the same time, by designing the appropriate position of the touch signal line and the touch signal line connection vias, the common electrodes are separated, so that different touch signal lines are connected to the corresponding common electrode blocks, thereby integrating the touch function. However, for the traditional oxide multi-gate structure, in order to achieve the touch function, in the related technology, the common electrode is divided into blocks in the traditional way, and an opening structure is set above the gate line, which will form a fringe electric field between the gate line and the common electrode, causing the liquid crystal to deflect and produce L0 light leakage, thereby requiring a wider BM (black matrix) for shielding, resulting in a reduction in the pixel aperture ratio.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a base, and a first electrode, a second electrode, a plurality of rows of first routing wires, and a plurality of columns of second routing wires disposed on the base; the first routing wires and the second routing wires intersect to define a plurality of pixel regions, each of the pixel regions being provided with at least one sub-pixel, the sub-pixel comprising the first electrode and the second electrode; the first routing wire is located in the first routing region, and the second routing wire is located in the second routing region;

[0005] The first electrode is located between the substrate and the second electrode; the second electrode includes a plurality of second electrode portions arranged in an array, and the second electrode portions are located in the corresponding pixel areas; the orthographic projections of the second electrode and the first wiring area on the substrate are independent of each other; the orthographic projections of the first electrode and the first wiring area on the substrate overlap;

[0006] The first electrode of at least one of the pixel regions has an opening structure, and the opening structure extends along a first direction, and the first direction is parallel to an extension direction of the first wiring;

[0007] Along the second direction, the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first trace disposed on the first side of the opening structure on the substrate is a first distance, and the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first trace disposed on the second side of the opening structure on the substrate is a second distance.

[0008] The first side and the second side are opposite to each other; the first direction intersects with the second direction.

[0009] Optionally, the first distance is smaller than the second distance, and a ratio between the first distance and the second distance is greater than or equal to 0.25 and less than or equal to 0.5.

[0010] Optionally, an orthographic projection of the opening structure on the substrate at least partially overlaps with an orthographic projection of the second electrode on the substrate.

[0011] Optionally, an orthographic projection of the opening structure on the substrate does not overlap with an orthographic projection of the second electrode on the substrate.

[0012] Optionally, an orthographic projection of the opening structure on the substrate partially overlaps with an orthographic projection of at least one second electrode portion of the second electrode on the substrate.

[0013] Optionally, along the first direction, the length of the opening structure is less than or equal to the length of the second electrode portion.

[0014] Optionally, the M second electrode portions are included in the same pixel; the M second electrode portions are arranged in the same pixel area;

[0015] M is an integer greater than or equal to 3;

[0016] In the same pixel area, m opening structures are provided;

[0017] m is a positive integer, and m is less than or equal to M.

[0018] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0019] In the same pixel area, a first opening structure, a second opening structure and a third opening structure are provided;

[0020] The first opening structure is disposed in the first sub-pixel region, the second opening structure is disposed in the second sub-pixel region, and the third opening structure is disposed in the third sub-pixel region.

[0021] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0022] In the same pixel area, a first opening structure and a second opening structure are provided;

[0023] The first opening structure is disposed in the first sub-pixel region, and the second opening structure is disposed in the second sub-pixel region.

[0024] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0025] In the same pixel area, a first opening structure and a second opening structure are provided;

[0026] The first opening structure is disposed in the first sub-pixel region, and the second opening structure is disposed in the third sub-pixel region.

[0027] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0028] In the same pixel area, a first opening structure and a second opening structure are provided;

[0029] The first opening structure is disposed in the second sub-pixel region, and the second opening structure is disposed in the third sub-pixel region.

[0030] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0031] In the same pixel area, a first opening structure is provided;

[0032] The first opening structure is disposed in the first sub-pixel region, the second sub-pixel region or the third sub-pixel region.

[0033] Optionally, the second electrode portion includes a plurality of second electrode portions extending along the first direction; the second electrode portions are arranged along the second direction;

[0034] A length of the second electrode portion along the second direction is greater than or equal to 1.8 μm and less than or equal to 3.5 μm.

[0035] Optionally, a distance between two adjacent second electrode portions included in the second electrode portion in the second direction is greater than or equal to 2.3 μm and less than or equal to 6 μm.

[0036] Optionally, an extension direction of the second electrode portion is substantially the same as an extension direction of the first trace.

[0037] Optionally, a column of third wiring is provided between two adjacent columns of second electrode portions in the second direction; the first electrode includes a plurality of mutually independent first electrode portions arranged in an array;

[0038] The third wiring is electrically connected to the first electrode portion.

[0039] Optionally, a column of second wiring is provided between two adjacent columns of second electrode portions in the second direction;

[0040] The second routing line and the third routing line are adjacent to each other.

[0041] Optionally, along the first direction, the width of the third routing line is less than or equal to the width of the second routing line;

[0042] A distance between two adjacent columns of second electrode portions in the first direction is greater than or equal to 3 μm and less than or equal to 6 μm.

[0043] Optionally, along the first direction, the width of the third routing line is greater than the width of the second routing line.

[0044] Optionally, the display substrate includes a pixel array, a display area, and a peripheral area; the pixel array includes the sub-pixels;

[0045] The pixel array is arranged in the display area, and the display substrate further includes virtual sub-pixels arranged in the peripheral area;

[0046] The virtual sub-pixel is arranged adjacent to the display area;

[0047] The length of at least some of the virtual sub-pixels along the first direction is smaller than the length of the sub-pixels along the first direction.

[0048] Optionally, the first trace includes a first end and a second end;

[0049] The display substrate further comprises a plurality of electrostatic discharge blocks disposed on the base, wherein the electrostatic discharge blocks are conductive blocks;

[0050] The electrostatic discharge block is electrically connected to the first end or the second end of the first trace.

[0051] Optionally, the electrostatic discharge block and the first trace are provided in the same layer and made of the same material.

[0052] Optionally, a length of the electrostatic discharge block along the second direction is greater than a line width of the first trace. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a layout diagram of a plurality of second electrode portions in at least one embodiment of the present disclosure;

[0054] FIG2 is a layout diagram of a plurality of first traces in at least one embodiment of the present disclosure;

[0055] FIG3 is a layout diagram of a plurality of second electrode portions in at least one embodiment of the present disclosure;

[0056] 4A is a schematic diagram showing how the light efficiency of a pixel structure varies with the length of the opening structure of the first electrode along the first direction in at least one embodiment of the present disclosure;

[0057] FIG4B is a light effect diagram when W is equal to 3.8 μm;

[0058] FIG4C is a light effect diagram when W is equal to 6.8 μm;

[0059] FIG4D is a light effect diagram when W is equal to 9.8 μm;

[0060] FIG5 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0061] FIG6 is a layout diagram of the gate metal layer in FIG5 ;

[0062] FIG7 is a layout diagram of the source / drain metal layer in FIG5 ;

[0063] FIG8 is a layout diagram of the common electrode layer in FIG5 ;

[0064] FIG9 is a layout diagram of the pixel electrode layer in FIG5 ;

[0065] FIG10 is a stacked diagram of the gate metal layer, active layer, common electrode layer and source / drain metal layer in FIG5 ;

[0066] FIG11 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0067] FIG12A is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0068] FIG12B is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0069] FIG12C is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0070] FIG12D is a cross-sectional view of AA′ in FIG12C;

[0071] FIG12E is a light effect diagram when W is equal to 3.8 μm;

[0072] FIG12F is a schematic diagram showing the relationship between light efficiency and the width W of the opening structure;

[0073] FIG12G is a light effect diagram when W is equal to 6.8 μm;

[0074] FIG12H is a light effect diagram when W is equal to 9.8 μm;

[0075] FIG12I is a schematic diagram showing the relationship between light efficiency and the width W1 of the second electrode portion;

[0076] FIG12J is a light effect diagram when the width W1 of the second electrode portion is 1.8 μm;

[0077] FIG12K is a light effect diagram when the width W1 of the second electrode portion is 3 μm;

[0078] FIG12L is a preparation flow chart in at least one embodiment of the present disclosure;

[0079] FIG13 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0080] FIG14 is a layout diagram of the gate metal layer in FIG13;

[0081] FIG15 is a layout diagram of the source / drain metal layer in FIG13 ;

[0082] FIG16 is a layout diagram of the common electrode layer in FIG13;

[0083] FIG17 is a layout diagram of the pixel electrode layer in FIG13;

[0084] FIG18A is a layout diagram showing a virtual sub-pixel region in the upper left corner of a display substrate;

[0085] FIG18B is a layout diagram showing a virtual sub-pixel region in the upper left corner of a substrate;

[0086] FIG18C is a layout diagram of the gate metal layer in FIG18A;

[0087] FIG18D is a layout diagram of the second electrode layer in FIG18A;

[0088] FIG18E is a layout diagram of the first electrode layer in FIG18A ;

[0089] FIG18F is a layout diagram of the source / drain metal layer in FIG18A ;

[0090] FIG19A is a layout diagram of a portion of a dummy sub-pixel region included in a display substrate;

[0091] FIG19B is a layout diagram showing a portion of a dummy sub-pixel region included in a display substrate;

[0092] FIG19C is a layout diagram of the gate metal layer in FIG19A;

[0093] FIG19D is a layout diagram of the second electrode layer in FIG19A;

[0094] FIG19E is a layout diagram of the first electrode layer in FIG19A ;

[0095] FIG19F is a layout diagram of the source / drain metal layer in FIG19A . DETAILED DESCRIPTION

[0096] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0097] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0098] As used in this disclosure, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 10% of either one.

[0099] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0100] The present disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0101] In the present disclosure, circles, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0102] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0103] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0104] The display substrate of the embodiment of the present disclosure includes a substrate, and a first electrode, a second electrode, a plurality of rows of first wirings, and a plurality of columns of second wirings arranged on the substrate;

[0105] The first wiring and the second wiring intersect each other to define a plurality of pixel regions, each of the pixel regions is provided with at least one sub-pixel, and the sub-pixel includes the first electrode and the second electrode;

[0106] The first routing line is located in a first routing area, and the second routing line is located in a second routing area;

[0107] The first electrode is located between the substrate and the second electrode; the second electrode includes a plurality of second electrode portions arranged in an array, and the second electrode portions are located in the corresponding pixel areas; the orthographic projections of the second electrode and the first wiring area on the substrate are independent of each other; and the orthographic projections of the first electrode and the first wiring area on the substrate overlap;

[0108] The first electrode in at least one of the pixel regions has an opening structure, the opening structure extends along a first direction, and the first direction is parallel to an extending direction of the first wiring;

[0109] Along the second direction, the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first trace disposed on the first side of the opening structure on the substrate is a first distance, and the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first trace disposed on the second side of the opening structure on the substrate is a second distance.

[0110] The first side and the second side are opposite to each other; the first direction intersects with the second direction.

[0111] In at least one embodiment of the present disclosure, the first direction may be a horizontal direction, or the first direction may be approximately the same as the horizontal direction;

[0112] The second direction may be a vertical direction.

[0113] For example, the first side may be the upper side, and the second side may be the lower side; or, the first side may be the lower side, and the second side may be the upper side; or, taking a first routing line corresponding to a pixel area as a reference, the first side is the side of the opening structure close to the first routing line, and the second side is the side of the opening structure away from the first routing line, but is not limited to this.

[0114] Optionally, the second direction may be a longitudinal direction, and the first direction may be substantially parallel to the direction in which the gate lines extend.

[0115] In at least one embodiment of the present disclosure, the first electrode may be a common electrode, the second electrode may be a pixel electrode; the first wiring may be a gate line, the second wiring may be a data line, or the first wiring may be a data line, the second wiring may be a gate line; the third wiring may be a touch signal line.

[0116] In at least one embodiment of the present disclosure, the sub-pixel including the first electrode and the second electrode may refer to: the sub-pixel including a portion of the electrode included in the first electrode and a portion of the electrode included in the second electrode.

[0117] In the related art, for the traditional oxide multi-gate structure, in order to achieve the touch function, in the related art, the common electrode is divided into blocks in the traditional way, and an opening structure is set above the gate line, which will form a fringe electric field between the gate line and the common electrode, causing the liquid crystal to deflect and produce L0 light leakage, thereby requiring a wider BM (black matrix) for blocking, resulting in a reduction in the pixel aperture ratio.

[0118] In order to solve the above problems, the display substrate described in at least one embodiment of the present disclosure sets the orthographic projection of the opening structure of the first electrode on the substrate so as not to overlap with the orthographic projection of the first wiring on the substrate, so as to avoid the formation of a fringe electric field between the first wiring (the first wiring can be a gate line) and the first electrode (the first electrode can be a common electrode), thereby improving the phenomenon of L0 light leakage caused by liquid crystal deflection.

[0119] Optionally, the first distance is smaller than the second distance, and a ratio between the first distance and the second distance is greater than or equal to 0.25 and less than or equal to 0.5.

[0120] In at least one embodiment of the present disclosure, the aperture ratio can be improved by setting the ratio range between the first distance and the second distance to be greater than or equal to 0.25 and less than or equal to 0.5, that is, setting the distance between the opening structure and the first routing line arranged on its first side to be smaller than the distance between the opening structure and the second routing line arranged on its second side.

[0121] In at least one embodiment of the present disclosure, the first electrode includes a plurality of mutually independent first electrode portions arranged in an array, each first electrode portion can cover multiple rows and columns of pixel areas, and each pixel area can be provided with a sub-pixel. A split opening structure extending along the first direction separates the first electrode portions adjacent in the vertical direction, while a common electrode pattern between two adjacent first electrode portions in the horizontal direction is excavated to separate the two columns of first electrode portions. However, for process consistency, at least one opening structure extending along the first direction can also be provided within each first electrode portion, but the lateral width of the opening structure is narrower and does not separate the first electrode portions.

[0122] In the related art, the output of small and medium-sized NBs (laptop computers) and car display screens has been steadily increasing, the technical specifications have been gradually tightened, and the demand for in-cell touch has been gradually increasing. In the existing TDDI (touch and display driver integration) products, the number of source drivers is large, and the price of source drivers is high, resulting in the high cost of current TDDI products. Based on this, a display substrate can be provided, in which the pixel electrodes are placed horizontally, that is, the extension direction of the pixel electrodes is roughly the same as the extension direction of the gate lines. In this way, the number of gate lines used is three times that of the relevant display products, and the number of data lines used is 1 / 3 of the relevant display products. While ensuring that the resolution of the display product remains unchanged, the number of data lines used is greatly reduced, thereby reducing the number of source drivers used and reducing costs. At the same time, by designing the appropriate position of the touch signal line and the touch signal line connection vias, the common electrodes are separated, so that different touch signal lines are connected to the corresponding common electrode blocks, thereby integrating the touch function.

[0123] FIG1 is a layout diagram of a plurality of second electrode portions in at least one embodiment of the present disclosure;

[0124] In FIG1 , the first second electrode portion is labeled PZ1 , the second second electrode portion is labeled PZ2 , and the third second electrode portion is labeled PZ3 .

[0125] FIG2 is a layout diagram of a plurality of first routing lines in at least one embodiment of the present disclosure. Optionally, the first routing lines may be gate lines.

[0126] In FIG2 , the first gate line is labeled G1, the second gate line is labeled G2, the third gate line is labeled G3, and the fourth gate line is labeled G4;

[0127] G1 is disposed in the first routing area AG1 , G2 is disposed in the second routing area AG2 , G3 is disposed in the third routing area AG3 , and G4 is disposed in the fourth routing area AG4 .

[0128] Optionally, the first wiring may be a gate line; and the second electrode portion may include a plurality of second electrode portions extending along the first direction.

[0129] As shown in FIG3 , based on at least one embodiment of the plurality of second electrode portions shown in FIG1 , the first pixel electrode of the second second electrode portion PZ2 is labeled P21, the second pixel electrode of the second second electrode portion PZ2 is labeled P22, the third pixel electrode of the second second electrode portion PZ2 is labeled P23, the fourth pixel electrode of the second second electrode portion PZ2 is labeled P24, and the fifth pixel electrode of the second second electrode portion PZ2 is labeled P25;

[0130] P21 , P22 , P23 , P24 and P25 all extend along the first direction.

[0131] Optionally, the second electrode may be a pixel electrode.

[0132] In the drawings of the present disclosure, the direction labeled X is the first direction, the direction labeled Y is the second direction, and the direction labeled Z is the third direction;

[0133] The first direction X may be a horizontal direction, the second direction Y may be a vertical direction, and the third direction Z may be a direction perpendicular to the substrate.

[0134] In at least one embodiment of the present disclosure, an orthographic projection of the opening structure on the substrate at least partially overlaps with an orthographic projection of the second electrode on the substrate.

[0135] In a specific implementation, the orthographic projection of the opening structure on the substrate can at least partially overlap with the orthographic projection of the second electrode on the substrate, that is, at least one second electrode portion included in the second electrode portion can be provided above the opening structure, so that there is no interference from the gate line electric field under L0, and no light leakage occurs. Under the grayscale L255, there is no weak area due to the existence of the fringe electric field between the opening structure and the second electrode portion, and the transmittance will be increased by about 10% compared with the traditional design, thereby improving the competitiveness of the display product.

[0136] In actual operation, the orthographic projection of the opening structure on the substrate may at least partially overlap with the orthographic projection of the second electrode on the substrate, but the present invention is not limited thereto.

[0137] In at least one embodiment of the present disclosure, an orthographic projection of the opening structure on the substrate does not overlap with an orthographic projection of at least one second electrode portion of the second electrode on the substrate.

[0138] In a specific implementation, the second electrode portion may not be provided above the opening structure. The electric field in the hollow area of ​​the second electrode layer is very weak, forming a weak area, which is the same as the single gate TDDI design. The third wiring is set in the display area to block the transmission of part of the light.

[0139] In at least one embodiment of the present disclosure, the third trace may be a touch signal line.

[0140] In a specific implementation, an orthographic projection of the opening structure on the substrate partially overlaps with an orthographic projection of at least one second electrode portion of the second electrode on the substrate.

[0141] In at least one embodiment of the present disclosure, when the orthographic projection of the opening structure on the substrate partially overlaps with the orthographic projection of at least one second electrode portion in the second electrode on the substrate, the length of the opening structure along the first direction can be less than or equal to the length of the second electrode portion, so that in the first direction, the opening structure can be completely covered by the second electrode portion.

[0142] Optionally, a length of the opening structure along the first direction is less than or equal to 5.6 μm.

[0143] In at least one embodiment of the present disclosure, a schematic diagram showing how the light effect of a pixel structure varies with the length of the opening structure along the first direction is shown in FIG4 .

[0144] As shown in Figure 4A, when the length W of the opening structure along the first direction is less than or equal to 5.6 μm, the light efficiency does not change much as the length W increases. However, when the length W exceeds 5.6 μm, the light efficiency decreases significantly as W increases, resulting in dimming of horizontal stripes in the image quality. Based on this consideration, W can be reasonably designed to take into account process feasibility.

[0145] FIG4B is a light effect diagram when W is equal to 3.8 μm; FIG4C is a light effect diagram when W is equal to 6.8 μm; and FIG4D is a light effect diagram when W is equal to 9.8 μm.

[0146] In at least one embodiment of the present disclosure, M second electrode portions are included in the same pixel; M second electrode portions are disposed in the same pixel region; M is an integer greater than or equal to 3;

[0147] In the same pixel area, m opening structures are provided;

[0148] m is a positive integer, and m is less than or equal to M.

[0149] In a specific implementation, the pixel may include at least three second electrode portions, and the at least three second electrode portions may be arranged in the same pixel area. A number m of opening structures may be arranged in the pixel area, where m is less than or equal to M.

[0150] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0151] In the same pixel area, a first opening structure, a second opening structure and a third opening structure are provided;

[0152] The first opening structure is disposed in the first sub-pixel region, the second opening structure is disposed in the second sub-pixel region, and the third opening structure is disposed in the third sub-pixel region.

[0153] In a specific implementation, the pixel may include a first second electrode portion, a second second electrode portion and a third second electrode portion. Three opening structures may be provided in the same pixel region, and each opening structure is provided corresponding to a sub-pixel region.

[0154] In at least one embodiment of the present disclosure, the first wiring may be a gate line, the second wiring may be a data line, the third wiring may be a touch signal line, the first electrode may be a common electrode, and the second electrode may be a pixel electrode.

[0155] As shown in FIG5 , the first row of gate lines is labeled G1, the second row of gate lines is labeled G2, the third row of gate lines is labeled G3, the fourth row of gate lines is labeled G4, the first column of touch signal lines is labeled TX1, the second column of touch signal lines is labeled TX2, the first column of data lines is labeled DL1, and the second column of data lines is labeled DL2;

[0156] The first sub-pixel region is labeled P1, the second sub-pixel region is labeled P2, and the third sub-pixel region is labeled P3; P1, P2, and P3 are arranged along the vertical direction.

[0157] 6 is a layout diagram of the gate metal layer in FIG5 , FIG7 is a layout diagram of the source and drain metal layer in FIG5 , FIG8 is a layout diagram of the common electrode layer in FIG5 , and FIG9 is a layout diagram of the pixel electrode layer in FIG5 .

[0158] In at least one embodiment shown in FIG. 5 , the gate metal layer, the active layer, the source / drain metal layer, the common electrode layer, and the pixel electrode layer are sequentially arranged in a direction away from the substrate.

[0159] In FIG. 10 , only the gate metal layer, the active layer, the common electrode layer, and the source / drain metal layer in FIG. 5 are shown.

[0160] In FIG6 , the first row of grid lines is labeled G1, the second row of grid lines is labeled G2, the third row of grid lines is labeled G3, and the fourth row of grid lines is labeled G4;

[0161] In FIG7 , the line labeled TX1 is the first column of touch signal lines, the line labeled TX2 is the second column of touch signal lines, the line labeled DL1 is the first column of data lines, and the line labeled DL2 is the second column of data lines;

[0162] In FIG8 , the common electrode block is labeled VM, the first opening structure is labeled X1, the second opening structure is labeled X2, and the third opening structure is labeled X3.

[0163] In FIG9 , the first pixel electrode included in the first second electrode portion is labeled P11, the second pixel electrode included in the first second electrode portion is labeled P12, the third pixel electrode included in the first second electrode portion is labeled P13, the fourth pixel electrode included in the first second electrode portion is labeled P14, and the fifth pixel electrode included in the first second electrode portion is labeled P15.

[0164] The first pixel electrode labeled P21 is included in the second second electrode portion, the first pixel electrode labeled P22 is included in the second second electrode portion, the third pixel electrode labeled P23 is included in the second second electrode portion, the fourth pixel electrode labeled P24 is included in the second second electrode portion, and the fifth pixel electrode labeled P25 is included in the second second electrode portion;

[0165] The first pixel electrode labeled P31 is included in the third second electrode portion, the first pixel electrode labeled P32 is included in the third second electrode portion, the third pixel electrode labeled P33 is included in the third second electrode portion, the fourth pixel electrode labeled P34 is included in the third second electrode portion, and the fifth pixel electrode labeled P35 is included in the third second electrode portion.

[0166] As shown in FIG5 to FIG10 , the orthographic projection of the first opening structure X1 on the substrate at least partially overlaps with the orthographic projection of P11 on the substrate;

[0167] The orthographic projection of the second opening structure X2 on the substrate at least partially overlaps with the orthographic projection of P21 on the substrate;

[0168] The orthographic projection of the third opening decoupling strand X3 on the substrate at least partially overlaps with the orthographic projection of P31 on the substrate;

[0169] X1 is set in the first sub-pixel area, X2 is set in the second sub-pixel area, and X3 is set in the third sub-pixel area;

[0170] TX1 and DL1 are adjacently arranged on the left side of each second electrode portion, and TX2 and DL2 are adjacently arranged on the right side of each second electrode portion.

[0171] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0172] In the same pixel area, a first opening structure and a second opening structure are provided;

[0173] The first opening structure is disposed in the first sub-pixel region, and the second opening structure is disposed in the second sub-pixel region.

[0174] In a specific implementation, two opening structures may be provided in one pixel region, wherein the first opening structure is provided in the first sub-pixel region, and the second opening structure is provided in the second sub-pixel region.

[0175] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0176] In the same pixel area, a first opening structure and a second opening structure are provided;

[0177] The first opening structure is disposed in the first sub-pixel region, and the second opening structure is disposed in the third sub-pixel region.

[0178] In a specific implementation, two opening structures may be provided in one pixel region, wherein the first opening structure is provided in the first sub-pixel region, and the second opening structure is provided in the third sub-pixel region.

[0179] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0180] In the same pixel area, a first opening structure and a second opening structure are provided;

[0181] The first opening structure is disposed in the second sub-pixel region, and the second opening structure is disposed in the third sub-pixel region.

[0182] In a specific implementation, two opening structures may be provided in one pixel region, wherein the first opening structure is provided in the second sub-pixel region, and the second opening structure is provided in the third sub-pixel region.

[0183] Optionally, the same pixel includes a first second electrode portion, a second second electrode portion, and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region;

[0184] In the same pixel area, a first opening structure is provided;

[0185] The first opening structure is disposed in the first sub-pixel region, the second sub-pixel region or the third sub-pixel region.

[0186] In a specific implementation, an opening structure may be provided in a pixel region. The opening structure may be provided in the first sub-pixel region, the second sub-pixel region or the third sub-pixel region.

[0187] As shown in FIG11 , the first opening structure X1 is provided in the first sub-pixel region P1;

[0188] In FIG11 , the second sub-pixel region is labeled P2 , and the third sub-pixel region is labeled P3 .

[0189] As shown in FIG12A , the first opening structure X1 is disposed in the first sub-pixel region P1 ; the second opening structure is disposed in the second sub-pixel region P2 ;

[0190] In FIG. 12A , the second sub-pixel region is labeled P2 .

[0191] As shown in FIG12B , the distance between the orthographic projection of the first opening structure X1 on the substrate and the orthographic projection of the first gate line G1 on the substrate is a first distance L1;

[0192] The distance between the orthographic projection of the first opening structure X1 on the substrate and the orthographic projection of the second gate line G2 on the substrate is a second distance L2;

[0193] The ratio between L2 and L1 is greater than or equal to 0.25 and less than or equal to 0.5. For example, the ratio between L2 and L1 may be approximately 0.3.

[0194] In FIG12C , the first pixel electrode labeled P11 is included in the first second electrode portion, the second pixel electrode labeled P12 is included in the first second electrode portion, the third pixel electrode labeled P13 is included in the first second electrode portion, the fourth pixel electrode labeled P14 is included in the first second electrode portion, and the fifth pixel electrode labeled P15 is included in the first second electrode portion;

[0195] A first opening structure is provided below P14.

[0196] FIG12D is a cross-sectional view taken along line AA′ in FIG12C .

[0197] In FIG12D , X1 is a first opening structure, 121 is a first first electrode pattern included in the first electrode, and 122 is a second first electrode pattern included in the first electrode;

[0198] The width of the orthographic projection of X1 on the substrate in the horizontal direction is a first width L01, and L01 may be 5 μm;

[0199] The distance between the orthographic projection of P14 on the substrate and the orthographic projection of the first first electrode pattern 121 on the substrate is a third distance L3, and the distance between the orthographic projection of P14 on the substrate and the orthographic projection of the second first electrode pattern 122 on the substrate is a fourth distance L4. L3 and L4 may be 1.3 μm.

[0200] The width of the orthographic projection of P13 on the base is a second width L02, the width of the orthographic projection of P14 on the base is a third width L03, and the width of the orthographic projection of P15 on the base is a fourth width L04;

[0201] L02, L03 and L04 can all be 2.4μm;

[0202] The distance between the orthographic projection of P13 and the orthographic projection of P14 on the substrate is a fifth distance L5, and the distance between the orthographic projection of P14 and the orthographic projection of P15 on the substrate is a sixth distance L6. L5 and L6 can both be 4 μm.

[0203] In the related art, the common electrode is divided into blocks in a traditional manner, that is, the common electrode above the gate line is disconnected, which will form a fringe electric field between the common electrode and the gate line, causing the liquid crystal to deflect and produce L0 light leakage. This requires a wider BM (black matrix) for shielding, which will cause the pixel aperture ratio to decrease. However, at least one embodiment of the present disclosure transfers the common electrode block area to the pixel area, and places the pixel electrode in the common electrode hollow. As a result, there is no interference from the gate line electric field under L0, and no light leakage will occur. In the hollow area under L255, there is no weak electric field area due to the presence of the fringe electric field of the common electrode and the pixel electrode. Compared with the traditional design, the transmittance of the pixel structure designed in the present disclosure will be increased by more than 10%, and its light effect diagram is shown in Figure 12E (at this time W can be equal to 3.8μm). At the same time, the light effect of the pixel structure changes with the width W of the opening structure as shown in Figure 12F (in Figure 12F, the horizontal axis is W, the unit is μm, and the vertical axis is the light effect PH). As shown in FIG12F , when the width W of the opening structure is greater than 0 and less than or equal to 5.6 μm, the light efficiency does not change much as W increases. When the width W of the opening structure is greater than 5.6 μm, its light efficiency will significantly decrease as W increases, as can be clearly seen in FIG12G (in FIG12G , W is 6.8 μm) and FIG12H (in FIG12H , W is 9.8 μm), which will cause poor image quality horizontal stripes. When the width W of the opening structure remains unchanged, the effect of adjusting the width W1 of the second electrode portion on the light efficiency is shown in FIG12I . When W1 is too small, for example, 1.8 μm, the spacing between the second electrode portions is large, forming a dark area, and the light efficiency is reduced, as shown in FIG12J . When W1 is too large, for example, 3 μm, the width of the second electrode portion is large, forming a dark area, and the light efficiency is reduced, as shown in FIG12K . Considering process feasibility, a more appropriate width W1 of the second electrode portion, the spacing S between two adjacent second electrode portions, and the width W of the opening structure are selected based on this. For example, W1 can be greater than or equal to 1.5 μm and less than or equal to 3.5 μm, S can be greater than or equal to 2.5 μm and less than or equal to 5 μm, and W can be greater than or equal to 2.5 μm and less than or equal to 8 μm. The preparation process in at least one embodiment of the present disclosure is shown in Figure 12L.

[0204] In Figure 12L, GA is the gate metal layer, A1 is the semiconductor layer, GI is the gate insulating layer, SD is the source and drain metal layer, PVX1 is the first passivation layer, ITO1 is the first electrode layer, PVX2 is the second passivation layer, and ITO2 is the second electrode layer. PVX1 and PVX2 can be formed by one-step etching.

[0205] In at least one embodiment of the present disclosure, the transmittance may be greater than or equal to 2% and less than or equal to 8%, and this range is under the condition that the incremental film is not used.

[0206] FIG13 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0207] In at least one embodiment of the present disclosure, the third wiring may be a touch signal line, the second wiring may be a data line, and the first wiring may be a gate line.

[0208] In FIG13 , the line labeled TX1 is a first touch signal line, the line labeled DL1 is a first data line, the line labeled TX2 is a second touch signal line, and the line labeled DL2 is a second data line;

[0209] The first row of grid lines is labeled G1, the second row of grid lines is labeled G2, the third row of grid lines is labeled G3, and the fourth row of grid lines is labeled G4;

[0210] The first sub-pixel region is labeled P1, the second sub-pixel region is labeled P2, and the third sub-pixel region is labeled P3; P1, P2, and P3 are arranged along the vertical direction.

[0211] 14 is a layout diagram of the gate metal layer in FIG13 , FIG15 is a layout diagram of the source / drain metal layer in FIG13 , FIG16 is a layout diagram of the common electrode layer in FIG13 , and FIG17 is a layout diagram of the pixel electrode layer in FIG13 .

[0212] In at least one embodiment shown in FIG. 13 , the gate metal layer, the active layer, the source / drain metal layer, the common electrode layer, and the pixel electrode layer are sequentially arranged in a direction away from the substrate.

[0213] In FIG13 , the first opening structure labeled X1 , in at least one embodiment shown in FIG13 , is not provided with a pixel electrode on a side of the first opening structure away from the substrate.

[0214] In FIG14 , the first row of gate lines is labeled G1 , the second row of gate lines is labeled G2 , the third row of gate lines is labeled G3 , and the fourth row of gate lines is labeled G4 .

[0215] In FIG15 , TX1 is a first touch signal line, DL1 is a first data line, TX2 is a second touch signal line, and DL2 is a second data line.

[0216] In FIG16 , the common electrode portion is labeled VM, and the first opening structure is labeled X1.

[0217] In FIG17 , the first second electrode portion is labeled PZ1 , the second second electrode portion is labeled PZ2 , the third second electrode portion is labeled PZ3 , and the fourth second electrode portion is labeled PZ4 .

[0218] In at least one embodiment of the present disclosure, the second electrode portion includes a plurality of second electrode portions extending along the first direction; the second electrode portions are arranged along the second direction;

[0219] A length of the second electrode portion along the second direction is greater than or equal to 1.8 μm and less than or equal to 3.5 μm.

[0220] In a specific implementation, the extension direction of the second electrode portion may be substantially the same as the extension direction of the gate line, and the length of the second electrode portion along the vertical direction may be greater than or equal to 1.8 μm and less than or equal to 3.5 μm, but is not limited thereto.

[0221] Optionally, the second direction may be a vertical direction.

[0222] In at least one embodiment of the present disclosure, the extending direction of the second electrode portion is substantially the same as the extending direction of the gate line, which may refer to:

[0223] The extending direction of the second electrode portion is the same as the extending direction of the gate line; or,

[0224] The angle between the extension direction of the second electrode portion and the extension direction of the gate line is within 5 degrees;

[0225] But it is not limited to this.

[0226] Optionally, a distance between two adjacent second electrode portions included in the second electrode portion in the second direction is greater than or equal to 2.3 μm and less than or equal to 6 μm.

[0227] In a specific implementation, a distance between two adjacent second electrode portions included in the second electrode unit in the vertical direction may be greater than or equal to 2.3 μm and less than or equal to 6 μm, but is not limited thereto.

[0228] In at least one embodiment of the present disclosure, an extension direction of the second electrode portion is substantially the same as an extension direction of the first trace.

[0229] Optionally, the first trace may be a gate line.

[0230] In at least one embodiment of the present disclosure, a column of third traces is provided between two adjacent columns of second electrode portions in the second direction;

[0231] The third wiring is electrically connected to the first electrode portion. The first electrode portion is multiplexed as a touch electrode block in the touch stage. Whether the first electrode portion is touched can be determined according to the signal on the touch signal line.

[0232] Optionally, the third trace may be a touch signal line.

[0233] In at least one embodiment of the present disclosure, a column of second wiring is provided between two adjacent columns of second electrode portions in the second direction;

[0234] The second routing line and the third routing line are adjacent to each other.

[0235] Optionally, the second wiring may be a data line, and the third wiring may be a touch signal line.

[0236] In a specific implementation, the distance between the adjacent data lines and the touch signal lines may be greater than or equal to 3 μm and less than or equal to 6 μm, for example, may be 4.5 μm, but is not limited thereto.

[0237] In at least one embodiment of the present disclosure, the distance between the adjacent data lines and the touch signal lines is determined by the load of the data lines. Too large a distance affects the aperture ratio, while too small a distance increases the load of the data lines or causes metal residue to cause a short circuit.

[0238] In a specific implementation, a sub-pixel includes a pixel electrode and a switching transistor. The gate of the switching transistor is electrically connected to the gate line, the source of the switching transistor is electrically connected to the data line, and the drain of the switching transistor is electrically connected to the pixel electrode. The channel width of the switching transistor can be, for example, 6 μm, and the channel length of the switching transistor can be, for example, 4 μm, but are not limited thereto. The channel width-to-length ratio of the switching transistor can be determined based on a comprehensive consideration of the aperture ratio and the charge rate.

[0239] Optionally, the width of the touch signal line in the first direction is greater than or equal to 3 μm and less than or equal to 4 μm, and the width of the data line in the first direction is greater than or equal to 3 μm and less than or equal to 5 μm;

[0240] A distance between two adjacent columns of second electrode portions in the first direction is greater than or equal to 3 μm and less than or equal to 6 μm.

[0241] In a specific implementation, the line width of the touch signal line may be greater than or equal to 3 μm and less than or equal to 4 μm. For example, the line width of the touch signal line may be 4 μm.

[0242] The line width of the data line is greater than or equal to 3 μm and less than or equal to 5 μm. For example, the line width of the data line may be 3.5 μm.

[0243] But it is not limited to this.

[0244] In at least one embodiment of the present disclosure, the width of the gate line along the vertical direction may be greater than or equal to 3.5 μm and less than or equal to 7 μm. For example, the width of the gate line along the vertical direction may be 3.5 μm; but the present invention is not limited thereto.

[0245] In at least one embodiment of the present disclosure, along the first direction, the width of the third line is greater than the width of the second line. The third line may be a touch signal line, and the second line may be a data line.

[0246] In at least one embodiment shown in FIG5 , the via hole labeled H1 is the first via hole, and the via hole labeled H2 is the second via hole;

[0247] The first via hole H1 is a via hole penetrating the organic film and is used to electrically connect the source electrode of the switching transistor and the pixel electrode;

[0248] The second via hole H2 is a via hole that penetrates the passivation layer. The second via hole H2 is disposed within the first via hole H1. The touch signal line is electrically connected to the common electrode through the second via hole H2.

[0249] In at least one embodiment of the present disclosure, the side length of the edge of the orthographic projection of the first via hole H1 on the substrate can be designed to be greater than or equal to 7 μm and less than or equal to 10 μm, and the side length of the edge of the orthographic projection of the second via hole H2 on the substrate can be designed to be greater than or equal to 4 μm and less than or equal to 8 μm, but the present invention is not limited thereto.

[0250] In a specific implementation, a first passivation layer and an organic film layer are stacked between the source / drain metal layer and the common electrode layer, and a second passivation layer is disposed between the common electrode layer and the pixel electrode layer.

[0251] The organic film layer is arranged between the first passivation layer and the common electrode layer.

[0252] In at least one embodiment of the present disclosure, the display substrate includes a pixel array, a display area, and a peripheral area; the pixel array includes the sub-pixels;

[0253] The pixel array is arranged in the display area, and the display substrate further includes virtual sub-pixels arranged in the peripheral area;

[0254] The virtual sub-pixel is arranged adjacent to the display area;

[0255] The length of at least some of the virtual sub-pixels along the first direction is smaller than the length of the sub-pixels along the first direction.

[0256] In a specific implementation, virtual sub-pixels may be provided in the peripheral area. The virtual sub-pixels may be provided adjacent to the display area, and the horizontal length of at least some of the virtual sub-pixels may be greater than the horizontal length of the sub-pixels.

[0257] FIG18A is a layout diagram showing a dummy sub-pixel region at the upper left corner of a display substrate. In FIG18A , the region labeled AX1 is a first dummy sub-pixel region, and the region labeled AX2 is a second dummy sub-pixel region.

[0258] In at least one embodiment of the present disclosure, the length of the virtual sub-pixel in the first virtual sub-pixel area AX1 along the first direction is less than the length of the sub-pixel along the first direction, and the length of the virtual sub-pixel in the second virtual sub-pixel area AX2 along the first direction can be equal to the length of the sub-pixel along the first direction, but is not limited to this.

[0259] In FIG18B , the first virtual sub-pixel is labeled XP1. As shown in FIG18B , the length of the first virtual sub-pixel XP1 along the first direction is smaller than the length of the sub-pixel along the first direction.

[0260] Figure 18C is a layout diagram of the gate metal layer in Figure 18A, and Figure 18D is a layout diagram of the second electrode layer in Figure 18A; in Figure 18C, the gate line is labeled GL, and the electrostatic discharge block is labeled EK; in Figure 18D, the first virtual pixel electrode is labeled XJ1.

[0261] Fig. 18E is a layout diagram of the first electrode layer in Fig. 18 A. In Fig. 18E, the common electrode is labeled VCOM.

[0262] Figure 18F is a layout diagram of the source / drain metal layer in Figure 18A. In Figure 18F, the conductive pattern is labeled DX.

[0263] Optionally, the first trace includes a first end and a second end;

[0264] The display substrate further comprises a plurality of electrostatic discharge blocks disposed on the base, wherein the electrostatic discharge blocks are conductive blocks;

[0265] The electrostatic discharge block is electrically connected to the first end or the second end of the first trace.

[0266] Optionally, the first trace is a gate line.

[0267] As shown in FIG. 18C , the left end portion of the gate line GL is electrically connected to the electrostatic discharge block EK, which is a conductive block.

[0268] Optionally, the electrostatic discharge block and the first trace are provided in the same layer and made of the same material.

[0269] As shown in FIG. 18C , the electrostatic discharge block EK and the gate line GL are provided in the same layer and made of the same material.

[0270] In at least one embodiment of the present disclosure, a length of the electrostatic discharge block along the second direction is greater than a line width of the first trace.

[0271] In a specific implementation, the vertical length of the electrostatic discharge block EK is greater than the line width of the gate line GL. The electrostatic discharge block EK can prevent discharge at the tip end of the gate line. For example, the line width of the gate line can be 3.5 μm, and the orthographic projection of the electrostatic discharge block EK on the substrate can be a square. The side length of the orthographic projection of the electrostatic discharge block EK on the substrate can be 18 μm, but this is not limited to this.

[0272] FIG19A is a layout diagram of a portion of dummy sub-pixel regions included in a display substrate. In FIG19A , the region labeled AX3 is the third dummy sub-pixel region, and the region labeled AX4 is the fourth dummy sub-pixel region.

[0273] In at least one embodiment of the present disclosure, the length of the virtual sub-pixel in the third virtual sub-pixel area AX3 along the first direction is less than the length of the sub-pixel along the first direction, and the length of the virtual sub-pixel in the fourth virtual sub-pixel area AX4 along the first direction can be equal to the length of the sub-pixel along the first direction, but is not limited to this.

[0274] In Figure 19B , the second virtual sub-pixel is labeled XP2. As shown in Figure 19B , the length of the second virtual sub-pixel XP2 along the first direction is smaller than the length of the sub-pixel along the first direction.

[0275] Figure 19C is a layout diagram of the gate metal layer in Figure 19A, and Figure 19D is a layout diagram of the second electrode layer in Figure 19A; in Figure 19C, the gate line is labeled GL, and the electrostatic discharge block is labeled EK; in Figure 19D, the second virtual pixel electrode is labeled XJ2.

[0276] Fig. 19E is a layout diagram of the first electrode layer in Fig. 19A. In Fig. 19E, the common electrode is labeled VCOM.

[0277] Figure 19F is a layout diagram of the source / drain metal layer in Figure 19A. In Figure 19F, the conductive pattern is labeled DX.

[0278] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a substrate, and a first electrode, a second electrode, a plurality of rows of first wirings and a plurality of columns of second wirings arranged on the substrate; the first wirings and the second wirings intersect with each other to define a plurality of pixel regions, each of the pixel regions is provided with at least one sub-pixel, and the sub-pixel comprises the first electrode and the second electrode; the first wiring is located in a first wiring region, and the second wiring is located in a second wiring region; The first electrode is located between the substrate and the second electrode; the second electrode includes a plurality of second electrode portions arranged in an array, and the second electrode portions are located in the corresponding pixel area; the orthographic projections of the second electrode and the first wiring area on the substrate are independent of each other; the orthographic projections of the first electrode and the first wiring area on the substrate overlap; The first electrode of at least one of the pixel regions has an opening structure, and the opening structure extends along a first direction, and the first direction is parallel to an extending direction of the first wiring; Along the second direction, the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first routing line arranged on the first side of the opening structure on the substrate is a first distance, and the distance between the orthographic projection of the opening structure on the substrate and the orthographic projection of the first routing line arranged on the second side of the opening structure on the substrate is a second distance. The first side and the second side are opposite sides; the first direction intersects with the second direction.

2. The display substrate according to claim 1, wherein: The first distance is smaller than the second distance, and a ratio of the first distance to the second distance is greater than or equal to 0.25 and less than or equal to 0.

5.

3. The display substrate according to claim 1, wherein: An orthographic projection of the opening structure on the substrate at least partially overlaps with an orthographic projection of the second electrode on the substrate.

4. The display substrate according to claim 1, wherein: An orthographic projection of the opening structure on the substrate does not overlap with an orthographic projection of the second electrode on the substrate.

5. The display substrate according to any one of claims 1 to 4, wherein: An orthographic projection of the opening structure on the substrate partially overlaps with an orthographic projection of at least one second electrode portion of the second electrode on the substrate.

6. The display substrate according to any one of claims 1 to 4, wherein: Along the first direction, the length of the opening structure is less than or equal to the length of the second electrode portion.

7. The display substrate according to any one of claims 1 to 4, wherein: The M second electrode portions are included in the same pixel; the M second electrode portions are arranged in the same pixel area; M is an integer greater than or equal to 3; In the same pixel area, m opening structures are arranged; m is a positive integer, and m is less than or equal to M.

8. The display substrate according to claim 7, wherein: The same pixel includes a first second electrode portion, a second second electrode portion and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region; In the same pixel region, a first opening structure, a second opening structure and a third opening structure are provided; The first opening structure is disposed in the first sub-pixel region, the second opening structure is disposed in the second sub-pixel region, and the third opening structure is disposed in the third sub-pixel region.

9. The display substrate according to claim 7, wherein: The same pixel includes a first second electrode portion, a second second electrode portion and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region; In the same pixel region, a first opening structure and a second opening structure are provided; The first opening structure is disposed in the first sub-pixel region, and the second opening structure is disposed in the second sub-pixel region.

10. The display substrate according to claim 7, wherein: The same pixel includes a first second electrode portion, a second second electrode portion and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region; In the same pixel region, a first opening structure and a second opening structure are provided; The first opening structure is disposed in the first sub-pixel region, and the second opening structure is disposed in the third sub-pixel region.

11. The display substrate according to claim 7, wherein: The same pixel includes a first second electrode portion, a second second electrode portion and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region; In the same pixel region, a first opening structure and a second opening structure are provided; The first opening structure is disposed in the second sub-pixel region, and the second opening structure is disposed in the third sub-pixel region.

12. The display substrate according to claim 7, wherein: The same pixel includes a first second electrode portion, a second second electrode portion and a third second electrode portion, wherein the first second electrode portion is arranged in a first sub-pixel region of the same pixel region, the second second electrode portion is arranged in a second sub-pixel region of the same pixel region, and the third second electrode portion is arranged in a third sub-pixel region of the same pixel region; In the same pixel area, a first opening structure is provided; The first opening structure is disposed in the first sub-pixel region, the second sub-pixel region or the third sub-pixel region.

13. The display substrate according to any one of claims 1 to 4, wherein: The second electrode portion includes a plurality of second electrode portions extending along the first direction; the second electrode portions are arranged along the second direction; A length of the second electrode portion along the second direction is greater than or equal to 1.8 μm and less than or equal to 3.5 μm.

14. The display substrate according to claim 13, wherein: A distance between two adjacent second electrode portions included in the second electrode portion in the second direction is greater than or equal to 2.3 μm and less than or equal to 6 μm.

15. The display substrate according to claim 13, wherein: An extending direction of the second electrode portion is substantially the same as an extending direction of the first wiring.

16. The display substrate according to any one of claims 1 to 4, wherein: A column of third wiring is arranged between two adjacent columns of second electrode portions in the second direction; the first electrode comprises a plurality of mutually independent first electrode portions arranged in an array; A third wiring is electrically connected to the first electrode portion.

17. The display substrate according to claim 16, wherein: A column of second wirings is arranged between two adjacent columns of second electrode portions in the second direction; The second routing line and the third routing line are arranged adjacent to each other.

18. The display substrate according to claim 17, wherein: Along the first direction, the width of the third routing line is less than or equal to the width of the second routing line; A distance between two adjacent columns of second electrode portions in the first direction is greater than or equal to 3 μm and less than or equal to 6 μm.

19. The display substrate according to claim 17, wherein: Along the first direction, the width of the third routing line is greater than the width of the second routing line.

20. The display substrate according to any one of claims 1 to 4, wherein: The display substrate comprises a pixel array, a display area and a peripheral area; the pixel array comprises the sub-pixels; The pixel array is arranged in the display area, and the display substrate further comprises virtual sub-pixels arranged in the peripheral area; The virtual sub-pixel is arranged adjacent to the display area; The length of at least some of the virtual sub-pixels along the first direction is smaller than the length of the sub-pixels along the first direction.

21. The display substrate according to any one of claims 1 to 4, wherein: The first trace includes a first end and a second end; The display substrate further comprises a plurality of electrostatic discharge blocks disposed on the base, wherein the electrostatic discharge blocks are conductive blocks; The electrostatic discharge block is electrically connected to the first end or the second end of the first trace.

22. The display substrate according to claim 21, wherein: The electrostatic discharge block and the first wiring are arranged on the same layer and made of the same material.

23. The display substrate according to claim 21, wherein: A length of the electrostatic discharge block along the second direction is greater than a line width of the first trace.

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