High performance display architecture

Abstract

The present disclosure provides systems, devices, apparatuses, and methods, including computer programs encoded on storage media, for a high-efficiency display architecture. A display processor (500) can obtain an indication that a UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor can drive a first display via a first controller (416) of a first DPU (410A) based on the indication. In the case that the UC is to be displayed at the first resolution, the display processor can drive a second display via a controller (422) of a second DPU (410B), or in the case that the UC is to be displayed at the second resolution, the display processor can drive the second display via a second controller (424) of the first DPU (410A).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Patent Application Serial No. 18 / 056,649, entitled “POWER EFFICIENT DISPLAY ARCHITECTURE” and filed on November 17, 2022, which is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to processing systems, and more specifically to one or more techniques for display processing. BACKGROUND

[0004] Computing devices often perform graphics and / or display processing (e.g., with a graphics processing unit (GPU), central processing unit (CPU), display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. A GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. A central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are often capable of executing multiple applications concurrently, each of which can need to utilize the GPU during execution. A display processor can be configured to convert digital information received from the CPU into analog values and can issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display can utilize a CPU, GPU, and / or display processor.

[0005] Current techniques for display processing for virtual reality (VR) applications can fail to address issues related to supporting both high resolution user content and low resolution user content in a system with multiple display processing unit (DPU) cores. Improved techniques for managing multiple DPU cores for VR applications and for synchronizing timing between multiple DPU cores are needed. SUMMARY

[0006] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0007] In one aspect of the disclosure, a method, a computer-readable medium, and an apparatus for display processing are provided. The apparatus includes a memory and at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to obtain an indication that user content (UC) is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution, drive a first display via a first controller of a first display processing unit (DPU) based on the indication, and drive a second display via a controller of a second DPU in a case that the UC is to be displayed at the first resolution or drive the second display via a second controller of the first DPU in a case that the UC is to be displayed at the second resolution.

[0008] To the accomplishment of the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects can be employed, and this description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure.

[0010] Figure 2 is an example GPU in accordance with one or more techniques of this disclosure.

[0011] Figure 3 is an example display framework including a display processor and a display.

[0012] Figure 4 is a diagram illustrating an example of a high-throughput display processing unit (DPU) configuration.

[0013] Figure 5 is a diagram illustrating an example of a low-throughput DPU configuration.

[0014] Figure 6 is a diagram illustrating an example of a DPU pipeline associated with a first DPU.

[0015] Figure 7 is a diagram illustrating an example of a DPU pipeline associated with a second DPU.

[0016] Figure 8 is a diagram illustrating an example of a first DPU core.

[0017] Figure 9 is a diagram illustrating an example of a second DPU core.

[0018] Figure 10 is a diagram illustrating an example of a multiplexer (MUX).

[0019] Figure 11 is a diagram illustrating an example of an interface of a DPU core.

[0020] Figure 12 is a diagram illustrating an example of timing synchronization between DPU cores.

[0021] Figure 13 is a diagram illustrating an example of timing between different DPU interfaces.

[0022] Figure 14 is a diagram illustrating example aspects of clock synchronization with respect to a master DPU.

[0023] Figure 15 is a diagram illustrating example aspects of clock synchronization with respect to a slave DPU.

[0024] Figure 16 is a call flow diagram illustrating example communications between a DPU and a graphics processing unit (GPU).

[0025] Figure 17 is a flow diagram of an example method of display processing in accordance with one or more techniques of the present disclosure. DETAILED DESCRIPTION

[0026] Various aspects of systems, apparatuses, computer program products, and methods will now be described in greater detail below with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover other structures, functions, and alternatives of each aspect of the disclosure that are disclosed herein. Any aspect disclosed herein can be embodied by one or more elements of a claim.

[0027] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. While some potential benefits and advantages of aspects of the disclosure are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, processing systems, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and description below. The following detailed description is directed to certain specific aspects for the purposes of explanation and not limitation.

[0028] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

[0029] For example, an element, or any portion of an element, or any combination of elements can be implemented as a “processing system” that includes one or more processors (which can also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SoC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described herein. One or more processors in the processing system can execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0030] The term“application” can refer to software. As described herein, one or more techniques can refer to an application (e.g., software) configured to perform one or more functions. In such examples, the application can be stored in a memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware, such as a processor, described herein can be configured to execute the application. For example, the application can be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware can access the code from the memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in the present disclosure. In such examples, a component can be hardware, software, or a combination thereof. Components can be individual components or subcomponents of a single component.

[0031] In one or more examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise a random-access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), compact disk ROM (CD-ROM), diskette, a hard disk drive, magnetic tape, other magnetic media, a flash memory, other solid-state memory, a combination of any of the foregoing, or any other medium that can be used to store computer-executable or computer- readable code in the form of instructions or data structures that can be accessed by a computer.

[0032] As used herein, examples of the term“content” can refer to“graphics content,”“images,” and the like, regardless of whether the term is used as an adjective, a noun, or other part of speech. In some examples, as used herein, the term“graphics content” can refer to content produced by one or more processes of a graphics processing pipeline. In further examples, as used herein, the term“graphics content” can refer to content produced by a processing unit configured to perform graphics processing. In yet further examples, as used herein, the term“graphics content” can refer to content produced by a graphics processing unit.

[0033] To display user content (UC) associated with a virtual reality (VR) application to a user, a display processing unit (DPU) can extract GPU rendered layers of the UC, apply color aberration correction (CAC) to the GPU rendered layers, and display the processed superimposed layers to left and right eye panels of a VR headset (e.g., VR glasses), respectively. Different VR applications can be associated with different display resolutions. For example, a first VR application can display UC (e.g., image frames) at a first resolution (e.g., approximately 2000 x 2000 pixels per eye panel at 60 frames per second (FPS)), and a second VR application can display UC at a second resolution (e.g., approximately 4000 x 4000 pixels per eye panel at 60 FPS). To accommodate the higher resolution, the VR headset can be configured with a system on a chip (SOC) (also referred to as a system on a chip) that includes multiple DPU cores. Current techniques for display processing for VR applications can fail to address issues related to supporting both high resolution user content and low resolution user content in a system with multiple display processing unit (DPU) cores. Moreover, current techniques for display processing can fail to address timing synchronization issues that can occur between multiple DPU cores.

[0034] Various techniques related to high-efficiency, flexible VR display architectures and multi-DPU core synchronization are described herein. In one example, an apparatus obtains an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The apparatus drives a first display via a first controller of a first DPU based on the indication. In a case where the UC is to be displayed at the first resolution, the apparatus drives a second display via a controller of a second DPU, or in a case where the UC is to be displayed at the second resolution, the apparatus drives the second display via a second controller of the first DPU. By selectively driving the second display via the second controller of the first DPU or the controller of the second DPU based on whether the UC is to be displayed at the first resolution (e.g., a high resolution) or the second resolution (e.g., a low resolution), the apparatus can provide reduced power consumption for displaying the UC. In another example, the apparatus can establish a display timing at a first interface of the first DPU. The display timing can include one or more of a display frame rate, a line rate, and / or a pixel rate. The apparatus can synchronize the first DPU and the second DPU based on the display timing. Thus, the apparatus can provide timing synchronization across multiple DPU cores.

[0035] Figure 1is a block diagram of an example content generation system 100 that is configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 can include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of the device 104 can be components of a system on a chip (SOC). The device 104 can include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the device 104 can include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 can include multiple components (e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131). The display 131 can refer to one or more displays 131. For example, the display 131 can include a single display or multiple displays, which can include a first display and a second display. The first display can be a left eye display and the second display can be a right eye display. In some examples, the first display and the second display can receive different frames for presentation thereon. In other examples, the first display and the second display can receive the same frames for presentation thereon. In further examples, the results of the graphics processing can not be displayed on the device, e.g., the first display and the second display can not receive any frames for presentation thereon. Rather, the frames or graphics processing results can be passed to another device. In some aspects, this scenario is referred to as split rendering.

[0036] The processing unit 120 can include an internal memory 121. The processing unit 120 can be configured to perform graphics processing using the graphics processing pipeline 107. The content encoder / decoder 122 can include an internal memory 123. In some examples, the device 104 can include a processor that can be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before displaying the frames through one or more displays 131. While the processor in the example content generation system 100 is configured as a display processor 127, it should be understood that the display processor 127 is one example of a processor and other types of processors, controllers, etc. can be used in place of the display processor 127. The display processor 127 can be configured to perform display processing. For example, the display processor 127 can be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 can be configured to display or otherwise present the frames processed by the display processor 127. In some examples, the one or more displays 131 can include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0037] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, can be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 can be configured to read from and / or write to the external memory, such as system memory 124. The processing unit 120 can be communicatively coupled to the system memory 124 by a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 can be communicatively coupled to the internal memory 121 by the bus or via a different connection.

[0038] The content encoder / decoder 122 can be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 can be configured to store received encoded or decoded graphics content. The content encoder / decoder 122 can be configured to receive encoded or decoded graphics content, for example, from the system memory 124 and / or the communication interface 126, in the form of encoded pixel data. The content encoder / decoder 122 can be configured to encode or decode any graphics content.

[0039] The internal memory 121 or system memory 124 can include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 121 or system memory 124 can include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, a magnetic data medium, or an optical storage medium or any other type of memory. According to some examples, the internal memory 121 or system memory 124 can be a non-transitory storage medium. The term "non-transitory" can indicate that the storage medium is not embodied in a carrier wave or a propagating signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or system memory 124 is non-removable or that its contents are static. For example, the system memory 124 can be removed from the device 104 and moved to another device. As another example, the system memory 124 can be non-removable from the device 104.

[0040] The processing unit 120 can be a CPU, GPU, GPGPU, or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 can be integrated into a motherboard of the device 104. In further examples, the processing unit 120 can be present on a graphics card that is installed in a port of the motherboard of the device 104, or can be incorporated in other manners into a peripheral device configured to interoperate with the device 104. The processing unit 120 can include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 can store instructions for the software in suitable, non-transitory computer-readable storage media (e.g., the internal memory 121) and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered one or more processors.

[0041] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into a motherboard of the device 104. The content encoder / decoder 122 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder / decoder 122 can store instructions for the software in a suitable, non-transitory computer-readable storage medium (e.g., the internal memory 123) and execute the instructions in hardware to perform the techniques of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered one or more processors.

[0042] In some aspects, the content generation system 100 can include a communication interface 126. The communication interface 126 can include a receiver 128 and a transmitter 130. The receiver 128 can be configured to perform any of the receiving functions described herein with respect to the device 104. Additionally, the receiver 128 can be configured to receive information from another device, such as eye or head position information, rendering commands, and / or position information. The transmitter 130 can be configured to perform any of the transmitting functions described herein with respect to the device 104. For example, the transmitter 130 can be configured to transmit information to another device, which can include a request for content. The receiver 128 and the transmitter 130 can be combined into a transceiver 132. In such examples, the transceiver 132 can be configured to perform any of the receiving functions and / or the transmitting functions described herein with respect to the device 104.

[0043] Referring again to Figure 1 In certain aspects, the display processor 127 can include a DPU selector 198 configured to obtain an indication that the UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The DPU selector 198 is configured to drive the first display via a first controller of the first DPU based on the indication. The DPU selector 198 is configured to drive the second display via a controller of the second DPU in the event that the UC is to be displayed at the first resolution or to drive the second display via a second controller of the first DPU in the event that the UC is to be displayed at the second resolution. Although the following description can focus on display processing, the concepts described herein can be applicable to other similar processing techniques.

[0044] A device such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the techniques described herein. For example, a device can be a server, a base station, a user equipment, a client device, a station, an access point, a computer (such as a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), an end product, a gadget, a telephone, a smartphone, a server, a video game platform or console, a handheld device (such as a portable video game device or a personal digital assistant (PDA)), a wearable computing device (such as a smartwatch, an augmented reality device, or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediary network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the techniques described herein. Processes herein can be described as being performed by a particular component (e.g., a GPU), but in other embodiments, other components (e.g., a CPU) that are consistent with the disclosed embodiments can be used to perform.

[0045] A GPU can process multiple types of data or data packets in a GPU pipeline. For example, in certain aspects, a GPU can process two types of data or data packets, such as context register packets and draw call data. A context register packet can be a set of global state information, such as information about global registers, shading programs, or constant data, that can adjust how a graphics context will be processed. For example, a context register packet can include information about a color format. In certain aspects of a context register packet, there can be a bit that indicates which workload belongs to the context register. Additionally, multiple functions or programs can be run simultaneously and / or in parallel. For example, a function or program can describe a certain operation, such as a color mode or color format. Thus, a context register can define multiple states of a GPU.

[0046] A context state can be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) runs and / or in which mode a processing unit runs. To do so, a GPU can use context registers and programming data. In some aspects, a GPU can generate workloads, such as vertex or pixel workloads, in a pipeline based on context registers of a mode or state. Certain processing units (e.g., a VFD) can use these states to determine certain functions, such as how to gather vertices. Since these modes or states can change, a GPU can need to change the corresponding context. Additionally, workloads corresponding to the modes or states can follow the changed modes or states.

[0047] Figure 2 An exemplary GPU 200 according to one or more technologies of this disclosure is illustrated. For example... Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, an L2 cache (UCHE) 238, and system memory 240. Although Figure 2 The GPU 200 includes processing units 220 to 238, but the GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and the GPU may use any combination or order of processing units in accordance with this disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0048] like Figure 2 As shown, the GPU can use a CP (e.g., CP 210) or a hardware accelerator to resolve the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then transfer the context register packet 260 or the draw call data packet 212 to a processing unit or block in the GPU via a separate path. Furthermore, the command buffer 250 can alternate between different states of the context registers and draw calls. For example, the command buffer can be constructed as follows: context register of context N, draw call of context N, context register of context N+1, and draw call of context N+1.

[0049] GPUs can render images in a variety of different ways. In some instances, GPUs can render images using both tiled rendering and / or tiled rendering. In a tiled rendering GPU, an image can be divided or separated into different parts or tiles. After the image is divided, each part or tile can be rendered individually. A tiled rendering GPU can divide a computer graphics image into a grid format, so that each part of the grid (i.e., a tile) is rendered individually. In some aspects, during a binning pass, an image can be divided into different bins or tiles. In some aspects, during a binning pass, a visibility stream can be constructed, where visible primitives or draw calls can be identified. In contrast to tiled rendering, direct rendering does not divide a frame into smaller bins or tiles. Instead, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs allow both tiled rendering and direct rendering (e.g., flex rendering).

[0050] In some aspects, a GPU can apply a draw or render process to different bins or tiles. For example, a GPU can render for one bin and perform all the drawing for primitives or pixels in the bin. During the process of rendering for a bin, a render target can be located in the GPU internal memory (GMEM). In some instances, after rendering for one bin, the contents of the render target can be moved to system memory and the GMEM is freed to render the next bin. Additionally, the GPU can render for another bin and perform drawing for primitives or pixels in the bin. Thus, in some aspects, there can be a small number of bins (e.g., four bins) that cover all the drawing in one surface. Further, the GPU can loop through all the drawing in one bin, but perform drawing for visible draw calls, i.e., draw calls that contain visible geometry. In some aspects, a visibility stream can be generated, e.g., during the binning process, to determine visibility information for each primitive in an image or scene. For example, such a visibility stream can identify whether a certain primitive is visible. In some aspects, this information can be used to remove primitives that are not visible, e.g., during the rendering process. Further, at least some primitives that are identified as visible can be rendered during the rendering process.

[0051] In some aspects of tile rendering, there can be multiple processing stages or passes. For example, rendering can be performed in two passes, e.g., a visibility or bin-visibility pass and a rendering or bin-rendering pass. During the visibility pass, a GPU can input a rendering workload, record the location of primitives or triangles, and then determine which primitives or triangles fall into which bin or region. In certain aspects of the visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in a visibility stream. During the rendering pass, the GPU can input the visibility stream and process one bin or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or not visible. Thus, visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce unnecessary workload of processing or rendering primitives or triangles that are not visible.

[0052] In some aspects, during the visibility process, certain types of primitive geometry can be processed, e.g., only positioned geometry. Additionally, primitives can be sorted into different bins or regions depending on their position or location. In some instances, sorting primitives or triangles into different bins can be performed by determining visibility information for these primitives or triangles. For example, a GPU can determine or write the visibility information for each primitive in each bin, e.g., into system memory. This visibility information can be used to determine or generate a visibility stream. During the rendering process, the primitives in each bin can be rendered individually. In these cases, the visibility stream can be extracted from memory for discarding primitives that are not visible for that bin.

[0053] Some aspects of a GPU or GPU architecture can provide a number of different options for rendering, e.g., software rendering and hardware rendering. In software rendering, a driver or CPU can copy the entire frame geometry by processing each view Figure 1 In software rendering, software can copy the entire workload by changing some states that can be used for rendering for each viewpoint in the image. In certain aspects, there can be an increased amount of overhead since the GPU can submit the same workload multiple times for each viewpoint in the image. In hardware rendering, hardware or a GPU can be responsible for copying or processing the geometry for each viewpoint in the image. Thus, hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0054] Figure 3 is a block diagram 300 illustrating an example display framework including a processing unit 120, system memory 124, display processor 127, and display 131 as can be identified in device 104.

[0055] A GPU can be included in a device that provides content for visual presentation on a display. For example, processing unit 120 can include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which can be a computer workstation, a mobile telephone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of GPU 310 can be controlled based on one or more graphics processing commands provided by CPU 315. CPU 315 can be configured to concurrently execute multiple applications. In some cases, each of the multiple applications that are concurrently executed can simultaneously utilize GPU 310. Processing techniques can be performed via processing unit 120 to output frames over a physical or wireless communication channel.

[0056] System memory 124, which can be executed by processing unit 120, can include user space 320 and kernel space 325. User space 320 (sometimes referred to as “application space”) can include software applications and / or application frameworks. For example, software applications can include an operating system, a media application, a graphics application, a workspace application, etc. Application frameworks can include frameworks used by one or more software applications, such as libraries, services (e.g., a display service, an input service, etc.), application program interfaces (APIs), etc. Kernel space 325 can further include a display driver 330. Display driver 330 can be configured to control display processor 127. For example, display driver 330 can cause display processor 127 to compose frames and send data for the frames to a display.

[0057] Display processor 127 includes a display control block 335 and a display interface 340. Display processor 127 can be configured to manipulate functionality of display 131 (e.g., based on input received from display driver 330). Display control block 335 can be further configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 can additionally or alternatively perform post-processing of image data provided based on processing unit 120’s execution of system memory 124.

[0058] Display interface 340 can be configured to cause display 131 to display image frames. Display interface 340 can output image data to display 131 according to an interface protocol, such as, for example, MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface). That is, display 131 can be configured according to the MIPI DSI standard. The MIPI DSI standard supports a video mode and a command mode. In examples where display 131 operates in the video mode, display processor 127 can continuously refresh graphical content of display 131. For example, the entire graphical content can be refreshed (e.g., line-by-line) at each refresh period. In examples where display 131 operates in the command mode, display processor 127 can write graphical content for a frame to a buffer 350.

[0059] In some such examples, display processor 127 can not continuously refresh graphical content of display 131. Rather, display processor 127 can use a vertical sync (Vsync) pulse to coordinate rendering and consumption of graphical content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 can output new graphical content to buffer 350. Thus, generation of a Vsync pulse can indicate that current graphical content has been rendered at buffer 350.

[0060] Based on display controller 345, display client 355, and buffer 350, frames are displayed at display 131. Display controller 345 can receive image data from display interface 340 and store the received image data in buffer 350. In some examples, display controller 345 can output image data stored in buffer 350 to display client 355. Thus, buffer 350 can represent local memory to display 131. In some examples, display controller 345 can output image data received from display interface 340 directly to display client 355.

[0061] Display client 355 can be associated with a touch panel that senses interaction between a user and display 131. When a user interacts with display 131, one or more sensors in the touch panel can output a signal to display controller 345 indicating which of the one or more sensors has sensor activity, a duration of the sensor activity, a pressure applied to the one or more sensors, and the like. Display controller 345 can use the sensor output to determine a manner in which the user interacts with display 131. Display 131 can further be associated with / include other devices that operate in conjunction with display client 355, such as a camera, a microphone, and / or a speaker.

[0062] Figure 4is a diagram 400 illustrating an example of a high-throughput DPU configuration. A GPU 402 can obtain a first frame 404A and a second frame 404B. The first frame 404A and the second frame 404B can be associated with user content (UC) to be displayed to a user (e.g., concurrently displayed to the user). In one example, the first frame 404A can be for display on a first display 406A of a wearable headset 408, and the second frame 404B can be for display on a second display 406B of the wearable headset 408. For example, the first frame 404A can be for display to a left eye of the user, and the second frame 404B can be for display to a right eye of the user. In one example, the first display 406A and the second display 406B can be embedded DisplayPort (eDP) displays. In another example, the first display 406A and the second display 406B can be part of a single display panel, i.e., the first display 406A can be a first portion (e.g., a left portion) of a single display and the second display 406B can be a second portion (e.g., a right portion) of the single display. The wearable headset 408 can be an augmented reality (AR) headset, a virtual reality (VR) headset, a mixed reality (MR) headset, and / or an extended reality (XR) headset. Accordingly, the first frame 404A and the second frame 404B can be associated with AR content, VR content, MR content, and / or XR content. In one example, the first frame 404A and the second frame 404B can have a resolution of 4300 x 4300 pixels.

[0063] The GPU 402 can provide the first frame 404A to a first DPU 410A (labeled as “DPU0” in Figure 4 The first DPU 410A can be included in the wearable headset 408. The first DPU 410A can divide the first frame 404A into a first slice 412A and an Nth slice 412B, where N is a positive integer greater than one. The first slice 412A and the Nth slice 412B can be collectively referred to as a “first plurality of slices 412A-412B.” In one example, each slice of the first plurality of slices 412A-412B can be a vertical slice. In an example where N is 4, each slice of the first plurality of slices 412A-412B can have a resolution of 1075 x 4300 pixels. In an example where N is 2, each slice of the first plurality of slices 412A-412B can have a resolution of 2150 x 4300 pixels.

[0064] The first DPU 410A can perform color artifact correction (CAC) on each slice of the first plurality of slices 412A-B. Color artifacts can refer to optical aberrations caused by a lens not being able to focus all colors at the same point. Color artifacts can be observed as color fringes along a border separating dark and light portions of an image. CAC can refer to a process that minimizes color artifacts.

[0065] The first DPU 410A can perform scaling / DSC operations on each slice of the first plurality of slices 412A-B. Scaling / DSC operations can refer to display stream compression. Display stream compression can be a visual lossless compression that reduces bandwidth demand on a DPU. The first DPU 410A can merge each slice of the first plurality of slices 412A-B to generate a first processed frame 414A. The first processed frame 414A can have the same resolution as the first frame 404A (e.g., 4300 x 4300 pixels). A first embedded DisplayPort (eDP) controller 416 of the first DPU 410A can cause the first processed frame 414A to be displayed on the first display 406A (e.g., via an eDP interface).

[0066] The eDP crossbar (e.g.,“eDP XBAR 418”) can be associated with the first DPU 410A and the second DPU 410B (labeled“DPU1” in Figure 4 In one example, the eDP XBAR 418 can be part of the first DPU 410A and / or the second DPU 410B. The eDP XBAR 418 can obtain an indication that the UC is to be displayed (e.g., rendered) at a high resolution (e.g., 4300 x 4300 pixels on each of the first display 406A and the second display 406B). The eDP XBAR 418 can determine, based on the indication, that the second DPU 410B is to be utilized to drive display of the second frame 404B. In one aspect, the eDP XBAR 418 can be an XBAR module that can be implemented to multiplex (MUX) eDP interfaces from controllers of the first DPU 410A and the second DPU 410B. The eDP XBAR 418 can be software controllable. According to examples, the eDP XBAR 418 can be controlled by a display driver, display driver software, or a CPU. In one example, the first DPU 410A and the second DPU 410B can be part of a system on a chip (SOC).

[0067] Based on the output of the eDP XBAR 418, the GPU 402 can provide the second frame 404B to the second DPU 410B. The second DPU 410B can be included in the wearable headset 408. The second DPU 410B can divide the second frame 404B into a first tile 420A and an Nth tile 420B, where N is a positive integer greater than one. The first tile 420A and the Nth tile 420B can be collectively referred to as a “second plurality of tiles 420A-420B.” In one example, each tile of the second plurality of tiles 420A-420B can be a vertical tile. In an example where N is 4, each tile of the second plurality of tiles 420A-420B can have a resolution of 1075 x 4300 pixels. In an example where N is 2, each tile of the second plurality of tiles 420A-420B can have a resolution of 2150 x 4300 pixels.

[0068] The second DPU 410B can perform CAC on each tile of the second plurality of tiles 420A-420B. The second DPU 410B can perform scaling / DSC operations on each tile of the second plurality of tiles 420A-420B. The second DPU 410B can merge each tile of the second plurality of tiles 420A-420B to generate a second processed frame 414B. The second processed frame 414B can have the same resolution as the second frame 404B (e.g., 4300 x 4300 pixels). The eDP controller 422 of the second DPU 410B can cause the second processed frame 414B to be displayed on the second display 406B concurrently with the first processed frame 414A (e.g., via the eDP interface). The second eDP controller 424 of the first DPU 410A can remain inactive based on the eDP XBAR 418 determining that the UC is to be rendered at a high resolution.

[0069] Figure 5 FIG. 500 is a diagram that illustrates an example of a low-throughput DPU configuration. In the low-throughput DPU configuration, the eDP XBAR 418 can obtain an indication that the UC is to be displayed (e.g., rendered) at a low resolution (e.g., 2048 x 2048 pixels on each of the first display 406A and the second display 406B). The eDP XBAR 418 can determine, based on the indication, that the second eDP controller 424 of the first DPU 410A is to be utilized to drive display of the second frame 404B, while the second DPU 410B is to be placed in a power collapse state. The term power collapse state can refer to a situation in which power is removed (i.e., current and voltage are cut off) from a DPU. In one example, the power collapse state can be a global distributed switch (GDS) power collapse state.

[0070] In a low-throughput DPU configuration, GPU 402 can obtain a first frame 404A and a second frame 404B. Based on a determination by eDP XBAR 418, GPU 402 can provide first frame 404A and second frame 404B to first DPU 410A. First DPU 410A can divide first frame 404A and second frame 404B into a first plurality of slices 412A-412B and a second plurality of slices 420A-420B. In one example, each slice of first plurality of slices 412A-412B and each slice of second plurality of slices 420A-420B can have a resolution of 1024 x 2048 pixels. First DPU 410A can perform CAC on each of first plurality of slices 412A-412B and second plurality of slices 420A-420B. First DPU 410A can perform scaling / DSC operations on each slice of first plurality of slices 412A-412B and each slice of second plurality of slices 420A-420B. First DPU 410A can merge each slice of first plurality of slices 412A-412B to generate a first processed frame 414A. First DPU 410A can merge each slice of second plurality of slices 420A-420B to generate a second processed frame 414B.

[0071] First eDP controller of first DPU 410A can cause first processed frame 414A to be displayed on first display 406A. Similarly, based on a determination by eDP XBAR 418, second eDP controller 424 of first DPU 410A can cause second processed frame 414B to be displayed on second display 406B concurrently with first processed frame 414A being displayed on first display 406A.

[0072] Figure 6 FIG. 600 is a diagram illustrating an example of a DPU pipeline associated with first DPU 410A. The DPU pipeline can be associated with a throughput of four pixels per clock cycle. First DPU 410A can divide first frame 404A (not illustrated in FIG. 6OO) into first plurality of slices 412A-412B. First DPU 410A can perform a first direct memory access (DMA) operation 602 with respect to a first subset of first plurality of slices 412A-412B (e.g., two slices). DMA can refer to an operation by which a DPU can directly pixel access double data rate (DDR) memory and send data for display without scaling. First DPU 410A can perform a second DMA operation 604 with respect to a second subset of first plurality of slices 412A-412B. Figure 6

[0073] ​The first DPU 410A can perform a first VIG operation 606 on a first slice of a first subset of the first plurality of slices 412A-B. The VIG operation can refer to an operation performed by a video input processing unit. The first DPU 410A can perform a second VIG operation 608 on a second slice of the first subset of the first plurality of slices 412A-B. The first DPU 410A can perform a third DMA operation 610 with respect to the first subset of the plurality of slices 412A-B.

[0074] The first DPU 410A can perform a third VIG operation 612 on a third slice of a second subset of the first plurality of slices 412A-B. The first DPU 410A can perform a fourth VIG operation 614 on a fourth slice of the second subset of the first plurality of slices 412A-B. The first DPU 410A can perform a fourth DMA operation 616 with respect to the first subset of the plurality of slices 412A-B.

[0075] The first DPU 410A can perform a first layer mixer (LM) operation 618 on a first slice of the first subset of the first plurality of slices 412A-B. The LM operation can refer to a per-pixel blending of pixels associated with different DMA operations and different VIG operations to produce a final output pixel. The first DPU 410A can perform a second LM operation 620 on a second slice of the first subset of the first plurality of slices 412A-B. The first DPU 410A can perform a third LM operation 622 on a third slice of the second subset of the first plurality of slices 412A-B. The first DPU 410A can perform a fourth LM operation 624 on a fourth slice of the second subset of the first plurality of slices 412A-B.

[0076] The first DPU 410A can perform a first DST scaling operation 626 on a first slice of the first subset of the first plurality of slices 412A-B. The DST scaling operation can refer to a scaling operation performed with respect to an intended destination (e.g., a display panel) of the slice. The first DPU 410A can perform a second DST scaling operation 628 on a second slice of the first subset of the first plurality of slices 412A-B. The first DPU 410A can perform a third DST scaling operation 630 on a third slice of the second subset of the first plurality of slices 412A-B. The first DPU 410A can perform a fourth DST scaling operation 632 on a fourth slice of the second subset of the first plurality of slices 412A-B.

[0077] The first DPU 410A can perform a first ping-pong buffer (PPB) operation 634 on a first slice of a first subset of the first plurality of slices 412A-B. A PPB can refer to a memory storage system in which two buffers are utilized in order to prevent inefficient memory access. For example, ping-pong buffering can be a manner in which data / memory is stored in multiple buffers such that different portions of the system can utilize the multiple buffers simultaneously and without memory access conflicts. The first DPU 410A can perform a second PPB operation 636 on a second slice of the first subset of the first plurality of slices 412A-B. The first DPU 410A can perform a third PPB operation 638 on a third slice of a second subset of the first plurality of slices 412A-B. The first DPU 410A can perform a fourth PPB operation 640 on a fourth slice of the second subset of the first plurality of slices 412A-B.

[0078] The first DPU 410A can perform a first DSC / VDC operation 642 on a first slice of a first subset of the first plurality of slices 412A-B. DSC can refer to display stream compression and VDC can refer to video display stream compression. The first DPU 410A can perform a second DSC / VDC operation 644 on a second slice of the first subset of the first plurality of slices 412A-B. The first DPU 410A can merge an output of the first DSC / VDC operation 642 and an output of the second DSC / VDC operation 644. The first DPU 410A can perform a third DSC / VDC operation 646 on a third slice of a second subset of the first plurality of slices 412A-B. The first DPU 410A can perform a fourth DSC / VDC operation 648 on a fourth slice of the second subset of the first plurality of slices 412A-B. The first DPU 410A can merge an output of the third DSC / VDC operation 646 and an output of the fourth DSC / VDC operation 648.

[0079] The first DPU 410A can perform a four-way merge operation 650 to merge the output of the first DSC / VDC operation 642 and the output of the second DSC / VDC operation 644 with the output of the third DSC / VDC operation 646 and the fourth DSC / VDC operation 648. A four-way merge operation can refer to concatenating four separate processed display slices into a single combined display output. The first DPU 410A can provide an output of the four-way merge operation 650 to an eDP interface / display serial interface (DSI) 652. The eDP interface / DSI 652 can output the first processed frame 414A.

[0080] Figure 7is a diagram 700 illustrating an example of a DPU pipeline associated with the second DPU 410B. The DPU pipeline can be associated with a throughput of four pixels per clock cycle. The second DPU 410B can divide the second frame 404B (not illustrated in the middle) into a second plurality of slices 420A-420B. The second DPU 410B can perform a first DMA operation 702 with respect to a first subset (e.g., two slices) of the second plurality of slices 420A-420B. The second DPU 410B can perform a second DMA operation 704 with respect to a second subset of the second plurality of slices 420A-420B. Figure 6

[0081] The second DPU 410B can perform a first VIG operation 706 on a first slice of the first subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a second VIG operation 708 on a second slice of the first subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a third DMA operation 710 with respect to the first subset of the second plurality of slices 420A-420B.

[0082] The second DPU 410B can perform a third VIG operation 712 on a third slice of the second subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a fourth VIG operation 714 on a fourth slice of the second subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a fourth DMA operation 716 with respect to the first subset of the second plurality of slices 420A-420B.

[0083] The second DPU 410B can perform a first LM operation 718 on the first slice of the first subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a second LM operation 720 on the second slice of the first subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a third LM operation 722 on the third slice of the second subset of the second plurality of slices 420A-420B. The second DPU 410B can perform a fourth LM operation 724 on the fourth slice of the second subset of the second plurality of slices 420A-420B.

[0084] ​The second DPU 410B can perform a first DST scaling operation 726 on a first slice of the first subset of the second plurality of slices 420A-B. The second DPU 410B can perform a second DST scaling operation 728 on a second slice of the first subset of the second plurality of slices 420A-B. The second DPU 410B can perform a third DST scaling operation 730 on a third slice of the second subset of the second plurality of slices 420A-B. The second DPU 410B can perform a fourth DST scaling operation 732 on a fourth slice of the second subset of the second plurality of slices 420A-B.

[0085] The second DPU 410B can perform a first PPB operation 734 on the first slice of the first subset of the second plurality of slices 420A-B. The second DPU 410B can perform a second PPB operation 736 on the second slice of the first subset of the second plurality of slices 420A-B. The second DPU 410B can perform a third PPB operation 738 on the third slice of the second subset of the second plurality of slices 420A-B. The second DPU 410B can perform a fourth PPB operation 740 on the fourth slice of the second subset of the second plurality of slices 420A-B.

[0086] The second DPU 410B can perform a first DSC / VDC operation 742 on the first slice of the first subset of the second plurality of slices 420A-B. The second DPU 410B can perform a second DSC / VDC operation 744 on the second slice of the first subset of the second plurality of slices 420A-B. The second DPU 410B can merge the output of the first DSC / VDC operation 742 and the output of the second DSC / VDC operation 744. The second DPU 410B can perform a third DSC / VDC operation 746 on the third slice of the second subset of the second plurality of slices 420A-B. The second DPU 410B can perform a fourth DSC / VDC operation 748 on the fourth slice of the second subset of the second plurality of slices 420A-B. The second DPU 410B can merge the output of the third DSC / VDC operation 746 and the output of the fourth DSC / VDC operation 748.

[0087] The second DPU 410B can perform a four-way merge operation 750 to merge the output of the first DSC / VDC operation 742 and the output of the second DSC / VDC operation 744 with the output of the third DSC / VDC operation 746 and the fourth DSC / VDC operation 748. The second DPU 410B can provide the output of the four-way merge operation 750 to the eDP interface / DSI 752. The eDP interface / DSI 752 can output the second processed frame 414B.

[0088] Figure 8 is a diagram 800 illustrating an example of a first DPU core 802. In one example, the first DPU core 802 can be included in the first DPU 410A. The first DPU core 802 can include a first controller 804 (referred to as “DPTX3” in Figure 8 ), a first root clock gate (RCG) 806, a first power switch (P.S) 808, a multiplexer 810 (referred to as “eDP PHY MUX” in Figure 8 ), and an eDP link 812 (referred to as “eDP” in Figure 8 ). The RCG can turn on or off a clock to a hardware block. In one example, if a hardware block is not being utilized, the RCG can be turned off to conserve power. The first DPU core 802 can also include a second controller 814 (referred to as “DPTX2” in Figure 8 ), a second RCG 816, and a second P.S 818. The eDP link 812 can also be referred to as an eDP interface. The eDP link 812 can be associated with a first display (or a first portion of a display). In one example, the first display can be the first display 406A. The multiplexer 810 can correspond to the eDP XBAR 418. In one example, the first controller 804 can correspond to the first eDP controller 416 of the first DPU 410A, and the second controller 814 can correspond to the second eDP controller 424 of the first DPU 410A.

[0089] The first controller 804 can be coupled to the multiplexer 810 via a software interface (SWI) interface and an auxiliary interface. The SWI interface can be associated with software. The auxiliary interface can be an eDP auxiliary data channel. Additionally, the first controller can be coupled to the multiplexer 810 via the first P.S 808 and a link interface. The link interface can be an eDP main data link channel. The first controller 804 can also be coupled to the first RCG 806. The multiplexer 810 can be coupled to the eDP link 812 via the SWI interface, the auxiliary interface, and the link interface. The eDP link 812 can be coupled to the first RCG 806.

[0090] The second controller 814 can be coupled to the second RCG 816. The first RCG 806, the second RCG 816, the first P.S 808, the second P.S 818, and the multiplexer 810 can be associated with an MX domain 820. The MX domain 820 can refer to a SOC internal static random access memory (SRAM) voltage domain. The first controller 804 and the second controller 814 can be associated with a DPU internal MMCX domain 822. MMCX can refer to a multimedia logic voltage domain.

[0091] Figure 9is a diagram 900 illustrating an example of a second DPU core 902. In one example, the second DPU core 902 is included in the first DPU 410A. The second DPU core 902 can include a first controller 904 (referred to as "DPTX3" in Figure 9 ), a first RCG 906, a first power switch (P.S) 908, a multiplexer 910 (referred to as "eDP PHY MUX" in Figure 9 ), and an eDP link 912 (referred to as "eDP" in Figure 8 ). The eDP link 812 can also be referred to as an eDP interface. The eDP link 912 can be associated with a second display (or a second portion of a display). In one example, the second display can be the second display 406B. The second DPU core 902 can also include a second controller 914 (referred to as "DPTX2" in Figure 9 ), a second RCG 916, and a second P.S 918. In one aspect, the second controller 914, the second RCG 916, and the second P.S 918 can not be utilized during operation of the second DPU core 902. The multiplexer 910 can correspond to the eDP XBAR 418. In one example, the first controller 904 can correspond to the eDP controller 422 of the second DPU 410B.

[0092] The first controller 904 can be coupled to the multiplexer 910 via a SWI interface and an auxiliary interface. Additionally, the first controller 904 can be coupled to the multiplexer 910 via the first P.S 908 and a link interface. The first controller 904 can also be coupled to the first RCG 906. The multiplexer 910 can be coupled to the eDP link 912 via the SWI interface, the auxiliary interface, and the link interface. The eDP link 912 can be coupled to the first RCG 906.

[0093] The second controller 914 can be coupled to the second RCG 916. The first RCG 906, the second RCG 916, the first P.S 908, the second P.S 918, and the multiplexer 910 can be associated with the MX domain 820. The first controller 904 and the second controller 914 can be associated with the DPU internal MMCX domain 822. The first DPU core 802 and the second DPU core 902 can be part of a SOC.

[0094] Referring now to Figure 8 and Figure 9 , the second RCG 816 of the first DPU core 802 can be coupled to the first RCG 906 of the second DPU core 902 (referred to as "DPTX3" in Figure 8 and Figure 9 ).(Indicated by "A" in the middle). The second controller 814 can be coupled to the multiplexer 910 of the second DPU core 902 via the SWI interface and auxiliary interface (in Figure 8 and Figure 9 (Indicated by "B" in the middle). The second controller 814 can also be coupled to the multiplexer 910 via a link interface and via the second PS 818 (in Figure 8 and Figure 9 (Also indicated by "B").

[0095] In one example, the first DPU core 802 can act as the master DPU. Therefore, the multiplexer 810 can receive an indication that the first DPU core 802 will act as the master DPU (e.g., "Edp_phy_mux_sel = 0"). The first DPU core 802 can provide an indication to the multiplexer 910 of the second DPU core 902 regarding whether the second DPU core 902 should drive the eDP link 912 of the second DPU core 902 (e.g., "Edp_phy_mux_sel = 0") or whether the second controller 814 of the first DPU core 802 should drive the eDP link 912 of the second DPU core 902 (e.g., "Edp_phy_mux_sel = 1") (in...). Figure 4 and Figure 5 (Example: "C"). Multiplexer 910 can also receive data / signals from second controller 814 via SWI interface, auxiliary interface, and link interface. In one example, the value of "Edp_phy_mux_sel" can be software-controllable. For example, the value of "Edp_phy_mux_sel" can be set in a software register.

[0096] To display a high-resolution UC (e.g., as mentioned above) Figure 10 In the example of the high-throughput DPU configuration associated with the UC described in the description, "Edp_phy_mux_sel" can be set to "0". In this example, both the first DPU core 802 and the second DPU core 902 can be in an "on" state. The first controller 804 of the first DPU core 802 can drive the eDP link 812, and the first controller 904 of the second DPU core 902 can drive the eDP link 912 based on a signal output by the multiplexer 910, where the signal can be based on "Edp_phy_mux_sel" being set to "0". For example, the first controller 804 can cause the first UC to be displayed on a first display (or a first portion of a single display), and the first controller 904 can cause the second UC to be displayed on a second display (or a second portion of a single display).

[0097] To display a low-resolution UC (e.g., as mentioned above) Figure 10In the example of the low-throughput DPU configuration associated with the UC described in the description of FIG. 8, “Edp_phy_mux_sel” can be set to “1”. In this example, the first DPU core 802 can be in the “on” state and the second DPU core 902 can be in the GDS power collapse state. The first controller 804 of the first DPU core 802 can drive the eDP link 812. The second controller 814 of the first DPU core 802 can drive the eDP link 912 based on a signal output by the multiplexer 910, where the signal can be based on “Edp_phy_mux_sel” being set to “1”. For example, the first controller 804 can cause a first UC to be displayed on a first display (or a first portion of a single display) and the second controller 814 can cause a second UC to be displayed on a second display (or a second portion of a single display). In one aspect, a clock from a phase-locked loop (PLL) associated with the eDP link 912 can be routed to the first RCG 906 and the second RCG 816.

[0098] Figure 10 is a diagram 1000 illustrating an example implementation of the multiplexer 910. As Figure 10 depicted, the multiplexer 910 can include a first multiplexer 1002, a second multiplexer 1004, a third multiplexer 1006, a fourth multiplexer 1008, a fifth multiplexer 1010, a sixth multiplexer 1012, a seventh multiplexer 1014, and an eighth multiplexer 1016 (collectively, “a plurality of multiplexers 1002-1016). Generally, a multiplexer of the plurality of multiplexers 1002-1016 can be configured to receive data / signals (indicated in Figure 11 by the arrows entering the multiplexer) as inputs from various sources (e.g., other multiplexers of the plurality of multiplexers, the second P.S 818, the first P.S. 908, the second RCG 816, the first RCG 906, the eDP link 912, various software registers (such as a software register associated with “Edp_phy_mux_sel”), a display driver, etc.). The multiplexer of the plurality of multiplexers 1002-1016 can be configured to output data or signals (indicated in Figure 11 by the arrows exiting the multiplexer) based on the inputs.

[0099] Figure 11 is a diagram 1100 illustrating examples of interfaces of a DPU core. The diagram 1100 depicts a first example 1102 and a second example 1104. The first example 1102 can include a first DPU 1106 (referred to in Figure 11 as “DPU0”). The first DPU 1106 can be referred to as a “primary DPU”. The first DPU 1106 can include a primary interface 1108 (referred to in Figure 11In the interface, it is referred to as "main INTF" and slave interface 1110 (in Figure 11 (Referring to "Slave INTF" in the original text). The master interface 1108 and slave interface 1110 can drive multiple display panels (or different portions of the same display panel). In the case of a high-resolution UC, multiple interfaces (e.g., multiple master and slave interfaces) can be used to drive a single panel. In one example, the master interface 1108 can drive the first half of a frame to be displayed, and the slave interface 1110 can drive the second half of that frame. The master interface 1108 can be configured to provide timing (e.g., "TIMEGEN_EN") to the slave interface 1110 so that the first half and the second half of the frame are displayed correctly. In other words, the master interface 1108 can enable the timing engine of the slave interface 1110. The first DPU 1106 can be or includes a first DPU 410A and / or a first DPU core 802.

[0100] The first example 1102 may also include a second DPU 1112 (in Figure 11 The first DPU 1106 is referred to as "DPU1" in this context. The second DPU 1112 may be referred to as "Slave DPU". The second DPU 1112 may include a master interface 1114 and a slave interface 1116. The master interface 1114 and slave interface 1116 can drive multiple display panels. The master interface 1108 of the first DPU 1106 can provide timing to the master interface 1114 of the second DPU 1112. The master interface 1114 of the second DPU 1112 can be configured to receive timing (e.g., "TIMEGEN_EN") from the master interface 1108 of the first DPU 1106. In other words, the master interface 1108 of the first DPU 1106 can enable the timing engine of the master interface 1114 of the second DPU 1112. The master interface of the second DPU 1112 can be configured to accept "TIMEGEN_EN" via a multiplexer (e.g., "TIMING_EN_MUX"). Therefore, the second DPU 1112 can follow the timing of the first DPU 1106. The master interface 1114 of the second DPU 1112 can be configured to provide timing (e.g., "TIMEGEN_EN") to the slave interface 1116 of the second DPU 1112. In other words, the master interface 1114 can enable the timing engine of the slave interface 1116. The second DPU 1112 can be or includes the second DPU 410B and / or the second DPU core 902.

[0101] In one aspect, the video timing of the master interface 1108 of the first DPU 1106 can be ahead of the video timing of the master interface 1114 of the second DPU 1112. In one aspect, the delay / offset between the first DPU 1106 and the second DPU 1112 can be software controllable. In one aspect, the first DPU 1106 and the second DPU 1112 can be associated with a first software register (e.g., "DPU_SYNC_PROG_INTF_OFFSET_EN"). The first software register can have a field that can take a value. The value can be a 32-bit value (e.g., bit position 31 : bit position 0). In one example, the value can have a default value of "0xFFFFFFFF". The first software register can refer to a programmable offset (in processor clock (pclk) cycles) to enable from other timing engines in the DPU (e.g., the second DPU 1112). The value of the first register can not be double buffered. In one aspect, the first DPU 1106 and the second DPU 1112 can be associated with a second software register (e.g., "TIMING_EN_MUX"). The second software register can have a field that indicates a selection. The field can have a 1-bit value (e.g., bit position 0). The second software register can select a timing engine to enable. In one example, when the second software register is set to a "0" bit, the DPU (e.g., the second DPU 1112) can follow the timing of the DPU's internal register (e.g., "TIMING_ENGINE_EN"). When the software register is set to a "1" bit, the DPU (e.g., the second DPU 1112) can follow the timing of the master DPU (e.g., the first DPU 1106).

[0102] The second example 1104 can also include the first DPU 1106 and the second DPU 1112 described above. The second example 1104 can have similar functionality as the first example 1102 described above. However, in the second example 1104, the master interface 1108 of the first DPU 1106 can additionally provide timing to the master interface 1120 of a third DPU 1118 (referred to as "DPU2" in Figure 12 ) and the master interface 1126 of a fourth DPU 1124 (referred to as "DPU3" in Figure 12 ). The master interface 1120 of the third DPU 1118 can be configured to provide timing to the slave interface 1122 of the third DPU 1118 (described above), and the master interface 1126 of the fourth DPU 1124 can be configured to provide timing to the slave interface 1128 of the fourth DPU 1124.

[0103] Figure 12 is a diagram 1200 illustrating an example of timing synchronization between DPU cores. The diagram 1200 depicts a first DPU core 1202 (referred to as "DPU0" inFigure 12 referred to as "DPU0") and a second DPU core 1204 (referred to as "DPU1") in Figure 12 one example, the first DPU core 1202 can correspond to the first DPU 1106, and the second DPU core 1204 can correspond to the second DPU 1112. The first DPU core 1202 can include a first interface 1206 (referred to as "INTF1") and a second interface 1208 (referred to as "INTF5") in Figure 12 one example, the first interface 1206 can correspond to the master interface 1108, and the second interface 1208 can correspond to the slave interface 1110. The second DPU core 1204 can include a first interface 1210 (referred to as "INTF1") and a second interface 1212 (referred to as "INTF5") in Figure 12 one example, the first interface 1210 can correspond to the master interface 1114, and the second interface 1212 can correspond to the slave interface 1116. Figure 12 Figure 12 The first interface 1206 of the first DPU core 1202 can be associated with a counter 1214 (referred to as "Vsync count") in The counter 1214 can be associated with a timing engine of the first DPU core 1202. The counter 1214 can count a number of clock cycles for each frame to be displayed. The counter 1214 can be a vertical sync (Vsync) timer. Vsync timing is a means of synchronizing the frame rate of an application (e.g., a video game) with the refresh rate of a corresponding display or monitor. A DPU, GPU, and / or application can utilize Vsync timing to eliminate certain visual artifacts, such as screen tearing (i.e., a split in a portion of a displayed frame, where one portion of the frame lags behind other portions). When the counter 1214 reaches a programmable value (referred to as "Q_DPU_SYNC_PROG_INTF_OFFSET_EN_VALUE0") in

[0104] The first interface 1206 can drive an output signal (referred to as "o_dpu_offset_time_gen_en") to the second DPU core 1204 (i.e., the slave DPU core) that enables the timing engine when the counter 1214 reaches the programmable value. The programmable value can correspond to a value of the first software register ("DPU_SYNC_PROG_INTF_OFFSET_EN") described above. The programmable value can be an offset value. Figure 12 Figure 12 The first interface 1206 of the first DPU core 1202 can be associated with a counter 1214 (referred to as "Vsync count") in Figure 12 The counter 1214 can be associated with a timing engine of the first DPU core 1202. The counter 1214 can count a number of clock cycles for each frame to be displayed. The counter 1214 can be a vertical sync (Vsync) timer. Vsync timing is a means of synchronizing the frame rate of an application (e.g., a video game) with the refresh rate of a corresponding display or monitor. A DPU, GPU, and / or application can utilize Vsync timing to eliminate certain visual artifacts, such as screen tearing (i.e., a split in a portion of a displayed frame, where one portion of the frame lags behind other portions). When the counter 1214 reaches a programmable value (referred to as "Q_DPU_SYNC_PROG_INTF_OFFSET_EN_VALUE0") in

[0105] ​In one example, the first DPU core 1202 can include a first multiplexer 1216. The first multiplexer 1216 can select an active display timing interface from a plurality of possible display timing interfaces and output a signal associated with the selected timing interface to the second DPU core 1204. The first multiplexer 1216 can receive an output signal (o_dpu_offset_time_gen_en) and another output signal from the second interface 1208. The first multiplexer can also receive a "q_dpu_syn_intf_mux_sel" which can be a signal that selects which timing interface is active in the hardware. The multiplexer can output a timing engine enable signal (referred to in Figure 13 the middle as "dpu_offset_time_gen_en") to the first interface 1210 and the second interface 1212 of the second DPU core 1204. For example, "dpu_offset_time_gen_en" can refer to a hardware function that can be enabled by software to have a fixed time offset of the display timing generated by the two timing interfaces.

[0106] The first interface 1210 of the second DPU core 1204 can receive the signals output from the first DPU core 1202. The first interface 1210 can include a second multiplexer 1218. The second multiplexer 1218 can accept the timing engine enable (e.g., "dpu_offset_time_gen_en") from the first interface 1206 of the first DPU core 1202 or the second multiplexer 1218 can accept the timing engine ("q_timing_intf_en_pclk") from an internally generated timing engine. As Figure 12 illustrated, "q_intf_tim_en_sel" can be a hardware function. For example, "q_timing_intf_en_pclk" can be a hardware function that synchronizes the start of the two timing interfaces. The incoming signal ("dpu_offset_time_gen_en") can be synchronized with the pclk domain and used as the timing engine enable.

[0107] Figure 14is a diagram 1300 illustrating an example of timing between different DPU interfaces. The diagram 1300 depicts a first example 1301 of synchronizing dual DPU cores. At 1302, the timing engine of the first interface 1206 (i.e., the master interface) of the first DPU core 1202 can be enabled. At 1304, the counter 1214 can start running. In one example, 1304 can correspond to the start of a frame on the first DPU core 1202. At 1306, the counter 1214 can reach the programmable value (‘Q_DPU_SYNC_PROG_INTF_OFFSET_EN_VALUE’) defined in the first software register (‘DPU_SYNC_PROG_INTF_OFFSET_EN’) described above, and the first interface 1206 can output the signal (‘dpu_offset_time_gen_en’) described above. At 1308, a second counter (not illustrated in the middle) associated with the first interface 1210 of the second DPU core 1204 can start running based on the first interface 1210 receiving the signal. In one example, 1308 can correspond to the start of a frame on the second DPU core 1204. In other words, the relative offset between the counter 1214 (i.e., the Vsync counter of the first DPU core 1202) and the second counter (i.e., the Vsync counter of the second DPU core 1204) can be offset by the programmable value (‘Q_DPU_SYNC_PROG_INTF_OFFSET_EN_VALUE’). Figure 14

[0108] The diagram 1300 also depicts a second example 1303 in which each DPU core includes two DSI interfaces. The second example 1303 depicts an example of the timing relationship between the first interface of the first DPU core, the second interface of the first DPU core, the first interface of the second DPU core, and the second interface of the second DPU core. The second example 1303 can be associated with the first example 1102 described above.

[0109] Figure 14 is a diagram 1400 illustrating example aspects of synchronization with respect to a clock of a master DPU 1402. The master DPU 1402 can be the first DPU 410A or the first DPU 1106. The master DPU 1402 can include the first DPU core 802 or the first DPU core 1202. The master DPU 1402 can include a master physical DSI 1404 (referred to as “DSI0 PHY (master)” in the middle) and a slave physical DSI 1406 (referred to as “DSI1 PHY (slave)” in the middle). Figure 14 Figure 14 ​​The master interface can generate a clock that is fed to both the master physical DSI 1404 and the slave physical DSI 1406, such that both the master physical DSI 1404 and the slave physical DSI 1406 can run / execute in sync in terms of display timing. The master DPU 1402 can include a first DSI RGG 1408 (referred to as "DSI0 RGG" in Figure 15 and a second DSI RGG 1410 (referred to as "DSI1 RGG" in Figure 14 ).

[0110] Figure 14 is a diagram 1500 illustrating example aspects with respect to clock synchronization of a slave DPU 1502. The slave DPU 1502 can be the second DPU 410B or the second DPU 1112. The slave DPU 1502 can include the second DPU core 902 or the second DPU core 1204. The slave DPU 1402 can include a master physical DSI 1504 (referred to as "DSI2 PHY (master)" in Figure 14 and a slave physical DSI 1506 (referred to as "DSI3 PHY (slave)" in Figure 14 ). The master DPU 1502 can include a first DSI RGG 1508 (referred to as "DSI2 RGG" in Figure 14 and a second DSI RGG 1510 (referred to as "DSI3 RGG" in Figure 15 ).

[0111] Referring now to Figure 14 and Figure 15 , the master physical DSI 1404 of the master DPU 1402 can be coupled to the master physical DSI 1504 of the slave DPU 1502 (indicated by "D" in Figure 14 and Figure 15 ). The master physical DSI 1404 of the master DPU 1402 can be coupled to the first DSI RCG 1508 and the second DSI RCG 1510 of the slave DPU 1502 via a first connection (indicated by "E" in Figure 14 and Figure 15 ). The master physical DSI 1404 of the master DPU 1402 can also be coupled to the first DSI RCG 1508 and the second DSI RCG 1510 of the slave DPU 1502 via a second connection (indicated by "F" in Figure 16 and Figure 17 ).

[0112] The master physical DSI 1404 of the master DPU 1402 can be configured to provide "DisphyO_aclk" to the master physical DSI 1504 of the slave DPU 1502, where "DisphyO_aclk" can refer to a DSI clock communicated between the master physical DSI 1404 and the master physical DSI 1504. The master physical DSI 1404 can also be configured to provide "Pll_dsiclk" to the first DSI RCG 1508 and the second DSI RCG 1510 of the slave DPU 1502 via a first connection. In one example, "Pll_dsiclk" can be a DSI clock output from a DSI PHY to a DSI clock controller / clock generator. The master physical DSI 1404 can also be configured to provide "Pll_byte_clk" to the first DSI RCG 1508 and the second DSI RCG 1510 of the slave DPU 1502 via a second connection. In one example, "Pll_byte_clk" can refer to a clock used by a DSI controller to send a DSI data stream from the DSI controller to a DSIPHY. In one aspect, a pixel clock can be generated from a master phase-locked loop (PLL) of the master DPU 1402, and the pixel clock can drive the logic of the interface of the slave DPU 1502.

[0113] Figure 1 to Figure 16 is a call flow diagram 1600 illustrating example communications between a DPU 1602 and a GPU 1604. The DPU 1602 can include a first DPU and a second DPU. In one example, the first DPU can be or include the first DPU 410A, the first DPU core 802, the first DPU 1106, the first DPU core 1202, or the master DPU 1402. In one example, the second DPU can be or include the second DPU 410B, the second DPU core 902, the second DPU 1112, the second DPU core 1204, or the slave DPU 1502.

[0114] At 1606, the first DPU can obtain, from the GPU 1604, an indication to display (e.g., render) a UC at a first resolution (e.g., a high resolution) or a second resolution (e.g., a low resolution), where the first resolution is greater than the second resolution. In one example, the UC is video content associated with an AR application, a VR application, or an MR application. At 1608, the first DPU can obtain the UC from the GPU 1604.

[0115] At 1610, the first DPU can determine, based on the indication, whether to display (e.g., render) the UC at the first resolution or the second resolution. At 1612, the first DPU can establish display timing at the first interface of the first DPU. At 1614, the first interface of the first DPU can provide the display timing to the second interface of the second DPU. At 1616, the first DPU and the second DPU can synchronize based on the display timing. At 1618, the first DPU can drive the first display via the first controller of the first DPU. At 1620A, in a case where the UC is to be displayed (e.g., rendered) at the first resolution, the second DPU can drive the second display via the controller of the second DPU. At 1620B, in a case where the UC is to be displayed (e.g., rendered) at the second resolution, the first DPU can drive the second display via the second controller of the first DPU.

[0116] Figure 16 is a flow diagram 1700 of an example method of display processing in accordance with one or more techniques of this disclosure. The method can be performed by an apparatus such as a device for display processing, a display processing unit (DPU) or other display processor, a wireless communication device, etc., as used in connection with various aspects described herein. In one example, the method can be performed by the DPU selector 198. Figure 4

[0117] At 1702, the apparatus (e.g., DPU) obtains an indication that a UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. For example, Figure 5 At 1606, it is shown that the first DPU (included in the DPU 1602) can obtain an indication that a UC is to be displayed at a first resolution or a second resolution. In one example, the UC can be or include the first frame 404A and the second frame 404B. In another example, the first resolution can be 4300 x 4300 pixels, as illustrated in Figure 16 , and the second resolution can be 2048 x 2048 pixels, as illustrated in Figure 8 In one example, 1702 can be performed by the DPU selector 198.

[0118] At 1704, the apparatus (e.g., DPU) drives, based on the indication, a first display via a first controller of the first DPU. For example, Figure 10 At 1618, it is shown that the first DPU (included in the DPU 1602) can drive a first display via a first controller of the first DPU. In one example, the first display can be the first display 406A, the first controller can be the first eDP controller 416, and the first DPU can be the first DPU 410A. In another example, the first controller and the first DPU can correspond to the above-mentioned​Figure 16 and Figure 16 The described aspects. For example, the first controller can be the first controller 804. In another example, the first DPU can be the first DPU 1106 or the master DPU 1402. The first DPU can also include the first DPU core 802 or the first DPU core 1202. In one example, 1704 can be performed by the DPU selector 198.

[0119] At 1706, the apparatus (e.g., DPU) drives the second display via a controller of the second DPU if the UC is to be displayed at the first resolution, or the apparatus (e.g., DPU) drives the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution. For example, Figure 4 At 1620A, it is shown that the second display can be driven via a controller of the second DPU if the UC is to be displayed at the first resolution, and Figure 5 At 1620B, it is shown that the second display can be driven via a second controller of the first DPU if the UC is to be displayed at the second resolution. In one example, the controller of the second DPU can be the eDP controller 422 and the second DPU can be the second DPU 410B. In one example, the second controller of the first DPU can be the second eDP controller 424. In another example, the controller of the second DPU can be the first controller 904. In another example, the second controller of the first DPU can be the second controller 814. In another example, the second display can be the second display 406B. In one example, 1706 can be performed by the DPU selector 198.

[0120] In one example, the UC can be associated with a VR application, an AR application, or an XR application. For example, Figure 5 and Figure 5 depicts a UC that can be associated with a VR application, an AR application, or an XR application.

[0121] In one aspect, the controller of the second DPU can be a first embedded eDP controller, the first controller of the first DPU can be a second eDP controller, and the second controller of the first DPU can be a third eDP controller. For example, the controller of the second DPU can be the eDP controller 422, the first controller of the first DPU can be the first eDP controller 416, and the second controller of the first DPU can be the second eDP controller 424.

[0122] In one aspect, the controller of the second DPU can be in a power collapse state if the UC is to be displayed at the second resolution. For example, Figure 4The eDP controller 422 of the second DPU 410B can be in a power collapse state, as illustrated, in a case where the UC is to be displayed at the second resolution.

[0123] In one aspect, the power collapse state can be a GDS collapse state. For example, Figure 5 The illustrated power collapse state can be a GDS collapse state.

[0124] In one aspect, the first resolution can be associated with a first throughput configuration, where the second resolution can be associated with a second throughput configuration. For example, the first throughput configuration can be associated with Figure 4 Aspects described can be associated with, and the second throughput configuration can be associated with Figure 6 Aspects described.

[0125] In one aspect, the apparatus (e.g., DPU) can divide frames of the UC into a first set of slices and a second set of slices. For example, Figure 4 The first frame 404A can be divided into a first plurality of slices 412A-412B and the second frame 404B can be divided into a second plurality of slices 420A-420B, as illustrated. In another example, Figure 4 The first frame 404A can be divided into a first plurality of slices 412A-412B, as illustrated.

[0126] In one aspect, the apparatus (e.g., DPU) can provide the first set of slices to a first controller of the first DPU. For example, Figure 5 The first plurality of slices 412A-412B can be provided to a first controller of the first DPU 410A, as illustrated.

[0127] In one aspect, the apparatus (e.g., DPU) can provide the second set of slices to a controller of the second DPU, in a case where the UC is to be displayed at the first resolution. For example, Figure 5 The second plurality of slices 420A-420B can be provided to a second controller (e.g., eDP controller 422) of the second DPU 410B, as illustrated, in a case where the UC is to be displayed at the first resolution.

[0128] In one aspect, the apparatus (e.g., DPU) can divide frames of the UC into a first set of slices and a second set of slices. For example, Figure 5 The frames can be divided into a first set of slices and a second set of slices, as illustrated.

[0129] In one aspect, the apparatus (e.g., DPU) can provide the first set of slices to a first controller of the first DPU. For example, Figure 4 The first set of slices can be provided to a first controller (e.g., first eDP controller 416) of the first DPU 410A, as illustrated.

[0130] In one aspect, the apparatus (e.g., DPU) can provide the second set of slices to a second controller of the first DPU in a case where the UC is to be displayed at the second resolution. For example, Figure 5 The second set of slices can be provided to a second controller (e.g., second eDP controller 424) of the first DPU 410A is illustrated.

[0131] In one aspect, driving the first display can include sending a first indication to the first display to cause a first UC associated with the UC to be displayed on the first display, and driving the second display can include sending a second indication to the second display to cause a second UC associated with the UC to be displayed on the second display. For example, Figure 10 and Figure 8 It is shown that the first processed frame 414A (i.e., the first UC) can be displayed on the first display 406A and the second processed frame 414B (i.e., the second UC) can be displayed on the second display 406B.

[0132] In one aspect, the MUX can multiplex a first signal associated with the first DPU and a second signal associated with the second DPU, and driving the second display can be based on the multiplexing of the first signal and the second signal. For example, the MUX can be the multiplexer 910, and the multiplexer 910 can multiplex a first signal associated with the first DPU and a second signal associated with the second DPU. In another example, the MUX can include aspects described in connection with Figure 9

[0133] In one aspect, the MUX can be controlled by at least one of: software, a display driver, display driver software, a first display driver associated with the first DPU, a second display driver associated with the second DPU, or a CPU. For example, the multiplexer 910 can be controlled by software, a display driver, display driver software, a first display driver associated with the first DPU, a second display driver associated with the second DPU, and / or a CPU.

[0134] In one aspect, obtaining an indication that the UC is to be displayed can include setting a bit of a register of software or display driver software, where in a case where the UC is to be displayed at the first resolution, the bit can be set to a first bit, where in a case where the UC is to be displayed at the second resolution, the bit can be set to a second bit, where the first bit is different than the second bit. For example, the bit of the register of the software or display driver software can be associated with aspects described in connection with Figure 16 and Figure 4

[0135] ​​In one aspect, the first DPU and the second DPU can be associated with a SOC. For example, the first DPU 410A and the second DPU 410B can be associated with a SOC.

[0136] In one aspect, the apparatus (e.g., DPU) can receive the UC from the GPU prior to driving the first display and prior to driving the second display. For example, Figure 5 Receiving the UC from the GPU 1604 is shown at 1608.

[0137] In one aspect, the first display and the second display can be included by a headset worn on a head of a user. For example, the headset worn on the head of the user can be Figure 16 and Figure 11 the illustrated headset.

[0138] In one aspect, a clock output of a PLL associated with the controller is routed to a first RCG of the second DPU and a second RCG of the first DPU. For example, a clock output of a PLL associated with the first controller can be routed to the first RCG 906 of the second DPU core 902 and the second RCG 816 of the first DPU core 802.

[0139] In one aspect, the apparatus (e.g., DPU) can establish display timing at a first interface of the first DPU. For example, Figure 12 Establishing the display timing at the first interface of the first DPU is shown at 1612. For example, Figure 16 Establishing the display timing (e.g., “TIMEGEN_EN”) at the master interface 1108 of the first DPU 1106 is shown. In another example, Figure 11 Establishing the display timing at the first interface 1206 of the first DPU core 1202 is shown.

[0140] In one aspect, the apparatus (e.g., DPU) can synchronize the first DPU and the second DPU based on the display timing. For example, Figure 12 Synchronizing the first DPU and the second DPU based on the display timing is shown at 1616. For example, Figure 16 Synchronizing the first DPU 1106 and the second DPU 1112 based on the display timing is illustrated. For example, Figure 11 Synchronizing the first DPU core 1202 and the second DPU core 1204 based on the display timing is illustrated.

[0141] In one aspect, the apparatus (e.g., DPU) can provide the display timing to a second interface of the second DPU prior to synchronizing the first DPU with the second DPU. For example, Figure 11The display timing can be provided to a second interface of a second DPU, as shown at 1614. For example, Figure 12 The first DPU 1106 can provide the display timing to a master interface 1114 of the second DPU 1112 before synchronizing the first DPU 1106 and the second DPU 1112, as shown.

[0142] In one aspect, the first interface of the first DPU can be a first master interface and the second interface of the second DPU can be a second master interface. For example, Figure 13 It is exemplified that the first DPU 1106 can include a master interface 1108 and the second DPU 1112 can include a master interface 1114.

[0143] In one aspect, providing the display timing to the second interface of the second DPU can include providing the display timing to the second interface of the second DPU based on an output of a MUX. For example, Figure 12 It is exemplified that the display timing can be provided to the first interface 1210 of the second DPU core 1204 based on an output of the first multiplexer 1216 and / or the second multiplexer 1218.

[0144] In one aspect, at least one of the delay or skew between the first DPU and the second DPU can be controlled by software or display driver software. For example, Figure 16 It is exemplified that at least one of the delay or skew between the first DPU and the second DPU can be controlled by software or display driver software.

[0145] In one aspect, the first DPU and the second DPU can be synchronized based on a counter reaching a value. For example, the counter can be the counter 1214 and the value can be "Q_DPU_SYNC_PROG_INTF_OFFSET_EN_VALUE0" or another appropriate value.

[0146] In one aspect, the value can be indicated by a bit in a software register. For example, the value associated with the counter 1214 can be indicated by a bit in a software register.

[0147] In one aspect, the counter can be associated with a VSync operation of at least one of the first display or the second display. For example, ​ It is exemplified that the counter 1214 can be associated with a VSync operation.

[0148] In one aspect, the first display and the second display can be driven based on the display timing in a case where the UC is to be displayed at a first resolution. For example, the first display 406A and the second display 406B can be driven based on the display timing in a case where the UC is to be displayed at a first resolution.

[0149] In one aspect, the indication that the UC is to be displayed at the first resolution or the second resolution can indicate that the UC is to be rendered at the first resolution or the second resolution. For example, the indication received at 1606 by the first DPU (included in DPU 1602) can indicate that the UC is to be rendered at the first resolution or the second resolution.

[0150] In one aspect, the apparatus (e.g., DPU) can determine whether the UC is to be displayed at the first resolution or the second resolution based on the indication. For example, ​ At 1610, the apparatus can determine whether the UC is to be displayed at the first resolution or the second resolution based on the indication received at 1616.

[0151] In various configurations, methods or apparatuses for display processing are provided. The apparatus can be a DPU, a display processor, or some other processor that can perform display processing. In aspects, the apparatus can be the display processor 127 within the device 104, or can be some other hardware within the device 104 or another device. The apparatus can include means for obtaining an indication that a UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The apparatus can also include means for determining whether the UC is to be displayed at the first resolution or the second resolution based on the indication. The apparatus can include means for driving a first display via a first controller of a first DPU based on the indication. In a case where the UC is to be displayed at the first resolution, the apparatus can include means for driving a second display via a controller of a second DPU, or in a case where the UC is to be displayed at the second resolution, the apparatus can include means for driving the second display via a second controller of the first DPU. The apparatus can include means for dividing a frame of the UC into a first set of slices and a second set of slices. The apparatus can include means for providing the first set of slices to the first controller of the first DPU. In a case where the UC is to be displayed at the first resolution, the apparatus can include means for providing the second set of slices to the controller of the second DPU. The apparatus can include means for dividing a frame of the UC into a first set of slices and a second set of slices. The apparatus can include means for providing the first set of slices to the first controller of the first DPU. In a case where the UC is to be displayed at the second resolution, the apparatus can include means for providing the second set of slices to the second controller of the first DPU. The means for driving the first display can include means for sending a first indication to cause a first UC associated with the UC to be displayed on the first display. The means for driving the second display can include means for sending a second indication to cause a second UC associated with the UC to be displayed on the second display. The means for obtaining the indication that the UC is to be displayed can include means for setting a bit of a register of software or display driver software, where the bit is set to a first bit in a case where the UC is to be displayed at the first resolution, where the bit is set to a second bit in a case where the UC is to be displayed at the second resolution, where the first bit is different than the second bit. The apparatus can include means for receiving the UC from a GPU prior to driving the first display and prior to driving the second display. The apparatus can include means for establishing a display timing at a first interface of the first DPU. The apparatus can include means for synchronizing the first DPU and the second DPU based on the display timing. The apparatus can include means for providing the display timing to a second interface of the second DPU prior to synchronizing the first DPU and the second DPU.

[0152] It should be understood that the specific order or hierarchy of steps / frames in the processes, flow diagrams, and / or call flow diagrams disclosed herein are merely examples. It is possible, for instance, that the order of steps / frames can be rearranged or that some steps / frames can be omitted or added without detracting from the spirit of the example methods. Further, some steps / frames can be combined or separated into multiple steps / frames. Other steps / frames can also be added. The accompanying method claims present elements of the various steps / frames in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0153] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more." The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0154] Unless specifically stated otherwise, the term "some" refers to one or more. The term "or" can be construed in either an inclusive or exclusive sense, depending on the context in which it is used. Combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of the group consisting of A, B, and C," "one or more of the group consisting of A, B, and C," and the like, include the combinations of A, B, and / or C, and can include multiple instances of A, B, or C. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of the group consisting of A, B, and C," "one or more of the group consisting of A, B, and C," and the like, can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combination can contain one or more member(s) of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words "module," "mechanism," "element," "device," and the like can not be a substitute for the word "means." As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase "means for."

[0155] In one or more examples, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. Though described with reference to a term "processing unit" throughout this disclosure, such processing units can be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module can be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0156] Computer-readable media can include computer data storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media can be viewed as a tangible computer-readable storage medium or a communication medium. Data storage media can be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other storage medium(s) that can be used to store instructions, code, and / or data structures for implementing the techniques described in this disclosure. Combinations of the above should also be included within the scope of computer-readable media. Computer program products can include computer-readable media.

[0157] The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or ICs (e.g., a chip set). Various components, modules, or units are described herein as being stored in or on one or more computer-readable media, such as SDRAM, ROM, etc. However, this is merely for ease of illustration. If implemented in software, one or more of the techniques described herein can be implemented in assembly-language, machine language, machine code, higher-level languages, such as C, or in any other programming language suitable for executing on the various platforms described herein (or any other hardware platform, real or virtual). Also, it is understood that the various blocks, modules, elements, components, or units described herein can be implemented in a computer program product tangibly embodied in an information carrier, such as one or more non-transitory machine-accessible storage media, including but not limited to magnetic storage media (e.g., diskette, fixed disk, magnetic tape, etc.), optical storage media (e.g., optical disk, optical tape, etc.), flash memory, cache memory, and the like. Such computer program product can go by many names, including, but not limited to, computer program product, program, software, software application, software package, application, software module, module, script, or code. A computer program product can include one or more software elements tangibly embodied in the information carrier. It should be understood that a software element can include, but is not limited to, an object, an executable, a thread of execution, a program, and / or a component of a program, library, or other module. It should be further understood that a software element can be sourced from any combination of sources, including, but not limited to, one or more of: source code, compiled code, interpreted code, encrypted code, machine code, high-level languages, assembly code, object code, byte code, and the like.

[0158] The following aspects are merely illustrative and can be combined with other aspects or teachings described herein without limitation.

[0159] Aspect 1 A method of display processing, the method comprising: obtaining an indication that user content (UC) is to be displayed at a first resolution or a second resolution, wherein the first resolution is greater than the second resolution; driving a first display via a first controller of a first display processing unit (DPU); and driving a second display via a controller of a second DPU in a case that the UC is to be displayed at the first resolution or driving the second display via a second controller of the first DPU in a case that the UC is to be displayed at the second resolution.

[0160] Aspect 2 can be combined with aspect 1 and includes that the UC is associated with a virtual reality (VR) application, an augmented reality (AR) application, or an extended reality (XR) application.

[0161] Aspect 3 can be combined with any of aspects 1-2 and includes that the controller of the second DPU is a first embedded DisplayPort (eDP) controller, the first controller of the first DPU is a second eDP controller, and the second controller of the first DPU is a third eDP controller.

[0162] Aspect 4 can be combined with any of aspects 1-3 and includes that in the case that the UC is to be displayed at the second resolution, the controller of the second DPU is in a power collapse state.

[0163] Aspect 5 can be combined with aspect 4 and includes that the power collapse state is a global distributed switch (GDS) collapse state.

[0164] Aspect 6 can be combined with any of aspects 1-5 and includes that the first resolution is associated with a first throughput configuration, wherein the second resolution is associated with a second throughput configuration.

[0165] Aspect 7 can be combined with any of aspects 1-6 and further includes: dividing a frame of the UC into a first set of slices and a second set of slices; providing the first set of slices to the first controller of the first DPU; and providing the second set of slices to the controller of the second DPU in the case that the UC is to be displayed at the first resolution.

[0166] Aspect 8 can be combined with any of aspects 1-6 and further includes: dividing a frame of the UC into a first set of slices and a second set of slices; providing the first set of slices to the first controller of the first DPU; and providing the second set of slices to the second controller of the first DPU in the case that the UC is to be displayed at the second resolution.

[0167] Aspect 9 can be combined with any of aspects 1 to 8 and includes that driving the first display includes sending to the first display a first indication to cause a first UC associated with the UC to be displayed on the first display, and wherein driving the second display includes sending to the second display a second indication to cause a second UC associated with the UC to be displayed on the second display.

[0168] Aspect 10 can be combined with any of aspects 1 to 9 and includes that a multiplexer (MUX) multiplexes a first signal associated with the first DPU and a second signal associated with the second DPU, wherein driving the second display is based on the multiplexing of the first signal and the second signal.

[0169] Aspect 11 can be combined with aspect 10 and includes that the MUX is controlled by at least one of: software, a display driver, display driver software, a first display driver associated with the first DPU, a second display driver associated with the second DPU, or a central processing unit (CPU).

[0170] Aspect 12 can be combined with aspect 11 and includes that obtaining the indication to display the UC includes setting a bit of a register of the software or the display driver software, wherein the bit is set to a first bit in an instance in which the UC is to be displayed at the first resolution, wherein the bit is set to a second bit in an instance in which the UC is to be displayed at the second resolution, wherein the first bit is different than the second bit.

[0171] Aspect 13 can be combined with any of aspects 1 to 12 and includes that the first DPU and the second DPU are associated with a system on a chip (SOC).

[0172] Aspect 14 can be combined with any of aspects 1 to 13 and further includes that prior to driving the first display and prior to driving the second display, receiving the UC from a graphics processing unit (GPU).

[0173] Aspect 15 can be combined with any of aspects 1 to 14 and includes that the first display and the second display are included by a headset worn on a head of a user.

[0174] Aspect 16 can be combined with any of aspects 1 to 15 and includes that a clock output of a phase-locked loop (PLL) associated with the controller is routed to a first root clock gate (RCG) of the second DPU and a second RCG of the first DPU.

[0175] Aspect 17 can be combined with any of aspects 1 to 16 and further includes establishing a display timing at a first interface of the first DPU, and synchronizing the first DPU and the second DPU based on the display timing.

[0176] Aspect 18 can be combined with aspect 17 and further includes providing the display timing to a second interface of the second DPU prior to synchronizing the first DPU and the second DPU.

[0177] Aspect 19 can be combined with aspect 18 and further includes the first interface of the first DPU being a first master interface and the second interface of the second DPU being a second master interface.

[0178] Aspect 20 can be combined with any of aspects 18 to 19 and includes providing the display timing to the second interface of the second DPU based on an output of a multiplexer (MUX).

[0179] Aspect 21 can be combined with any of aspects 18 to 20 and includes at least one of a delay or skew between the first DPU and the second DPU being controlled by software or display driver software.

[0180] Aspect 22 can be combined with any of aspects 18 to 21 and includes the first DPU and the second DPU being synchronized based on a counter reaching a value.

[0181] Aspect 23 can be combined with aspect 22 and includes the value being indicated by a bit in a software register.

[0182] Aspect 24 can be combined with any of aspects 22 to 23 and includes the counter being associated with a vertical sync (VSync) operation of at least one of the first display or the second display.

[0183] Aspect 25 can be combined with any of aspects 17 to 24 and includes the first display and the second display being driven based on the display timing in an instance in which the UC is to be displayed at the first resolution.

[0184] Aspect 26 can be combined with any of aspects 1 to 25 and includes the indication that the UC is to be displayed at the first resolution or the second resolution indicating that the UC is to be rendered at the first resolution or the second resolution.

[0185] Aspect 27 can be combined with any of aspects 1 through 26 and further includes determining, based on the indication, whether to display the UC at the first resolution or the second resolution, wherein the first display and the second display are driven based on the determination.

[0186] Aspect 28 is an apparatus for display processing, the apparatus comprising at least one processor coupled to a memory, and based at least in part on information stored in the memory, the at least one processor configured to implement a method according to any of aspects 1 through 27.

[0187] Aspect 29 can be combined with aspect 28 and includes that the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein to obtain the indication, the at least one processor is configured to receive the indication via at least one of the antenna or the transceiver.

[0188] Aspect 30 is an apparatus for display processing, the apparatus comprising means for implementing a method according to any of aspects 1 through 27.

[0189] Aspect 31 is a computer-readable medium (for example, a non-transitory computer- readable medium) storing computer executable code, the code when executed by at least one processor cause the at least one processor to implement a method according to any of aspects 1 through 27.

[0190] Various aspects have been described herein. These and other aspects are within the scope of the following claims.

Claims

1. An apparatus for display processing, the apparatus comprising: a memory; and at least one processor coupled to the memory and configured to, based at least in part on information stored in the memory: obtain an indication that user content (UC) is to be displayed at a first resolution or a second resolution, wherein the first resolution is higher than the second resolution; drive a first display via a first controller included in a first display processing unit (DPU) based on the indication; and in response to the indication indicating that the UC is to be displayed at the first resolution, drive a second display via a third controller included in a second DPU; or in response to the indication indicating that the UC is to be displayed at the second resolution, drive the second display via a second controller included in the first DPU.

2. The apparatus of claim 1, wherein the UC is associated with a virtual reality (VR) application, an augmented reality (AR) application, or an extended reality (XR) application.

3. The apparatus of claim 1, wherein the third controller included in the second DPU is an embedded DisplayPort (eDP) controller, the first controller included in the first DPU is a first eDP controller, and the second controller included in the first DPU is a second eDP controller.

4. The apparatus of claim 1, wherein in an instance in which the UC is to be displayed at the second resolution, the third controller included in the second DPU is in a power collapse state.

5. The apparatus of claim 4, wherein the power collapse state is a global distributed switch (GDS) collapse state.

6. The apparatus of claim 1, wherein the first resolution is associated with a first throughput configuration, wherein the second resolution is associated with a second throughput configuration.

7. The apparatus of claim 1, wherein the at least one processor is further configured to: divide a frame of the UC into a first set of slices and a second set of slices; provide the first set of slices to the first controller included in the first DPU; and in an instance in which the UC is to be displayed at the first resolution, provide the second set of slices to the third controller included in the second DPU.

8. The apparatus of claim 1, wherein the at least one processor is further configured to: divide a frame of the UC into a first set of slices and a second set of slices; provide the first set of slices to the first controller included in the first DPU; and in an instance in which the UC is to be displayed at the second resolution, provide the second set of slices to the second controller included in the first DPU.

9. The apparatus of claim 1, wherein to drive the first display, the at least one processor is configured to send a first indication to the first display indicating that a first UC associated with the UC is to be displayed on the first display, and wherein to drive the second display, the at least one processor is configured to send a second indication to the second display indicating that a second UC associated with the UC is to be displayed on the second display.

10. The apparatus of claim 1, wherein a multiplexer (MUX) multiplexes a first signal associated with the first DPU and a second signal associated with the second DPU, wherein to drive the second display, the at least one processor is configured to drive the second display based on the multiplexing of the first signal and the second signal.

11. The apparatus of claim 10, wherein the MUX is controlled by at least one of: software, a display driver, display driver software, a first display driver associated with the first DPU, a second display driver associated with the second DPU, or a central processing unit (CPU).

12. The apparatus of claim 11, wherein to obtain the indication that the UC is to be displayed, the at least one processor is configured to: set a bit of a register of the software or the display driver software, wherein in a case that the UC is to be displayed at the first resolution, the bit is configured to be set to a first bit, wherein in a case that the UC is to be displayed at the second resolution, the bit is configured to be set to a second bit, wherein the first bit is different than the second bit.

13. The apparatus of claim 1, wherein the first DPU and the second DPU are associated with a system on a chip (SOC).

14. The apparatus of claim 1, wherein the at least one processor is further configured to: receive the UC from a graphics processing unit (GPU) prior to driving the first display and prior to driving the second display.

15. The apparatus of claim 1, wherein the first display and the second display are included by a headset worn on a head of a user.

16. The apparatus of claim 1, wherein a clock output of a phase-locked loop (PLL) associated with the third controller is configured to be routed to a first root clock gate (RCG) of the second DPU and a second RCG of the first DPU.

17. The apparatus of claim 1, wherein the at least one processor is further configured to: establish a display timing at a first interface of the first DPU; and synchronize the first DPU and the second DPU based on the display timing.

18. The apparatus of claim 17, wherein the at least one processor is further configured to: provide the display timing to a second interface of the second DPU prior to the synchronizing.

19. The apparatus of claim 18, wherein the first interface of the first DPU is a first master interface and the second interface of the second DPU is a second master interface.

20. The apparatus of claim 18, wherein to provide the display timing to the second interface of the second DPU, the at least one processor is configured to provide the display timing to the second interface of the second DPU based on an output of a multiplexer (MUX).

21. The apparatus of claim 18, wherein at least one of a delay or skew between the first DPU and the second DPU is controlled by software or display driver software.

22. The apparatus of claim 18, wherein to synchronize the first DPU and the second DPU, the at least one processor is configured to synchronize the first DPU and the second DPU based on a counter reaching a value.

23. The apparatus of claim 22, wherein the value is indicated by a bit in a software register.

24. The apparatus of claim 22, wherein the counter is associated with a vertical sync (VSync) operation of at least one of the first display or the second display.

25. The apparatus of claim 17, wherein to drive the first display and the second display, the at least one processor is configured to drive the first display and the second display based on the display timing in an instance in which the UC is to be displayed at the first resolution.

26. The apparatus of claim 1, wherein the indication that the UC is to be displayed at the first resolution or the second resolution indicates that the UC is to be rendered at the first resolution or the second resolution.

27. The apparatus of claim 1, wherein the at least one processor is further configured to: determine whether the UC is to be displayed at the first resolution or the second resolution based on the indication, wherein to drive the first display and the second display, the at least one processor is configured to drive the first display and the second display based on the determination.

28. The apparatus of claim 1, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein to obtain the indication, the at least one processor is configured to receive the indication via at least one of the antenna or the transceiver.

29. A method of display processing, the method comprising: obtaining an indication that user content (UC) is to be displayed at a first resolution or a second resolution, wherein the first resolution is higher than the second resolution; driving a first display via a first controller included in a first display processing unit (DPU); driving a second display via a third controller included in a second DPU in response to the indication indicating that the UC is to be displayed at the first resolution; or driving the first display and the second display based on the indication. drive the second display via a second controller included in the first DPU in response to the indication indicating that the UC is to be displayed at the second resolution.

30. A non-transitory computer readable medium storing computer executable code which, when executed by at least one processor, causes the at least one processor to: obtain an indication that user content (UC) is to be displayed at a first resolution or a second resolution, wherein the first resolution is higher than the second resolution; drive a first display via a first controller included in a first display processing unit (DPU) based on the indication; and drive a second display via a third controller included in a second DPU in response to the indication indicating that the UC is to be displayed at the first resolution; or drive the second display via a second controller included in the first DPU in response to the indication indicating that the UC is to be displayed at the second resolution. ​

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