Robust ICEFILL approach to provide void-free trench fill for logic and memory applications

Abstract

The method of filling the gap with the dielectric material includes using a suppression plasma during deposition. The suppression plasma increases nucleation hindrance of the deposited film. The suppression plasma selectively interacts near the top of the feature, thereby suppressing deposition at the top of the feature as compared to the bottom of the feature, thereby enhancing bottom-up filling.

Description

Incorporation by reference

[0001] The PCT application form is filed simultaneously with this specification as part of this application. Each application identified in the PCT application form filed simultaneously for which this application claims the benefit or priority thereof is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION

[0002] Many semiconductor devices process involves film formation, and the film includes a silicon-containing film such as silicon oxide or silicon nitride, for example. Plasma-enhanced atomic layer deposition (PEALD) can be used to deposit the silicon-containing film. When depositing a film in a gap, it may be particularly challenging to deposit a high-quality film. The challenges may include forming voids and / or seams in the film.

[0003] The background description provided herein is for the purpose of generally presenting the background of the present disclosure. Aspects of the work of the currently named inventors that are within the scope described in this background art section and that are not determined to be prior art at the time of filing the application are neither expressly nor implicitly admitted to be prior art to the present disclosure. SUMMARY OF THE INVENTION

[0004] Methods and systems for filling gaps in a fill structure are disclosed herein. In one aspect of the embodiments herein, a method for filling a gap is provided, the method comprising: providing a substrate in a processing chamber, the substrate having one or more structures, each structure comprising a gap; and performing a first set of cycles of operations: (a) exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of each gap, and (b) after (a), depositing a dielectric material in each gap, wherein during a first subset and a second subset of the first set of cycles, the substrate is exposed to the inhibition plasma for a first duration, and during the second subset of the first set of cycles, at least one non-duration-based parameter of exposing the substrate to the inhibition plasma is modified.

[0005] In some embodiments, the non-duration-based parameter is the flow rate of an inhibitor, the flow rate of a dilution gas, pressure, or radio frequency (RF) power. In some embodiments, the first subset of the first set of cycles inhibits deposition in the gap to a greater depth in the gap compared to the second subset of the first set of cycles. In some embodiments, exposing the substrate to the inhibitor plasma comprises flowing an inhibitor into the processing chamber, and wherein the flow rate of the inhibitor during the second subset of the first set of cycles is lower than that during the first subset of the first set of cycles. In some embodiments, the difference in the flow rate of the inhibitor between the first subset and the second subset of the first set of cycles is between about 1 sccm and about 5 sccm. In some embodiments, exposing the substrate to the inhibitor plasma comprises co-flowing the inhibitor and an inert gas into the processing chamber, and wherein the ratio of the inhibitor to the inert gas during the second subset of the first set of cycles is higher than that during the first subset of the first set of cycles. In some embodiments, the inhibitor comprises a nitrogen-containing material. In some embodiments, exposing the substrate to the inhibitor plasma comprises providing radio frequency (RF) energy to the processing chamber, and wherein the RF during the second subset of the first set of cycles is lower than that during the first subset of the first set of cycles. In some embodiments, the difference in RF power between the first subset and the second subset of the first set of cycles is between about 50 W and about 700 W. In some embodiments, the RF power is between about 250 W and about 1250 W per substrate. In some embodiments, each of the one or more structures has one or more concave features. In some embodiments, at least one of the concave features in the substrate has a critical dimension change of at least 10%. In some embodiments, the at least one non-duration-based parameter is modified based on the critical dimension change of the at least one concave feature of the one or more structures. In some embodiments, at least one of the concave features has a depth change of at least 10% between structures. In some embodiments, the at least one non-duration-based parameter is modified based on the depth change of the at least one concave feature of the one or more structures. In some embodiments, the dielectric material is an oxide material. In some embodiments, the oxide material is silicon dioxide. In some embodiments, the method further comprises a second set of cycles of performing the following operations: (a) exposing the substrate to the inhibitor plasma to inhibit deposition on a second portion of the gap, wherein during a first subset and a second subset of the second set of cycles, the substrate is exposed to the inhibitor plasma for a second duration different from the first duration, and during the second subset of the second set of cycles, the at least one non-duration-based parameter of the inhibitor plasma is modified; and (b) depositing a dielectric material in the gap after (a).

[0006] In another aspect of the embodiments herein, a system for filling gaps is provided, the system comprising: a processing chamber, and one or more memories and one or more processors, the one or more memories being configured to have computer-executable instructions for controlling the one or more processors to: provide a substrate in the processing chamber, the substrate having one or more structures, each structure comprising a gap; and perform a first set of cycles of operations: (a) exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of each gap, and (b) after (a), depositing a dielectric material in each gap, wherein during a first subset and a second subset of the first set of cycles, the substrate is exposed to the inhibition plasma for a first duration, and during the second subset of the first set of cycles, at least one non-duration-based parameter of exposing the substrate to the inhibition plasma is modified.

[0007] Methods and systems for filling gaps in structures at stations of a tool are disclosed herein, the tool having different fill rates between stations. In another aspect of the embodiments herein, a system is provided that includes: a processing chamber that includes a plurality of stations; one or more processors and one or more memories configured to: receive a plurality of substrates at the plurality of stations, each substrate having a structure that includes a gap, perform a first set of cycles of operations in each of the stations: (a) exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of the gap, and (b) after (a), depositing a dielectric material in the gap, and after performing the first set of cycles, perform a second set of cycles of operations in each station of a first subset of the plurality of stations: (c) depositing a dielectric material only within the gap of the substrate in the stations of the first subset of the plurality of stations.

[0008] In some embodiments, after the first set of cycles, the first substrate in the stations of the first subset of the plurality of stations has a lower depth of filling of the dielectric material compared to the second substrate among the plurality of substrates. In some embodiments, the second substrate is in stations that are not part of the first subset of the plurality of stations. In some embodiments, after the second set of cycles, the first substrate has a depth of filling of the dielectric material that is substantially equal to that of the second substrate. In some embodiments, one or more processors and one or more memories are further configured to, prior to (c), expose the substrate to an inhibitory plasma to inhibit deposition on the first portion of the gap. In some embodiments, one or more processors and one or more memories are further configured not to perform (c) in one or more stations that are not in the first subset of the plurality of stations. In some embodiments, one or more processors and one or more memories are further configured to flow one or more reactants to each of the one or more stations during the second set of cycles. In some embodiments, during the second set of cycles, the one or more reactants do not react with the substrate in stations that are not in the first subset of the plurality of stations. In some embodiments, one or more processors and one or more memories are further configured to provide radio frequency (RF) power to the first subset of the plurality of stations during the second set of cycles and not to provide RF power to stations that are not in the first subset of the plurality of stations during the second set of cycles. In some embodiments, one or more processors and one or more memories are further configured to flow one or more reactants to each of the plurality of stations during the second set of cycles. In some embodiments, one or more processors and one or more memories are further configured to flow one or more reactants to the first subset of the plurality of stations during the second set of cycles and not to flow one or more reactants to stations that are not in the first subset of the plurality of stations during the second set of cycles. In some embodiments, it further includes a second processing chamber, and wherein the first subset of the plurality of stations is part of the processing chamber, and the stations that are not in the first subset of the plurality of stations are part of the second processing chamber.

[0009] In another aspect of the embodiments herein, a method is provided that includes: (a) exposing a substrate to an inhibitory plasma to inhibit deposition on the first portion of the gap, and (b) after (a), depositing a dielectric material in the gap, and a second set of cycles that, after performing the first set of cycles, are performed at each station of the first subset of the plurality of stations: (c) depositing a dielectric material only within the gap of the substrate in the stations of the first subset of the plurality of stations.

[0010] In some embodiments, after the first set of cycles, the first substrate in the stations of the first subset of the plurality of stations has a lower depth of filling of the dielectric material compared to the second substrate among the plurality of substrates. In some embodiments, the second substrate is in stations that are not part of the first subset of the plurality of stations. In some embodiments, after the second set of cycles, the first substrate has a filling depth of the dielectric material that is substantially equal to that of the second substrate. In some embodiments, further comprising: exposing the substrate to an inhibition plasma prior to (c) to inhibit deposition on the first portion of the gap. In some embodiments, further comprising: not performing (c) in one or more stations that are not in the first subset of the plurality of stations. In some embodiments, further comprising: flowing one or more reactants to each of the one or more stations during the second set of cycles. In some embodiments, during the second set of cycles, one or more reactants do not react with the substrates in stations that are not in the first subset of the plurality of stations. In some embodiments, further comprising: providing radio frequency (RF) power to the first subset of the plurality of stations during the second set of cycles, and not providing RF power to stations that are not in the first subset of the plurality of stations during the second set of cycles. In some embodiments, further comprising: flowing one or more reactants to each of the plurality of stations during the second set of cycles. In some embodiments, further comprising: flowing one or more reactants to the first subset of the plurality of stations during the second set of cycles, and not flowing one or more reactants to stations that are not in the first subset of the plurality of stations during the second set of cycles. In some embodiments, it further comprises a second processing chamber, and wherein the first subset of the plurality of stations is part of the processing chamber, and the stations that are not in the first subset of the plurality of stations are part of the second processing chamber.

[0011] These and other features of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A flowchart presenting the operations for an exemplary embodiment is shown.

[0013] Figures 2A to 2D A diagram presenting an exemplary embodiment for reducing void formation within a feature is shown.

[0014] Figure 3 A flowchart presenting the operations for an exemplary embodiment is shown.

[0015] Figures 4A to 4B A diagram presenting an exemplary illustration of the gap filling variation between chambers according to various embodiments herein is shown.

[0016] Figure 5 A flowchart presenting the operations for an atomic layer deposition process is shown.

[0017] Figure 6 A flowchart presenting the operations for an exemplary embodiment is shown.

[0018] Figures 7 to 10 A schematic diagram of an example of a processing chamber for performing a method according to the disclosed embodiments is shown. Detailed Description

[0019] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that it is not intended to limit the disclosed embodiments.

[0020] Semiconductor manufacturing processes typically include dielectric gap filling of features using chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) methods. Methods for filling features with dielectric materials, including but not limited to oxide films and silicon-containing films such as silicon oxides, related systems, and devices are described herein. The methods described herein can be used to fill features formed in a substrate in a vertical orientation. Such features may be referred to as gaps, recessed features, negative features, unfilled features, or simply features. Filling such features may be referred to as gap filling. Features formed in a substrate may have one or more narrow and / or concave openings, constrictions within the features, and high aspect ratios as features. In certain embodiments, the features may have an aspect ratio of at least about 2:1, at least about 4:1, at least about 6:1, at least about 20:1, at least about 100:1, or greater. The substrate may be a silicon wafer, such as a 200-mm wafer, a 300-mm wafer, a 450-mm wafer, which includes a wafer having one or more layers of material (such as dielectric, conductive, or semiconductor material) deposited thereon.

[0021] Aspects of the present disclosure relate to methods of using a plasma suppressant during atomic layer deposition (ALD) of a dielectric material in a gap, which facilitate void-free bottom gap filling. The plasma suppressant creates a passivated surface and increases the nucleation barrier of the deposited ALD film. When the plasma suppressant interacts with the materials in the feature, the materials at the bottom of the feature are subjected to less plasma treatment due to geometric shadowing effects compared to the materials located closer to the top or field of the feature. Thus, deposition at the top of the feature is selectively inhibited while deposition in the lower portion of the feature proceeds with less or no inhibition. Accordingly, bottom-up filling is implemented in the ALD process, resulting in a more favorable tapered profile that mitigates the seam effect and prevents void formation. A halogen-containing plasma can be an effective plasma suppressant. For example, for some applications, a plasma produced from nitrogen trifluoride (NF3) can provide an inhibitory effect in a significantly reduced time compared to a plasma produced from molecular nitrogen (N2).

[0022] Figure 1 A process flow diagram of a method for filling a gap with a dielectric material is shown. The method begins with providing a structure (101) having one or more gaps to be filled. The structure can be formed by one or more material layers deposited on a substrate. The substrate can be a silicon or other semiconductor wafer (e.g., a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer), a wafer comprising one or more material layers having, for example, a dielectric material, a conductive material, or a semiconductor material deposited thereon. The method can also be applied to other substrates (e.g., glass, plastic, etc.) for gap filling, including in the fabrication of microelectromechanical (MEMS) devices.

[0023] Examples of structures include 3D NAND structures, DRAM structures, and shallow trench isolation (STI) structures. The structure includes gaps, and the sidewalls of these gaps are formed of materials susceptible to etching. In one example, a 3D NAND structure includes an oxide-nitride-oxide-nitride (ONON) stack covered with a polysilicon layer. In another example, the structure can include a lateral / tunnel structure extending horizontally from a common vertical trench. Other examples of sidewall materials include oxides, metals, and semiconductor materials. The methods described herein are not limited to a particular type of sidewall material and can be used to inhibit any susceptible material.

[0024] A suppression plasma is used to deposit a dielectric material (105) in a gap. As further discussed below, this step may involve a cycle of the suppression plasma followed by a cycle of ALD of the dielectric material. The suppression plasma treatment can be characterized by an Inhibited Effective Depth (IED). The IED describes a depth above which deposition will be inhibited. By varying the parameters of the suppression plasma treatment, including changing the time, pressure, species, and flow rate, the IED can be increased or decreased. The IED can be affected by multiple parameters, including the specific species used, the duration of the suppression plasma treatment, the plasma power, the ratio of the gas flow of the suppressing species (as opposed to a carrier gas such as an inert gas, e.g., helium or argon), and the pressure. In particular, the duration of the suppression used has a large impact on the IED. For example, a plasma generated from nitrogen trifluoride (NF3) can inhibit a micron-scale depth gap in a few seconds, while a smaller depth can be inhibited with as little as 0.1 second of exposure to the suppression plasma. For high aspect ratio and deep structures, such as structures with at least about 100:1 and 3 μm or deeper, NF3 is an ideal choice for the species used to suppress to sufficiently inhibit the structure to avoid pinching while also not completely inhibiting the structure. Other species can also be used, including halogen-containing species such as NF3 and non-halogen-containing species such as N2.

[0025] During the design of a bottom-up fill process, multiple suppression blocks can be planned where the suppression plasma treatment can be varied between the suppression blocks. For example, the suppression plasma treatment can be adjusted such that the IED is closer to the bottom of the feature, e.g., 75% of the total depth of the feature is inhibited. Then a cycle of ALD treatment can be performed to fill the bottom 25% of the feature. Then the suppression plasma parameters can be adjusted to inhibit, e.g., the top 50% of the feature (relative to the total depth, regardless of any fill), and then the next bottom portion of the feature can be filled.

[0026] In some embodiments, the IED may be affected by the geometry of the feature to be filled. For example, a reentrancy feature affects the mass transport of the suppressing species in the feature. A reentrancy feature can be characterized by a narrowing of the distance between sidewalls at a certain depth within the gap, where the distance can be measured along an axis parallel to the top or bottom surface of the substrate, and where the sidewall distance above or below the reentrancy feature is larger. Reentrancy features present challenges during deposition because the narrow portion within the gap increases the risk of void formation below the smaller gap. "Pinching" occurs when the gap at the reentrancy feature is deposited before the void below the reentrancy feature is fully filled, resulting in an internal void.

[0027] One way to reduce pinching and internal voids is to inhibit deposition at and above the recessed feature until sufficient deposition has occurred below the recessed feature. The plasma inhibition process can be adjusted to inhibit at the recessed feature and the inhibition can be carried out until the gap has been sufficiently filled. Once the gap has been sufficiently filled, deposition can occur at and / or above the recessed feature with a reduced risk of creating internal voids. The inhibition plasma can then be adjusted to reduce the IED such that deposition occurs at and / or above the recessed feature. It should be noted that it is not necessary to completely fill the gap below the recessed feature prior to deposition at the recessed feature, but only sufficiently filled to reduce the risk of pinching and voids. Since deposition is inhibited at the recessed feature before reaching below the recessed feature, the gap below the recessed feature can be sufficiently filled.

[0028] Although the IED at this depth of the recessed feature can reduce or eliminate pinching, in some embodiments, the recessed feature and / or the overall gap may have within-wafer (WW) and / or wafer-to-wafer (W2W) variations. In some embodiments, this variation may cause a corresponding WW or W2W variation in the IED. This is undesirable and can increase the risk of pinching when the IED is greater than or less than this depth of the recessed feature for the reasons mentioned above. In some embodiments, the depth of the recessed feature may vary by at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%. The variation in the IED may be due to the effect of the recessed feature on the IED. For example, variations in critical dimensions across the gap and at the recessed feature affect mass transport within the feature, thus changing the depth at which the inhibition plasma affects the surface, i.e., the IED. Additionally, the depth of the recessed feature may vary such that a single IED cannot inhibit at the depth of the recessed feature for all gaps to be filled. This situation may be undesirable as the gap may be inhibited too far above or below the recessed feature, resulting in pinching at the recessed feature and thus voids.

[0029] To address this variation, in some embodiments, the suppression plasma treatment can be modified to suppress within a range at the target depth. For example, multiple suppression plasma treatments can be adjusted to have an IED at 78%, 75%, and 72% depth instead of only 75%. This can be achieved by performing multiple suppression plasma treatments. Typically, multiple suppression plasma treatments are performed for a specific target IED such as 75% because the suppression effect may weaken before the gap is fully filled. Once the gap has been fully filled, the suppression plasma can be modified to target a different IED (e.g., 50%). However, in some embodiments, the suppression plasma can be modified to suppress within a range that includes the target IED. In some embodiments, ten or more suppression plasma treatments with the same parameters (e.g., same duration, plasma power, gas flow, etc.) can be performed to target a single IED, yet the parameters can be modified to suppress within a range that includes the single IED.

[0030] Thus, in some embodiments, the suppression plasma treatment can be adjusted such that the suppression plasma treatment suppresses slightly more than and / or less than the average depth of the recessed feature. This adjustment can be advantageous when the depth of the recessed feature varies by at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%, or when the critical dimension of the recessed feature varies by at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%. In some embodiments, the non-duration-based parameters between suppression plasma treatments can be changed. The non-duration-based parameters can be any parameter other than the time (i.e., its duration) allotted to an operation such as a suppression plasma treatment. Duration has the greatest impact on the IED of the suppression plasma treatment such that changing the duration can significantly increase or decrease the IED, which is not desirable. The desired change in IED can be less than about 3%, less than about 5%, less than about 10%, or less than about 20%, such that changing the duration may change the IED beyond what is needed. In some embodiments, the least sensitive parameter of the suppression plasma treatment can be modified. In some embodiments, the plasma power of the suppression plasma treatment can be the least sensitive parameter. For example, a 10% increase in HF power will cause less than a 3% change in IED compared to a more than 4.5% change in IED for a 10% change in duration.

[0031] Figures 2A to 2D Illustrates gap filling where the gap has varying recessed features. Figures 2A to 2B Presents a structure depicting what can occur when using a suppression plasma treatment with a single IED when there are variations in the recessed feature. Figure 2Ashows an example of the structure 200 during various stages of the gap filling method described herein. At 201, the structure 200a shows a gap 206 to be filled with a dielectric material. At Figure 2A In an example of, the gap 206 is formed between structures that may comprise a dielectric material, a conductive material, or a semiconductor material. In some embodiments, the structure 200 is a low aspect ratio structure. In some embodiments, the low aspect ratio structure may be a structure having an aspect ratio between about 3:1 and about 7:1. In some embodiments, the low aspect ratio structure may have a depth of at least about 1 μm. In certain embodiments, the structure 200 is a high aspect ratio structure. In certain embodiments, a conformal layer (not shown) is provided, which may be a liner deposited prior to using suppression plasma deposition. The conformal layer may protect the underlying layer from undesired etching during subsequent suppression plasma processing. In some embodiments, the conformal layer is a silicon nitride layer. In some embodiments, the conformal layer is a silicon oxide layer. In some embodiments, the conformal layer is a metal oxide layer, such as titanium oxide, zirconium oxide, tin oxide, hafnium oxide, or a combination thereof. In some embodiments, the conformal layer is a silicon layer, such as polysilicon. In some embodiments, no conformal layer is present.

[0032] At Figure 2A In, the gap 206 may be characterized by the concave features 208a to 208b. As indicated by the vertical lines, the concave feature 208a is smaller than the concave feature 208b, where the dimension may be based on the difference between the critical dimension at the narrowest part and the critical dimension at the widest part of the concave feature.

[0033] In certain embodiments, the depth of the concave feature, the critical dimension at any point within the gap, and the difference between the critical dimension at the concave feature and the critical dimension above / below the concave feature may vary. Each of these variations may affect the IED and / or mass transport within the feature and thus affect deposition.

[0034] At 201, the structure 200a may also be characterized by the inhibition effective depth (IED) lines 204a-1 to 204a-2. The IED lines 204a-1 to 204a-2 depict the inhibition depth resulting from the plasma suppression process. It is worth noting that the IED line 204a-1 at the concave feature 208a is lower than the concave feature 208a, while the IED line 204a-2 at the concave feature 208b is higher than the concave feature 208b. Although each gap is exposed to the same suppression plasma, this IED difference may still occur. The difference in IED is caused by the dimensional difference between the concave features 208a and 208b. Since the concave feature 208b is larger than the concave feature 208a, the mass flow rate of the suppression material within the gap having the concave feature 208b is smaller, resulting in a corresponding reduction in IED.

[0035] At 203, the gap 206 is filled with the dielectric material 210a in a bottom-up manner. At 203, the gap having the concave feature 208b has a void 202. This void results from the IED line 204a-2 being too shallow, i.e., insufficient suppression. Since the suppression effect is not deep enough, deposition occurs at the concave feature, resulting in a pinching effect that causes the void 202.

[0036] Similarly, Figure 2B Another example of how a void can occur due to a change in the concave feature is depicted. At 205, the structure 200b has gaps 206 with concave features 208c and 208d. The concave feature 208d is at a greater depth within the gap than the concave feature 208c. After the suppression plasma treatment, the IED lines 204b of both gaps are the same. However, compared to the concave feature 208c, the concave feature 208d suppresses at a greater depth within the feature (i.e., at a greater depth). At 207, the gap 206 is filled with the dielectric material 210b in a bottom-up manner such that there is relatively little or no deposition on the sidewalls above the fill line. However, a void 202 forms in the dielectric material 210b. Although the IED is the correct depth for the concave feature 208d, the IED that is deeper than the concave feature 208c still causes the void.

[0037] Figures 2C to 2D A structure is presented that depicts a method for improving uniformity and reducing voids caused by variations in the concave structure.

[0038] Figure 2C A structure 200c having a gap 206 and concave features 208a to 208b is depicted. The structure 200c can be the same structure as the structure 200a. At 211, the structure 200c has two sets of IED lines. The IED lines 204a-1 and 204a-2 can be the same as those shown in Figure 2A Additionally, IED lines 204c1 to 204c2 are shown and the IED lines 204c-1 to 204c-2 can be caused by different suppression plasma treatments. The IED lines 204c-1 and 204c-2 have different depths based on the difference between the concave features 208a and 208b. The IED lines 204c-1 and 204c-2 are slightly deeper in the gap 206. Thus, the IED line 204a-1 can be an appropriate depth for the suppression of the concave feature 208a, and the IED line 204c-2 can be an appropriate depth for the suppression of the concave feature 208b.

[0039] In some embodiments, the variation in the critical dimension within the gap and the variation in the recess feature dimension can be at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%. In some embodiments, the variation in the critical dimension or the recess feature dimension has a greater impact on the IED than the variation in the recess feature depth. For example, a 10% change in the recess feature depth affects 10% of the required IED, while a 10% change in the critical dimension or the recess feature dimension affects more than 15% of the required IED. Thus, in various embodiments, the parameters for suppressing plasma processing can be changed based on the variations in the critical dimension, the recess feature dimension, and the recess feature depth to target the IED lines 204a-1, 204a-2, 204c01, and 204c-2.

[0040] At 213, the gap 206 is filled with the dielectric material 210c in a bottom-up manner. In particular, the dielectric material 210c is void-free. This result is due to filling the gap using a plasma suppression process that results in the IED lines 204c-1 and 204c-2, followed by an additional gap fill using a plasma suppression process that results in the IED lines 204a-1 and 204a-2. It is noted that although both the IED lines 204a1 to 204a2 and the IED lines 204c1 to 204c2 are shown at 211, it should be understood that they correspond to different plasma suppression processes (the IED line 204c-1 may have been implied at the line 204a-1 considering the depth of suppression of the upper sidewalls shown by these lines). The gap fill can be initially performed using a plasma suppression process that results in the IED lines 204c-1 and 204c-2. Then the plasma suppression process can be modified to result in the IED lines 204a-1 and 204a-2 and the gap fill continued until the gap above the recess features 208a and 208b is filled.

[0041] Figure 2D A structure 200d having a gap 206 and recess features 208c to 208d is depicted, which is similar to Figure 2B . At 215, the structure 200d has two sets of IED lines. The IED line 204b can be the same as that shown in Figure 2B , while the IED line 204d can be caused by a different plasma suppression process. It is noted that the IED line 204b is at the correct depth of the recess feature 208d, while the IED line 204d is at the correct depth of the recess feature 208c.

[0042] In 217, the gap 206 is filled with the dielectric material 210d in a bottom-up manner. The dielectric material 210 has no voids. This result is due to filling the gap using a plasma suppression process that results in the IED line 204b, followed by additional gap filling using a plasma suppression process that results in the IED line 204d. It should be noted that although both IED lines 204b and 204d are shown in 215, it should be understood that they correspond to different plasma suppression processes). The gap filling can be initially performed using the plasma suppression process that results in the IED line 204b. Then, the plasma suppression process can be modified to result in the IED line 204d and the gap filling continued until the gaps above the recessed features 208c and 208d are filled.

[0043] Figure 3 An example of a processing sequence that can be used according to the disclosed embodiments is shown. Figure 3 The processing sequence in includes using a plasma suppression process on the substrate. In some embodiments, other operations (such as soaking, passivation) can be omitted, and in some embodiments, operations can be added. In Figure 3 In the exemplary processing sequence of, one or more wafers undergo gap filling. The process can start with a soak (302) after being provided to the deposition chamber. For example, this can be beneficial for removing particles or other pre-treatments. Then, n1 cycles of ALD deposition of the liner are performed (304). More details of the liner ALD are discussed below.

[0044] After depositing the optional liner, n suppression blocks are performed, with the operations of the first suppression block (n = 1) shown. The first operation is a plasma suppression, which is a surface treatment. As discussed above (308), the plasma can include halogen species, including, for example, F - , Cl - , I - , Br - , anions and radical species such as fluorine radicals. Other plasma suppressions can be used. In some embodiments, the plasma suppression is produced from non-halogen-containing species, including nitrogen-containing species and nitrogen-containing non-halogen-containing species. For example, a plasma produced from molecular nitrogen (N2), molecular hydrogen (H2), ammonia (NH3), amines, diols, diamines, amino alcohols, thiols, alkyl halides, halides, HF, fluorine-containing species, chlorine-containing species, iodine-containing species, or a combination thereof can be used as the plasma suppression. In some embodiments, the plasma suppression process is performed at the high pressures described herein.

[0045] When suppressing the interaction of the plasma with the materials in the feature, the materials at the bottom of the feature are subjected to less plasma treatment due to the geometric shielding effect compared to the materials closer to the top of the feature or in the field. Thus, the deposition at the top of the feature is selectively suppressed, while the deposition at the lower part of the feature proceeds with less or no suppression. In Figure 3 , the next operation in the suppression block is n2 cycles (310) of ALD fill. The dielectric material is selectively deposited at the bottom of the feature. The suppressing plasma and the n2 cycles of ALD fill together constitute a growth cycle. This can be repeated n3 times to continue filling the feature with intermittent suppression operations when the suppression effect weakens. The number of growth cycles in the suppression block can depend on the re-entrancy of the feature, i.e., whether it narrows at one or more points from the bottom to the top of the feature. Features with more re-entrancy may use a longer suppression time or multiple suppression blocks. In certain embodiments, the n2 cycles of ALD fill can include at least one ALD cycle, at least about 10 ALD cycles, or between 1 and about 15 ALD cycles. The suppressing plasma and the n2 cycles of ALD fill together constitute a growth cycle. This cycle can be repeated n3 times to continue filling the feature with intermittent suppression operations when the suppression effect weakens.

[0046] In certain embodiments, non-duration-based parameters (311) of the suppressing plasma can be changed between growth cycles. For example, the plasma power or the inhibitor species flow rate can be changed. In certain embodiments, the non-duration-based parameters are changed to reduce the IED of the suppressing plasma treatment. In certain embodiments, the duration of the suppressing plasma treatment is the main parameter adjusted to change the IED because the IED is highly sensitive to the duration of exposure to the suppressing plasma. However, changing the duration can change the IED more than changes in the re-entrant feature, such that voids may still occur due to over-suppression or under-suppression. By changing a parameter to which the IED is less sensitive, such as the plasma power, the IED can be similarly slightly reduced to appropriately suppress the variation between re-entrant features. In certain embodiments, the least sensitive parameter of the suppressing plasma can be changed, where the least sensitive parameter can be selected from the group including the inhibitor flow rate, the dilution gas flow rate (e.g., N2 or Ar), and the plasma power.

[0047] Thus, in some embodiments, during a first growth cycle, the suppression plasma can be suppressed to a first IED, and one or more cycles of ALD fill can be performed. During a subsequent second growth cycle, non-duration-based parameters of the suppression plasma are modified to reduce the IED (notably, the duration of the suppression plasma can be the same during the first and second growth cycles). Additional cycles of ALD fill can be performed. This modification can be performed multiple times depending on the variation of the recessed feature. For example, more modifications to the suppression plasma within a single suppression block can be performed for a larger variation in the critical dimension of the recessed feature.

[0048] In Figure 3 the example of, the suppression block ends with an optional passivation operation (312). This is a surface treatment to remove residual inhibitors and also densify the surface of the deposited film. In some embodiments, an oxygen plasma is used.

[0049] One or more additional suppression blocks (314) including a growth cycle and passivation can be performed on a total of n suppression blocks. The number of suppression blocks depends on how much material is used to fill the feature. The suppression plasma, ALD, and passivation conditions can vary between suppression blocks to fill the feature. For example, the duration of the suppression plasma can be 20 seconds until the bottom quarter of the feature is filled (suppression block 1), then the duration is changed to 5 seconds for the middle 50% of the structure (suppression block 2), etc. Each suppression block can have a different IED, where the processing parameters of the suppression plasma treatment for the suppression block are changed to target different IEDs. Each suppression block can fill a portion of the feature below the IED of that suppression block.

[0050] In some embodiments, a change in a non-duration-based parameter in (311) can change the IED by less than about 3%, less than about 5%, less than about 10%, or less than about 20%. In some embodiments, a change in a non-duration-based parameter in (311) can change the IED by less than about 100 nm, less than about 200 nm, less than about 300 nm, less than about 400 nm, or less than about 700 nm. This can be contrasted with the modification of the suppression plasma between blocks, where the suppression plasma can be modified to change the IED by more than about 10% or more than about 20%. For example, in some embodiments, a gap-fill process can have four suppression blocks, where the parameters of the suppression plasma between the suppression blocks can be set to suppress at 8 um, 4 um, 2 um, and 1 um. Changes to the suppression plasma within the suppression blocks can be performed to appropriately suppress the concave features of the WW or W2W variations. In some embodiments, such concave feature variations can result in an IED change that is much less than the IED change between the suppression blocks. In some embodiments, the target IED change between the suppression blocks is maximized to effectively fill the feature without voids. Since the IED is highly sensitive to the duration of the suppression plasma process, the duration is typically modified between the suppression blocks. In contrast, the change in the suppression plasma within the suppression blocks can be much smaller, such that the duration is too sensitive to be changed for variations in the concave features. As mentioned above, a small change in the suppression plasma process duration has a significantly greater impact on the IED compared to a similar small change in RF power or suppression species flow rate.

[0051] In various embodiments, non-duration parameters can be changed between suppression plasma processes to target the IED ranges as discussed above. Reducing the flow rate of the suppression species (e.g., as a percentage of the total flow rate), reducing the RF power, and / or reducing the pressure can reduce the IED. In some embodiments, the flow rate of the suppression species between a first suppression plasma process and a second suppression plasma process can be changed between about 1 sccm and about 5 sccm. In some embodiments, the RF power between a first suppression plasma process and a second suppression plasma process can be changed between about 50 W and about 700 W.

[0052] When the feature is near full, suppression may no longer be needed, and the fill can be completed using n4 cycles of ALD fill (316). In some embodiments, an optional dielectric capping or overcoat layer (318) can then be deposited. Plasma-enhanced chemical vapor deposition (PECVD) can be used at this stage for rapid deposition.

[0053] Another aspect of the present disclosure relates to Figure 1The processes shown in. In certain embodiments, the processes shown in may be performed simultaneously at multiple stations in a processing chamber or tool. Figure 1 The processes shown in. As further described below with respect to Figures 5 to 8 A processing chamber or tool may have multiple stations, each of which may be configured to receive a substrate having a structure with gaps to be filled. The gap filling processes described herein may be performed simultaneously at each station to fill the gaps in each substrate, where each station may share or be connected to a central reactant delivery system or a radio frequency (RF) power source.

[0054] In certain embodiments, gap filling may occur at different rates between stations on a single tool or across stations of multiple tools. Differences in the film growth rate between these stations may be caused by various imbalances. For example, the hydrodynamics of the reactant flow to each station or the RF generators at each station may perform differently, resulting in variations in the processing between stations. The plasma treatment inhibition as described herein may be particularly sensitive to such variations. In certain embodiments, an NF3 inhibition plasma treatment as short as 0.1 seconds may be performed, such that variations in the plasma or flow characteristics between stations will affect the inhibition plasma, resulting in corresponding changes in the growth rate due to under-inhibition or over-inhibition. Different from other ALD processes that may rely on saturation, the substrate may be exposed to the inhibition plasma for a short enough duration to preferentially inhibit the upper part of the gap in order to facilitate bottom-up filling. Thus, variations such as hardware variations between stations may cause some stations to fill at a slower rate compared to other stations, which is undesirable.

[0055] Figure 4A and 4B presents a diagram of a 4-station processing chamber (also referred to as a 4-station tool) according to various embodiments herein. In Figure 2A , four stations 402a-d are presented, each station having a corresponding showerhead 406a-d and a showerhead inlet valve 405a-d. Each showerhead may be fluidly connected to a reactant delivery system 401. In certain embodiments, each showerhead may include an RF generator that may provide RF power thereto to generate a plasma (the hatched pattern, which indicates the flow of RF power to the showerhead). In Figure 4A , the gap filling processes have been performed simultaneously in each of the stations 402a-d. In stations 402a-b, a dielectric material 407a-b has been deposited to a target fill depth 411, while stations 402c-d are filled with a dielectric material 407c-d that is below the target fill depth 411. This fill difference may be consistent between stations 402a-b and stations 402c-d, i.e., stations 402c-d consistently under-fill under repeated operations across different substrates, indicating that the fill variation is independent of any wafer-to-wafer variation.

[0056] Figure 4B depicts a method of correcting this fill difference by performing additional depositions at stations 402c-d but not at stations 402a-b. At stations 402c-d, RF power is still provided to generate a plasma (as indicated by the dot pattern on showerheads 406c-d), while no RF power is provided to stations 402a-b. Similarly, the reactant flow to stations 402c-d can be maintained, but the reactants do not flow to stations 402a-b (as indicated by the voids in the fill pattern below showerhead inlet valves 405a-b). The showerhead inlet valves 405a-b can be closed to inhibit the flow of gas to stations 402a-b. With the reactant flow and plasma power provided to stations 402c-d but not to stations 402a-b, additional dielectric material will be deposited on the substrates at stations 402c-d, resulting in the deposition of dielectric materials 409c-d that are deposited to the target fill depth 411, thus matching the depth of the fill and dielectric materials 407a-b in stations 402a-b. In some embodiments, additional growth cycles are performed at stations 402c-d but not at stations 402a-b. For example, in Figure 4B , 50 growth cycles can be performed at stations 402a-b and 60 growth cycles can be performed at stations 402c-d, where although the total number of growth cycles is different, the total depth of dielectric fill is the same in the substrates of all stations. During the 10 additional growth cycles performed at stations 402c-d, no deposition occurs at stations 402a-b.

[0057] In some embodiments, neither RF power nor reactant flow is provided to stations 402a-b. In other embodiments, only the RF power or only the reactant flow can be stopped to some stations. In some embodiments, the deposition process is a plasma-enhanced process such that in the absence of a plasma, the reactants will not deposit and will not meaningfully interact with the substrates in the chamber. Thus, even with the reactant flow, the lack of a plasma still results in no deposition, inhibition, or etching process. In some embodiments, not providing RF power to a station may be preferred over stopping the reactant flow because stopping the flow of reactants to one or more stations may affect the flow of reactants to other stations, which is not desirable.

[0058] Alternatively, in some embodiments, the flow of reactants to one or more stations can be stopped. This can be performed in embodiments where deposition can occur without a plasma (such as a thermal deposition process). In some embodiments, without an expensive or time-consuming process, the stations may not be cooled sufficiently below the thermal deposition temperature. In the absence of reactants, deposition from such reactants will not occur.

[0059] In embodiments where RF power and / or reactant flow is stopped to one or more stations, the RF power and / or reactant flow can be appropriately adjusted to accommodate the remaining stations where deposition processing can still be performed. For example, in certain embodiments, for a four-station chamber such as shown in Figure 4A the RF power can be about 7000 W, with each station receiving about 1250 W. In Figure 4B where the RF power is only provided to two stations, the RF power can be adjusted to 2700 W, with each station still receiving about 1250 W. Similar variations can be performed on the reactant flow to maintain a similar per-station flow rate when depositing in two stations as when depositing in four stations.

[0060] Figure 5 Shows an example of a processing sequence that can be used according to the disclosed embodiments. Figure 5 Embodiments can be disclosed having operations identical to the reference numerals disclosed above with respect to Figure 3 When the same reference numerals are used, the same or similar operations can be performed.

[0061] Figure 3 The processing sequence in includes using an inhibition plasma to process a substrate. In certain embodiments, other operations (e.g., soak) can be omitted and in certain embodiments, operations can be added. In the exemplary processing sequence of Figure 3 one or more wafers are gap filled. The processing can begin with a soak (302) after being provided to the deposition chamber. This can be beneficial for, e.g., removing particles or other pre-treatments. Then, n1 cycles of ALD deposition of a liner are performed (304). Further details of liner ALD are discussed below.

[0062] Under the operation showing the first inhibition block (n = 1), n inhibition blocks are performed after depositing an optional liner. The first operation is an inhibition plasma (308) as a surface treatment. As discussed above, the plasma can include a halogen species containing anionic and radical species, such as F - , Cl - , I - , Br - , fluorine radicals, etc. Other inhibition plasmas can be used. In certain embodiments, the inhibition plasma is produced from a halogen-free species, including a nitrogen-containing halogen-free species. For example, a plasma produced from molecular nitrogen (N2), molecular hydrogen (H2), ammonia (NH3), amines, diols, diamines, amino alcohols, thiols, haloalkanes, halides, HF, fluorine-containing species, chlorine-containing species, iodine-containing species, or a combination thereof can be used as the inhibition plasma.

[0063] When suppressing the interaction of the plasma with the materials in the features, due to the geometric shadowing effect, the materials at the bottom of the features receive less plasma treatment compared to the materials located closer to the top of the features or in the field regions. Therefore, the deposition at the top of the features is selectively suppressed, while the deposition in the lower part of the features proceeds with less or no suppression. In Figure 3 In, the next operation in the suppression block is n2 cycles (310) of ALD fill. Dielectric material is selectively deposited at the bottom of the features. In some embodiments, the n2 cycles of ALD fill may include at least one ALD cycle, at least about 10 ALD cycles, or between 1 and about 15 ALD cycles. Suppressing the plasma together with the n2 cycles of ALD fill constitutes a growth cycle. This cycle may be repeated n3 times to continue filling the features with intermittent suppression operations when the suppression effect weakens.

[0064] In some embodiments, additional growth cycles (313) may be performed on a subset of the stations in the tool. As described above, one or more stations in the tool may have a lower deposition rate such that the features of the substrate in that station are underfilled relative to other stations. Such substrates may have gaps with a lower fill depth containing dielectric material compared to substrates in different stations. Additional growth cycles may be performed in such underfilled stations. This can be achieved by suppressing the RF power or reactant flow to other stations such that only a subset of the stations will be filled with additional dielectric material during subsequent growth cycles. The additional growth cycles do not result in additional dielectric material deposition in stations not included in that subset of stations.

[0065] In some embodiments, additional n2 cycles of ALD fill are performed on a subset of the stations. For example, the n2 cycles of ALD fill may be performed in all stations during 310, and additional ALD cycles may be performed on a subset of the stations.

[0066] In some embodiments, additional growth cycles may be performed on a subset of the stations during each suppression block. As mentioned above, each suppression block may be characterized by an IED, which is the depth at which deposition above it is suppressed. If the gaps are not sufficiently filled before the end of a suppression block, voids may form during a subsequent suppression block due to the pinching effect. This may occur when the subsequent suppression block will have a higher IED such that deposition in the gaps may occur at a higher level. Since the deposition will proceed from the sidewalls towards the center of the feature, due to the film growth at a higher depth within the feature, the reactants may not be able to diffuse to the bottom of the feature to completely fill it with dielectric material.

[0067] To avoid such pinching, in some embodiments, additional ALD cycles or growth cycles may be performed within a subset of the stations in each suppression block. In some embodiments, each station may have substantially the same fill depth of the substrate between suppression blocks. Thus, in some embodiments, an additional n2 cycles, such as additional ALD cycles, may be performed within a subset of the stations. In some embodiments, an additional n3 cycles, such as additional suppression plasma treatment and ALD cycles, may be performed within a subset of the stations.

[0068] In various embodiments, the subset of the stations may be one, two, or three stations of a four-station tool. The tool may also have more or fewer stations than four; in some embodiments, the tool has at least two stations, and additional growth cycles are performed only in one station. The additional growth cycles may be performed until the fill depth in the subset of the stations is substantially similar to the fill depth in the stations that are not part of the subset of the stations.

[0069] In Figure 3 the example of, the suppression block ends (312) under a passivation operation. In some embodiments, the passivation operation may not be performed in each suppression block. Passivation is a surface treatment that removes residual inhibitors and may also densify the surface of the deposited film. In some embodiments, a hydrogen and / or oxygen plasma is used.

[0070] One or more additional suppression blocks including growth cycles and passivation may be performed up to a total of n suppression blocks (314). The number of suppression blocks depends on how much material is used to fill the feature. The suppression plasma, ALD, and passivation conditions may be varied between the suppression blocks for filling the feature. For example, the suppression plasma duration may be 20 seconds until the bottom quarter of the feature is filled (suppression block 1), then the duration may be changed to 5 seconds for the middle 50% of the structure (suppression block 2), and so on. Each suppression block may have a different IED, where the processing parameters for the suppression plasma treatment of the suppression block are changed to target different IEDs. Each suppression block may fill a portion of the feature below the IED of that suppression block.

[0071] In some embodiments, additional suppression blocks may be performed within a subset of the stations. Similar to operation 311 above, additional suppression blocks may be performed within a subset of the stations, which include suppression plasma, ALD gap fill, and passivation. No additional suppression blocks are performed in the stations that are not part of the subset of the stations, such that additional suppression blocks are performed only within the subset of the stations.

[0072] When the feature is almost filled, suppression may no longer be needed, and the fill can be completed with n4 cycles of ALD fill (316). In some embodiments, an optional capping or overlying layer of dielectric may then be deposited (318). Plasma enhanced chemical vapor deposition (PECVD) can be used for rapid deposition at this stage.

[0073] ALD is a technique for depositing thin layers of material in sequence. ALD processing uses surface-mediated deposition reactions to deposit films in a layer-by-layer cycle. The concept of an ALD "cycle" is relevant to the discussion of many embodiments herein. Generally, a cycle is the minimum set of operations used to perform one surface deposition reaction. The result of a cycle is that at least a partially silicon-containing film layer is produced on the substrate surface. Typically, an ALD cycle includes operations for delivering and adsorbing at least one reactant to the substrate surface and then reacting the adsorbed reactant with one or more reactants to form a partial film layer. The cycle may include, for example, several auxiliary operations for sweeping away one of the reactants or by-products and / or treating the deposited partial film. Generally, a cycle includes an example of a unique sequence of operations.

[0074] For example, an ALD cycle may include the following operations: (i) delivering / adsorbing a precursor; (ii) sweeping the precursor from the chamber; (iii) delivering a second reactant and optionally igniting a plasma; and (iv) sweeping the by-products from the chamber. The reaction between the second reactant, which forms the film on the substrate surface, and the adsorbed precursor can affect film composition and properties such as non-uniformity, stress, wet etch rate, dry etch rate, electrical properties (such as breakdown voltage and leakage current), etc.

[0075] In one example of ALD processing, a substrate surface containing many surface active sites is exposed to a gas phase distribution of a first precursor (e.g., a silicon-containing precursor) provided to the chamber containing the substrate in a certain dose. Molecules of the first precursor adsorb onto the substrate surface, comprising chemisorbed species and / or physically adsorbed molecules of the first precursor. When a compound is adsorbed onto the substrate surface as described herein, the adsorbed layer may contain the compound and derivatives of the compound. For example, the adsorbed layer of the silicon-containing precursor may contain the silicon-containing precursor and derivatives of the silicon-containing precursor. After dosing with the first precursor, the chamber is then evacuated to remove most or all of the remaining gas phase first precursor, such that most or only the adsorbed species remain. In some embodiments, the chamber may not be completely evacuated. For example, the reactor may be vented such that the partial pressure of the gas phase first precursor is low enough to moderate the reaction. A second reactant such as an oxygen-containing gas or a nitrogen-containing gas is introduced into the chamber such that some of these molecules react with the first precursor adsorbed on the surface. In some processes, the second reactant reacts immediately with the adsorbed first precursor. In other embodiments, the second reactant reacts only in the presence of a temporarily applied activation source such as a plasma. The chamber may then be evacuated again to remove unreacted second reactant molecules. As described above, in some embodiments, the chamber may not be completely evacuated. Additional ALD cycles may be used to build the film thickness.

[0076] Figure 6 A process flow diagram for a single plasma-enhanced ALD cycle is presented, which single plasma-enhanced ALD cycle can be implemented as Figure 3 part of operations 304, 310, and / or 316 shown in. In operation 602, the substrate is exposed to a silicon-containing precursor to adsorb the precursor onto the surface of the feature. This operation may be self-limiting. In some embodiments, the precursor adsorbs onto less than all of the active sites on the surface of the feature. In operation 604, the processing chamber is optionally purged to remove any unadsorbed silicon-containing precursor. In operation 606, the substrate is exposed to a plasma generated from a co-reactant. Examples include O2 and / or N2O for forming a silicon oxide layer or a silicon oxynitride layer, N2 or NH3 for forming a silicon nitride layer, methane (CH4) for producing a silicon carbide layer, etc. In operation 608, the processing chamber is optionally purged to remove by-products from the reaction between the silicon-containing precursor and the oxidant. Operations 602 to 608 are repeated for several cycles to deposit a silicon-containing layer in the feature to the desired thickness.

[0077] It should be noted that the processes described herein are not limited to a particular reaction mechanism. Thus, with respect to Figure 3The processes described in and 4 include all deposition processes that use sequential exposure to silicon-containing reactants and conversion plasmas (including those that are not strictly self-limiting). The process includes a sequence in which one or more gases used to generate the plasma flow continuously throughout the process with intermittent plasma ignition.

[0078] In some embodiments, the suppression plasma treatment can be performed at a pressure greater than about 1 Torr, at least about 10 Torr, at least about 15 Torr, at least about 20 Torr, between about 10 Torr and about 30 Torr, or between about 15 Torr and about 30 Torr.

[0079] The duration of the suppression plasma treatment can be between about 0.3 seconds and about 60 seconds, between about 0.3 seconds and about 30 seconds, at least about 0.3 seconds, at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 20 seconds, or at least about 30 seconds. Compared to non-halogen-containing materials, the suppression plasma treatment using halogen-containing materials can generally be used for a shorter duration because halogen-containing materials can passivate the surface more effectively than non-halogen-containing materials.

[0080] The suppression plasma treatment can be used for many aspect ratios and structure depths. In some embodiments, the suppression plasma treatment can be used for low aspect ratio structures. Low aspect ratio structures can have an aspect ratio between about 3:1 and about 7:1, less than about 10:1, between about 3:1 and about 10:1, between about 3:1 and about 15:1, or less than about 15:1. Low aspect ratio structures can have a depth of at least about 100 nm, at least about 1 μm, at least about 2 μm, or at least about 3 μm.

[0081] In some embodiments, the IED can have a percentage characteristic, for example, 30% IED refers to the effective depth of suppression of 30% of the total depth of the feature. Thus, if the feature has a depth of 1 μm, 30% IED means that deposition will be suppressed along the sidewall surface of the feature (i.e., within 300 nm from the top of the feature), while the remaining depth is not suppressed. In some embodiments, the IED of the suppression plasma treatment according to the embodiments described herein can be about 20%, about 30%, about 40%, about 50%, about 60%, or about 70%.

[0082] In some embodiments, the structure may have varying recessed features. In some embodiments, the critical dimension at any given depth within the gap may vary by at least about 5%, at least about 10%, at least about 15%, at least about 20%, or between about 10% and about 20%. In some embodiments, the dimensions of the recessed features may vary by at least about 5%, at least about 10%, at least about 15%, at least about 20%, or between about 10% and about 20%, where the dimension may be based on the difference between the critical dimension at the narrowest part and the critical dimension at the widest part of the recessed feature. In some embodiments, the depth of the recessed features may vary by at least about 5%, at least about 10%, at least about 15%, at least about 20%, or between about 10% and about 20%.

[0083] In some embodiments, the ratio of the inhibitor to the inert gas may be about 1:5, about 1:10, between about 1:10 and about 1:20, between about 1:100 and about 1:700, or between about 1:5 and about 1:7000. Generally, increasing the ratio of the gas flow rate of the inhibitor such as NF3 will increase the inhibitory effect of exposing the substrate to the inhibitory plasma. Similarly, reducing the ratio of the gas flow rate of the inhibitor by modifying the flow rate of the inhibitor or the inert gas will reduce the inhibitory effect. In some embodiments, the flow of the non-halogen-containing substance (e.g., N2) may be between about 10 slm and about 100 slm. In some embodiments, the inert gas may co-flow with the substance used for inhibition. The inert gas may include helium, argon, xenon, or other gases that do not react with other substances in the gas or on the surface of the substrate. In use, the flow rate of the inert gas may be between about 3.5 slm and about 15 slm or between about 10 slm and about 40 slm. In some embodiments, an oxygen-containing or hydrogen-containing substance may co-flow with the substance used for inhibition. If the substance used for inhibition contains nitrogen atoms, the nitrogen atoms may react with the silicon precursor or the silicon film to form silicon nitride. Adding an oxygen-containing or hydrogen-containing substance may inhibit the formation of silicon oxide or the conversion of silicon to silicon nitride, respectively. In some embodiments, the co-flow of the oxygen-containing or hydrogen-containing substance may be at least about 100 sccm, or between about 0 and about 5 slm.

[0084] In various embodiments, the plasma is an in-situ plasma such that the plasma is formed directly above the surface of the substrate in the station. In some embodiments, the exemplary power per substrate area of the in-situ plasma is between about 0.2122 W / cm 2 and about 2.122 W / cm 2Between. For example, for a chamber processing 4 300 mm wafers, the power range can be from about 1000 W to about 8000 W. In one embodiment, for 4 300 mm wafers, the power can be between about 2700 W and 8000 W. The plasma for ALD processing can be generated by applying a radio frequency (RF) field to a gas using two capacitively coupled plates. The plasma is ignited by the ionization of the gas between the plates by the RF field, thereby forming free electrons in the plasma discharge region. These electrons are accelerated by the RF field and can collide with the gas-phase reactant molecules. The collisions of these electrons with the reactant molecules can form radical species that participate in the deposition process. It should be understood that the RF field can be coupled via any suitable electrode. Non-limiting examples of the electrode include a process gas distribution showerhead and a substrate support pedestal. It should be understood that in addition to the capacitive coupling of the RF field to the gas, the plasma for ALD processing can be formed by one or more suitable methods. In one embodiment, the plasma is a remote plasma such that the second reactant is ignited in a remote plasma generator upstream of the station and then transported to the station housing the substrate.

[0085] To deposit a silicon-containing film, one or more silicon-containing precursors can be used. In some examples, the silicon-containing precursors can include silane (e.g., SiH4), polysilane (H3Si-(SiH2) n -SiH3), where n≥1, organosilanes, halosilanes, aminosilanes, alkoxysilanes, etc. For example, methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di(tert-butyl)silane, allylsilane, sec-butylsilane, tert-hexylsilane, isoamylsilane, tert-butyldisilane, di(tert-butyl)disilane, and other organosilanes.

[0086] Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilane, bromosilane, chlorosilane, and fluorosilane. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, tert-butyldichlorosilane, n-hexyldimethylchlorosilane, etc.

[0087] An aminosilane contains at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogen, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively) and substituted mono-, di-, tri-, and tetra-aminosilanes such as tert-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2 (BTBAS), tert-butylsilyl carbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, di-isopropylaminosilane (DIPAS), di-sec-butylaminosilane (DSBAS), SiH2[N(CH2CH3)2]2 (BDEAS), etc. Further examples of aminosilanes are trisilylamine (N(SiH3)). In some embodiments, an aminosilane having two or more amine groups attached to a central silicon atom may be used. These may result in less damage compared to aminosilanes having only a single amine group attached.

[0088] Another example of a silicon-containing precursor includes trimethylsilane (3MS); ethylsilane; butasilane; pentasilane; octasilane; heptasilane; hexasilane; cyclobutasilane; cycloheptasilane; cyclohexasilane; cyclooctasilane; cyclopentasilane; 1,4-dioxo-2,3,5,6-tetrasilacyclohexane; diethoxymethylsilane (DEMS); diethoxysilane (DES); dimethoxymethylsilane; dimethoxysilane (DMOS); methyldiethoxysilane (MDES); methyldimethoxysilane (MDMS); octamethoxydodecasiloxane (OMODDS); tert-butoxydisilane; tetramethylcyclotetrasiloxane (TMCTS); tetraoxymethylcyclotetrasiloxane (TOMCTS); triethoxysilane (TES); triethoxysiloxane (TRIES); and trimethoxyoctasilane (TMS or TriMOS).

[0089] In certain embodiments, the silicon-containing precursor may include a siloxane or an amino-group-containing siloxane. In certain embodiments, the siloxane used herein may have the chemical formula X(R 1 ) a Si-O-Si(R 2 ) b Y, where a and b are integers from 0 to 2, and X and Y may independently be H or NR 3 R 4 , where R 1 , R 2 , R 3 , and R 4Each of them is hydrogen, a straight-chain alkyl group, a branched-chain alkyl group, a saturated heterocyclic group, an unsaturated heterocyclic group, or a combination thereof. In certain embodiments, when at least one of X or Y is NR 3 R 4 , R 3 and R 4 together with the atom to which each is attached form a saturated heterocyclic compound. In certain embodiments, the silicon-containing precursor is a pentamethylated amino-containing siloxane or a dimethylated amino-containing siloxane. Examples of amino-containing siloxanes include: 1-diethylamino-1,1,3,3,3-pentamethyldisiloxane, 1-diisopropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-dipropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-di-n-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-di-sec-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-N-methylethylamino-1,1,3,3,3-pentamethyldisiloxane, 1-N-methylpropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-N-methylbutylamino-1,1,3,3,3-pentamethyldisiloxane, 1-tert-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-piperidino-1,1,3,3,3-pentamethyldisiloxane, 1-dimethylamino-1,1-dimethyldisiloxane, 1-diethylamino-1,1-dimethyldisiloxane, 1-diisopropylamino-1,1-dimethyldisiloxane, 1-dipropylamino-1,1-dimethyldisiloxane, 1-di-n-butylamino-1,1-dimethyldisiloxane, 1-di-sec-butylamino-1,1-dimethyldisiloxane, 1-N-methylethylamino-1,1-dimethyldisiloxane, 1-N-methylpropylamino-1,1-dimethyldisiloxane, 1-N-methylbutylamino-1,1-dimethyldisiloxane, 1-piperidino-1,1-dimethyldisiloxane, 1-tert-butylamino-1,1-dimethyldisiloxane, 1-dimethylamino-disiloxane, 1-diethylamino-disiloxane, 1-diisopropylamino-disiloxane, 1-dipropylamino-disiloxane, 1-di-n-butylamino-disiloxane, 1-di-sec-butylamino-disiloxane, 1-N-methylethylamino-disiloxane, 1-N-methylpropylamino-disiloxane, 1-N-methylbutylamino-disiloxane, 1-piperidino-disiloxane, 1-tert-butylamino-disiloxane, and 1-dimethylamino-1,1,5,5,5-pentamethyldisiloxane.

[0090] In the case where the deposited film contains oxygen, an oxygen-containing reactant can be used. Examples of oxygen-containing reactants include, but are not limited to, oxygen (O2), ozone (O3), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2), dinitrogen trioxide (N2O3), dinitrogen tetroxide (N2O4), dinitrogen pentoxide (N2O5), carbon monoxide (CO), carbon dioxide (CO2), sulfur oxides (SO), sulfur dioxide (SO2), oxygen-containing hydrocarbons (C x H y O z ), water (H2O), formaldehyde (CH2O), carbonyl sulfide (COS), and mixtures thereof, etc.

[0091] In the case where the deposited film contains nitrogen, a nitrogen-containing reactant can be used. The nitrogen-containing reactant contains at least one nitrogen, such as nitrogen (N2), ammonia (NH3), hydrazine (N2H4), amines such as methylamine (CH5N), dimethylamine ((CH3)2NH), ethylamine (C2H5NH2), isopropylamine (C3H9N), tert-butylamine (C4H 11 N), bis(tert-butylamine) (C8H 19 N), cyclopropylamine (C3H5NH2), sec-butylamine (C4H 11 N), cyclobutylamine (C4H7NH2), isopentylamine (C5H 13 N), 2-methylbutan-2-amine (C5H 13 N), trimethylamine (C3H9N), diisopropylamine (C6H 15 N), diethylisopropylamine (C7H 17 N), bis(tert-butyl)hydrazine (C8H 20 N2) and other amines (e.g., amines with carbon), and aromatic-containing amines such as aniline, pyridine, and benzylamine. The amine can be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). In addition to nitrogen, the nitrogen-containing reactant can include heteroatoms, such as hydroxylamine, tert-butoxycarbonylamine, and N-tert-butylhydroxylamine as nitrogen-containing reactants. Other examples include N x O y compounds such as nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2), dinitrogen trioxide (N2O3), dinitrogen tetroxide (N2O4), and / or dinitrogen pentoxide (N2O5). Device

[0092] Figure 7Schematically shows an embodiment of a processing station 700 that can be used to deposit materials using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), where either ALD or CVD can be plasma-enhanced. For simplicity, the processing station 700 is depicted as a stand-alone processing station having a processing chamber body 702 for maintaining a low-pressure environment. However, it should be understood that multiple processing stations 700 can be included in a common processing tool environment. Additionally, it should be understood that in some embodiments, one or more hardware parameters of the processing station 700 can be programmatically adjusted by one or more computer controllers 750, including those hardware parameters discussed in detail below.

[0093] The processing station 700 is in fluid communication with a reactant delivery system 701 to deliver processing gases to a distribution showerhead 706. The reactant delivery system 701 includes a mixing vessel 704 that is used to blend and / or condition the processing gases for delivery to the showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of the processing gases into the mixing vessel 704. Similarly, a showerhead inlet valve 705 can control the introduction of the processing gases into the showerhead 706. In some embodiments, an inhibitor or other gas can be delivered directly to the chamber body 702. One or more mixing vessel inlet valves 720 can control the introduction of the processing gases into the mixing vessel 704. These valves can be controlled depending on whether the processing gases, inhibitor gases, or carrier gases are enabled during various operations. In some embodiments, the inhibitor gas can be generated by vaporizing an inhibitor liquid using a heated vaporizer.

[0094] For example, Figure 7 an embodiment includes a vaporization point 703 that is used to vaporize a liquid reactant that will be supplied to the mixing vessel 704. In some embodiments, the vaporization point 703 can be a heated vaporizer. Reactant vapors generated from such a vaporizer will condense in the downstream delivery piping. Exposure of incompatible gases to the condensed reactants can generate small particles. These small particles can clog the piping, impede valve operation, contaminate the substrate, etc. Some methods for dealing with these issues involve purging and / or evacuating the delivery piping to remove residual reactants. However, purging the delivery piping increases the processing station cycle time and reduces the processing station throughput. Thus, in some embodiments, the delivery piping downstream of the vaporization point 703 can be heat traced. In some examples, the mixing vessel 704 can also be heat traced. In a non-limiting example, the piping downstream of the vaporization point 703 has a temperature profile that rises from about 100 °C to about 150 °C at the mixing vessel 704.

[0095] In some embodiments, the reactant liquid can be vaporized at the liquid injector. For example, the liquid injector can inject pulses of the liquid reactant into the carrier gas stream upstream of the mixing vessel. In one case, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another case, the liquid injector can atomize the liquid into dispersed droplets that are then vaporized in a heated delivery tube. It should be understood that smaller droplets can vaporize faster than larger droplets, thereby reducing the delay between liquid injection and completion of vaporization. Faster vaporization can reduce the length of the tubing downstream of the vaporization point 703. In one case, the liquid injector can be loaded directly into the mixing vessel 704. In another case, the liquid injector can be loaded directly into the showerhead 706.

[0096] In some embodiments, a liquid flow controller (LFC) can be provided upstream of the vaporization point 703 to control the mass flow rate of the liquid to be vaporized and delivered to the processing station 700. For example, the liquid flow controller can include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller that is in electrical communication with the MFM. However, it can take one second or longer to use the feedback control to stabilize the liquid flow. This can extend the time to dispense the liquid reactant. Thus, in some embodiments, the LFC can dynamically switch between a feedback control mode and a direct control mode. In some embodiments, the LFC can dynamically switch from the feedback control mode to the direct control mode by disabling the sensing line and the PID controller of the LFC.

[0097] The showerhead 706 distributes the processing gas toward the substrate 712. In Figure 5 the illustrated embodiment, the substrate 712 is located below the showerhead 706 and is shown disposed on a pedestal 708. It should be understood that the showerhead 706 can have any suitable shape and can have any suitable number and arrangement of ports for distributing the processing gas to the substrate 712.

[0098] In some embodiments, a microvolume 707 is located below the showerhead 706. Performing ALD and / or CVD processing in the microvolume rather than in the entire volume of the processing station can reduce reactant exposure and purge times, can reduce the time to change processing conditions (e.g., pressure, temperature, etc.), can limit exposure of the processing station manipulator to the processing gas, etc. Exemplary microvolume sizes include, but are not limited to, volumes between 0.1 liter and 2 liters. This microvolume also affects the productivity throughput. When the deposition rate per cycle decreases, the cycle time also decreases simultaneously. In some cases, for a given target film thickness, the effect of the reduced cycle time is significant enough to increase the overall throughput of the module.

[0099] In some embodiments, the pedestal 708 can be raised or lowered to expose the substrate 712 to the microvolume 707 and / or to change the volume of the microvolume 707. For example, during the substrate transfer stage, the pedestal 708 can be lowered so that the substrate 712 can be loaded onto the pedestal 708. During the deposition process stage, the pedestal 708 can be raised to position the substrate 712 within the microvolume 707. In some embodiments, the microvolume 707 can completely surround the substrate 712 and a portion of the pedestal 708 to form a region of high flow impedance during the deposition process.

[0100] Optionally, the pedestal 708 can be lowered and / or raised during portions of the deposition process to adjust the process pressure, reactant concentration, etc. within the microvolume 707. In a situation where the process chamber body 702 is maintained at a base pressure during the deposition process, lowering the pedestal 708 can enable the microvolume 707 to be evacuated. Exemplary ratios of the microvolume to the process chamber volume include, but are not limited to, volume ratios between 1:700 and 1:10. It should be understood that in some embodiments, the pedestal height can be programmatically adjusted by a suitable computer controller.

[0101] In another scenario, adjusting the height of the pedestal 708 can cause a change in plasma density during plasma initiation and / or process cycles included in the deposition process. At the end of the deposition process stage, the pedestal 708 can be lowered during another substrate transfer stage to enable the substrate 712 to be removed from the pedestal 708.

[0102] Although the exemplary microvolume variations described herein relate to a height-adjustable pedestal, it should be understood that in some embodiments, the position of the showerhead 706 can be adjusted relative to the pedestal 708 to change the volume of the microvolume 707. Additionally, it should be understood that the vertical positions of the pedestal 708 and / or the showerhead 706 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 can include a rotational axis for rotating the orientation of the substrate 712. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more suitable computer controllers.

[0103] Back to Figure 7In the illustrated embodiments, the showerhead 706 and the pedestal 708 are in electrical communication with an RF power source 714 and a matching network 716 for powering the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure of the processing station, the concentration of the gas, the RF source power, the RF source frequency, and the plasma power pulse timing. For example, the RF power source 714 and the matching network 716 can operate at any suitable power to form a plasma having a desired radical species composition. Examples of suitable power are included above. Similarly, the RF power source 714 can provide RF power at any appropriate frequency. In some embodiments, the RF power source 714 can be configured to control a high-frequency RF power source and a low-frequency RF power source independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 50 kHz and 700 kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It should be understood that any suitable parameters can be adjusted discretely or continuously to provide plasma energy for surface reactions. In one non-limiting example, with respect to a continuously powered plasma, the plasma power can be pulsed intermittently to reduce ion bombardment of the substrate surface.

[0104] In some embodiments, the plasma can be monitored in-situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage, current sensors (e.g., VI probes). In another case, the plasma density and / or the concentration of the processing gas can be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters can be adjusted programmatically based on measurements from such in-situ plasma monitors. For example, the OES sensor can be used in a feedback loop to provide programmed control of the plasma power. It should be understood that in some embodiments, other monitors can be used to monitor the plasma and other processing characteristics. Such monitors can include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure sensors.

[0105] In some embodiments, the plasma can be controlled via input / output control (IOC) sequencing instructions. In one example, instructions for setting the plasma conditions of a plasma processing stage can be included in the corresponding plasma activation recipe stage of a deposition processing recipe. In some cases, the processing recipe stages can be arranged in sequence such that all instructions for a deposition processing stage are executed concurrently with that processing stage. In some embodiments, instructions for setting one or more plasma parameters can be included in a recipe stage prior to the plasma processing stage. For example, a first recipe stage can include instructions for setting the flow rates of an inert gas and / or a reactant gas, instructions for setting the plasma generator to a power set point, and a time delay instruction for the first recipe stage. A subsequent second recipe stage can include instructions for enabling the plasma generator and a time delay instruction for the second recipe stage. A third recipe stage can include instructions for disabling the plasma generator and a time delay instruction for the third recipe stage. It should be understood that these recipe stages can be further subdivided and / or iterated in any suitable manner within the scope of the present disclosure.

[0106] In some deposition processes, the plasma excitation duration is several seconds or longer. In certain implementations, a shorter plasma excitation time can be used. These can be from about 10 ms to 1 second, typically about 20 to 80 ms, with 50 ms being a specific example. Such very short RF plasma excitation requires the plasma to be stabilized very quickly. To achieve this, the plasma generator can be configured such that the impedance matching is set to a preset specific voltage while allowing the frequency to float. Typically, a high-frequency plasma is generated at an RF frequency of about 13.56 MHz. In various embodiments disclosed herein, the frequency is allowed to float to a value different from this standard value. By allowing the frequency to float while fixing the impedance matching to a predetermined voltage, the plasma can be stabilized more quickly, which can be important when using very short plasma excitations associated with certain types of deposition cycles.

[0107] In some embodiments, the susceptor 708 can be temperature-controlled by a heater 710. Additionally, in some embodiments, the pressure control of the deposition processing station 700 can be provided by a butterfly valve 718. As Figure 5 shown in the embodiment of, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the processing station 700 can also be adjusted by changing the flow rates of one or more gases introduced into the processing station 500.

[0108] Figure 8is a block diagram of a processing system suitable for performing thin film deposition processing according to certain embodiments. System 800 includes a transfer module 803. The transfer module 803 provides a clean, pressurized environment to minimize the risk of contamination when the substrate being processed is moved between the various reactor modules. According to certain embodiments, mounted on the transfer module 803 are two multi-station reactors 809 and 810, each reactor capable of performing atomic layer deposition (ALD) and / or chemical vapor deposition (CVD). Reactors 809 and 810 may include a plurality of stations 811, 813, 815, and 817, which may perform operations sequentially or non-sequentially according to the disclosed embodiments. These stations may include a heated pedestal or substrate support, one or more gas inlets or showerheads or dispersion plates.

[0109] Also mounted on the transfer module 803 may be one or more single-station or multi-station modules 807, which are capable of performing plasma or chemical (non-plasma) pre-cleaning, or any other processing related to the disclosed methods. In some cases, module 807 may be used for various processes to, for example, prepare the substrate for deposition processing. Module 807 may also be designed / configured to perform various other processes, such as etching or polishing. System 800 also includes one or more wafer source modules 801, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 819 may first move the wafer from the source module 801 to the load lock 821. A wafer transfer device (typically a robotic arm unit) in the transfer module 803 moves the wafer from the load lock 821 to the modules mounted on the transfer module 803 and moves the wafer from the load lock 821 between the modules mounted on the transfer module 803.

[0110] In various embodiments, a system controller 829 is used to control the processing conditions during deposition. Controller 829 will typically include one or more memory devices and one or more processors. The processor may include a CPU or calculator, analog and / or digital input / output connections, a stepper motor controller board, and the like.

[0111] Controller 829 may control all of the activities of the deposition apparatus. The system controller 829 executes system control software, which includes a set of instructions for controlling timing, gas mixtures, chamber pressure, room temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters for special processing. Other computer programs stored in the memory device associated with controller 829 may be employed in some embodiments.

[0112] There is typically a user interface associated with the controller 829. The user interface may include a display screen, a graphical software display of the apparatus and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0113] The system control logic can be configured in any suitable manner. Generally, the logic can be designed or configured in hardware and / or software. Instructions for controlling the drive circuit can be hard-coded or provided as software. The instructions can be provided by "programming". Such programming is understood to include any form of logic, including hard-coded logic in a digital signal processor, an application specific integrated circuit, and other devices having a specific algorithm implemented as hardware. Programming is also understood to include software or firmware instructions executable on a general purpose processor. The system control software can be coded in any suitable computer-readable programming language.

[0114] The computer program code for controlling the inhibitor substance flow rate, RF power, hydrogen flow rate, oxygen flow rate, and silicon-containing precursor flow rate, as well as other processes in the processing sequence, can be written in any common computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by the processor to accomplish the tasks identified in the program. Also as indicated, the program code can be hard-coded.

[0115] The controller parameters are related to the processing conditions, such as, for example, the processing gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using the user interface. Signals for monitoring the processing can be provided through the analog and / or digital input connections of the system controller 829. Signals for controlling the processing are output through the analog and digital output connections of the deposition apparatus 800.

[0116] The system software can be designed or configured in many different ways. For example, according to the disclosed embodiments, various chamber component subroutines or control objects can be written to control the operation of the chamber components necessary to perform the deposition process (and in some cases other processes). Examples of programs or program segments for this purpose include substrate positioning code, processing gas control code, pressure control code, and heater control code.

[0117] In some implementations, a controller (e.g., controller 750 or 829) is part of a system that can be part of the above-described embodiments. Such systems can include semiconductor processing equipment that includes one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronics can be referred to as a “controller” that can control various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, controller 829 can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of the tool and other transfer tools, and / or load locks coupled or interfaced to the specific system.

[0118] Broadly speaking, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions that are transferred to the controller in various individual settings (or program files) that define operating parameters for performing specific processes on or with a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer for performing one or more processing steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0119] In some implementations, the controller can be part of a computer that is integrated with, coupled to, or networked to the system or combinations thereof. For example, the controller can be in the "cloud" or be all or part of a fab host system, thereby allowing remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide a processing recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows for the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed as well as the type of tool, and the controller is configured to connect to or control the type of tool. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work towards a common goal (e.g., the processes and controls described herein). An example of a distributed controller for these purposes can be one or more integrated circuits on a chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control in-chamber processing.

[0120] Exemplary systems can include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, an orbit chamber or module, and any other semiconductor processing system that can be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0121] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more of the following: other tool circuits or modules, other tool components, combined tools, other tool interfaces, adjacent tools, adjoining tools, tools located throughout the factory, a host, another controller, or tools used in material handling that transport a container of wafers between tool locations and / or load ports in a semiconductor manufacturing facility.

[0122] It should be understood that multiple processing stations can be included in a multi-station processing tool environment, such asFigure 9 As shown, it depicts a schematic diagram of an implementation of a multi-station processing tool. The processing apparatus 700 uses an integrated circuit fabrication chamber 963, which includes a plurality of fabrication processing stations, each of which can be used to perform processing operations on a substrate supported in a substrate support such as a platform at a specific processing station. In Figure 9 the implementation, the integrated circuit fabrication chamber 963 is shown to have four processing stations 951, 952, 953, and 954. Depending on the implementation and factors such as the desired degree of parallel wafer processing, size / space limitations, cost limitations, etc., other similar multi-station processing apparatuses may have more or fewer processing stations. Figure 9 Also visible in Figure 9 is the substrate transfer robot 975, which can operate under the control of the system controller 990 to move a plurality of substrates from a wafer cassette (not shown in

[0123] Figure 9 Also shown is an implementation of the system controller 990 for the processing conditions and hardware status of the processing apparatus 900. As described herein, the system controller 990 may include one or more memory devices, one or more mass storage devices, and one or more processors.

[0124] The RF subsystem 995 can generate RF power and transmit the RF power to the integrated circuit fabrication chamber 963 through the RF input port 967. In a specific implementation, the integrated circuit fabrication chamber 963 may further include input ports (additional input ports are not shown in Figure 7 ). Thus, the integrated circuit fabrication chamber 963 can use 8 RF input ports. In a specific implementation, each of the processing stations 951 - 954 in the integrated circuit fabrication chamber 963 can use a first and a second input port, where the first input port can transmit a signal having a first frequency and the second input port can transmit a signal having a second frequency. Using dual frequencies can provide enhanced plasma characteristics.

[0125] As described above, one or more processing stations can be included in a multi-station processing tool. Figure 10FIG. 0 shows a schematic view of an embodiment of a multi-station processing tool 1000 having an in-loading lock 1002 and an out-loading lock 1004, either or both of the in-loading lock 1002 and the out-loading lock 1004 may include a remote plasma source. A manipulator 1006 at atmospheric pressure is configured to move a substrate or wafer from a cassette loaded through a pod 1008 to the in-loading lock 1002 via an atmospheric port. In the in-loading lock 1002, the manipulator 1006 places the substrate on a pedestal 1012, the atmospheric port is closed, and the loading lock is evacuated. In the case where the in-loading lock 1002 includes a remote plasma source, the substrate may be exposed to remote plasma processing in the loading lock before being introduced into the processing chamber 1014. Additionally, the substrate may also be heated in the in-loading lock 1002, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 1016 leading to the processing chamber 1014 is opened, and another manipulator 1090 places the substrate on the pedestal of the first station shown in the reactor for processing. Although Figure 9 the embodiments depicted in include loading locks, it should be understood that in some embodiments, the substrate may enter the processing station directly. In various embodiments, when the substrate is placed on the pedestal 1012 by the manipulator 1006, soak gas is introduced into the station.

[0126] The depicted processing chamber 1014 includes four processing stations, numbered 1 to 4 in the Figure 10 embodiment shown. Each station has a heated pedestal (shown as 1018 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station may be used for different or multiple purposes. For example, in some embodiments, the processing station may switch between plasma suppression, plasma passivation, ALD, and / or PEALD processing modes. Additionally or alternatively, in some embodiments, the processing chamber 1014 may include one or more matched pairs of ALD and plasma-enhanced ALD processing stations. Although the depicted processing chamber 1014 includes four stations, it should be understood that a processing chamber according to the present invention may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0127] Figure 8 An embodiment of a wafer handling system 1090 for transferring substrates within the processing chamber 1014 is depicted. In some embodiments, the wafer handling system 1090 may transfer substrates between the various processing stations and / or between the processing stations and the loading lock. It should be understood that any suitable wafer processing system may be employed. Non-limiting examples include wafer conveyors and wafer processing manipulators. Figure 8Also depicted is an implementation of a system controller 1050 for controlling the processing conditions and hardware state of a processing tool 1000. The system controller 1050 can include one or more memory devices 1056, one or more mass storage devices 1054, and one or more processors 1052. The processor 1052 can include a CPU or computer, analog and / or digital input / output connectors, a stepper motor controller board, and the like. In some implementations, the system controller 1050 includes machine-readable instructions for performing operations such as those described herein.

[0128] In some implementations, the system controller 1050 controls the activities of the processing tool 1000. The system controller 1050 executes system control software 1058 stored in the mass storage device 1054, loaded into the memory device 1056, and executed on the processor 1052. Alternatively, the control logic can be hard-coded in the system controller 1050. Application-specific integrated circuits, programmable logic devices (such as field-programmable gate arrays or FPGAs), and the like can be used for these purposes. In the following discussion, wherever "software" or "coding" is used, functionally comparable hard-coded logic can be used therein. The system control software 1058 can include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, substrate temperatures, target power levels, RF power levels, substrate pedestals, chucks, and / or sensor positions, and other parameters for the particular processes performed by the processing tool 1000. The system control software 1058 can be configured in any suitable manner. For example, various processing tool component subroutines or control objects can be written to control the operation of the processing tool components for performing various processing tool processes. The system control software 1058 can be coded in any suitable computer-readable programming language. Conclusion

[0129] Although the foregoing implementations have been described in some detail for purposes of clear understanding, it is apparent that certain changes and modifications can be practiced within the scope of the appended claims. The implementations disclosed herein can be practiced without some or all of these specific details. In other instances, well-known processing operations have not been described in detail so as not to unnecessarily obscure the disclosed implementations. Further, although the disclosed implementations will be described in connection with specific implementations, it should be understood that the specific implementations are not intended to limit the disclosed implementations. It should be noted that there are many alternative ways to implement the processes, systems, and devices of the presented implementations. Accordingly, the presented implementations are considered illustrative and not restrictive, and the implementations are not limited to the details given herein.

Claims

1. A method, comprising: providing a substrate in a processing chamber, the substrate having one or more structures, each structure including a gap; and performing a first set of cycles of the following operations: (a) exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of each gap, and (b) after (a), depositing a dielectric material in each gap, wherein, During a first subset and a second subset of the first set of cycles, expose the substrate to the suppression plasma for a first duration, and during the second subset of the first set of cycles, modify at least one duration-independent parameter of exposing the substrate to the suppression plasma.

2. The method according to claim 1, wherein the non-duration-based parameter is a flow rate of an inhibition substance, a flow rate of a dilution gas, a pressure, or a radio frequency (RF) power.

3. The method according to claim 1, wherein the first subset of the first set of cycles inhibits deposition in the gap to a greater depth of the gap compared to the second subset of the first set of cycles.

4. The method according to claim 1, wherein exposing the substrate to the inhibition plasma comprises flowing an inhibition substance into the processing chamber, and wherein a flow rate of the inhibition substance during the second subset of the first set of cycles is lower than that during the first subset of the first set of cycles.

5. The method according to claim 4, wherein a flow rate difference of the inhibition substance between the first subset and the second subset of the first set of cycles is between about 1 sccm and about 5 sccm.

6. The method according to claim 1, wherein exposing the substrate to the inhibition plasma comprises co-flowing the inhibition substance and an inert gas into the processing chamber, and wherein a ratio of the inhibition substance to the inert gas during the second subset of the first set of cycles is higher than that during the first subset of the first set of cycles.

7. The method according to claim 4, wherein the inhibition substance comprises a nitrogen-containing substance.

8. The method according to claim 1, wherein exposing the substrate to the inhibition plasma comprises providing radio frequency (RF) energy to the processing chamber, and wherein the RF during the second subset of the first set of cycles is lower than that during the first subset of the first set of cycles.

9. The method according to claim 8, wherein an RF power difference between the first subset and the second subset of the first set of cycles is between about 50 W and about 700 W.

10. The method according to claim 8, wherein the RF power is between about 250 W and about 1250 W per substrate.

11. The method according to claim 1, wherein each of the one or more structures has one or more concave features.

12. The method according to claim 11, wherein at least one of the concave features in the substrate has a critical dimension variation of at least 10%.

13. The method according to claim 12, wherein at least one non-duration-based parameter is modified based on the critical dimension variation of the at least one concave feature of the one or more structures.

14. The method according to claim 11, wherein at least one of the concave features has a depth variation of at least 10% between structures.

15. The method according to claim 14, wherein at least one non-duration-based parameter is modified based on the depth variation of the at least one concave feature of the one or more structures.

16. The method according to claim 1, wherein the dielectric material is an oxide material.

17. The method according to claim 16, wherein the oxide material is silicon dioxide.

18. The method according to claim 1, further comprising a second set of cycles of performing the following operations: (a) Exposing the substrate to an inhibition plasma to inhibit deposition on a second portion of the gap, wherein, During a first subset and a second subset of the second set of cycles, expose the substrate to the suppression plasma for a second duration different from the first duration, and during the second subset of the second set of cycles, modify the at least one duration-independent parameter of the suppression plasma; and (b) After (a), deposit a dielectric material in the gap.

19. A system comprising: A processing chamber, and One or more memories and one or more processors, the one or more memories being configured to have computer-executable instructions for controlling the one or more processors to: Provide a substrate in the processing chamber, the substrate having one or more structures, each structure including a gap; and Perform a first set of cycles of performing the following operations: (a) Exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of each gap, and (b) After (a), depositing a dielectric material in each gap, wherein, During a first subset and a second subset of the first set of cycles, expose the substrate to the suppression plasma for a first duration, and during the second subset of the first set of cycles, modify at least one duration-independent parameter of exposing the substrate to the suppression plasma.

20. A system comprising: A processing chamber including a plurality of stations; One or more processors and one or more memories, which are configured to: Receiving a plurality of substrates at the plurality of stations, each substrate having a structure including a gap, Performing a first set of cycles of the following operations in each of the stations: (a) Exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of the gap, and (b) After (a), depositing a dielectric material in the gap, and After performing the first set of cycles, performing a second set of cycles of the following operations in each station of a first subset of the plurality of stations: (c) Depositing a dielectric material only in the gap of the substrate in the stations of the first subset of the plurality of stations.

21. A method, comprising: Receiving a plurality of substrates at the plurality of stations, each substrate having a structure including a gap, Performing a first set of cycles of the following operations in each of the stations: (a) Exposing the substrate to an inhibition plasma to inhibit deposition on a first portion of the gap, and (b) After (a), depositing a dielectric material in the gap, and After performing the first set of cycles, performing a second set of cycles of the following operations in each station of a first subset of the plurality of stations: (c) Depositing a dielectric material only in the gap of the substrate in the stations of the first subset of the plurality of stations.

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