A page table data allocation method, device, equipment and medium

Abstract

The present invention discloses a method, apparatus, device, and medium for allocating page table data. The method comprises: reading non-mandatory parameter interface input data and mandatory parameter interface input data based on a test request from an MMU circuit; creating a target page table tree based on the non-mandatory parameter interface input data; managing the address allocation space of the target page table tree according to the mandatory parameter interface input data and a bidirectional linked list structure, and allocating address space and page table data for the target page table tree while traversing the target page table tree. The technical solution of the embodiment of the present invention can improve the efficiency of page table data generation, break the data dependency of page table data allocation, and meet the requirements of large-scale random testing at the MMU IP level.

Description

Technical Field

[0001] The present invention relates to the field of memory management unit verification simulation technology, and in particular to a page table data allocation method, device, equipment and medium. Background Art

[0002] Page table data allocation is a critical step in MMU IP-level verification. In actual project verification, the following issues exist: 1) The randomization of page table data consumes a significant amount of simulation time and makes it difficult to accurately match the type and number of page tables, impacting the final verification results. 2) The page table data storage location must be calculated using virtual addresses, which creates a strong data dependency. Summary of the Invention

[0003] The present invention provides a page table data allocation method, apparatus, device and medium to solve the problems of strong data dependency and low efficiency of page table data generation in existing page table data allocation, which cannot meet the requirements of large-scale random testing at the MMU IP level.

[0004] According to one aspect of the present invention, a page table data allocation method is provided, comprising:

[0005] Reading non-mandatory parameter interface input data and mandatory parameter interface input data based on the test request of the MMU circuit;

[0006] Create the target page table tree based on the input data of the optional parameter interface;

[0007] According to the required parameter interface input data and the bidirectional linked list structure, the address allocation space of the target page table tree is managed, and while traversing the target page table tree, space is allocated for the address of the target page table tree and page table data is allocated.

[0008] According to another aspect of the present invention, a page table data allocation device is provided, comprising:

[0009] A data acquisition module is used to read the input data of the non-mandatory parameter interface and the input data of the mandatory parameter interface based on the test request of the MMU circuit;

[0010] A page table tree building module is used to create a target page table tree based on input data from a non-mandatory parameter interface;

[0011] The page table data allocation module is used to manage the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure, and allocate space and page table data for the address of the target page table tree while traversing the target page table tree.

[0012] According to another aspect of the present invention, an electronic device is provided, comprising:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the page table data allocation method according to any embodiment of the present invention.

[0016] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the page table data allocation method according to any embodiment of the present invention when executed.

[0017] The technical solution of the embodiment of the present invention reads non-mandatory parameter interface input data and mandatory parameter interface input data based on the test request of the MMU circuit, thereby creating a target page table tree based on the non-mandatory parameter interface input data, and then manages the address allocation space of the target page table tree according to the mandatory parameter interface input data and the bidirectional linked list structure, and while traversing the target page table tree, allocates space for the address of the target page table tree and allocates page table data. This solution is applicable to MMU circuit verification simulation scenarios, can obtain non-mandatory parameter interface input data and mandatory parameter interface input data flexibly configured by the user based on test needs, and automatically generates a target page table tree that meets the test requirements based on the non-mandatory parameter interface input data, and manages the address allocation space of the target page table tree through the bidirectional linked list structure, optimizes memory allocation efficiency, avoids fragmentation problems, realizes optimized allocation of page table data, solves the problems of strong data dependence and low page table data generation efficiency of existing page table data allocation, and cannot meet the large-scale random testing requirements of MMU IP level, can improve page table data generation efficiency, break the data dependence of page table data allocation, and meet the large-scale random testing requirements of MMU IP level.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flow chart of a page table data allocation method provided in Example 1 of the present invention;

[0021] Figure 2 A flowchart of a page table data allocation method provided in the second embodiment of the present invention;

[0022] Figure 3 A functional layered diagram of page table data allocation provided by the third embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the shape of a target page table tree provided in the third embodiment of the present invention;

[0024] Figure 5 A schematic structural diagram of a page table data allocation device provided in a fourth embodiment of the present invention;

[0025] Figure 6 A schematic structural diagram of an electronic device that can be used to implement an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Example 1

[0029] Figure 1 This is a flow chart of a page table data allocation method provided in the first embodiment of the present invention. This embodiment is applicable to the case of efficient data allocation of page table data. The method can be executed by a page table data allocation device. The page table data allocation device can be implemented in the form of hardware and / or software. The page table data allocation device can be configured in an electronic device. The electronic device can include but is not limited to a computer or a server. Figure 1 As shown, the method includes:

[0030] Step 110 : Based on the test request of the MMU circuit, read the non-mandatory parameter interface input data and the mandatory parameter interface input data.

[0031] The non-mandatory parameter interface input data may be data describing a page table structure. Optionally, the page table structure may be a tree structure. The mandatory parameter interface input data may be data describing a physical address space mapping of the page table data.

[0032] In an embodiment of the present invention, if a test request of the MMU circuit is detected, non-mandatory parameter interface input data in the non-mandatory data input interface and mandatory parameter interface input data written by the user based on the mandatory data input interface can be read.

[0033] Step 120: Create a target page table tree based on data input from the optional parameter interface.

[0034] The target page table tree may be a tree structure generated based on input data from a non-mandatory parameter interface.

[0035] In an embodiment of the present invention, data parsing can be performed on the input data of the optional parameter interface read to determine the randomness requirement for generating the page table tree, and then a target page table tree can be created based on the randomness requirement. The randomness requirement includes, but is not limited to, the randomness of the page table tree shape and the randomness of the node storing the page table information.

[0036] Optionally, a tree structure can be created based on the data parsing results of the input data from the optional parameter interface, and the page table information required to be stored at each node in the tree structure can be determined to obtain a target page table tree. The page table information includes but is not limited to the page table type, the number of page tables, and the address offset.

[0037] Step 130: manage the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure, and allocate space for the address of the target page table tree and allocate page table data while traversing the target page table tree.

[0038] The address allocation space may be an address space specified by a user through a mandatory parameter interface input, and is used to record page table related data determined based on page table information stored in a node in the target page table tree. The page table data may be page table related data written in the address allocation space.

[0039] In an embodiment of the present invention, the address allocation space can be parsed from the input data of the required parameter interface, and the parsed address allocation space can be managed through a bidirectional linked list structure. Then, when traversing the target page table tree, the address allocation space corresponding to the target page table tree is allocated and the page table data is allocated according to the page table information stored in each node in the target page table tree.

[0040] By introducing a tree structure and a doubly linked list, this solution decomposes the complex operations in traditional page table allocation methods into two logically independent and easily manageable processes: generating a target page table tree and traversing the page table tree nodes to generate the page table data to be allocated, i.e., functional layering. This decomposition approach offers the following advantages: 1) Simplified Logic: Splitting the complex page table allocation task into two distinct steps reduces implementation complexity. Each process focuses on a single task, making it easier to understand and maintain. 2) Improved Efficiency: The generation of node information for nodes in the target page table tree can be completed in advance, reducing the computational overhead during real-time allocation. When traversing the allocated page table data, nodes can be quickly located and allocated based on pre-generated node information, improving overall performance. 3) Enhanced Flexibility: The two processes are independent and can be optimized or extended separately based on needs. For example, the node information generation process can support multiple page table structures, while the allocation process can adapt to different memory management policies. 4) Easier Debugging and Testing: Each process can be tested independently, making it easier to locate and resolve issues. The node information generation process can generate intermediate results, facilitating verification of its correctness. 5) Reduced resource usage: By pre-generating node information, we can reduce memory and computing resource consumption during real-time allocation. Simulation performance has been shown to improve by approximately 7x when processing a 4-level page table structure and allocating more page table data.

[0041] The technical solution of the embodiment of the present invention reads non-mandatory parameter interface input data and mandatory parameter interface input data based on the test request of the MMU circuit, thereby creating a target page table tree based on the non-mandatory parameter interface input data, and then manages the address allocation space of the target page table tree according to the mandatory parameter interface input data and the bidirectional linked list structure, and while traversing the target page table tree, allocates space for the address of the target page table tree and allocates page table data. This solution is applicable to MMU circuit verification simulation scenarios, can obtain non-mandatory parameter interface input data and mandatory parameter interface input data flexibly configured by the user based on test needs, and automatically generates a target page table tree that meets the test requirements based on the non-mandatory parameter interface input data, and manages the address allocation space of the target page table tree through the bidirectional linked list structure, optimizes memory allocation efficiency, avoids fragmentation problems, realizes optimized allocation of page table data, solves the problems of strong data dependence and low page table data generation efficiency of existing page table data allocation, and cannot meet the large-scale random testing requirements of MMU IP level, can improve page table data generation efficiency, break the data dependence of page table data allocation, and meet the large-scale random testing requirements of MMU IP level.

[0042] Example 2

[0043] Figure 2 This is a flowchart of a page table data allocation method provided by the second embodiment of the present invention. This embodiment is specific based on the above embodiment and provides a specific optional implementation method for creating a target page table tree based on input data from a non-mandatory parameter interface. Figure 2 As shown, the method includes:

[0044] Step 210: Based on the test request of the MMU circuit, read the non-mandatory parameter interface input data and the mandatory parameter interface input data.

[0045] Step 220: Create a target page table tree based on the data inputted through the optional parameter interface.

[0046] In an optional embodiment of the present invention, creating a target page table tree based on non-mandatory parameter interface input data may include: when the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty, creating a target page table tree of a fixed shape according to the first non-mandatory parameter interface input data; when the first non-mandatory parameter interface input data and the second non-mandatory parameter interface input data in the non-mandatory parameter interface input data are both empty, generating a fully random target page table tree; when the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is empty and the second non-mandatory parameter interface input data is not empty, generating a non-fully random target page table tree.

[0047] The first non-mandatory parameter interface input data can be used to describe the tree shape characteristics of the target page table tree. The second non-mandatory parameter interface input data can constrain the data of the page table information stored by the nodes in the target page table tree. In a specific example, the second non-mandatory parameter interface input data can be that the page table tree depth is 2, there are only regular PTE type page table entries, and the total number does not exceed 200.

[0048] In an embodiment of the present invention, if the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is valid or specified, it indicates that the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty; if the second non-mandatory parameter interface input data is not specified, it indicates that the second non-mandatory parameter interface input data is empty; if the second non-mandatory parameter interface input data is specified, it indicates that the second non-mandatory parameter interface input data is not empty. The logical rules for creating a target page table tree based on the non-mandatory parameter interface input data are as follows:

[0049] When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty, a target page table tree of a fixed shape is created according to the non-mandatory parameter interface input data, that is, a target page table tree with a fixed node depth and a fixed number of forks. At this time, the nodes in the target page table tree store random page table information.

[0050] When the first non-mandatory parameter interface input data and the second non-mandatory parameter interface input data in the non-mandatory parameter interface input data are both empty, a target page table tree with a random tree shape and random node storage page table information is generated, that is, a fully random target page table tree.

[0051] When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is empty and the second non-mandatory parameter interface input data is not empty, a target page table tree with a random shape is generated but the page table information stored in the nodes in the target page table tree is controllable, that is, a non-completely random target page table tree.

[0052] For example, the logic rules for creating a target page table tree based on the input data of the optional parameter interface can be seen in Table 1:

[0053] Table 1 Target page table tree creation logic rules

[0054]

[0055] Step 230: manage the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure, and allocate space for the address of the target page table tree and allocate page table data while traversing the target page table tree.

[0056] In an optional embodiment of the present invention, the address allocation space of the target page table tree may include a page table data storage address space and a page table data mapping physical address space; managing the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure may include: parsing the required parameter interface input data, determining the page table data storage address space and the page table data mapping physical address space; managing the page table data storage address space based on the first bidirectional linked list structure, and managing the page table data mapping physical address space based on the second bidirectional linked list structure.

[0057] The page table data mapping physical address space may be a physical address space specified by the required parameter interface input data. The page table data storage address space may be an address space other than the page table data mapping physical address space specified by the required parameter interface input data. The page table data mapping physical address space and the page table data storage address space may be used to store page table data of different page table types. The first double-linked list structure and the second double-linked list structure are double-linked list structures that respectively manage different address spaces.

[0058] In an embodiment of the present invention, the input data of the required parameter interface can be parsed to obtain the address space specified by the user for storing page table data, namely, the page table data storage address space and the page table data mapping physical address space, and then the page table data storage address space is managed through the first double linked list structure, and the page table data mapping physical address space is managed through the second double linked list structure.

[0059] In an optional embodiment of the present invention, allocating space for the address of the target page table tree and allocating page table data may include: when the current page table entry traversed to the target page table tree is a page directory entry, determining the free space of the page table data storage address managed by the first double linked list structure; and allocating page table data to the free space of the page table data storage address managed by the first double linked list structure.

[0060] The page table data storage address free space may be an unallocated space in the page table data storage address space.

[0061] In an embodiment of the present invention, when traversing the current page table entry stored in the node in the target page table tree, if the current page table entry is a page directory entry, the unallocated space in the page table data storage address space is determined based on the first double-linked list structure, that is, the page table data storage address free space is obtained, and then the page table data corresponding to the current page table entry is allocated to the page table data storage address free space managed by the first double-linked list structure.

[0062] In an optional embodiment of the present invention, allocating space for the address of the target page table tree and allocating page table data may include: when the current page table entry in the target page table tree traversed is a page table entry, determining that the page table data managed by the second double linked list structure maps to the physical address free space; mapping the physical address free space to the page table data managed by the second double linked list structure and allocating the page table data.

[0063] The page table data mapping physical address free space may be an unallocated space in the page table data mapping physical address space.

[0064] In an embodiment of the present invention, when traversing the current page table entry stored in the node in the target page table tree, if the current page table entry is a page table entry, the unallocated space in the page table data mapping physical address space is determined based on the second double linked list structure, that is, the page table data mapping physical address free space is obtained, and then the page table data mapping physical address free space managed by the second double linked list structure is allocated to the page table data corresponding to the current page table entry.

[0065] It should be noted that as the depth of the page table hierarchy increases, the number of page table storage addresses and physical pages that need to be allocated will increase significantly. Traditional page table data address allocation methods are difficult to efficiently cope with large-scale and frequent address allocation tasks, resulting in a significant increase in simulation time. This is because the more address subspaces that need to be allocated, the longer the constraint solving process becomes, and each random solution process will bring all previously generated address spaces into the overall solution. The complexity of this algorithm is exponential and extremely inefficient. This solution abstracts the entire memory space into a linked list structure. All allocated and unallocated address spaces are linked by a doubly linked list. The doubly linked list can quickly find the adjacent free space and directly allocate addresses within the available space. The operational complexity of the doubly linked list structure is O(n), where n is the number of address spaces stored in the linked list. That is, the complexity of the doubly linked list structure increases linearly, significantly improving the address allocation efficiency compared to existing technologies. Unallocated address spaces can be independently linked to ensure rapid allocation and insertion of new address spaces. Multiple levels of sub-address spaces can be further allocated within the same address space, facilitating finer-grained memory segmentation and management, effectively addressing fragmentation. The use of a doubly linked list further optimizes memory allocation efficiency and avoids fragmentation.

[0066] Step 240: Get a page table tree refill instruction.

[0067] Among them, the page table tree refill instruction may be an instruction for updating the page table information stored in the node in the target page table tree. The page table tree refill instruction may include at least one of a specific level refill instruction, a specific branch refill instruction, and a specific node refill instruction. The specific level refill instruction may be an instruction for refilling the node information of a specified level in the target page table tree. The specific branch refill instruction may be an instruction for refilling the node information in a specified branch in the target page table tree. The specific node refill instruction may be an instruction for filling the node information of a specified node in the target page table tree. Assuming that the specific branch refill instruction is to fill in empty data, it is equivalent to pruning the target page table tree, and the specific node refill instruction is to fill in empty data, it is equivalent to removing the node in the target node tree.

[0068] In an embodiment of the present invention, the page table tree refill instruction that the user needs to write based on the simulation verification of the MMU circuit can be obtained, and the node information can be quickly updated when the page table hierarchy changes dynamically, and the allocation process can be efficiently allocated based on the latest information.

[0069] Step 250 : According to the page table tree refill instruction, determine the data to-be-updated node of the target page table tree where the page table data allocation is completed, and reallocate the page table data to the data to-be-updated node.

[0070] The node to be updated may be a node in the target page table tree where page table data is updated based on a page table tree refill instruction.

[0071] In an embodiment of the present invention, the page table tree refill instruction can be parsed to determine the data to be updated node of the target page table tree that needs to update the page table data, thereby allocating new page table data to the data to be updated node of the target page table tree that completes the page table data allocation.

[0072] In an optional embodiment of the present invention, after allocating space for the address of the target page table tree and allocating page table data, it can include: converting the target page table tree that has completed the page table data allocation into a data format according to the JSON format to obtain simulation analysis related data; wherein, the root node in the target page table tree branches out at least two child nodes backward, and the non-leaf node in the target page table tree branches out at least two child nodes backward.

[0073] The simulation analysis related data may be text data in JSON format converted from the data stream corresponding to the target page table tree. JSON (Java Script Object Notation) is a lightweight data exchange format.

[0074] In an embodiment of the present invention, the target page table tree that completes the page table data allocation can be converted into JSON format to obtain simulation analysis related data, which is convenient for reuse and verification between different levels, such as fast exchange of address configuration information between SOC Level (system on chip level) and IP Level.

[0075] The technical solution of the embodiment of the present invention reads the non-mandatory parameter interface input data and the mandatory parameter interface input data through a test request based on the memory management unit MMU circuit, thereby creating a target page table tree based on the non-mandatory parameter interface input data, and then managing the address allocation space of the target page table tree according to the mandatory parameter interface input data and the bidirectional linked list structure, and while traversing the target page table tree, allocating space for the address of the target page table tree and allocating page table data, and after obtaining the page table tree refill instruction, determining the data to-be-updated node of the target page table tree where the page table data allocation is completed according to the page table tree refill instruction, and reallocating the page table data to the data to-be-updated node. This solution is suitable for MMU circuit verification simulation scenarios. It can obtain non-mandatory parameter interface input data and mandatory parameter interface input data that users can flexibly configure based on test needs, and automatically generate a target page table tree that meets the test requirements based on the non-mandatory parameter interface input data. It manages the address allocation space of the target page table tree through a bidirectional linked list structure, optimizes memory allocation efficiency, avoids fragmentation problems, and achieves optimized allocation of page table data. It solves the problems of strong data dependence and low page table data generation efficiency in existing page table data allocation, which cannot meet the needs of large-scale random testing at the MMU IP level. It can improve the efficiency of page table data generation, break the data dependence of page table data allocation, and meet the needs of large-scale random testing at the MMU IP level.

[0076] Example 3

[0077] The third embodiment of the present invention provides an optional embodiment of a page table data allocation method, and its specific implementation can be found in the following embodiments. Among them, the technical terms that are the same as or corresponding to the above embodiments are not repeated here.

[0078] Figure 3 This is a functional layered diagram of a page table data allocation method provided by the third embodiment of the present invention. The page table data allocation method can be configured in the application program interface, such as Figure 3As shown, the API can be specifically divided into a node layer and a data layer. The node layer is used to generate the required page table tree structure. Each branch and leaf node in the tree structure stores the corresponding page table information. The data layer is used to traverse the nodes of the target page table tree and generate specific page table data based on the page table information. The node layer includes a page table tree component and a page table node solver. The data layer includes a page table allocator, a first page table storage domain, and a second page table storage domain. The primary purpose of implementing a layered structure in this solution is to decouple functions, making it more modular, and making data flow production and storage clearer and more efficient, facilitating future maintenance and functional expansion. The page table tree component generates the page table tree structure. The page table node solver resolves constraints (input data from the second optional parameter interface) and generates page table nodes. The page table allocator dynamically allocates page table data. The first page table storage domain manages the storage of page table data corresponding to the page table directory. The second page table storage domain manages the storage of page table data corresponding to the page table entry.

[0079] The aforementioned application program interface provides the user with three configuration interfaces (an optional page table tree node configuration interface, an optional page table node constraint configuration interface, and a physical address space mapping configuration interface; the optional page table tree node configuration interface is used to receive input data from the first non-mandatory parameter interface; the optional page table node constraint configuration interface is used to receive input data from the second non-mandatory parameter interface; and the physical address space mapping configuration interface is used to receive input data from the mandatory parameter interface) to control the current page table generation method.

[0080] Figure 4 This is a schematic diagram of the shape of a target page table tree provided by the third embodiment of the present invention. Figure 4 As shown in the figure, the root node is the starting point. Each branch generated horizontally from the root node represents a set of independent physical process PIDs (mapped to virtual processes in the software system). Vertically, the depth of the tree structure (branch length) is 4, indicating that the maximum possible page table structure is 4 levels. Among them, pid_0 represents physical process number 0, and pid_1 represents physical process number 1.

[0081] For example, the size of a single page table data is 8 bytes, and it is stored in the memory unit in an 8-byte aligned manner. The storage location of each page table data is mapped to each child node of the tree structure. Taking the 48-bit wide virtual address as an example, the virtual page number is fixed to 9 bits. Figure 4 The target page table tree shown represents a maximum of 512 memory locations.

[0082] Figure 4Each square in the tree represents a node, and each node can store 512 page table entries (PDEs or PTEs, with each level of virtual page numbers addressing a maximum of 512). The node depth is 4 levels, corresponding to a four-level page table structure: L0 node → L1 node → L2 node → L3 node. The root node can branch out to a maximum of 16 L0 nodes, corresponding to the 16 physical thread PIDs in the system. The L0 / L1 / L2 / L3 nodes can each branch out to a maximum of 512 child nodes, so the maximum number of valid storage locations that can be represented in the entire page table tree is 16x512x512x512x512.

[0083] In each simulation, the depth of the target page table tree nodes, the type of page table entries (PDE or PTE) stored in each leaf node, and the number of page tables are all randomly generated. This randomness is intended to maximize the diversity of the relationship between page table storage locations and the type and number of page tables, thereby covering a wider verification space and improving test coverage.

[0084] The target page table tree generated by the node layer is directly input into the data layer as a data stream. The API also prints the generated data stream to a text file, using the common JSON format, to facilitate subsequent simulation data analysis. The data stream fully records the page table information for each node. For example, a second-level page table node is marked with one PDE, 131 Norm PTEs, and 32 Frag PTEs, each of which is identified by an array of address offsets.

[0085] The required parameter interface input data acts on the data layer and affects the final physical page allocation. The required parameter interface input data specifies the actual physical address space mapping relationship.

[0086] The page table tree data stream clearly indicates the page table hierarchy, various page table types, and their number. The data layer parses this data stream and uses a depth-first algorithm to traverse all branches and nodes in the page table tree (i.e., exploring a branch as deeply as possible until it is unable to continue, then backtracking and exploring other branches). This traversal rule is designed to ensure that the cascading relationship between page tables is not broken, while also fully recursively traversing all nodes.

[0087] During the process of traversing the entire page table tree, the API dynamically allocates the final page table data based on the current page table information. First, the storage address of each page table entry is determined. The page table allocator requests an available address from the address allocation space and then writes the page table data to this address (that is, fills the requested physical page address into the page table data field).

[0088] For example, when traversing to the third-level page table and the current page table entry is a PDE (page directory entry), the page table allocator searches for the reserved third-level page table storage space in the page table region specified by the address allocation space and checks whether there is any free area available for allocation. If free space is found, the system allocates the corresponding storage address to it. Similarly, when traversing to a page table entry that is a PTE (page table entry), the page table allocator allocates a physical page to it from the physical address region (pa region) specified by the address allocation space.

[0089] Typical application scenarios of the page table data allocation method include:

[0090] 1) In large-scale random testing, the system needs to generate multiple page table types and their combinations to cover a wide range of verification scenarios. Through the application programming interface provided by the solution, users can specify or not specify the first non-mandatory parameter interface input data and the second non-mandatory parameter interface input data to generate a random page table tree structure. Each node in the page table tree can randomly generate different types of page table entries (such as PDE, PTE, etc.), and the number and storage location of page table entries are also randomly assigned. This randomness ensures test diversity and can cover more page table combinations and edge cases, thereby improving verification coverage. The application programming interface in this solution supports fully random, randomly controllable, and fixed-shape page table tree generation, and users can flexibly choose the generation method based on test requirements. The generated page table data is recorded in JSON format to facilitate subsequent analysis and debugging.

[0091] 2) In fixed stimulus testing, users usually need to generate a specific page table structure to verify certain specific functions or scenarios. By specifying the first non-mandatory parameter interface input data, users can generate a page table tree of fixed shape to ensure that the same page table structure is used for each simulation. The application interface will generate the corresponding page table data based on the tree structure specified by the user, and ensure that the type, number and storage location of the page table entries are as expected. The application interface supports user-defined page table tree structures to ensure that the generated page table data is consistent with expectations. By optimizing the multi-level page table allocation algorithm, complex page table structures can be quickly generated, significantly improving simulation performance.

[0092] 3) During page switching tests, the system needs to handle scenarios such as page faults or context switches. When a page fault occurs, the system may need to refill page table data at a specific level. Through the aforementioned application programming interface, users can dynamically generate new page table data and accurately replace the page table data stored in the original page table location without destroying the original data storage structure. This supports dynamic generation of page table data multiple times during the simulation process, ensuring flexibility and efficiency during page switching. This means that the system supports dynamic overwriting or replacement of the original page table data, ensuring a quick response to page faults or context switches.

[0093] 4) During cross-validation between the SOC Level and IP Level, page table data needs to be generated and reused to ensure consistency across validation levels. Through the aforementioned API, users can easily describe or specify page table structures and quickly exchange address configuration information between the SOC Level and IP Level. The page table data generated by the API can be recorded in a common format (such as JSON) to facilitate reuse and validation across different levels. This supports a unified system address space allocation method and ensures consistency between SOC Level and IP Level page table data. Through a tree structure and a bidirectional linked list allocation algorithm, complex page table structures can be quickly generated, significantly improving cross-validation efficiency.

[0094] Example 4

[0095] Figure 5 This is a schematic diagram of the structure of a page table data allocation device provided by the fourth embodiment of the present invention. Figure 5 As shown, the device includes:

[0096] The data acquisition module 310 is used to read the input data of the optional parameter interface and the input data of the mandatory parameter interface based on the test request of the MMU circuit;

[0097] A page table tree building module 320 is used to create a target page table tree based on data input from a non-mandatory parameter interface;

[0098] The page table data allocation module 330 is used to manage the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure, and allocate space and page table data for the address of the target page table tree while traversing the target page table tree.

[0099] The technical solution of the embodiment of the present invention reads non-mandatory parameter interface input data and mandatory parameter interface input data based on the test request of the MMU circuit, thereby creating a target page table tree based on the non-mandatory parameter interface input data, and then manages the address allocation space of the target page table tree according to the mandatory parameter interface input data and the bidirectional linked list structure, and while traversing the target page table tree, allocates space for the address of the target page table tree and allocates page table data. This solution is applicable to MMU circuit verification simulation scenarios, can obtain non-mandatory parameter interface input data and mandatory parameter interface input data flexibly configured by the user based on test needs, and automatically generates a target page table tree that meets the test requirements based on the non-mandatory parameter interface input data, and manages the address allocation space of the target page table tree through the bidirectional linked list structure, optimizes memory allocation efficiency, avoids fragmentation problems, realizes optimized allocation of page table data, solves the problems of strong data dependence and low page table data generation efficiency of existing page table data allocation, and cannot meet the large-scale random testing requirements of MMU IP level, can improve page table data generation efficiency, break the data dependence of page table data allocation, and meet the large-scale random testing requirements of MMU IP level.

[0100] Optionally, the page table tree establishment module 320 is specifically used to create a target page table tree of a fixed shape according to the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data when the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty; generate a fully random target page table tree when the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data and the second non-mandatory parameter interface input data in the non-mandatory parameter interface input data are both empty; generate a non-fully random target page table tree when the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is empty and the second non-mandatory parameter interface input data is not empty.

[0101] Optionally, the address allocation space of the target page table tree includes a page table data storage address space and a page table data mapping physical address space; the page table data allocation module 330 includes an address space management unit and a page table data allocation unit. The address space management unit is configured to parse the required parameter interface input data to determine the page table data storage address space and the page table data mapping physical address space; manage the page table data storage address space based on a first double-linked list structure, and manage the page table data mapping physical address space based on a second double-linked list structure.

[0102] Optionally, the address space management unit is used to determine the free space of the page table data storage address managed by the first double linked list structure when the current page table entry in the target page table tree traversed is a page directory entry; and allocate the page table data to the free space of the page table data storage address managed by the first double linked list structure.

[0103] Optionally, a page table data allocation unit is used to determine the physical address free space mapped to the page table data managed by the second double linked list structure when the current page table entry in the target page table tree traversed is a page table entry; and allocate the page table data to the physical address free space mapped to the page table data managed by the second double linked list structure.

[0104] Optionally, the page table data allocation device also includes a data format conversion module, which is used to convert the data format of the target page table tree that completes the page table data allocation into JSON format to obtain simulation analysis related data; wherein, the root node in the target page table tree branches out backward into at least two child nodes, and the non-leaf node in the target page table tree branches out backward into at least two child nodes.

[0105] Optionally, the page table data allocation device also includes a page table data update module for obtaining a page table tree refill instruction; wherein the page table tree refill instruction includes at least one of a specific level refill instruction, a specific branch refill instruction, and a specific node refill instruction; according to the page table tree refill instruction, the data to-be-updated node of the target page table tree where the page table data allocation is completed is determined, and the page table data is reallocated to the data to-be-updated node.

[0106] The page table data allocation device provided in the embodiment of the present invention can execute the page table data allocation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0107] Example 5

[0108] Figure 6 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are provided for example only and are not intended to limit the implementation of the present inventions described and / or claimed herein.

[0109] like Figure 6As shown, electronic device 10 includes at least one processor 11 and memory, such as ROM 12 and RAM 13, communicatively connected to at least one processor 11. The memory stores computer programs executable by the at least one processor, and processor 11 can perform various appropriate actions and processes based on the computer programs stored in ROM 12 or loaded from storage unit 18 into RAM 13. RAM 13 can also store various programs and data required for the operation of electronic device 10. Processor 11, ROM 12, and RAM 13 are interconnected via bus 14. An I / O interface 15 is also connected to bus 14. ROM 12 is a read-only memory, RAM 13 is a random access memory, and I / O interface 15 is an input / output interface.

[0110] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0111] Processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any other suitable processor, controller, microcontroller, etc. Processor 11 executes the various methods and processes described above, such as the page table data allocation method.

[0112] In some embodiments, the page table data allocation method can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the page table data allocation method described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the page table data allocation method in any other appropriate manner (e.g., via firmware).

[0113] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0114] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0115] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or apparatus. A computer-readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, RAM, ROM, an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0116] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device that has: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0117] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0118] A computing system may include clients and servers. The clients and servers are generally remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosts and VPS servers.

[0119] The present application also discloses a computer program product, comprising a computer program that, when executed by a processor, implements the page table data allocation method provided in any of the embodiments of the present application. This program product and the page table data allocation method disclosed in each embodiment of the present application share the same inventive concept and are therefore not described in detail here.

[0120] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0121] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A page table data allocation method, characterized in that: include: Reading non-mandatory parameter interface input data and mandatory parameter interface input data based on a test request of a memory management unit MMU circuit; Creating a target page table tree based on the input data of the optional parameter interface; Managing the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure, and allocating space for the address of the target page table tree and allocating page table data while traversing the target page table tree; Creating a target page table tree based on the non-mandatory parameter interface input data includes: When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty, creating a target page table tree of a fixed shape according to the first non-mandatory parameter interface input data; When both the first non-mandatory parameter interface input data and the second non-mandatory parameter interface input data in the non-mandatory parameter interface input data are empty, generating a fully random target page table tree; When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is empty and the second non-mandatory parameter interface input data is not empty, a non-fully random target page table tree is generated.

2. The method according to claim 1, characterized in that The address allocation space of the target page table tree includes a page table data storage address space and a page table data mapping physical address space; Managing the address allocation space of the target page table tree according to the mandatory parameter interface input data and the bidirectional linked list structure, including: Parse the required parameter interface input data to determine the page table data storage address space and the page table data mapping physical address space; The page table data storage address space is managed based on a first double-linked list structure, and the page table data mapping physical address space is managed based on a second double-linked list structure.

3. The method according to claim 2, characterized in that Allocating space for the address of the target page table tree and allocating page table data includes: When the current page table entry in the target page table tree is traversed to be a page directory entry, determining a free space of a page table data storage address managed by the first double-linked list structure; The page table data is allocated to the free space of the page table data storage address managed by the first double-linked list structure.

4. The method according to claim 2, characterized in that Allocating space for the address of the target page table tree and allocating page table data includes: When the current page table entry in the target page table tree is traversed to be a page table entry, determining a free space of a physical address mapping of page table data managed by the second double-linked list structure; A physical address free space is mapped to the page table data managed by the second double-linked list structure, and the page table data is allocated.

5. The method according to claim 1, wherein After allocating space for the address of the target page table tree and allocating page table data, the method includes: The target page table tree to which the page table data has been allocated is converted into a data format according to the JSON format to obtain simulation analysis related data; The root node in the target page table tree branches out at least two child nodes, and the non-leaf node in the target page table tree branches out at least two child nodes.

6. The method according to claim 1, characterized in that After allocating space for the address of the target page table tree and allocating page table data, the method further includes: Obtain a page table tree refill instruction; wherein the page table tree refill instruction includes at least one of a specific level refill instruction, a specific branch refill instruction, and a specific node refill instruction; the page table tree refill instruction is an instruction for refilling node information of a specified level in a target page table tree; the specific branch refill instruction is an instruction for refilling node information in a specified branch in the target page table tree; the specific node refill instruction is an instruction for filling node information of a specified node in the target page table tree; According to the page table tree refill instruction, a data to-be-updated node of the target page table tree where page table data allocation is completed is determined, and the page table data is reallocated to the data to-be-updated node.

7. A page table data allocation device, characterized in that: include: A data acquisition module is used to read the input data of the non-mandatory parameter interface and the input data of the mandatory parameter interface based on the test request of the MMU circuit; A page table tree establishment module, configured to create a target page table tree based on data input from the optional parameter interface; A page table data allocation module is used to manage the address allocation space of the target page table tree according to the required parameter interface input data and the bidirectional linked list structure, and allocate page table data to the address allocation space of the target page table tree while traversing the target page table tree; The page table tree establishing module is specifically configured to create a target page table tree of a fixed shape according to the first non-mandatory parameter interface input data when the first non-mandatory parameter interface input data among the non-mandatory parameter interface input data is not empty; When both the first non-mandatory parameter interface input data and the second non-mandatory parameter interface input data in the non-mandatory parameter interface input data are empty, generating a fully random target page table tree; When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is empty and the second non-mandatory parameter interface input data is not empty, a non-fully random target page table tree is generated.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the page table data allocation method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the page table data allocation method according to any one of claims 1 to 6 when executed.

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