Decision feedback equalizer, memory device and memory system

Abstract

The embodiment of the invention discloses a DFE (Decision Feedback Equalizer), a memory device and a memory system. The DFE includes: an adder including a first node and a second node, and configured to receive an input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal, and output a first internal signal from the first node and a second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; and a tap bias voltage generation circuit configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage, the tap code, and a temperature code dependent on a temperature of the DFE.

Description

Technical Field

[0001] The inventive concept relates to a decision feedback equalizer, and a storage device and a memory system including the decision feedback equalizer. Background Art

[0002] As the processing speed of semiconductors increases, the processing speed of semiconductor systems is developing, but the development of channel conditions is slower than that of circuits. Therefore, when transmitting high-speed data using a channel, the received data may be lost, and thus a technique for compensating for the loss may be necessary. Generally, a decision feedback equalizer (DFE) is an effective circuit for compensating for such channel loss. Summary of the Invention

[0003] The inventive concept provides a decision feedback equalizer (DFE) that adjusts tap values according to temperature, a storage device including the DFE, and a memory system.

[0004] According to an aspect of the inventive concept, there is provided a DFE including: an adder including a first node and a second node, configured to receive an input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and output a first internal signal from the first node and a second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; and a tap bias voltage generation circuit configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage and a temperature code dependent on the temperature of the DFE.

[0005] According to another aspect of the inventive concept, there is provided a storage device including a DFE configured to receive an input signal and output a first internal signal and a second internal signal. The DFE includes: an adder including a first node and a second node, configured to receive an input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and output a first internal signal from the first node and a second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; and a tap bias voltage generation circuit configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage and a temperature code dependent on the temperature of the storage device.

[0006] According to another aspect of the inventive concept, a memory system is provided that includes a memory controller and a storage device connected to the memory controller. The storage device includes a DFE configured to receive an input signal and output a first internal signal and a second internal signal, and includes: an adder including a first node and a second node and configured to receive the input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and output the first internal signal from the first node and the second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; and a tap bias voltage generation circuit configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage and a temperature code dependent on the temperature of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram showing a memory system including a storage device according to an exemplary embodiment; Figure 2 is a block diagram showing a storage device according to an exemplary embodiment; Figure 3A is a flowchart showing the operation of a memory system according to an exemplary embodiment; Figure 1 is a flowchart showing the operation of the memory system according to an exemplary embodiment; Figure 3B is a diagram showing a comparative example; Figure 4 is a block diagram showing an input buffer according to an exemplary embodiment; Figure 5 is a diagram showing the effect of a decision feedback equalizer (DFE) of a data line according to an exemplary embodiment; Figure 6 is a diagram showing a DFE according to an exemplary embodiment; Figure 5 is a diagram showing a DFE according to an exemplary embodiment; Figure 7 is a diagram showing a tap bias voltage generation circuit according to an exemplary embodiment; Figure 4 is a diagram showing a tap bias voltage generation circuit according to an exemplary embodiment; Figure 8 is a diagram showing an equivalent circuit of a filter circuit according to an exemplary embodiment; Figure 9 is a diagram showing a tap bias voltage generation circuit according to an exemplary embodiment; Figure 10is a diagram showing an equivalent circuit of a tap bias voltage generation circuit according to an exemplary embodiment; and Figure 11 is a diagram showing the effect of a DFE including a temperature calibration circuit according to an exemplary embodiment. Detailed Description

[0008] Figure 1 is a block diagram showing a memory system including a storage device according to an exemplary embodiment.

[0009] Reference Figure 1 , the memory system 10 may include a memory controller 100 and a storage device 120. The memory system 10 may refer to a computing device, a virtual machine, or its virtual computing device, such as an integrated circuit, an electronic device or system, a smart phone, a tablet PC, a computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), and other suitable computers. Alternatively, the memory system 10 may refer to some of the components of a computing system, such as a graphics card. According to an embodiment, the memory system 10 may be provided as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a low-load DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), or a small DIMM (SODIMM).

[0010] The memory controller 100 may be communicatively connected to the storage device 120 through a memory bus 110. The memory controller 100 may include a register control word 102 (hereinafter referred to as "RCW"), a training circuit 104, and a memory physical layer (PHY) 106.

[0011] The RCW 102 may be set to control the initialization and / or operation characteristics of the storage device 120. The RCW 102 may include various algorithms for configuring the memory controller 100 such that the memory controller 100 can interact with the storage device 120 normally. For example, codes representing the frequency, timing, driving, detailed operation parameters, etc. of the storage device 120 may be set in the RCW 102. Memory training of the storage device 120 may be performed according to the codes of the RCW 102.

[0012] The training circuit 104 may perform memory core parameter training associated with the memory core of the memory device 120 and / or peripheral circuit parameter training for other peripheral circuits other than the memory core under the control of the memory controller 100. The training circuit 104 may determine the optimal parameters of the memory core parameters and / or peripheral circuit parameters of the memory device 120. As a main component of the memory controller 100, the training circuit 104 may perform memory training of the memory device 120. In an embodiment, the training circuit 104 is shown in the memory controller 100. However, as a main component of the memory device 120, the training circuit 104 may be provided in the memory device 120 to perform memory training.

[0013] The memory PHY 106 may include a physical layer or electrical layer and a logic layer, which are provided for signals, frequencies, timing, driving, detailed operation parameters, and functions required for effective communication between the memory controller 100 and the memory device 120. The memory PHY 106 may support features of the double data rate (DDR) and / or low power DDR (LPDDR) protocols of the Joint Electron Device Engineering Council (JEDEC) standard.

[0014] The memory PHY 106 may connect the memory controller 100 and the memory device 120 to each other via the memory bus 110. To simplify the illustration, a single signal line between the memory controller 100 and the memory device 120 is shown to provide the clock CLK, command / address CA, or data DQ. However, in practice, the clock CLK, command / address CA, or data DQ may be provided via multiple signal lines or buses. The signal lines between the memory controller 100 and the memory device 120 may be connected through a connector. The connector may be provided as pins, balls, signal lines, or other hardware components.

[0015] The signal of the clock CLK may be transmitted from the memory controller 100 to the memory device 120 via the clock signal line of the memory bus 110. The signal of the command / address CA may be transmitted from the memory controller 100 to the memory device 120 via the command / address bus of the memory bus 110. The signal of the chip select CS may be transmitted from the memory controller 100 to the memory device 120 via the line of the chip select CS of the memory bus 110. The data DQ may be transmitted from the memory controller 100 to the memory device 120 or from the memory device 120 to the memory controller 100 via a bus (or DQ line) including bidirectional signal lines for the data DQ of the memory bus 110.

[0016] The memory device 120 may write or read data DQ under the control of the memory controller 100. The memory device 120 may include a memory cell array 200, a mode register set 210 (hereinafter referred to as “MRS”), a control logic circuit 220, and a temperature monitoring circuit 280.

[0017] The memory cell array 200 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersections of the word lines and the bit lines. The memory cells of the memory cell array 200 may include volatile memory cells (e.g., dynamic random access memory (DRAM) cells or static RAM (SRAM) cells), non-volatile memory cells (e.g., flash memory cells, resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells), or other types of memory cells.

[0018] The MRS 210 may be programmed to set a plurality of operation parameters, options, various functions, characteristics, and modes of the memory device 120. The MRS 210 may store parameter codes including appropriate bit values provided via the command / address CA bus of the memory bus 110 when an MRS command is issued from the memory controller 100.

[0019] For example, the MRS 210 may be used to control burst length, read / write latency, preamble / postamble length, write equalization enable / disable, number of decision feedback equalizers (hereinafter referred to as “DFE”), pull-down / on-die termination (ODT), and pull-up / output high voltage (Voh) calibration, pre-emphasis, or reference voltage setting.

[0020] The burst length may be provided to set the maximum number of column positions accessible by a read and / or write command. The read / write latency may be provided to define the clock cycle delay between a read and / or write command and the first bit of valid output and / or input data. Write equalization may be provided to enable or disable skew compensation between a clock signal and a data strobe signal during a write operation.

[0021] The number of DFE may be provided to subtract remaining bits of previously read data DQ in order to determine a current data bit. Pull-down / ODT and pull-up / output high voltage (Voh) calibration may be provided to improve signal integrity (SI) by adjusting the swing width and / or drive strength of signals received via the command / address CA bus and / or the bus for data DQ.

[0022] A pre - emphasis function can be provided to improve SI by magnifying the open region of the data eye diagram of the signal transmitted through the bus for data DQ. A reference voltage setting can be provided to compare the voltage of the received signal with the voltage of the signal received from the command bus, so as to read the logical value of the received signal.

[0023] The control logic circuit 220 can receive the signal of the clock CLK through the clock signal line of the memory bus 110 and control the operation timing of the memory device 120. In addition to the signal of the clock CLK, the operation timing of the memory device 120 can also be provided based on the signal (e.g., a strobe signal) provided to the memory device 120. The control logic circuit 220 can receive the command received through the bus for command / address CA and generate a control signal in response to the command to perform various storage operations within the memory device 120.

[0024] The temperature monitoring circuit 280 can provide a calibration value according to the temperature change to the data input buffer 260 ( Figure 2 such that after the initialization and training operations are performed on the memory system 10 (i.e., when the memory device 120 is performing normal operations), the data transmitted to the memory device 120 has optimal SI and a data eye diagram according to the temperature change. For example, the temperature can be the temperature of a specific part of the memory device 120 or the temperature outside the memory device 120. For another example, the temperature can be the temperature of a specific part of the memory system 10 or the temperature outside the memory system 10.

[0025] Figure 2 is a block diagram showing the memory device 120 according to an exemplary embodiment.

[0026] Reference Figure 1 and Figure 2 , the memory device 120 can include a memory cell array 200, a row decoder 202, a word line driver 204, a column decoder 206, an input / output gating circuit 208, an MRS 210, a control logic circuit 220, an address buffer 230, an ODT circuit 240, a reference voltage generation circuit 250, a data input buffer 260, a data output buffer 270, and a temperature monitoring circuit 280.

[0027] The memory cell array 200 includes a plurality of memory cells provided in a matrix form arranged in rows and columns. The memory cell array 200 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL can be connected to the rows of the memory cells, and the plurality of bit lines BL can be connected to the columns of the memory cells.

[0028] The row decoder 202 can select one of the multiple word lines WL connected to the memory cell array 200. The row decoder 202 can decode the row address ROW_ADDR received from the address buffer 230 and select one word line corresponding to the row address ROW_ADDR, and can connect the selected word line to the word line driver 204 that activates the selected word line. The column decoder 206 can select certain bit lines BL from the multiple bit lines BL of the memory cell array 200. The column decoder 206 can generate a column selection signal by decoding the column address COL_ADDR received from the address buffer 230, and can connect the bit lines BL selected by the column selection signal to the input / output gating circuit 208. The input / output gating circuit 208 can include a read data latch and a write driver. The read data latch is used to store the read data from the bit lines BL selected by the column selection signal, and the write driver is used to write the write data into the memory cell array 200. The read data stored in the read data latch of the input / output gating circuit 208 can be provided to the bus for data DQ through the data output buffer 270. The write data can be applied to the memory cell array 200 through the data input buffer 260 connected to the bus for data DQ and through the write driver of the input / output gating circuit 208.

[0029] The control logic circuit 220 can receive the signals of the clock CLK and the command CMD and generate a control signal CTRLS, and the control signal CTRLS controls the operation timing and / or the memory operation of the memory device 120. The control logic circuit 220 can use the control signal CTRLS to read data from the memory cell array 200 and write data into the memory cell array 200.

[0030] To set the operation conditions of the memory device 120, the MRS 210 can store the information used by the control logic circuit 220 so that the operation of the memory device 120 is configured. The MRS 210 can include a register that stores the parameter codes of various operation and control parameters for setting the operation conditions of the memory device 120. The parameter codes can be received by the memory device 120 through the bus for command / address CA. The control logic circuit 220 provides the control signal CTRLS to the circuits of the memory device 120 so that the circuits operate as set in the operation and control parameters stored in the MRS 210.

[0031] The ODT circuit 240 can provide a termination resistor when the bus for command / address CA and / or the bus for data DQ is enabled. The termination resistor can improve the SI of the signals received via the bus. The enabling of the ODT circuit 240 and the magnitude of the termination resistor provided to the bus can be set by recording appropriate parameter codes on the MRS 210.

[0032] The reference voltage generation circuit 250 may provide a reference voltage VREF used by the circuits of the storage device 120. For example, the reference voltage VREF may be used by the control logic circuit 220 to compare the voltage of the received signal with the voltage of the signal received from the command bus in order to determine the logical value of the received signal. The reference voltage VREF and / or the range of the reference voltage VREF may be set by writing a reference voltage operation parameter code on the MRS 210.

[0033] The data input buffer 260 may provide the write data received via the bus for the data DQ to the input / output gating circuit 208.

[0034] The data output buffer 270 may provide the read data stored in the read data latch of the input / output gating circuit 208 to the memory controller 100 via the bus for the data DQ.

[0035] The temperature monitoring circuit 280 may provide a calibration value according to the temperature change to the data input buffer 260, so that after the initialization and training operations are performed on the memory system 10 (i.e., when the storage device 120 is performing normal operations), the data transmitted to the storage device 120 has an optimal SI and data eye diagram according to the temperature change.

[0036] Figure 3A is a flowchart showing the operation of a memory system according to an exemplary embodiment Figure 1 of. Figure 3B is a diagram showing a comparative example.

[0037] Refer to Figure 1 , Figure 2 and Figure 3A , the memory system 10 may be initialized in operation S310. When the memory system 10 is powered on, the memory controller 100 and the storage device 120 may perform an initial setting operation according to a preset method. Default operation parameters may be set when the storage device 120 is initialized.

[0038] In operation S320, the memory system 10 may perform a command address training operation. The memory controller 100 and the storage device 120 may perform a command address training operation to improve the timing margin of the command CMD and the address ADDR.

[0039] In operation S330, the memory system 10 may perform a read training operation. The memory controller 100 may adjust the operation parameter code of the storage device 120 so that the data read from the storage device 120 has an optimal SI and data eye diagram.

[0040] In operation S340 , the memory system 10 may perform a write training operation. The memory controller 100 may transfer data to the memory device 120 and adjust an operation parameter code of the memory device 120 so that the transferred data has an optimal SI and a data eye diagram.

[0041] In operation S350 , the memory system 10 may perform a normal operation after performing the initialization and training operations of operations S310 to S340 .

[0042] Furthermore, the initialization and training operations of operations S310 to S340 may be performed based on the temperature when the memory system 10 is powered on. Therefore, when the temperature of the memory system 10 increases or decreases, the memory system 10 may not have optimal SI and data eye diagrams.

[0043] Specifically, the tap values ​​C1 to C2 are determined according to the DFE quantity (DFEQ) optimized for the input signal (eg, data DQ). n (or called the first plug value C1 to the nth tap value C n ) includes a value determined based on the temperature when the memory system 10 is powered on. Therefore, it is necessary to adjust the first tap value C1 to the nth tap value C according to the temperature change. n .

[0044] refer to Figure 3B As can be seen, the figure shows a distorted input signal 2, a calibration signal 4 calibrated by the DFE at the training temperature, and a calibration signal 6 calibrated by the DFE at a temperature lower than the training temperature.

[0045] Comparing the calibration signal 4 with the calibration signal 6, it can be seen that the post cursor is less calibrated due to the temperature drop. For example, the first tap value C1 may decrease as the temperature decreases.

[0046] This phenomenon occurs because the DFE adder 33 ( Figure 6 ) has a different temperature coefficient of gain than the DFE taps 31_1 to 31_n ( Figure 6 ) of the tap values ​​C1 to C n The temperature coefficient of

[0047] For example, as the temperature decreases, the adder 33 ( Figure 6 ) can be increased, but the DFE taps 31_1 to 31_n ( Figure 6 ) of the tap values ​​C1 to C n can be reduced. Therefore, the rear cursor can be added by adder 33 ( Figure 6 ) is further amplified, and the post-vernier can be tapped by DFE taps 31_1 to 31_n ( Figure 6 ) are less calibrated.

[0048] According to an embodiment, the memory system 10 is configured to adjust bias voltages corresponding to tap values C1 to C according to a temperature change. Thus, although there is a temperature change, the transmitted data may have optimal SI and a data eye diagram. n

[0049] Figure 4 FIG. is a block diagram showing an input buffer according to an exemplary embodiment. Figure 5 FIG. is a diagram showing the effect of a DFE on a line of data DQ according to an exemplary embodiment. Figure 6 FIG. is a diagram showing a DFE according to an exemplary embodiment of Figure 5 .

[0050] Referring to Figure 4 , the input buffer 300 may include a DFE 310.

[0051] The DFE 310 may include a filter circuit 311, a sampler 313, and a tap bias voltage generation circuit 315.

[0052] First, referring to Figure 5 and Figure 6 , the filter circuit 311 and the sampler 313 will be described.

[0053] Referring to Figure 5 , the DQ line 24 may experience signal loss and signal reflection. In the DQ line 24, inter-symbol interference (ISI) may cause one bit of data to interfere with subsequent bits and distort one bit of data (i.e., smear out and overflow).

[0054] One bit of the data signal 22 transmitted via the DQ line 24 may be received as a distorted signal 26 having a residue of a previous bit. As the data rate increases, the ISI may become more prominent, and the pulse width representing the data bit becomes correspondingly narrower. The value of the distorted signal 26 received at each sampling point may be referred to as a tap value, such as a main tap value C0, a first tap value C1, a second tap value C2, etc., which corresponds to the data signal 22 transmitted via the DQ line 24.

[0055] The DFE 310 may calibrate the distorted signal 26 received at each sampling point by subtracting the residue of the previous bit in order to determine the current bit, and thus may generate a calibrated signal 28. Figure 5 FIG. shows an example in which only the first tap value C1 is calibrated by the DFE 310. However, this is only for ease of description, and the present embodiment is not limited thereto.

[0056] Hereinafter, the signal for the data DQ is referred to as an input signal DQ.

[0057] Referring to Figure 6 ​, the DFE 310 may include a filtering circuit 311 for calibrating the received input signal DQ and a sampler 313 for sampling the filtered input signal.

[0058] The filtering circuit 311 may include coefficient multipliers (or referred to as the first to n DFE taps) 31_1 to 31_n, delay units 32_1 to 32_(n - 1), and an adder 33.

[0059] The first to n DFE taps 31_1 to 31_n may multiply the delayed sample signals H1 to Hn (or referred to as the delayed first to n sample signals H1 to Hn) by the tap values C1 to C n . The delayed sample signals H1 to Hn may be provided by the delay units 32_1 to 32_(n - 1) that delay the sampled sample signal SDQ received from the sampler 313. In some embodiments, the delayed first sample signal H1 has exceeded one cycle (or half a cycle) of the write clock signal DQS, and thus may be directly provided to the first DFE tap 31_1 without passing through the delay units 32_1 to 32_(n - 1).

[0060] The adder 33 may add or subtract the tap values C1 to C to the input signal DQ before forwarding the internal signal INT_DQ calibrated by the filtering circuit 311 to the sampler 313 n .

[0061] The sampler 313 may sample the calibrated internal signal INT_DQ at a certain sampling interval set by the write clock signal DQS and output the sampled sample signal SDQ.

[0062] An optimized DFE quantity (DFEQ) for DQ data may be provided for the DFE taps 31_1 to 31_n, and the tap values C1 to C may be determined by multiplying the optimized DFEQ by the delayed sample signals H1 to Hn n . The DFEQ may be provided from the MRS 210 ( Figure 2 ).

[0063] The optimal DFEQ for the DQ line may be determined respectively by the read training operation or the write training operation in Figure 3A operation S330 or operation S340, and the information about the optimal DFEQ may be stored in the MRS 210 as a parameter code.

[0064] Return reference Figure 4 , the tap bias voltage generation circuit 315 may generate a tap bias voltage VBTAP. This will be described in detail in Figure 7 reference.

[0065] Figure 7A diagram showing a tap bias voltage generation circuit 315 according to an exemplary embodiment. Figure 4 of the tap bias voltage generation circuit 315.

[0066] Referring Figure 7 , the tap bias voltage generation circuit 315 may provide a tap bias voltage VBTAP to the filter circuit 311 based on the DQ bias voltage VBDQ.

[0067] Here, the DQ bias voltage VBDQ represents the bias voltage required to drive the adder 33 ( Figure 6 ) of the filter circuit 311, and the tap bias voltage VBTAP represents the bias voltage required to drive the DFE taps 31_1 to 31_n ( Figure 6 ) of the filter circuit 311.

[0068] In addition, the tap bias voltage VBTAP may include a first tap bias voltage VBTAP1, a second tap bias voltage VBTAP2, a third tap bias voltage VBTAP3, and an nth tap bias voltage VBTAPn, and one tap bias voltage may correspond to one DFE tap.

[0069] For example, the first tap bias voltage VBTAP1 may correspond to the first DFE tap 31_1. For example, the first tap bias voltage VBTAP1 may include the bias voltage required to drive the first DFE tap 31_1 having a first tap value C1.

[0070] In addition, the DQ bias voltage VBDQ may be determined respectively through Figure 3A the read training operation or the write training operation in the operation S330 or the operation S340. For example, the tap bias voltage generation circuit 315 may provide the DQ bias voltage VBDQ determined through the training operation to the filter circuit 311. In some embodiments, the control logic circuit 220 may provide the DQ bias voltage VBDQ to the filter circuit 311 or the tap bias voltage generation circuit 315 based on the parameter code stored in the MRS210.

[0071] In addition, the tap bias voltage VBTAP may be determined respectively through Figure 3A the read training operation or the write training operation in the operation S330 or the operation S340. Different from the DQ bias voltage VBDQ, the tap bias voltage VBTAP may be re-determined according to the temperature change after the training operation.

[0072] For example, the tap bias voltage generation circuit 315 may provide the tap bias voltage VBTAP to the filter circuit 311 based on the temperature change after the training operation.

[0073] Since the tap bias voltage VBTAP changes according to the temperature change, the tap values C1 to Cn It may be different from the value determined in the training operation. Therefore, even after the training operation, the tap values C1 to C can be determined again according to the temperature change. n .

[0074] The tap bias voltage generation circuit 315 can output a tap bias voltage VBTAP based on the DQ bias voltage VBDQ, the tap code TAP_CODE set in the training operation, and the temperature code TEMP_CODE dependent on temperature.

[0075] In addition, the temperature code TEMP_CODE can include a bit string of n bits, and the temperature code TEMP_CODE can be provided from the temperature monitoring circuit 280.

[0076] In some embodiments, the temperature code TEMP_CODE can be represented as a unary code. For example, when the temperature code TEMP_CODE is represented as 0000, it represents a value of 0; when the temperature code TEMP_CODE is represented as 0001, it represents a value of 1; when the temperature code TEMP_CODE is represented as 0011, it represents a value of 2; when the temperature code TEMP_CODE is represented as 0111, it represents a value of 3; and when the temperature code TEMP_CODE is represented as 1111, it represents a value of 4. The 4-bit temperature code TEMP_CODE can represent 0 to 4.

[0077] In some embodiments, the temperature code TEMP_CODE can be represented as a unary code. For example, when the temperature code TEMP_CODE is represented as 0000, it represents a value of 0; when the temperature code TEMP_CODE is represented as 1000, it represents a value of 1; when the temperature code TEMP_CODE is represented as 1100, it represents a value of 2; when the temperature code TEMP_CODE is represented as 1110, it represents a value of 3; and when the temperature code TEMP_CODE is represented as 1111, it represents a value of 4. The 4-bit temperature code TEMP_CODE can represent 0 to 4.

[0078] In addition, the tap code TAP_CODE can include a bit string of 6 bits, and the tap code TAP_CODE can be provided from the MRS210. In some embodiments, the control logic circuit 220 can provide the tap code TAP_CODE to the tap bias voltage generation circuit 315 based on the parameter code stored in the MRS 210.

[0079] In addition, the tap code TAP_CODE can be represented as a binary code. For example, when the tap code TAP_CODE is represented as 000000, it represents 0; when the tap code TAP_CODE is represented as 000011, it represents 3; when the tap code TAP_CODE is represented as 111111, it represents 63. The tap code TAP_CODE can represent values from 0 to 63.

[0080] In some embodiments, the tap bias voltage generation circuit 315 may further include a decoder that converts a digital signal into an analog signal. The tap bias voltage generation circuit 315 can use the decoder to provide a tap bias voltage VBTAP to the filter circuit 311 based on the tap code TAP_CODE and the temperature code TEMP_CODE.

[0081] In addition, the filter circuit 311 can amplify the difference between the voltage level of the input signal DQ and the voltage level of the reference voltage VREF to generate a first internal signal INT_P and a second internal signal INT_N, and then can provide the first internal signal INT_P and the second internal signal INT_N to the sampler 313. Here, the voltage level difference between the first internal signal INT_P and the second internal signal INT_N can correspond to the internal signal INT_DQ.

[0082] The sampler 313 can sample the first internal signal INT_P and the second internal signal INT_N using the write clock signal DQS, and then output a first sample signal PRE_H and a second sample signal PRE_HB. In addition, the voltage level difference between the first sample signal PRE_H and the second sample signal PRE_HB can correspond to the sample signal SDQ. The sample signal SDQ can include a digital signal corresponding to the bit of the input signal DQ.

[0083] In addition, the first internal signal INT_P and the second internal signal INT_N can be signals calibrated by the first sample signal PRE_H and the second sample signal PRE_HB of the sampler 313 respectively. In addition, the voltage level difference between the first sample signal PRE_H and the second sample signal PRE_HB can correspond to the delayed first sample signal H1.

[0084] Figure 8 is a diagram showing an equivalent circuit of the filter circuit 311a according to an exemplary embodiment. Figure 8 An example is shown in which the filter circuit 311a includes only the first DFE tap 31_1a. However, this is only for ease of description, and the present embodiment is not limited thereto. For example, the filter circuit 311a can include the first DFE tap 31_1a to the nth DFE tap 31_na.

[0085] Reference Figure 8, the filter circuit 311a may include an adder 33a and a first DFE tap 31_1a.

[0086] In addition, the adder 33a may amplify the difference between the voltage level of the input signal DQ and the voltage level of the reference voltage VREF to generate a first internal signal INT_P and a second internal signal INT_N, and then may provide the first internal signal INT_P and the second internal signal INT_N to the sampler 313 ( Figure 6 ). The difference between the voltage level of the first internal signal INT_P and the voltage level of the second internal signal INT_N may correspond to the calibrated internal signal INT_DQ described in Figure 6 .

[0087] The adder 33a may compare the voltage level of the input signal DQ with the voltage level of the reference voltage VREF, amplify the difference between the voltage level of the input signal DQ and the voltage level of the reference voltage VREF, and generate the first internal signal INT_P and the second internal signal INT_N at the first node N1 and the second node N2, respectively. The reference voltage VREF may be provided from the reference voltage generation circuit 250 ( Figure 2 ).

[0088] The adder 33a may include transistors MN1, MN2, and MN3 and resistors R1 and R2. The transistors MN1, MN2, and MN3 may be provided as n-type metal oxide semiconductor (NMOS) transistors.

[0089] The line of the input signal DQ may be connected to the gate terminal of the transistor MN1. The source terminal of the transistor MN1 may be connected to the drain terminal of the transistor MN3, and the drain terminal of the transistor MN1 may be connected to the resistor R1. The transistor MN1 may control the amount of current flowing between the drain terminal and the source terminal of the transistor MN1 according to the voltage level of the input signal DQ.

[0090] The line of the reference voltage VREF may be connected to the gate terminal of the transistor MN2. The source terminal of the transistor MN2 may be connected to the drain terminal of the transistor MN3, and the drain terminal of the transistor MN2 may be connected to the resistor R2.

[0091] The transistor MN3 may be referred to as a CS1 current source. The CS1 current source may provide a first bias current IDQ flowing through the transistors MN1 and MN2. The line of the DQ bias voltage VBDQ may be connected to the gate terminal of the transistor MN3. The drain terminal of the transistor MN3 may be connected to the source terminals of the transistors MN1 and MN2, and the source terminal of the transistor MN3 may be connected to the ground voltage VSS.

[0092] The resistor R1 can be connected between the power supply voltage VDD and the drain terminal of the transistor MN1. The resistor R2 can be connected between the power supply voltage VDD and the drain terminal of the transistor MN2. Each of the resistors R1 and R2 can be formed using a passive element or a transistor. The transistors MN1 and MN2 can have the same configuration, and the resistors R1 and R2 can also have the same configuration.

[0093] The adder 33a can include a current mode logic (CML) circuit. The first internal signal INT_P can be output from a first node N1 between the drain terminal of the transistor MN2 and the resistor R2, and the second internal signal INT_N can be output from a second node N2 between the drain terminal of the transistor MN1 and the resistor R1. In the adder 33a, the voltage levels (i.e., swing levels) of the first internal signal INT_P and the second internal signal INT_N can be determined based on the difference between the voltage level of the input signal DQ and the voltage level of the reference voltage VREF.

[0094] The first DFE tap 31_1a can provide a second bias current ITAP1 to one of the lines of the first internal signal INT_P and the second internal signal INT_N based on the delayed first sample signal H1, and can reduce the voltage level output from the line to which the second bias current ITAP1 is provided by a first tap value C1. In addition, when R1 = R2 = RL, the first tap value C1 can be RL ITAP1.

[0095] In addition, the delayed first sample signal H1 can represent the value of the previous data bit of the current data bit of the input signal DQ, and the value indicated by the delayed first sample signal H1 can be "0" or "1". For example, when the delayed first sample signal H1 is sampled at the rising edge of the write clock signal DQS applied to the sampler 313 ( Figure 6 ), the current data bit of the input signal DQ (i.e., the sample signal SDQ) can be sampled at the next falling edge of the write clock signal DQS. In addition, when the first sample signal H1 is sampled at the falling edge of the write clock signal DQS applied to the sampler 313 ( Figure 6 ), the current data bit of the input signal DQ (i.e., the sample signal SDQ) can be sampled at the next rising edge of the write clock signal DQS.

[0096] The first DFE tap 31_1a can include transistors MN4, MN5, and MN6. The transistors MN4, MN5, and MN6 can be provided as NMOS transistors.

[0097] The line of the first sample signal PRE_H can be connected to the gate terminal of transistor MN4. The source terminal of transistor MN4 can be connected to the drain terminal of transistor MN6, and the drain terminal of transistor MN4 can be connected to the line of the first internal signal INT_P. Transistor MN4 can control the amount of current flowing between the drain terminal and the source terminal of transistor MN4 in response to the first sample signal PRE_H.

[0098] The line of the inverted second sample signal PRE_HB can be connected to the gate terminal of transistor MN5. Additionally, the first sample signal PRE_H and the second sample signal PRE_HB can be a differential pair. In some embodiments, the second sample signal PRE_HB can correspond to the output of an inverter that receives the first sample signal PRE_H and outputs the second sample signal PRE_HB, and the inverter can be provided in the line of the first sample signal PRE_H.

[0099] The source terminal of transistor MN5 can be connected to the drain terminal of transistor MN6, and the drain terminal of transistor MN5 can be connected to the line of the second internal signal INT_N. Transistor MN5 can control the amount of current flowing between the drain terminal and the source terminal of transistor MN5 in response to the inverted second sample signal PRE_HB.

[0100] Furthermore, the voltage level difference between the first sample signal PRE_H and the second sample signal PRE_HB can correspond to the delayed first sample signal H1.

[0101] If the value indicated by the first sample signal H1 is "1", transistor MN4 can be configured such that current flows between the drain terminal and the source terminal of transistor MN4, and transistor MN5 can be configured such that no current flows between the drain terminal and the source terminal of transistor MN5.

[0102] If the value indicated by the first sample signal H1 is "0", transistor MN4 can be configured such that no current flows between the drain terminal and the source terminal of transistor MN4, and transistor MN5 can be configured such that current flows between the drain terminal and the source terminal of transistor MN5.

[0103] Transistor MN6 can be referred to as a CS2 current source. The CS2 current source can provide a second bias current ITAP1 that flows through one of transistors MN4 and MN5. The line of the first tap bias voltage VBTAP1 can be connected to the gate terminal of transistor MN6. The drain terminal of transistor MN6 can be connected to the source terminals of transistors MN4 and MN5, and the source terminal of transistor MN6 can be connected to the ground voltage VSS.

[0104] For example, if the value indicated by the first sample signal H1 is "1", the CS2 current source can supply a second bias current ITAP1 flowing through the transistor MN4 to the line of the first internal signal INT_P. If the value indicated by the first sample signal H1 is "0", the CS2 current source can supply a second bias current ITAP1 flowing through the transistor MN5 to the line of the second internal signal INT_N.

[0105] Figure 9 is a diagram showing a tap bias voltage generation circuit 400 according to an exemplary embodiment. Figure 9 shows the tap bias voltage generation circuit 400 that outputs the first tap bias voltage VBTAP1 provided to the first DFE tap 31_1a ( Figure 8 ), but the embodiment is not limited thereto. The tap bias voltage generation circuit 400 can output the first tap bias voltage VBTAP1 to the nth tap bias voltage VBTAPn by appropriately modifying the content described below.

[0106] Reference Figure 9 , the tap bias voltage generation circuit 400 can include a temperature calibration circuit 410 and a calibration circuit 420.

[0107] The temperature calibration circuit 410 can include multiple current paths (e.g., 411a in Figure 10 ) that are turned on or off based on the temperature code TEMP_CODE and at least one current path (e.g., 413a in Figure 10 ) that is connected to the ground voltage and continuously conducts current. For example, at least one current path can include a PMOS transistor having a gate terminal connected to the ground voltage such that current can flow in at least one current path.

[0108] Hereinafter, the current path provided in the temperature calibration circuit 410 and turned on or off based on the temperature code TEMP_CODE is referred to as an input current path. In addition, the current path provided in the temperature calibration circuit 410 that is connected to the ground voltage and continuously conducts current is referred to as a default current path. In an embodiment, the temperature calibration circuit 410 can include multiple default current paths.

[0109] In addition, the temperature calibration circuit 410 can further include an NMOS transistor MN7 ( Figure 10 ) that provides a DQ bias current IDQ ( Figure 10 ) flowing through multiple input current paths and at least one default current path. In addition, the DQ bias current IDQ ( Figure 10 ) can be provided by a DQ bias voltage VBDQ applied to the gate terminal of the NMOS transistor MN7 ( Figure 10 ).

[0110] The gate terminal of the NMOS transistor MN7 that provides the DQ bias current IDQ ( Figure 10 ) can be connected to the line of the DQ bias voltage VBDQ. The gate terminal of the NMOS transistor MN7 that provides the DQ bias current IDQ ( Figure 10 ) can be connected to the line of the DQ bias voltage VBDQ. The source terminal of the NMOS transistor MN7 that provides the DQ bias current IDQ ( Figure 10 ) can be connected to the ground voltage, and the drain terminal of the NMOS transistor MN7 that provides the DQ bias current IDQ ( Figure 10 ) can be connected to the ground voltage, and the drain terminal of the NMOS transistor MN7 that provides the DQ bias current IDQ ( Figure 10 ) can be connected in parallel to a plurality of input current paths and at least one default current path. Figure 10 ) can be connected in parallel to a plurality of input current paths and at least one default current path.

[0111] In addition, the plurality of input current paths of the temperature calibration circuit 410 may include a first PMOS transistor (e.g., Figure 10 MPA31, MPA21, MPA11, and MPA01 in Figure 10 ) and a second PMOS transistor (e.g.,

[0112] ) and a second PMOS transistor (e.g.,

[0113] MPA32, MPA22, MPA12, and MPA02 in Figure 10 ), each first PMOS transistor having a gate terminal connected to the line of the temperature code TEMP_CODE, and the second PMOS transistor having a gate terminal connected to the line of the bias voltage VB.

[0114] In addition, the source terminal of the first PMOS transistor can be connected to the power supply voltage, and the drain terminal of each first PMOS transistor can be connected to the corresponding source terminal of each second PMOS transistor. Figure 10 In addition, the source terminal of the first PMOS transistor can be connected to the power supply voltage, and the drain terminal of each first PMOS transistor can be connected to the corresponding source terminal of each second PMOS transistor. Figure 10 In addition, the source terminal of the first PMOS transistor can be connected to the power supply voltage, and the drain terminal of each first PMOS transistor can be connected to the corresponding source terminal of each second PMOS transistor.

[0115] In addition, the drain terminal of the second PMOS transistor can be connected to the drain terminal of the NMOS transistor MN7 (

[0116] The drain terminal of the fourth PMOS transistor can be connected to the drain terminal of the NMOS transistor MN7 that provides the DQ bias current. The gate terminal of the fourth PMOS transistor can be connected to the drain terminal of the fourth PMOS transistor. That is, each second PMOS transistor can be provided as a diode-connected transistor.

[0117] The temperature calibration circuit 410 can output a bias voltage VB based on the DQ bias voltage VBDQ and the number of conductive input current paths. In an embodiment, the temperature calibration circuit 410 can provide the bias voltage VB to the calibration circuit 420.

[0118] The number of conductive input current paths can correspond to the number of first PMOS transistors among the first PMOS transistors in each of the plurality of input current paths that are conductive in response to the temperature code TEMP_CODE. That is, depending on the conduction or cutoff of the first PMOS transistors in the plurality of input current paths, the conduction or cutoff of the corresponding input current paths can be determined.

[0119] In addition, the drain terminal and the gate terminal of the second PMOS transistor are connected to each other. Therefore, depending on the magnitude of the current flowing in an input current path, the voltage level of the line to which the bias voltage VB to which the gate terminal of the second PMOS transistor is connected can vary.

[0120] Similarly, the drain terminal and the gate terminal of the fourth PMOS transistor are connected to each other. Therefore, depending on the magnitude of the current flowing in a default current path, the voltage level of the line to which the bias voltage VB to which the gate terminal of the fourth PMOS transistor is connected can vary.

[0121] Furthermore, each of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor can have the same configuration. Therefore, the magnitude of the current (e.g., Figure 10 Ib) flowing through a default current path can be the same as the magnitude of the current (e.g., Figure 10 Ia) flowing through an input current path.

[0122] In addition, since the NMOS transistor MN7 ( Figure 10 ) provides the DQ bias current IDQ ( Figure 10 ), the total magnitude of the currents flowing through the conductive input current paths and at least one default current path must be equal to the magnitude of the DQ bias current IDQ ( Figure 10 ). Therefore, the magnitude of the current flowing through each conductive input current path and at least one default current path can be equal to by dividing the DQ bias current IDQ ( Figure 10The value obtained by dividing the magnitude of () by the number of conductive input current paths and default current paths.

[0123] When the magnitude of the current flowing in a default current path (e.g., Figure 10 Ib) is the same as the magnitude of the current flowing in an input current path (e.g., Figure 10 Ia), each of the fourth PMOS transistor and the second PMOS transistor can output the bias voltage VB through the shared line of the bias voltage VB depending on the magnitude of the same current flowing in each current path.

[0124] For example, the temperature calibration circuit 410 can output the bias voltage VB to the calibration circuit 420 through the line of the bias voltage VB based on the value obtained by dividing the magnitude of the DQ bias current IDQ ( Figure 10 ) by the number of conductive input current paths and default current paths. In addition, the DQ bias current IDQ ( Figure 10 ) can be provided by the DQ bias voltage VBDQ applied to the gate terminal of the NMOS transistor MN7 ( Figure 10 ).

[0125] In an embodiment, the temperature calibration circuit 410 can include the NMOS transistor MN7 ( Figure 10 ) configured such that the DQ bias voltage VBDQ is applied to the gate terminal of the NMOS transistor MN7, the drain terminal of the NMOS transistor MN7 is connected in parallel to multiple input current paths and at least one default current path, and the DQ bias current IDQ ( Figure 10 ) flows between the drain terminal and the source terminal of the NMOS transistor MN7. Each of the multiple input current paths can include a corresponding PMOS transistor (e.g., one of the second PMOS transistors) configured such that based on the magnitude of the current flowing between the drain terminal and the source terminal of the corresponding PMOS transistor, the bias voltage VB is output through the gate terminal of the corresponding PMOS transistor. The magnitude of the DQ bias current IDQ ( Figure 10 ) can be obtained by adding the total magnitude of the current flowing through all conductive input current paths and the total magnitude of the current flowing through all default current paths.

[0126] The calibration circuit 420 can include multiple current paths (e.g., Figure 10 421a) that are turned on or off based on the first tap code TAP1_CODE. Hereinafter, the current paths provided in the calibration circuit 420 and turned on or off based on the first tap code TAP1_CODE are referred to as output current paths.

[0127] In addition, the calibration circuit 420 may further include an NMOS transistor MN8 ( Figure 10 ), which outputs a first tap bias voltage VBTAP1 based on a first tap bias current ITAP1 ( Figure 10 ) flowing through multiple output current paths. In addition, the first tap bias voltage VBTAP1 may be provided by the first tap bias current ITAP1 ( Figure 10 ) flowing between the drain terminal and the source terminal of the NMOS transistor MN8 ( Figure 10 ). The gate terminal of the NMOS transistor MN8 ( Figure 10 ) that provides the first tap bias voltage VBTAP1 may be connected to the line of the first tap bias voltage VBTAP1. In an embodiment, the NMOS transistor MN8 ( Figure 10 ) may provide the first tap bias voltage VBTAP1 to the first DFE tap 31_1a ( Figure 8 ).

[0128] Specifically, the line of the first tap bias voltage VBTAP1 may be connected to the gate terminal of the transistor MN6 of the first DFE tap 31_1a ( Figure 8 ). If the transistor MN6 and the transistor MN8 have the same configuration, the transistor MN6 and the transistor MN8 may form a current mirror by sharing the first tap bias voltage VBTAP1 applied to their gate terminals. For example, the currents flowing from the drain terminals to the source terminals of the transistor MN6 and the transistor MN8 may have the same magnitude.

[0129] In addition, the gate terminal of the NMOS transistor MN8 ( Figure 10 ) that provides the first tap bias voltage VBTAP1 may be connected to the drain terminal of the NMOS transistor MN8 ( Figure 10 ) that provides the first tap bias voltage VBTAP1. That is, the NMOS transistor MN8 ( Figure 10 ) may be provided as a diode-connected transistor.

[0130] In addition, the source terminal of the NMOS transistor MN8 ( Figure 10 ) that provides the first tap bias voltage VBTAP1 may be connected to the ground voltage, and the drain terminal of the NMOS transistor MN8 ( Figure 10 ) that provides the first tap bias voltage VBTAP1 may be connected in parallel to multiple output current paths.

[0131] In addition, each of the multiple output current paths of the calibration circuit 420 may include a fifth PMOS transistor (e.g., Figure 10MPC51, MPC41, MPC31, MPC21, MPC11, and MPC01) and a sixth PMOS transistor (e.g., Figure 10 MPC52, MPC42, MPC32, MPC22, MPC12, and MPC02) in it. Each fifth PMOS transistor has a gate terminal connected to the line of the first tap code TAP1_CODE, and the sixth PMOS transistor has a gate terminal connected to the line of the bias voltage VB.

[0132] In addition, the source terminal of the fifth PMOS transistor can be connected to the power supply voltage, and the drain terminal of each fifth PMOS transistor can be connected to the corresponding source terminal of each sixth PMOS transistor.

[0133] Furthermore, the drain terminal of the sixth PMOS transistor can be connected to the drain terminal of the NMOS transistor MN8 ( Figure 10 ) that provides the first tap bias voltage VBTAP1. The gate terminal of the sixth PMOS transistor can be connected to the line of the bias voltage VB.

[0134] The calibration circuit 420 can output the first tap bias voltage VBTAP1 based on the bias voltage VB and the number of conducting output current paths. In an embodiment, the calibration circuit 420 can provide the first tap bias voltage VBTAP1 to the first DFE tap 31_1a ( Figure 8 ).

[0135] The number of conducting output current paths can correspond to the number of fifth PMOS transistors among each output current path in the multiple output current paths that are turned on in response to the first tap code TAP1_CODE. That is, depending on the on or off state of the fifth PMOS transistors in the multiple output current paths, the on or off state of the corresponding output current paths can be determined.

[0136] In addition, since the gate terminals of the sixth PMOS transistors in the multiple output current paths are connected to the line of the bias voltage VB, the magnitude of the current flowing through the multiple output current paths can be determined according to the bias voltage VB.

[0137] For example, the second PMOS transistor, the fourth PMOS transistor, and the sixth PMOS transistor can form a current mirror by sharing the bias voltage VB applied to their gate terminals respectively. In addition, the current flowing through one of the sixth PMOS transistors (e.g., Figure 10 Ic) can be determined by the current flowing through one of the second PMOS transistors (e.g., Figure 10 Ia) or the current flowing through the fourth PMOS transistor (e.g., Figure 10 Ib).

[0138] Here, each of the first to sixth PMOS transistors may have the same configuration. Thus, the magnitude of the current flowing in one output current path (e.g., Figure 10 Ic) can be the same as the magnitude of the current flowing in a default current path (e.g., Figure 10 Ib) or the magnitude of the current flowing in an input current path (e.g., Figure 10 Ia).

[0139] In addition, since the multiple output current paths and the NMOS transistor MN8 ( Figure 10 ) are connected in parallel with each other, the magnitude of the first tap bias current ITAP1 ( Figure 10 ) flowing between the drain terminal and the source terminal of the NMOS transistor MN8 ( Figure 10 ) must be equal to the total magnitude of the current flowing through the output current paths. Thus, the magnitude of the first tap bias current ITAP1 ( Figure 10 ) can be equal to the value obtained by multiplying the magnitude of the current flowing in one conducting output current path by the number of conducting output current paths.

[0140] For example, the calibration circuit 420 can output the first tap bias voltage VBTAP1 based on the value obtained by multiplying the magnitude of the current flowing in one conducting output current path by the number of conducting output current paths. In addition, the first tap bias voltage VBTAP1 can be determined by the first tap bias current ITAP1 ( Figure 10 ) flowing between the drain terminal and the source terminal of the NMOS transistor MN8 ( Figure 10 ).

[0141] In an embodiment, the calibration circuit 420 may further include the NMOS transistor MN8 ( Figure 10 ), which is configured such that the drain terminal of the NMOS transistor MN8 is connected in parallel to the multiple output current paths, the first tap bias current ITAP1 ( Figure 10 ) flows between the drain terminal and the source terminal of the NMOS transistor MN8, and the first tap bias voltage VBTAP1 is output through the gate terminal of the NMOS transistor MN8. Each of the multiple output current paths may include a corresponding PMOS transistor (e.g., one of the sixth PMOS transistors), and the corresponding PMOS transistor provides a current flowing between the drain terminal and the source terminal of the corresponding PMOS transistor based on the bias voltage VB. The magnitude of the first tap bias current ITAP1 can be equal to the total magnitude of the current flowing through all the conducting output current paths.

[0142] In addition, when each of the first PMOS transistor to the sixth PMOS transistor has the same configuration, the magnitude of the first tap bias current ITAP1 ( Figure 10 ), and the magnitude of the DQ bias current IDQ ( Figure 10 ) may have a relationship as shown in Equation 1 below.

[0143] [Equation 1]

[0144] In Equation 1, where ITAP1 represents the magnitude of the first tap bias current, IDQ represents the magnitude of the DQ bias current, A represents the number of conducting input current paths, B represents the number of default current paths, and C represents the number of conducting output current paths.

[0145] Figure 10 is a diagram showing an equivalent circuit of a tap bias voltage generation circuit according to an exemplary embodiment. Hereinafter, it can be described with reference to Figure 9 and its repeated description is omitted.

[0146] The tap bias voltage generation circuit 400a may include a temperature calibration circuit 410a and a calibration circuit 420a.

[0147] The temperature calibration circuit 410a may include a plurality of input current paths 411a that are turned on or off based on the temperature code TEMP_CODE[3:0], and at least one current path 413a and an NMOS transistor MN7 that are connected to the ground voltage VSS and continuously conduct current.

[0148] The calibration circuit 420a may include a plurality of output current paths 421a that are turned on or off based on the first tap code TAP1_CODE and an NMOS transistor MN8.

[0149] The plurality of input current paths 411a of the temperature calibration circuit 410a may include a first PMOS transistor (e.g., MPA31, MPA21, MPA11, and MPA01) and a second PMOS transistor (e.g., MPA32, MPA22, MPA12, and MPA02), each first PMOS transistor having a gate terminal connected to a line of the temperature code TEMP_CODE[3:0], and the second PMOS transistor having a gate terminal connected to a line of the bias voltage VB.

[0150] At least one default current path 413a of the temperature calibration circuit 410a may include a third PMOS transistor MPB01 and a fourth PMOS transistor MPB02. The third PMOS transistor MPB01 has a gate terminal connected to the ground voltage, and the fourth PMOS transistor MPB02 has a gate terminal connected to a line of the bias voltage VB.

[0151] Multiple output current paths of the calibration circuit 420a may include a fifth PMOS transistor (e.g., MPC51, MPC41, MPC31, MPC21, MPC11, and MPC01) and a sixth PMOS transistor (e.g., MPC52, MPC42, MPC32, MPC22, MPC12, and MPC02). Each fifth PMOS transistor has a gate terminal connected to a line of the first tap code TAP1_CODE[5:0], and the sixth PMOS transistor has a gate terminal connected to a line of the bias voltage VB.

[0152] Reference Figure 10 , the multiple input current paths 411a may be configured such that the number of the multiple input current paths 411a corresponds to the number of values that can be represented by the temperature code TEMP_CODE[3:0]. For example, the number of the multiple input current paths 411a may be obtained by subtracting 1 from the number of values that can be expressed by the temperature code TEMP_CODE[3:0].

[0153] In addition, the temperature code TEMP_CODE[3:0] may include a 4-bit bit string, and the temperature code TEMP_CODE[3:0] may be provided from the temperature monitoring circuit 280. In addition, the temperature code TEMP_CODE[3:0] may be represented as a unary code.

[0154] For example, when the temperature code TEMP_CODE[3:0] is represented as 0000, it represents a value of 0. When the temperature code TEMP_CODE[3:0] is represented as 0001, it represents a value of 1. When the temperature code TEMP_CODE[3:0] is represented as 0011, it represents a value of 2. When the temperature code TEMP_CODE[3:0] is represented as 0111, it represents a value of 3. When the temperature code TEMP_CODE[3:0] is represented as 1111, it represents a value of 4. The temperature code TEMP_CODE[3:0] may represent 0 to 4.

[0155] For example, when the temperature code TEMP_CODE[3:0] includes a 4-bit unary code, the number of the input current paths 411a may be 4.

[0156] In addition, reference Figure 10, ma can represent the number of input current paths assigned to each bit of the temperature code TEMP_CODE[3:0].

[0157] For example, since ma = 1, there is a zero - th input current path that conducts or cuts off in response to the bit value of the zero - th bit ([0]) of the temperature code TEMP_CODE[3:0]. In addition, since ma = 1, there is a first input current path that conducts or cuts off in response to the bit value of the first bit ([1]) of the temperature code TEMP_CODE[3:0]. In addition, since ma = 1, there is a second input current path that conducts or cuts off in response to the bit value of the second bit ([2]) of the temperature code TEMP_CODE[3:0]. In addition, since ma = 1, there is a third input current path that conducts or cuts off in response to the bit value of the third bit ([3]) of the temperature code TEMP_CODE[3:0].

[0158] Here, the first PMOS transistor in each of the multiple input current paths can be configured to conduct when the bit value is 0.

[0159] In an embodiment, the temperature code TEMP_CODE[3:0] can be represented as a unary code, and the temperature calibration circuit 410a can be configured to conduct as many input current paths 411a as the number of 0s represented in the temperature code TEMP_CODE[3:0].

[0160] In an embodiment, the temperature calibration circuit 410a can be configured such that the number of conducting input current paths increases by 1 as the value of the temperature code TEMP_CODE[3:0] decreases by 1.

[0161] Reference Figure 10 , mb can represent the number of default current paths 413a in at least one default current path 413a. That is, although only one default current path is shown in Figure 10 , N default current paths can be provided according to the embodiment.

[0162] Reference Figure 10 , the multiple output current paths 421a can be configured such that the number of the multiple output current paths 421a corresponds to the number of values that can be represented by the first tap code TAP1_CODE[5:0]. That is, the number of the multiple output current paths 421a can be obtained by subtracting 1 from the number of values that can be represented by the first tap code TAP1_CODE[5:0].

[0163] In addition, the first tap code TAP1_CODE[5:0] may include a 6-bit bit string, and the first tap code TAP1_CODE[5:0] may be provided from the MRS 210. In addition, the first tap code TAP1_CODE[5:0] may be represented as a binary code.

[0164] For example, when the first tap code TAP1_CODE[5:0] is represented as 000000, it represents 0. When the first tap code TAP1_CODE[5:0] is represented as 000011, it represents 3. When the first tap code TAP1_CODE[5:0] is represented as 111111, it represents 63. The first tap code TAP1_CODE[5:0] may represent values from 0 to 63.

[0165] That is, when the first tap code TAP1_CODE[5:0] includes a 6-bit binary code, the number of output current paths 421a may be 63.

[0166] In addition, referring to Figure 10 , mc may represent the number of output current paths assigned to each bit of the first tap code TAP1_CODE[5:0]. That is, for ease of description, in Figure 10 , only one output current path is shown for each bit of the first tap code TAP1_CODE[5:0], but different numbers of output current paths may be provided for each bit of the first tap code TAP1_CODE[5:0].

[0167] For example, since mc = 1, there is one zero-th output current path that is turned on or off in response to the bit value of the zero-th bit ([0]) of the first tap code TAP1_CODE[5:0]. In addition, since mc = 2, there are two first output current paths that are turned on or off in response to the bit value of the first bit ([1]) of the first tap code TAP1_CODE[5:0]. In addition, since mc = 4, there are four second output current paths that are turned on or off in response to the bit value of the second bit ([2]) of the first tap code TAP1_CODE[5:0]. In addition, since mc = 8, there are eight third output current paths that are turned on or off in response to the bit value of the third bit ([3]) of the first tap code TAP1_CODE[5:0]. In addition, since mc = 16, there are sixteen fourth output current paths that are turned on or off in response to the bit value of the fourth bit ([4]) of the first tap code TAP1_CODE[5:0]. In addition, since mc = 32, there are thirty-two fifth output current paths that are turned on or off in response to the bit value of the fifth bit ([5]) of the first tap code TAP1_CODE[5:0].

[0168] Here, the fifth PMOS transistor in each of the multiple output current paths can be configured to conduct when the bit value is 0.

[0169] In addition, when each of the first PMOS transistor to the sixth PMOS transistor can have the same configuration, the magnitude of the first tap bias current ITAP1 and the magnitude of the DQ bias current IDQ can have the relationship as shown in Equation 1 above. The relationship between the magnitude of the first tap bias current ITAP1 and the magnitude of the DQ bias current IDQ according to the temperature code and the first tap code is described below.

[0170] The temperature monitoring circuit 280 ( Figure 7 ) can generate a temperature code TEMP_CODE[3:0] such that the value of the temperature code TEMP_CODE[3:0] decreases as the temperature increases.

[0171] When the temperature code TEMP_CODE[3:0] is 1100 and the first tap code TAP1_CODE[5:0] is 111100, the relationship ITAP1 = 3 / (2 + N) IDQ is established. Specifically, this is because the temperature calibration circuit 410a can have 2 (the number of conducting input current paths) + N (the number of default current paths) current paths, and the calibration circuit 420 can have 3 (the number of the zero output current path + the number of the first output current path) current paths.

[0172] When the temperature code TEMP_CODE[3:0] is 0000 and the first tap code TAP1_CODE[5:0] is 111100, the relationship ITAP1 = 3 / (4 + N) IDQ is established. Specifically, this is because the temperature calibration circuit 410a can have 4 (the number of conducting input current paths) + N (the number of default current paths) current paths, and the calibration circuit 420 can have 3 (the number of the zero output current path + the number of the first output current path) current paths.

[0173] For example, as the temperature increases, the value of the temperature code TEMP_CODE[3:0] can decrease. Therefore, the magnitude of the first tap bias current ITAP1 can be decreased.

[0174] As the magnitude of the first tap bias current ITAP1 decreases, the first tap value C1 (which is RL ITAP1) can decrease.

[0175] Therefore, as the temperature increases, the first tap value C1 can be decreased by the temperature calibration circuit 410a.

[0176] Figure 11 This is a diagram showing the effect of a DFE including a temperature calibration circuit according to an exemplary embodiment.

[0177] Referring to Figure 11 , it can be seen that a first tap value 42 dependent on temperature, a first tap value 44 calibrated by a temperature calibration circuit 410 ( Figure 10 ), and a gain 46 dependent on temperature of an adder 33 ( Figure 6 ) are shown.

[0178] When comparing the first tap value 42 dependent on temperature with the gain 46 dependent on temperature of the adder 33 ( Figure 6 ), it can be seen that the temperature coefficient of the gain of the adder 33 ( Figure 6 ) is different from the temperature coefficient of the first tap value C1 of the first DFE tap 31_1 ( Figure 6 ).

[0179] For example, the temperature coefficient of the gain of the adder 33 ( Figure 6 ) may have a negative temperature coefficient (NTC), and the temperature coefficient of the first tap value C1 of the first DFE tap 31_1 ( Figure 6 ) may have a positive temperature coefficient (PTC).

[0180] According to the exemplary embodiment, the temperature code TEMP_CODE[3:0] is provided as described above. Thus, the DFE including the temperature calibration circuit 410 ( Figure 10 ) can adjust the first tap value C1 of the first DFE tap 31_1 ( Figure 6 ) according to the temperature range.

[0181] Referring to Figure 11 , at the first tap value 44 calibrated by the temperature calibration circuit 410 ( Figure 10 ), it can be seen that the temperature range from about 0 degrees to about 100 degrees is divided into five temperature ranges, and each range matches the value of the temperature code TEMP_CODE[3:0].

[0182] Thus, the change amount of the first tap value C1 of the first DFE tap 31_1 ( Figure 6 ) according to the temperature of the storage device 120 or the memory system 10 can be equal to the change amount of the gain of the adder 33 ( Figure 6 ) according to the temperature.

[0183] For example, when the temperature changes from about 0 degrees Celsius to about 20 degrees Celsius, the change amount of the first tap value C1 of the first DFE tap 31_1 ( Figure 6 ) can be equal to that of the adder 33 having a temperature code TEMP_CODE[3:0] of 1110 ( Figure 6The change in gain of ().

[0184] For example, according to the exemplary embodiment, even after the initialization and training of the memory system, the tap values C1 to C can be adjusted according to temperature changes n . Therefore, the transmitted data can have optimal SI and data eye diagrams.

[0185] Although the present invention has been specifically shown and described with reference to embodiments of the present invention, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A DFE, wherein the DFE is a decision feedback equalizer and comprises: an adder including a first node and a second node and configured to receive an input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and output a first internal signal from the first node and output a second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; as well as A tap bias voltage generating circuit is configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage, a tap code set in a training operation of the DFE, and a temperature code that depends on the temperature of the DFE.

2. The DFE according to claim 1, wherein: The tap bias voltage generating circuit comprises: a temperature calibration circuit, the temperature calibration circuit comprising a plurality of input current paths configured to be turned on or off based on the temperature code and at least one default current path connected to a ground voltage and configured to continuously flow current, wherein the temperature calibration circuit is configured to output a bias voltage based on the number of input current paths turned on and the DQ bias voltage; and A calibration circuit comprising a plurality of output current paths configured to be turned on or off based on the tap code, wherein the calibration circuit is configured to output the first tap bias voltage based on the bias voltage and the number of output current paths that are turned on.

3. The DFE of claim 2, wherein: The temperature calibration circuit also includes: an NMOS transistor, NMOS being an n-type metal oxide semiconductor, the NMOS transistor being configured such that the DQ bias voltage is applied to a gate terminal of the NMOS transistor, a drain terminal of the NMOS transistor is connected in parallel to the plurality of input current paths and the at least one default current path, and a DQ bias current flows between the drain terminal and a source terminal of the NMOS transistor, wherein each of the plurality of input current paths comprises a PMOS transistor, i.e., a p-type metal oxide semiconductor, the PMOS transistor being configured such that the bias voltage is output through a gate terminal of the PMOS transistor based on the magnitude of a current flowing between a drain terminal and a source terminal of the PMOS transistor, and The magnitude of the DQ bias current is obtained by adding the total magnitude of the current flowing through all the turned-on input current paths and the magnitude of the current flowing through the at least one default current path.

4. The DFE of claim 2, wherein: The calibration circuit further comprises: an NMOS transistor, NMOS being an n-type metal oxide semiconductor, wherein the NMOS transistor is configured such that a drain terminal of the NMOS transistor is connected in parallel to the plurality of output current paths, the first tap bias current flows between the drain terminal and a source terminal of the NMOS transistor, and the first tap bias voltage is output through a gate terminal of the NMOS transistor, Each of the plurality of output current paths includes a PMOS transistor, which is a p-type metal oxide semiconductor, and the PMOS transistor is configured to provide a current flowing between a drain terminal and a source terminal of the PMOS transistor based on the bias voltage, and The magnitude of the first tap bias current is equal to the total magnitude of the current flowing through all the turned-on output current paths.

5. The DFE of claim 2, wherein: The temperature code is represented as a unary code, and The temperature calibration circuit is configured to conduct the same number of input current paths as the number of zeros represented in the temperature code.

6. The DFE of claim 5, wherein: The temperature calibration circuit is configured such that the number of input current paths that are turned on increases by one as the value of the temperature code decreases by one.

7. The DFE of claim 1, wherein: The adder also includes: a first resistor connected between a power supply voltage and the second node; and a second resistor connected between the power supply voltage and the first node, wherein the tap value of the first DFE tap varies in dependence on the temperature in the same manner as the gain of the adder varies in dependence on the temperature, and The tap value is determined by multiplying the value of the first tap bias current by the resistance value of the first resistor or the second resistor.

8. A memory device, comprising a DFE, wherein the DFE is a decision feedback equalizer, and the DFE is configured to receive an input signal and output a first internal signal and a second internal signal, in, The DFE includes: an adder including a first node and a second node and configured to receive the input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and output the first internal signal from the first node and output the second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; and A tap bias voltage generating circuit is configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage, a tap code set in a training operation of the memory device, and a temperature code dependent on the temperature of the memory device.

9. The memory device according to claim 8, wherein: The tap bias voltage generating circuit comprises: a temperature calibration circuit, the temperature calibration circuit comprising a plurality of input current paths configured to be turned on or off based on the temperature code and at least one default current path connected to a ground voltage and configured to continuously flow current, wherein the temperature calibration circuit is configured to output a bias voltage based on the number of input current paths turned on and the DQ bias voltage; and A calibration circuit comprising a plurality of output current paths configured to be turned on or off based on the tap code, wherein the calibration circuit is configured to output the first tap bias voltage based on the bias voltage and the number of output current paths that are turned on.

10. The memory device according to claim 9, wherein: The temperature calibration circuit also includes: an NMOS transistor, NMOS being an n-type metal oxide semiconductor, the NMOS transistor being configured such that the DQ bias voltage is applied to a gate terminal of the NMOS transistor, a drain terminal of the NMOS transistor is connected in parallel to the plurality of input current paths and the at least one default current path, and a DQ bias current flows between the drain terminal and a source terminal of the NMOS transistor, wherein each of the plurality of input current paths comprises a PMOS transistor, i.e., a p-type metal oxide semiconductor, the PMOS transistor being configured such that the bias voltage is output through a gate terminal of the PMOS transistor based on the magnitude of a current flowing between a drain terminal and a source terminal of the PMOS transistor, and The magnitude of the DQ bias current is obtained by adding the total magnitude of the current flowing through all the turned-on input current paths and the magnitude of the current flowing through the at least one default current path.

11. The memory device according to claim 9, wherein: The temperature calibration circuit also includes: an NMOS transistor, NMOS being an n-type metal oxide semiconductor, the NMOS transistor being configured such that a drain terminal of the NMOS transistor is connected in parallel to the plurality of output current paths, the first tap bias current flows between the drain terminal and a source terminal of the NMOS transistor, and the first tap bias voltage is output through a gate terminal of the NMOS transistor, and Each of the plurality of output current paths includes a PMOS transistor, which is a p-type metal oxide semiconductor, and the PMOS transistor is configured to provide a current flowing between a drain terminal and a source terminal of the PMOS transistor based on the bias voltage, and The magnitude of the first tap bias current is equal to the total magnitude of the current flowing through all the turned-on output current paths.

12. The memory device according to claim 9, wherein: The temperature code is represented as a unary code, and The temperature calibration circuit is configured to conduct the same number of input current paths as the number of zeros represented in the temperature code.

13. The memory device according to claim 12, wherein: The temperature calibration circuit is configured such that the number of input current paths that are turned on increases by one as the value of the temperature code decreases by one.

14. The memory device according to claim 8, wherein: The adder also includes: a first resistor connected between a power supply voltage and the second node; and a second resistor connected between the power supply voltage and the first node, wherein the tap value of the first DFE tap varies in dependence on the temperature in the same manner as the gain of the adder varies in dependence on the temperature, and The tap value is determined by multiplying the value of the first tap bias current by the resistance value of the first resistor or the second resistor.

15. A memory system comprising a memory controller and a memory device connected to the memory controller, wherein: The memory device includes a DFE, the DFE being a decision feedback equalizer, and wherein the DFE is configured to receive an input signal and output a first internal signal and a second internal signal, and comprises: an adder including a first node and a second node and configured to receive the input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and output the first internal signal from the first node and output the second internal signal from the second node; a first DFE tap configured to provide a first tap bias current to one of the first node and the second node based on a first sample signal corresponding to a previous bit of the input signal; and a tap bias voltage generating circuit configured to provide a first tap bias voltage corresponding to the first tap bias current to the first DFE tap based on the DQ bias voltage, a tap code set in a training operation of the memory system, and a temperature code dependent on a temperature of the memory system.

16. The memory system according to claim 15, wherein: The tap bias voltage generating circuit comprises: a temperature calibration circuit, the temperature calibration circuit comprising a plurality of input current paths configured to be turned on or off based on the temperature code and at least one default current path connected to a ground voltage and configured to continuously flow current, wherein the temperature calibration circuit is configured to output a bias voltage based on the number of input current paths turned on and the DQ bias voltage; and A calibration circuit comprising a plurality of output current paths configured to be turned on or off based on the tap code, wherein the calibration circuit is configured to output the first tap bias voltage based on the bias voltage and the number of output current paths that are turned on.

17. The memory system of claim 16, wherein: The temperature calibration circuit also includes: an NMOS transistor, NMOS being an n-type metal oxide semiconductor, the NMOS transistor being configured such that the DQ bias voltage is applied to a gate terminal of the NMOS transistor, a drain terminal of the NMOS transistor is connected in parallel to the plurality of input current paths and the at least one default current path, and a DQ bias current flows between the drain terminal and a source terminal of the NMOS transistor, wherein each of the plurality of input current paths comprises a PMOS transistor, i.e., a p-type metal oxide semiconductor, the PMOS transistor being configured such that the bias voltage is output through a gate terminal of the PMOS transistor based on the magnitude of a current flowing between a drain terminal and a source terminal of the PMOS transistor, and The magnitude of the DQ bias current is obtained by adding the total magnitude of the current flowing through all the turned-on input current paths and the magnitude of the current flowing through the at least one default current path.

18. The memory system according to claim 16, wherein: The temperature calibration circuit also includes: an NMOS transistor, NMOS being an n-type metal oxide semiconductor, the NMOS transistor being configured such that a drain terminal of the NMOS transistor is connected in parallel to the plurality of output current paths, the first tap bias current flows between the drain terminal and a source terminal of the NMOS transistor, and the first tap bias voltage is output through a gate terminal of the NMOS transistor, and Each of the plurality of output current paths includes a PMOS transistor, which is a p-type metal oxide semiconductor, and the PMOS transistor is configured to provide a current flowing between a drain terminal and a source terminal of the PMOS transistor based on the bias voltage, and The magnitude of the first tap bias current is equal to the total magnitude of the current flowing through all the turned-on output current paths.

19. The memory system of claim 16, wherein: The temperature code is represented as a unary code, and The temperature calibration circuit is configured to conduct the same number of input current paths as the number of zeros represented in the temperature code.

20. The memory system of claim 15, wherein: The adder also includes: a first resistor connected between a power supply voltage and the second node; and a second resistor connected between the power supply voltage and the first node, wherein the tap value of the first DFE tap varies in dependence on the temperature in the same manner as the gain of the adder varies in dependence on the temperature, and The tap value is determined by multiplying the value of the first tap bias current by the resistance value of the first resistor or the second resistor.

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