MCU chip with built-in FLASH

Abstract

The invention discloses an MCU (Microprogrammed Control Unit) chip with a built-in FLASH, a FLASH controller circuit generates a read-write signal and a time sequence required by the FLASH according to a read-write instruction sent by a CPU (Central Processing Unit), and the state of a FLASH charge booster pump circuit control signal output by a programming time sequence generation module is 1 during continuous N programming pulse periods of a FLASH programming control signal; the state is 1 within a first set time before continuous N programming pulses, the state is 0 before the first set time before the continuous N programming pulses, and the state is 0 after a second set time after the continuous N programming pulses, so that FLASH continuous programming is realized. In the continuous programming mode, after the FLASH controller circuit receives the programming instruction sent by the CPU, continuous programming is directly carried out on the multiple FLASH addresses, extra charging and discharging time is not needed, the FLASH programming speed in the MCU chip can be increased, and the FLASH programming time can be shortened.

Description

Technical Field

[0001] The present invention relates to the technology of MCU (Micro Controller Unit) chips, and particularly to an MCU chip with built-in FLASH. Background Art

[0002] An MCU chip integrates a central processing unit (CPU), memory, a counter (Timer), A / D conversion, and peripheral interfaces such as UART (Universal Asynchronous Receiver / Transmitter) on a single chip, forming a chip-level computer for different combinations of control in different application scenarios. With the development of diverse applications, MCUs generally use built-in FLASH (flash memory) as the storage medium for the CPU to run programs.

[0003] The storage unit of FLASH is a three-terminal device with the same names as a field-effect transistor: source, drain, and gate. The difference is that the field-effect transistor has a single-gate structure, while FLASH has a double-gate structure with a floating gate added between the gate and the substrate. The structure is as Figure 1 shown.

[0004] There is a silicon dioxide insulating layer between the floating gate and the silicon substrate to protect the charges in the floating gate from leakage. Therefore, the data in FLASH remains after power-off.

[0005] 1) For programming of the flash memory, that is, controlling the gate to be charged and applying a voltage to the gate so that the charges stored in the floating gate increase and exceed the threshold, which represents data 0.

[0006] 2) For erasing the flash memory, by applying a voltage to the source to discharge the floating gate, when the charge is below the threshold, it represents data 1.

[0007] A high voltage needs to be applied to the control gate during programming to enable the charge to migrate to the floating gate. Taking 28nm FLASH as an example, this high voltage is 11V, while the operating voltage of the MCU is 3V. Therefore, a FLASH charge boost pump circuit is required inside the FLASH to raise the 3V voltage to 11V. After programming, to protect the service life of the device, the high voltage needs to be discharged through a buck pump circuit. During the entire programming process, the FLASH cannot perform read operations.

[0008] Taking the FLASH of a certain wafer fab as an example, before programming one byte of the FLASH, the charge time of the FLASH charge boost pump circuit is about 8 us, and after programming one byte of the FLASH, the discharge time of the buck pump circuit is 10 us for a time (discharge time), and the actual program time (program time) for one byte of the FLASH is 5 us. It can be seen that the time required for a single FLASH programming is about 23 us. The specification of the wafer fab requires that the timing of the main control signals of the FLASH module is as Figure 2 shown Figure 2 in the explanation table of the main control signals of the FLASH module in

[0009] Table 1

[0010]

[0011] For the existing MCU chip, after programming one address of the FLASH is completed, the high voltage is discharged, and then the programming of the next address is carried out. The programming timing of four addresses is as Figure 3 shown, and a total of 92 us is required. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide an MCU chip with built-in FLASH, which can directly perform continuous programming on multiple FLASH addresses, does not require additional charge and discharge time, can improve the FLASH programming speed in the MCU chip, and shorten the FLASH programming time.

[0013] To solve the above technical problem, the MCU chip with built-in FLASH provided by the present invention includes a central processing unit, a FLASH module, a FLASH charge boost pump circuit, and a FLASH controller circuit;

[0014] The FLASH controller circuit includes a programming timing generation module and a read timing generation module;

[0015] The programming timing generation module generates a FLASH charge boost pump circuit control signal and a FLASH programming control signal according to the read and write instructions issued by the CPU:

[0016] When the CPU issues a programming instruction for N byte addresses of the FLASH, N is an integer greater than 1:

[0017] The FLASH programming control signal output by the programming timing generation module is N consecutive programming pulses;

[0018] The control signal of the FLASH charge boost pump circuit output by the programming timing generation module is in the state of 1 during N consecutive programming pulses of the FLASH programming control signal, in the state of 1 within the first set time before the N consecutive programming pulses, in the state of 0 before the first set time before the N consecutive programming pulses, and in the state of 0 after the second set time after the N consecutive programming pulses;

[0019] The FLASH charge boost pump circuit is used to output a programming voltage to the control gate of the FLASH storage unit of the FLASH module, and the programming voltage is higher than the operating voltage of the MCU chip;

[0020] The FLASH charge boost pump circuit can work when the control signal of the FLASH charge boost pump circuit is 1 and stops working when the control signal of the FLASH charge boost pump circuit is 0.

[0021] Preferably, the read timing generation module generates a FLASH read control signal according to the read / write instruction issued by the CPU;

[0022] The FLASH read control signal generated by the read timing generation module is 0 when the control signal of the FLASH charge boost pump circuit is 1, 0 within the third set time after the control signal of the FLASH charge boost pump circuit changes from 1 to 0, and 1 after the third set time;

[0023] The FLASH cannot be read when the FLASH read control signal is 0, and the FLASH can be read when the FLASH read control signal is 1.

[0024] Preferably, the first set time is greater than the second set time, and the second set time is less than the programming pulse width.

[0025] Preferably, the second set time is greater than one programming pulse width and less than two programming pulse widths;

[0026] The third set time is greater than one programming pulse width and less than two programming pulse widths.

[0027] Preferably, the programming pulse width is 4 - 6 μs, the first set time is 7 - 9 μs, and the third set time is 9 - 11 μs.

[0028] Preferably, the programming voltage is 10V - 12V, and the operating voltage of the MCU chip is 2.5V - 5V.

[0029] Preferably, N is 4, 16, 128 or 1024.

[0030] Preferably, in the programming timing generation module, a finite state machine is used to generate the control signal of the FLASH charge boost pump circuit and the FLASH programming control signal.

[0031] For the MCU chip with built-in FLASH of the present invention, the FLASH controller circuit generates the read / write signals and timing required by the FLASH according to the read / write instructions issued by the CPU. The control signal (NVSTR) of the FLASH charge boost pump circuit output by the programming (write) timing generation module is in the state of 1 during N consecutive programming pulses of the FLASH programming control signal (PROG), in the state of 1 within the first set time before the N consecutive programming pulses, in the state of 0 before the first set time before the N consecutive programming pulses, and in the state of 0 after the second set time after the N consecutive programming pulses, so as to realize continuous programming of the FLASH. In the whole continuous programming mode, after receiving the programming instruction issued by the CPU, the FLASH controller circuit directly performs continuous programming on multiple FLASH addresses, without the need for additional charge / discharge time, which can improve the FLASH programming speed in the MCU chip and shorten the FLASH programming time. Description of the Drawings

[0032] In order to more clearly illustrate the technical solution of the present invention, the drawings required for the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0033] Figure 1 It is a schematic diagram of the FLASH storage cell structure;

[0034] Figure 2 It is the timing of the main control signals of the FLASH module required by the specification of an existing wafer fab;

[0035] Figure 3 It is the programming timing of the main control signals of the FLASH module for four addresses required by the specification of an existing wafer fab;

[0036] Figure 4 It is a schematic diagram of the structure of an embodiment of the MCU chip with built-in FLASH of the present invention;

[0037] Figure 5 It is the programming timing of the main control signals of the FLASH module of the MCU chip with built-in FLASH of the present invention for four addresses;

[0038] Figure 6 It is the programming timing of the main control signals of the FLASH module of the MCU chip with built-in FLASH of the present invention for four addresses. Detailed Embodiments

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] The "first", "second" and similar terms used in this application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right" are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0042] Embodiment 1

[0043] An MCU chip with built-in FLASH includes a central processing unit (CPU), a FLASH (flash memory) module, a FLASH charge boost pump circuit, and a FLASH controller circuit, as Figure 4 shown;

[0044] The FLASH controller circuit includes a programming (write) timing generation module (program sequence generate) and a read timing generation module (read sequence generate);

[0045] The programming (write) timing generation module generates a FLASH charge boost pump circuit control signal (NVSTR) and a FLASH programming control signal (PROG) according to the read / write instructions issued by the CPU, as Figure 5 shown, as Figure 5 in the main control signal explanation table 1 of the FLASH module:

[0046] When the CPU issues a programming (write) instruction for N byte addresses of the FLASH, N is an integer greater than 1:

[0047] The FLASH programming control signal (PROG) output by the programming (write) timing generation module is N consecutive programming pulses;

[0048] The control signal (NVSTR) of the FLASH charge boost pump circuit output by the programming (writing) timing generation module is in the state of 1 during N consecutive programming pulses of the FLASH programming control signal (PROG), in the state of 1 within the first set time before the N consecutive programming pulses, in the state of 0 before the first set time before the N consecutive programming pulses, and in the state of 0 after the second set time after the N consecutive programming pulses;

[0049] The FLASH charge boost pump circuit is used to output a programming voltage to the control gate of the FLASH storage unit of the FLASH module, and the programming voltage is higher than the operating voltage of the MCU chip;

[0050] The FLASH charge boost pump circuit can work when the control signal (NVSTR) of the FLASH charge boost pump circuit is 1 and stops working when the control signal of the FLASH charge boost pump circuit is 0.

[0051] For the MCU chip with built-in FLASH in Embodiment 1, the FLASH controller circuit generates the read / write signals and timing required by the FLASH according to the read / write instructions issued by the CPU. The control signal (NVSTR) of the FLASH charge boost pump circuit output by the programming (writing) timing generation module is in the state of 1 during N consecutive programming pulses of the FLASH programming control signal (PROG), in the state of 1 within the first set time before the N consecutive programming pulses, in the state of 0 before the first set time before the N consecutive programming pulses, and in the state of 0 after the second set time after the N consecutive programming pulses, realizing continuous FLASH programming. In the whole continuous programming mode, after receiving the programming instruction issued by the CPU, the FLASH controller circuit directly performs continuous programming on multiple FLASH addresses without additional charge / discharge time, which can improve the FLASH programming speed in the MCU chip and shorten the FLASH programming time. When programming a large amount of data, especially when burning the firmware program on the factory production line, by performing continuous programming on fixed-size data blocks, time can be greatly saved and efficiency can be improved.

[0052] For the MCU chip with built-in FLASH in Embodiment 1, as shown in Table 2, as long as the programming requests are continuous and the specifications meet the FLASH characteristics, the time required for programming four addresses is about 38 us, saving 58.7% of the time compared with single programming in the prior art respectively.

[0053] Table 2

[0054] Programming data block Single programming Continuous programming Time saving percentage 4 bytes 23 μs 23 μs 0％ 16 bytes 92 μs 38 μs 58.7％ 128 bytes 736 μs 178 μs 75.8％ 1 Kbytes 5888 μs 1298 μs 77.9％

[0055] Embodiment 2

[0056] Based on the MCU chip with built-in FLASH in Embodiment 1, asFigure 4 , Figure 5 As shown in Figure 5 , the read timing generation module generates a FLASH read control signal (READENA) according to the read / write instruction issued by the CPU.

[0057] The FLASH read control signal generated by the read timing generation module (read sequence generate) is 0 when the FLASH charge boost pump circuit control signal (NVSTR) is 1, is 0 within the third set time after the FLASH charge boost pump circuit control signal (NVSTR) changes from 1 to 0, and is 1 after the third set time.

[0058] When the FLASH read control signal is 0, the FLASH cannot be read, and when it is 1, the FLASH can be read.

[0059] Preferably, the first set time is greater than the second set time, and the second set time is less than the programming pulse width.

[0060] Preferably, the second set time is greater than one programming pulse width and less than two programming pulse widths.

[0061] The third set time is greater than one programming pulse width and less than two programming pulse widths.

[0062] Preferably, the programming pulse width is 4 - 6 μs (e.g., 5 μs), the first set time is 7 - 9 μs (e.g., 8 μs), and the third set time is 9 - 11 μs (e.g., 10 μs).

[0063] Preferably, the programming voltage is 10V - 12V (e.g., 11V), and the working voltage of the MCU chip is 2.5V - 5V (e.g., 3V).

[0064] Preferably, N is 4, 16, 128, 1024, etc.

[0065] Embodiment 3

[0066] The MCU chip with built-in FLASH based on Embodiment 2, such as Figure 6As shown, in the programming (writing) timing generation module (program sequence generate), the control signal (NVSTR) of the FLASH charge boost pump circuit and the programming control signal (PROG) of the FLASH are generated through an FSM (Finite State Machine). By adding a path for the programming state (PROGTIME) to jump to the initial state (START), the high voltage inside the FLASH is not released. After programming the current address, the high voltage is maintained, and programming of the next address continues until all addresses are programmed. Finally, the high voltage is discharged to achieve continuous programming of the FLASH. The FSM states in the programming (writing) timing generation module (program sequence generate) are shown in Table 3.

[0067] Table 3

[0068] Status name Description START Initial state, enters the next state after receiving the write start from the CPU CHARGE TIME Charging state, enters the next state when charging is completed PROG TIME Programming state, enters the next state when programming is completed DISCHARGE TIME Discharging state, enters the next state when discharging is completed

[0069] For the MCU chip with built-in FLASH in Embodiment 3, the programming (writing) timing generation module (program sequence generate) generates the control signal (NVSTR) of the FLASH charge boost pump circuit, the programming control signal (PROG) of the FLASH, etc. through an FSM (Finite State Machine). After the programming time of the current address ends, the FSM directly returns to the start state (the state of the FLASH programming control signal (PROG) is 0, the state of the FLASH charge boost pump circuit control signal (NVSTR) is 1, and the state of the FLASH read control signal READENA is 0), so that the high voltage inside the FLASH is not released; after receiving the programming (writing) instruction, the FSM can directly enter the programming time state to continue programming the next address.

[0070] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

Claims

1. An MCU chip with built-in FLASH, characterized in that, It includes a central processing unit, a FLASH module, a FLASH charge boost pump circuit and a FLASH controller circuit; The FLASH controller circuit includes a programming timing generation module and a read timing generation module; The programming timing generation module generates a control signal for the FLASH charge boost pump circuit and a FLASH programming control signal according to the read / write instructions issued by the CPU: When the CPU issues a programming instruction for the N-byte address of the FLASH, where N is an integer greater than 1: The FLASH programming control signal output by the programming timing generation module is N consecutive programming pulses; The control signal for the FLASH charge boost pump circuit output by the programming timing generation module is in the state of 1 during the N consecutive programming pulses of the FLASH programming control signal, in the state of 1 within the first set time before the N consecutive programming pulses, in the state of 0 before the first set time before the N consecutive programming pulses, and in the state of 0 after the second set time after the N consecutive programming pulses; The FLASH charge boost pump circuit is used to output a programming voltage to the control gate of the FLASH storage unit of the FLASH module, and the programming voltage is higher than the operating voltage of the MCU chip; The FLASH charge boost pump circuit can work when the control signal of the FLASH charge boost pump circuit is 1 and stops working when the control signal of the FLASH charge boost pump circuit is 0.

2. The MCU chip with built-in FLASH according to claim 1, characterized in that The read timing generation module generates a FLASH read control signal according to the read / write instructions issued by the CPU; The FLASH read control signal generated by the read timing generation module is 0 when the control signal of the FLASH charge boost pump circuit is 1, 0 within the third set time after the control signal of the FLASH charge boost pump circuit changes from 1 to 0, and 1 after the third set time; The FLASH cannot be read when the FLASH read control signal is 0, and the FLASH can be read when the FLASH read control signal is 1.

3. The MCU chip with built-in FLASH according to claim 2, characterized in that The first set time is greater than the second set time, and the second set time is less than the programming pulse width.

4. The MCU chip with built-in FLASH according to claim 2, characterized in that The second set time is greater than one programming pulse width and less than two programming pulse widths; The third set time is greater than one programming pulse width and less than two programming pulse widths.

5. The MCU chip with built-in FLASH according to claim 2, characterized in that The programming pulse width is 4 - 6 μs, the first set time is 7 - 9 μs, and the third set time is 9 - 11 μs.

6. The MCU chip with built-in FLASH according to claim 1, characterized in that The programming voltage is 10V - 12V, and the operating voltage of the MCU chip is 2.5V - 5V.

7. The MCU chip with built-in FLASH according to claim 1, characterized in that N is 4, 16, 128 or 1024.

8. The MCU chip with built-in FLASH according to claim 1, characterized in that in the programming timing generation module, a finite state machine is used to generate the control signal for the FLASH charge boost pump circuit and the FLASH programming control signal.

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