Semiconductor device and preparation method

Abstract

The embodiment of the invention discloses a semiconductor device and a preparation method, the semiconductor device comprises a chip, a dielectric film, an RDL line layer and an outer layer circuit, the chip is embedded in the dielectric film, then the RDL line layer is manufactured on the dielectric film, the chip PAD and the RDL line layer form interconnection, and the outer layer circuit is connected with the chip PAD. According to the method, a dielectric film is used as a packaging substrate, other required outer-layer circuits are manufactured in a layer adding mode, packaging of the chip is completed while manufacturing of the whole circuit is completed, the dielectric film is used as the packaging substrate, and the chip is fixed in an embedded mode. Therefore, the surface space of the packaging substrate can be greatly saved, the size of the packaged semiconductor device is greatly reduced, the semiconductor device provided by the embodiment of the invention can adopt a semiconductor packaging technology to achieve the design that the line width / line distance is 10 microns / 10 microns in the aspect of the fan-out of an I / O interface of a high-density chip, and the production efficiency is improved. Therefore, the surface space of the packaging substrate can be further saved, and the size of the packaged semiconductor device is greatly reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Since the packaging of integrated circuit devices has evolved from the development of single components to the integration of multiple components, driven by the improvement of product performance and the demand for thinness, lightness, and low power consumption, it has entered a new stage of packaging integration. Under the guidance of this development direction, two new major trends in the electronics industry have emerged: System-on-Chip (SoC) and System-in-Package (SiP).

[0003] As the advantages of Moore's Law become increasingly difficult to achieve and the costs are getting higher and higher, the global semiconductor industry is committed to finding a breakthrough in the post-Moore's Law era. The Semiconductor Industry Association (SIA) of the United States announced in 2015 that it would stop updating the ITRS (International Technology Roadmap for Semiconductors), and the baton was passed to the Heterogeneous Integration Roadmap (HIR, released in October 2019), which focuses on System-in-Package (SiP) and the development directions for the next 10 to 15 years: 3D, 3D interconnects, and wafer-level packaging.

[0004] SiP is a packaging method that, from the perspective of packaging, arranges different chips side by side or stacked, and preferentially assembles multiple active electronic components with different functions, optional passive devices, and other devices such as MEMS or optical devices together to form a single standard package with a certain function.

[0005] The SiP packaging technology arranges and assembles multiple bare chips or modules. If classified by the arrangement method, it can be generally divided into the structures of planar 2D packaging and 3D packaging. The stacked 3D technology can increase the number of wafers or modules used, thereby increasing the number of wafer layers that can be placed in the vertical direction and further enhancing the function integration ability of the SiP technology; and its internal bonding technology can be simple wire bonding, flip chip bonding, or a combination of both.

[0006] The mainstream SiP packaging form is still BGA, which is interconnected with the designed circuit board carrier by wire bonding or bump bonding to form a complete microsystem. The most advanced current 3D SiP uses an Interposer (silicon-based interposer) to bond the bare die to the substrate through TSV (through-silicon via process). Different from the wire bonding or bump bonding technology of common chip packaging, TSV can enable chips to have a greater stacking density and smaller form factor in the three-dimensional direction, and greatly improve chip speed and reduce power consumption, becoming a new development direction for 3D chips. However, the TSV process is difficult, the equipment is precise and complex, and the price is expensive. Currently, the mainstream SiP packaging (using wire bonding or bump bonding) is processed on the packaging substrate. On the one hand, it is necessary to reserve positions on the packaging substrate for chip bonding. On the other hand, in order to fan out the I / O interfaces of high-density chips, the manufacturing requirements for the packaging substrate are restricted by the process manufacturing limitations of the packaging substrate, and generally, the line width / line pitch can only be designed at 30um / 30um. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art or related technologies.

[0008] To this end, a first aspect of the present invention provides a semiconductor device.

[0009] A second aspect of the present invention provides a preparation method.

[0010] In view of this, according to a first aspect of the embodiments of the present application, a semiconductor device is proposed, including:

[0011] A chip;

[0012] A dielectric thin film, the chip being embedded in the dielectric thin film;

[0013] An RDL circuit layer, the RDL circuit layer being connected to the chip;

[0014] An outer layer circuit, the outer layer circuit being connected to the RDL circuit layer.

[0015] In a feasible implementation manner, the semiconductor device further includes:

[0016] A passive device, the passive device being connected to the outer layer circuit.

[0017] In a feasible implementation manner, the semiconductor device further includes:

[0018] A first photoresist layer, the first photoresist layer being arranged between the dielectric thin film and the chip and the RDL circuit layer.

[0019] In a feasible implementation manner, the semiconductor device further includes:

[0020] A backside circuit layer is arranged on a side of the chip and the dielectric film that is away from the RDL circuit layer.

[0021] In a feasible implementation manner, the back wiring layer includes:

[0022] A backside wiring and a second photoresist layer, wherein the second photoresist layer is arranged between the dielectric film and the backside wiring.

[0023] In a feasible implementation manner, the dielectric film is made of epoxy-based material.

[0024] In a feasible implementation manner, the dielectric film is made of semi-cured material.

[0025] In a feasible implementation manner, the outer layer circuit includes multiple layers of stacked circuits.

[0026] According to a second aspect of an embodiment of the present application, a preparation method is provided for preparing a semiconductor device as described in any of the above technical solutions, the preparation method comprising:

[0027] Provide a carrier plate;

[0028] Disposing a bonding tape on the carrier plate;

[0029] Using a laser drill to make position identification points, and pasting the chip on the bonding tape through the position identification points;

[0030] Pressing a dielectric film onto the chip so that the chip is embedded in the dielectric film, and then curing the film;

[0031] Separating the dielectric film and the chip from the carrier board, and preparing an RDL circuit layer on the dielectric film and the chip;

[0032] An outer layer circuit is prepared on the RDL circuit layer.

[0033] In a feasible implementation manner, the dielectric film is made of a semi-cured epoxy material;

[0034] Wherein, the thickness of the dielectric film is greater than the thickness of the chip, and the difference between the thickness of the dielectric film and the thickness of the chip is 20um to 30um;

[0035] Wherein, the thermal expansion coefficient of the material of the dielectric film is 10 PPM / °C to 30 PPM / °C.

[0036] Compared with the prior art, the present invention has at least the following beneficial effects:

[0037] The semiconductor device provided by the embodiment of the present application includes a chip, a dielectric film, an RDL circuit layer, and an outer circuit. The chip is embedded in the dielectric film, and then the RDL circuit layer is fabricated on the dielectric film to form an interconnection between the chip PAD and the RDL circuit layer. Then, the remaining required outer circuits are fabricated by the build-up method. While completing the entire circuit fabrication, the chip is also encapsulated. Based on this, the dielectric film is used as a packaging substrate, and the chip is fixed in an embedded manner, which can greatly save the surface space of the packaging substrate, thereby significantly reducing the size of the packaged semiconductor device. In terms of the I / O interface fan-out of high-density chips by the semiconductor device provided by the embodiment of the present application, a semiconductor packaging technology can be used to achieve a design with a line width / line pitch of 10um / 10um, which can further save the surface space of the packaging substrate, thereby significantly reducing the size of the packaged semiconductor device. Description of the Drawings

[0038] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0039] Figure 1 It is a schematic structural diagram of a semiconductor device according to an embodiment provided by the present application;

[0040] Figure 2 It is a schematic structural diagram of another semiconductor device according to an embodiment provided by the present application;

[0041] Figure 3 It is a schematic flowchart of a semiconductor device according to an embodiment provided by the present application;

[0042] Figure 4 It is a schematic process flowchart of a semiconductor device according to an embodiment provided by the present application;

[0043] Figure 5 It is a schematic process flowchart of another semiconductor device according to an embodiment provided by the present application.

[0044] Among them, Figure 1 、 Figure 2 、 Figure 4 and Figure 5 The corresponding relationship between the reference numerals and the component names in is as follows:

[0045] 110 Chip, 120 Dielectric film, 130 RDL circuit layer, 140 Outer circuit, 150 Passive device, 160 First photoresist layer, 170 Backside circuit layer, 111 Connection pad;

[0046] 210 carrier plate, 220 bonding tape. Detailed implementation mode

[0047] To better understand the above technical solution, the technical solution of the embodiments of the present application will be described in detail below through the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solution of the embodiments of the present application, rather than limitations on the technical solution of the present application. Without conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0048] As Figure 1 and Figure 2 shown, according to the first aspect of the embodiments of the present application, a semiconductor device is provided, including: a chip 110; a dielectric thin film 120, the chip 110 is embedded in the dielectric thin film 120; an RDL circuit layer 130, the RDL circuit layer 130 is connected to the chip 110; an outer circuit 140, the outer circuit 140 is connected to the RDL circuit layer 130.

[0049] The semiconductor device provided by the embodiments of the present application includes a chip 110, a dielectric thin film 120, an RDL circuit layer 130 and an outer circuit 140. The chip 110 is embedded in the dielectric thin film 120, and then the RDL circuit layer 130 is fabricated on the dielectric thin film 120 to form an interconnection between the chip 110 PAD and the RDL circuit layer 130. Then, the remaining required outer circuit 140 is fabricated by the build-up method. While completing the entire circuit fabrication, the chip 110 is also packaged. Based on this, the dielectric thin film 120 is used as a packaging substrate, and the chip 110 is fixed by an embedded method, which can greatly save the surface space of the packaging substrate, thereby significantly reducing the size of the packaged semiconductor device. For the I / O interface fan-out of the high-density chip 110 by the semiconductor device provided by the embodiments of the present application, a semiconductor packaging technology can be used to achieve a design with a line width / line pitch of 10um / 10um, which can further save the surface space of the packaging substrate, thereby significantly reducing the size of the packaged semiconductor device.

[0050] Through the semiconductor device provided by the embodiments of the present application, a single chip 110 can be packaged, or multiple chips 110 can be integrally packaged, and the structural design can be more flexible; the embedded design can save the product's planar wiring space and significantly reduce the product size; the chip 110 can be packaged according to the original thickness, or the chip 110 can be thinned to a thickness of 25um or more for packaging, with stronger applicability; by selecting the material for the dielectric thin film 120, the packaging method of the semiconductor device can be flexible and bendable, further expanding the application range of the semiconductor device.

[0051] It can be understood that through the arrangement of the RDL circuit layer 130, the RDL circuit layer 130 can be used as a rewiring to be connected to the functional PAD of the chip 110, and then wiring can be performed on the RDL circuit layer 130 to facilitate the wiring connection of the chip 110 and connect with the outer layer circuit 140 to form a closed loop, thereby realizing the function of the semiconductor device.

[0052] like Figure 1 and Figure 2 As shown, in a feasible implementation manner, the semiconductor device further includes: a passive device 150 , and the passive device 150 is connected to the outer layer circuit 140 .

[0053] In this technical solution, the semiconductor device may also include a passive device 150. The passive device 150 is connected to the outer circuit 140 to obtain a complete functional semiconductor device. The number and style of the passive device 150 can be set based on the design requirements of the semiconductor device, and this application does not make any specific limitations.

[0054] like Figure 1 and Figure 2 As shown, in a feasible implementation manner, the semiconductor device further includes: a first photoresist layer 160 , and the first photoresist layer 160 is arranged between the dielectric film 120 and the chip 110 and the RDL circuit layer 130 .

[0055] In this technical solution, the semiconductor device may further include a first photoresist layer 160. During the preparation of the semiconductor device, the first photoresist layer 160 is coated on the entirety formed by the dielectric film 120 and the chip 110. The first photoresist layer 160 is then etched to expose the connection pad 111 (PAD) on the chip 110. The RDL circuit layer 130 is then manufactured, and the RDL circuit layer 130 can be connected to the connection pad 111 of the chip 110.

[0056] like Figure 1 As shown, in a feasible implementation manner, the semiconductor device further includes: a backside wiring layer 170 , and the backside wiring layer 170 is arranged on a side of the chip 110 and the dielectric film 120 away from the RDL wiring layer 130 .

[0057] In this technical solution, the semiconductor device may further include a back wiring layer 170, which is arranged on the side of the chip 110 and the dielectric film 120 that is away from the RDL wiring layer 130, that is, the back wiring layer 170 is arranged on the side of the connection pad 111 (PAD) away from the chip 110. With this arrangement, the back wiring layer 170 can be used for wiring / routing at a higher density, which can further reduce the volume of the semiconductor device.

[0058] In a feasible implementation manner, the backside wiring layer 170 includes: a backside wiring and a second photoresist layer, and the second photoresist layer is disposed between the dielectric film 120 and the backside wiring.

[0059] In this technical solution, the structural composition of the backside wiring layer 170 is further provided. The backside wiring layer 170 may include a backside wiring and a second photoresist layer. Based on this, during the preparation process of the semiconductor device, a photoresist may be coated first on the side of the whole formed by the chip 110 and the dielectric film 120 that faces away from the landing pad 111 to form the second photoresist layer, and then the backside wiring is formed on the second photoresist layer. Such a setting facilitates the preparation of the backside wiring.

[0060] In a feasible implementation manner, the dielectric film 120 is made of an epoxy-based material. Such a setting is considered because the epoxy-based material has a stable structure after curing and a low coefficient of thermal expansion, which can reduce the probability of delamination and cracking of the semiconductor device.

[0061] In a feasible implementation manner, the dielectric film 120 is made of a semi-cured material. Such a setting enables the dielectric film 120 to have a certain flexibility after curing, so that the semiconductor device can be bent within a certain range, which can improve the application range of the semiconductor device.

[0062] It can be understood that the epoxy-based material and the semi-cured material may include epoxy-based semi-cured materials.

[0063] As Figure 4 and Figure 5 shown, in a feasible implementation manner, a landing pad 111 is formed on the chip 110, and the landing pad 111 is connected to the RDL wiring layer 130. Such a setting can make the connection and communication between the chip 110 and the RDL wiring layer 130 more reliable.

[0064] In a feasible implementation manner, the chip 110 is a bare chip 110, and the number of bare chips 110 is two or more. Such a setting can enrich the functions of the semiconductor device.

[0065] In a feasible implementation manner, the outer layer circuit 140 includes multiple stacked circuits. Such a setting can make full use of the space in the height direction on the chip 110, and can reduce the volume of the semiconductor device while ensuring that the semiconductor device can implement complex functions.

[0066] As Figure 3 shown, according to the second aspect of the embodiments of the present application, a preparation method is proposed for preparing a semiconductor device as in any of the above technical solutions. The preparation method includes:

[0067] Step 101: Provide a carrier plate;

[0068] Step 102: Set a bonding tape on the carrier plate;

[0069] Step 103: Use a laser drill to make position recognition points, and paste the chip on the bonding tape through the position recognition points;

[0070] Step 104: Press the dielectric film onto the chip to embed the chip into the dielectric film, and then cure it;

[0071] Step 105: Detach the dielectric film and the chip from the carrier plate, and prepare an RDL circuit layer on the dielectric film and the chip;

[0072] Step 106: Prepare an outer circuit on the RDL circuit layer.

[0073] As Figure 4 and Figure 5 shown, for the manufacturing method provided by the embodiments of the present application, since it is used to manufacture a semiconductor device according to any of the above technical solutions, this manufacturing method has all the beneficial effects of the semiconductor device of the above technical solutions.

[0074] Through the manufacturing method provided by the embodiments of the present application, first provide a carrier plate 210, then set a bonding tape 220 on the carrier plate 210, fix the chip 110 through the bonding tape 220, then set the dielectric film 120, and then perform debonding to peel off the carrier plate 210 and the bonding tape 220. After that, manufacturing an RDL circuit layer 130 and an outer circuit 140 on the whole formed by the chip 110 and the dielectric film 120 can complete the manufacturing of the semiconductor device. For the manufacturing method provided by the embodiments of the present application, all process flows are conventional packaging process technologies in the industry, without the need to purchase additional equipment or adopt more difficult process technologies for development and production. The manufactured semiconductor device includes a chip 110, a dielectric film 120, an RDL circuit layer 130, and an outer circuit 140. The chip 110 is embedded in the dielectric film 120, and then the RDL circuit layer 130 is manufactured on the dielectric film 120 to form an interconnection between the chip 110 PAD and the RDL circuit layer 130. Then, the remaining required outer circuit 140 is manufactured by the way of adding layers. While completing the manufacturing of the whole circuit, the chip 110 is also packaged. Based on this, the dielectric film 120 is used as a packaging substrate, and the chip 110 is fixed in an embedded manner, which can greatly save the surface space of the packaging substrate, thereby greatly reducing the size of the packaged semiconductor device. For the semiconductor device provided by the embodiments of the present application in terms of the fan-out of the I / O interfaces of high-density chips 110, a semiconductor packaging technology can be used to achieve a design with a line width / line pitch of 10um / 10um, which can further save the surface space of the packaging substrate, thereby greatly reducing the size of the packaged semiconductor device.

[0075] The manufacturing method provided by the embodiments of the present application uses laser drilling to fabricate position recognition points (MARKs), which has high precision and more accurate positioning. It replaces the process of etching MARKs on the substrate in the traditional technology, so there will be no errors caused by etching, and thus the position accuracy of the bonded chip 110 is higher.

[0076] In the manufacturing method provided by the embodiments of the present application, the chip 110 is embedded within the dielectric thin film 120. After embedding, the chip 110 and the dielectric thin film 120 are integrated into one body, and a flatter surface can be obtained, which brings operability and convenience to subsequent processes.

[0077] It can be understood that the bonding tape 220 can be bonded using a UV tape, or other thermal release adhesives can be used for bonding.

[0078] Such as Figure 4 and Figure 5 As shown, in a feasible implementation manner, before the steps of separating the dielectric thin film 120 and the chip 110 from the carrier plate 210 and fabricating the RDL circuit layer 130 on the dielectric thin film 120 and the chip 110, it further includes: thinning the cured dielectric thin film 120 and the chip 110 using a thinning process.

[0079] In this technical solution, the manufacturing method may further include thinning the whole formed by the cured dielectric thin film 120 and the chip 110. Such a setting can reduce the thickness of the final package. In the traditional technology, the thinning of the chip 110 is mostly carried out at the wafer level, with high manufacturing costs and great processing difficulties. Once problems occur during the thinning process, the entire wafer will face scrapping. However, in the technical solution provided by the embodiments of the present application, thinning the whole formed by the cured dielectric thin film 120 and the chip 110 is more flexible and diverse, with low processing difficulty and high product flexibility.

[0080] In a feasible implementation manner, the steps of separating the dielectric thin film 120 and the chip 110 from the carrier plate 210 and fabricating the RDL circuit layer 130 on the dielectric thin film 120 and the chip 110 include: exposing the connection pads 111 of the chip 110; coating a first photoresist layer 160 on the side of the chip 110 where the connection pads 111 are arranged; fabricating the RDL circuit layer 130 using the first photoresist layer 160 so that the RDL circuit layer 130 is interconnected with the connection pads 111.

[0081] In this technical solution, a preparation process for the RDL circuit layer 130 is further provided. The first photoresist layer 160 is coated on the whole formed by the dielectric template and the chip 110, and then the first photoresist layer 160 is etched to expose the bonding pad 111 (PAD) on the chip 110. Then, the RDL circuit layer 130 is fabricated, and the RDL circuit layer 130 can be connected to the bonding pad 111 of the chip 110, making the communication and connection between the RDL circuit layer 130 and the chip 110 more reliable.

[0082] As Figure 4 and Figure 5 shown, in a feasible implementation, the preparation method further includes: mounting the passive device 150, and the passive device 150 is connected to the outer circuit 140.

[0083] In this technical solution, the passive device 150 can be mounted by SMT, and finally a semiconductor device with an embedded chip 110 is formed, thereby completing the SiP packaging of the chip 110.

[0084] As Figure 4 shown, in a feasible implementation, before the steps of detaching the dielectric film 120 and the chip 110 from the carrier board 210 and fabricating the RDL circuit layer 130 on the dielectric film 120 and the chip 110, it further includes: forming a backside circuit layer 170 on the side of the chip 110 facing away from the bonding pad 111.

[0085] In this technical solution, the backside circuit layer 170 is arranged on the side of the chip 110 and the dielectric film 120 facing away from the RDL circuit layer 130, that is, the backside circuit layer 170 is arranged on the side facing away from the bonding pad 111 (PAD) of the chip 110. Such a setting can use the backside circuit layer 170 for lead / wiring with higher density, and can further reduce the volume of the semiconductor device.

[0086] In a feasible implementation, the carrier board 210 includes a glass plate or a metal plate.

[0087] In this technical solution, the style of the carrier board 210 is further provided. The carrier board 210 can include a glass plate or a metal plate, with a wide selection range and low cost.

[0088] In a feasible implementation, the dielectric film 120 is made of a semi-cured epoxy-based material. Such a setting can fix the chip 110 through the dielectric film 120 while making the formed semiconductor device have a certain flexibility after packaging.

[0089] In a feasible implementation, the thickness of the dielectric film 120 is greater than the thickness of the chip 110, and the difference between the thickness of the dielectric film 120 and the thickness of the chip 110 is 20 μm to 30 μm. Such a setting facilitates embedding the chip 110 into the dielectric film 120.

[0090] In a feasible implementation, the coefficient of thermal expansion of the material of the dielectric film 120 is 10 PPM / °C to 30 PPM / °C. With such a setting, the probability of damage or deformation generated when the chip 110 is embedded into the dielectric film 120 can be reduced, and at the same time, the probability of delamination of the semiconductor device can be reduced.

[0091] In summary, for the semiconductor device and the manufacturing method provided by the embodiments of the present application, compared with the conventional mainstream SiP packaging, the packaging substrate is first fabricated, areas for wire bonding or bump bonding are reserved on the packaging substrate, and then the chip 110 is mounted. In the present invention, the chip 110 is first mounted, the dielectric film 120 is used as the packaging substrate, and then the circuit is fanned out in a Fan-out manner. While the chip 110 is encapsulated, the packaging substrate is also fabricated, reducing the size of the semiconductor device and the process difficulty.

[0092] In the present invention, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance; the term "plurality" means two or more, unless otherwise clearly defined. Terms such as "mounted", "connected", "coupled", and "fixed" should be construed in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "coupled" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0093] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention.

[0094] In the description of this specification, the descriptions of the terms "one embodiment", "some embodiments", "specific embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or instance. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: chip; a dielectric film, wherein the chip is embedded in the dielectric film; An RDL circuit layer, wherein the RDL circuit layer is connected to the chip; An outer layer circuit is connected to the RDL circuit layer.

2. The semiconductor device according to claim 1, wherein Also includes: A passive device is connected to the outer layer circuit.

3. The semiconductor device according to claim 1, wherein Also includes: A first photoresist layer is arranged between the dielectric film and the chip and the RDL circuit layer.

4. The semiconductor device according to claim 1, wherein, Also includes: A backside circuit layer is arranged on a side of the chip and the dielectric film that is away from the RDL circuit layer.

5. The semiconductor device according to claim 4, wherein The back wiring layer comprises: A backside wiring and a second photoresist layer, wherein the second photoresist layer is arranged between the dielectric film and the backside wiring.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The dielectric film is made of epoxy material.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The dielectric film is made of semi-cured material.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that The outer layer circuit includes multiple layers of stacked circuits.

9. A preparation method, characterized in that, For preparing a semiconductor device according to any one of claims 1 to 8, the preparation method comprising: Provide a carrier plate; Disposing a bonding tape on the carrier plate; Using a laser drill to make position identification points, and pasting the chip on the bonding tape through the position identification points; Pressing a dielectric film onto the chip so that the chip is embedded in the dielectric film, and then curing the film; Separating the dielectric film and the chip from the carrier board, and preparing an RDL circuit layer on the dielectric film and the chip; An outer layer circuit is prepared on the RDL circuit layer.

10. The preparation method according to claim 9, characterized in that: The dielectric film is made of semi-cured epoxy material; Wherein, the thickness of the dielectric film is greater than the thickness of the chip, and the difference between the thickness of the dielectric film and the thickness of the chip is 20um to 30um; Wherein, the thermal expansion coefficient of the material of the dielectric film is 10 PPM / °C to 30 PPM / °C.

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