Circuit for discharging capacitor using power transistor operating in non-linear mode

Abstract

A circuit for discharging a capacitor using a power transistor operating in a non-linear mode includes a first power transistor and a second power transistor. The circuit also includes a controller configured to control the first power transistor to perform the first sequence of switching cycles by applying, for each switching cycle in the first sequence of switching cycles, a first gate voltage exceeding a threshold gate voltage to cause the first power transistor to operate according to a non-linear transfer function. The controller is further configured to control the second power transistor to perform the second sequence of switching cycles by applying, for each switching cycle in the second sequence of switching cycles, a second gate voltage that exceeds a threshold gate voltage to cause the second power transistor to operate according to a non-linear transfer function. The controller is configured to discharge the capacitor according to a sequence of discharge phases.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices (such as power transistors, etc.). Background Art

[0002] An electrical component can draw power from an electrical power source (such as a battery). For example, an electric vehicle can include one or more electric motors, an air conditioner and a heating unit, and other electrical components that draw power. A direct current (DC) link capacitor can be located between the electrical power source and one or more electrical components that draw power. When the DC link capacitor is charged, the DC link capacitor can protect one or more electrical components from voltage spikes caused by large current variations. When the amount of power drawn by a load varies significantly in a short period of time, the current variation can cause a voltage spike. The DC link capacitor can be charged to a high voltage. This means that in some cases, discharging the DC link capacitor may be beneficial. Summary of the Invention

[0003] Generally, the present disclosure relates to a circuit including a power transistor configured to discharge a direct current (DC) link capacitor over a period of time. For example, the circuit can include a first power transistor and a second power transistor connected in series with the first power transistor. The DC link capacitor can be connected to the first power transistor such that the DC link capacitor is configured to discharge through the first power transistor and the second power transistor. That is, when the DC link capacitor discharges, current can flow through the first power transistor and the second power transistor via a discharge current path. As the current flows out of the DC link capacitor via the discharge current path, the voltage of the DC link capacitor decreases.

[0004] A controller can control the first power transistor to execute a first switching cycle sequence and control the second power transistor to execute a second switching cycle sequence. A switching cycle can include an activation phase when the power transistor is turned on and a deactivation phase when the power transistor is turned off. When both the first power transistor and the second power transistor are turned on during the activation phase, current can flow through the first power transistor and the second power transistor from the capacitor via the discharge current path. The controller can control the first switching cycle sequence and the second switching cycle sequence such that there is one or more overlapping segments between the activation phase of the first switching cycle sequence and the activation phase of the second switching cycle sequence.

[0005] Additionally or alternatively, current can flow through a discharge current path from the capacitor via the parasitic capacitances of the first power transistor and the second power transistor. For example, current from a DC link capacitor can charge the parasitic capacitance of the first power transistor, the parasitic capacitance of the first power transistor can discharge to charge the parasitic capacitance of the second power transistor, and the parasitic capacitance of the second power transistor can discharge through the discharge current path. Even when the active phases of the first switching cycle sequence and the second switching cycle sequence do not overlap or overlap for a very short period of time, current can discharge through the discharge current path via the parasitic capacitances of the first power transistor and the second power transistor. This means that the controller can control the first switching cycle sequence and the second switching cycle sequence to discharge the DC link capacitor without stressing the first power transistor and the second power transistor associated with the overlapping active phases.

[0006] The first power transistor and the second power transistor can operate in a non-linear mode. In the non-linear mode, there is a non-linear relationship between the voltage applied to the gate terminal of the power transistor and the current flowing through the power transistor. On the other hand, when there is a linear relationship between the voltage applied to the gate terminal of the power transistor and the current flowing through the power transistor, the power transistor operates in a linear mode. When discharging the DC link capacitor, it may be beneficial for the first power transistor and the second power transistor to operate in a non-linear mode. By operating the first power transistor and the second power transistor in a non-linear mode, the controller can discharge the DC link capacitor without precisely controlling the voltage applied to the gate terminals of the first power transistor and the second power transistor to control the magnitude of the current flowing through the discharge current path.

[0007] The techniques of the present disclosure can provide one or more advantages. For example, by using the first power transistor and the second power transistor connected in series, the controller can discharge the DC link capacitor over a period of time. The controller can cause the first power transistor to execute a first switching cycle sequence and control the second power transistor to execute a second switching cycle sequence. The first switching cycle sequence and the second switching cycle sequence can cause the DC link capacitor to discharge according to a discharge phase sequence. This means that, compared to a system that does not control the power transistors to discharge the DC link capacitor according to a discharge phase sequence, the controller can control the DC link capacitor to discharge by applying less stress to the first power transistor and the second power transistor.

[0008] In some examples, a circuit includes: a first power transistor including a first gate terminal; and a second power transistor including a second gate terminal. The second power transistor is connected in series with the first power transistor. A capacitor, the first power transistor, and the second power transistor are located on a discharge current path. The circuit further includes a controller configured to control the first power transistor to perform a first switching cycle sequence by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence, the first gate voltage exceeding a threshold gate voltage such that the first power transistor operates according to a non-linear transfer function, and to control the second power transistor to perform a second switching cycle sequence by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence, the second gate voltage exceeding a threshold gate voltage such that the second power transistor operates according to a non-linear transfer function. By controlling the first power transistor to perform the first switching cycle sequence and controlling the second power transistor to perform the second switching cycle sequence, the controller is configured to cause the capacitor to discharge via the discharge current path according to a discharge phase sequence.

[0009] In some examples, a method includes: controlling, by a controller, a first power transistor including a first gate terminal to perform a first switching cycle sequence by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence, the first gate voltage exceeding a threshold gate voltage such that the first power transistor operates according to a non-linear transfer function; and controlling, by the controller, a second power transistor including a second gate terminal to perform a second switching cycle sequence by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence, the second gate voltage exceeding a threshold gate voltage such that the second power transistor operates according to a non-linear transfer function, wherein the second power transistor is connected in series with the first power transistor, and wherein a capacitor, the first power transistor, and the second power transistor are located on a discharge current path. By controlling the first power transistor to perform the first switching cycle sequence and controlling the second power transistor to perform the second switching cycle sequence, the method includes discharging the capacitor via the discharge current path according to a discharge phase sequence.

[0010] In some examples, a system includes: a capacitor; a first power transistor including a first gate terminal; and a second power transistor including a second gate terminal. The second power transistor is connected in series with the first power transistor. The capacitor, the first power transistor, and the second power transistor are located on a discharge current path. The system further includes a controller configured to: control the first power transistor to perform a first switching cycle sequence by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence, the first gate voltage exceeding a threshold gate voltage such that the first power transistor operates according to a non-linear transfer function; and control the second power transistor to perform a second switching cycle sequence by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence, the second gate voltage exceeding a threshold gate voltage such that the second power transistor operates according to a non-linear transfer function. By controlling the first power transistor to perform the first switching cycle sequence and controlling the second power transistor to perform the second switching cycle sequence, the system is configured to discharge the capacitor via the discharge current path according to a discharge phase sequence.

[0011] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a system for discharging a direct current (DC) link capacitor according to the present disclosure.

[0013] Figure 2 is a circuit diagram illustrating a system for discharging a DC link capacitor via a discharge current path across a first power transistor and a second power transistor according to the present disclosure.

[0014] Figure 3 is a graph illustrating a first timing curve of a first switching cycle sequence, a second switching cycle sequence, and a discharge phase sequence according to the present disclosure.

[0015] Figure 4 is a graph illustrating a second timing curve of a first switching cycle sequence, a second switching cycle sequence, and a discharge phase sequence according to the present disclosure.

[0016] Figure 5 is a graph illustrating a third timing curve of a first switching cycle sequence, a second switching cycle sequence, and a discharge phase sequence according to the present disclosure.

[0017] Figure 6 is a graph illustrating a fourth timing curve of a first switching cycle sequence, a second switching cycle sequence, and a discharge phase sequence according to the present disclosure.

[0018] Figure 7 is a block diagram illustrating an example system for disconnecting power to one or more electrical components and discharging a DC link capacitor in accordance with the present disclosure.

[0019] Figure 8 is a flowchart illustrating an example operation for discharging a DC link capacitor using a power transistor in accordance with one or more techniques of the present disclosure. Detailed Description

[0020] Figure 1 is a block diagram illustrating a system 100 for discharging a direct current (DC) link capacitor 102 in accordance with the present disclosure. For example, system 100 includes: a DC link capacitor 102; a controller 110 including processing circuitry 112 and a memory 114; a first power transistor 122; a second power transistor 124; a first gate driver circuit 142; a second gate driver circuit 144; safety logic 150; and a voltage sensor 152. The DC link capacitor 102 may be discharged via a discharge current path 104 via the first power transistor 122 and the second power transistor 124.

[0021] The DC link capacitor 102 may represent an electronic circuit component between a power source and a load. For example, an electric vehicle may include one or more electric motors that draw power from a high-voltage power supply such as a battery. The DC link capacitor 102 may be important for controlling the power delivered from the power source to the load. The DC link capacitor 102 may ensure that voltage spikes associated with powering on the electric motor remain below a voltage threshold and may regulate the power delivered to the load in a manner that protects the electrical components from damage. For example, when the DC link capacitor 102 is charged to a voltage similar to that of the high-voltage power source, this may prevent a large voltage imbalance between the high-voltage power source and the load.

[0022] In the context of a motor drive system, the DC link capacitor may represent a component used in the power electronics section of the motor drive system. An electric motor (especially in variable speed applications) may receive one or more control signals to control speed and torque. The system may use a power electronic converter such as an inverter or a variable frequency drive (VFD) to implement the control. The DC link capacitor may play an important role in one or more systems to control the electric motor by smoothing the voltage supplied to the motor and preventing overvoltage spikes. For example, even during one or more switching transients, the DC link capacitor 102 may play an important role in controlling the electric motor by smoothing the voltage supplied to the motor using an inverter.

[0023] In many motor drive systems, a rectifier can convert alternating current (AC) power to DC power. A DC link capacitor can be connected across the DC bus and helps smooth the rectified voltage. The DC link capacitor can act as a buffer, reducing voltage ripple and ensuring a stable DC voltage. The DC link capacitor can store energy during certain operating phases. For example, during braking or deceleration, when the motor acts as a generator, the excess energy can be fed into the DC bus. The DC link capacitor can observe this energy, prevent voltage spikes, and protect the drive components. The DC link capacitor can maintain a relatively constant DC voltage level, ensuring a stable power supply for the inverter or other power electronic components. The DC link capacitor can act as a filter for high-frequency components in the power system. The DC link capacitor 102 can smooth out rapid changes in voltage, contributing to a more efficient and reliable operation of the motor drive.

[0024] In some cases, discharging the DC link capacitor 102 can be beneficial. Since the DC link capacitor 102 is configured to charge to a high voltage, discharging the DC link capacitor 102 for safety reasons can be beneficial when one or more fault conditions occur. For example, when the system 100 detects a motor vehicle collision, the system 100 can automatically discharge the DC link capacitor 102 so that the high voltage of the DC link capacitor 102 does not harm the human passengers of the motor vehicle. The system 100 can also discharge the DC link capacitor 102 under certain normal operating conditions, such as each time the motor vehicle loses power. In any case, the system 100 can be configured to discharge the DC link capacitor 102 in response to one or more conditions and before a period of time has elapsed. For example, the system 100 can be configured to discharge the DC link capacitor 102 in response to detecting a collision event. The system 100 can be configured to discharge the DC link capacitor 102 in response to detecting a power loss event. The system 100 can be configured to discharge the DC link capacitor 102 in response to detecting that the vehicle is turned off.

[0025] The controller 110 can be configured to discharge the DC link capacitor 102 according to a discharge phase sequence before a period of time has elapsed. For example, the controller 110 can discharge the DC link capacitor 102 via a discharge current path 104. As Figure 1 seen, the discharge current path 104 passes through the first power transistor 122 and the second power transistor 124. This means that the controller 110 can control the first power transistor 122 via the first gate driver circuit 132 and control the second power transistor 124 via the second gate driver circuit 144 to discharge the DC link capacitor 102 via the discharge current path 104.

[0026] The controller 110 may include processing circuitry 112. The processing circuitry 112 may include, for example, one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or equivalent discrete or integrated logic circuitry, or any combination of the foregoing devices or circuitry. Thus, the processing circuitry 112 may include any suitable structure, whether in hardware, software, firmware, or any combination thereof, to perform the functions ascribed to the controller 110 herein.

[0027] The controller 110 may include a memory 114 that communicates with the processing circuitry 112. In some examples, the memory 114 that communicates with the processing circuitry 112 includes computer-readable instructions that, when executed by the processing circuitry 112, cause the controller 110 to perform the various functions ascribed to the controller 110 herein. The memory 114 may include any volatile, non-volatile, magnetic, optical, or dielectric, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), electrically erasable programmable ROM (EEPROM), flash memory, or any other digital medium capable of storing information.

[0028] In some examples, the first power transistor 122 and the second power transistor 124 may be collectively referred to as "power transistors 122, 124". The power transistors 122, 124 may represent semiconductor transistor devices or other types of switches configured for power delivery. In some cases, each of the power transistors 122, 124 may include a power switch, such as, but not limited to, any type of field effect transistor (FET) (including metal oxide semiconductor field effect transistor (MOFSET), bipolar junction transistor (BJT), insulated gate bipolar transistor (IGBT), junction field effect transistor (JFET), and high electron mobility transistor (HEMT)), or any one or combination of other types of elements controlled by voltage or current. Additionally, each of the power transistors 122, 124 may include any one or combination of n-type transistors, p-type transistors, and other types of power transistors. In some examples, each of the power transistors 122, 124 includes vertical transistors, lateral transistors, and / or horizontal transistors. In some examples, each of the power transistors 122, 124 includes other analog devices (such as diodes and / or thyristors). In some examples, each of the power transistors 122, 124 may operate as a switch and / or as an analog device.

[0029] In some examples, each of the power transistors 122, 124 includes three terminals: two load terminals and one control terminal. When the power transistor represents a MOSFET, the power transistor can include a drain terminal, a source terminal, and at least one gate terminal, where the control terminal is the gate terminal. When the power transistor represents a BJT switch, the control terminal can represent the base terminal. Current can flow between the two load terminals of the power transistor based on the voltage at the corresponding control terminal. Thus, current can flow across the power transistor based on a control signal delivered to the control terminal of the power transistor. In one example, if the voltage applied to the control terminal of the power transistor is greater than or equal to a voltage threshold, the power transistor can be activated, allowing the power transistor to conduct. Additionally, when the voltage applied to the control terminal of the power transistor is below the threshold voltage, the power transistor can be deactivated, thus preventing the power transistor from conducting. The controller 110 can be configured to control each of the power transistors 122, 124 by causing the first gate driver circuit 142 to deliver a first control signal to the gate terminal of the first power transistor 122 and causing the second gate driver circuit 144 to deliver a second control signal to the gate terminal of the second power transistor 124.

[0030] Each of the power transistors 122, 124 can include various material compounds (such as silicon, silicon carbide, gallium nitride, or any other combination of one or more semiconductor materials). In some examples, silicon carbide switches can experience lower switching power losses. Magnetic improvements and faster switching (such as gallium nitride switches) can allow the power transistors to draw short pulse currents. Compared to low-frequency devices, these higher-frequency devices may require more precise timing for sending control signals (such as voltage signals delivered to the control terminals of the power transistors).

[0031] As the DC link capacitor 102 discharges, current can flow out through the discharge current path 104 across the first power transistor 122 and the second power transistor 124. In some examples, the DC link capacitor 102 can discharge according to a discharge stage sequence. For example, the processing circuitry 112 of the controller 110 can control the first power transistor 122 to perform a first switching cycle sequence, and the processing circuitry 112 can control the second power transistor 124 to perform a second switching cycle sequence. The first switching cycle sequence and the second switching cycle sequence can define the discharge stage sequence. During each discharge stage in the discharge stage sequence, current can flow out of the DC link capacitor 102, and the voltage of the DC link capacitor 102 can decrease.

[0032] In some examples, current may flow through the discharge current path 104 from the DC link capacitor 102 only under certain conditions. An example condition for current to flow through the discharge current path 104 across the first power transistor 122 and the second power transistor 124 is when both the first power transistor 122 and the second power transistor 124 are turned on simultaneously. In response to both the first power transistor 122 and the second power transistor 124 being turned on simultaneously, current can flow through the discharge current path 104 across the first power transistor 122 and the second power transistor 124. In response to one or both of the first power transistor 122 and the second power transistor 124 being turned off, current may not be able to flow through the discharge current path 104 because the turned-off power transistor cuts off the discharge current path 104.

[0033] Another example condition for current to flow through the discharge current path 104 across the first power transistor 122 and the second power transistor 124 is when current from the DC link capacitor 102 at least partially traverses the discharge current path 104 through the parasitic capacitances of the first power transistor 122 and the second power transistor 124. In some cases, electronic circuit components other than capacitors can include parasitic capacitance. That is, even if an electronic circuit component is not a capacitor, the electronic circuit component can include attributes that cause the electronic circuit component to behave like a capacitor. For example, the first power transistor 122 and the second power transistor 124 can each include a power transistor such that each of the first power transistor 122 and the second power transistor 124 is configured to charge and discharge.

[0034] The first gate driver circuit 142 can be configured to output a first control signal to the gate terminal of the first power transistor 122 to control whether the first power transistor 122 is turned on or off. In some examples, the first control signal can indicate the frequency of the first power transistor 122, the duty cycle of the first power transistor 122, the gate voltage applied to the first power transistor 122, or any combination thereof. In some examples, the first gate driver circuit 142 can generate the first control signal for output to the first power transistor 122 based on first information received by the first gate driver circuit 142 from the controller 110. That is, the controller 110 can control the first control signal output by the first gate driver circuit 142 to the gate terminal of the first power transistor 122. This means that the controller 110 is configured to control the operation of the first power transistor 122 by outputting first information to the first gate driver circuit 142.

[0035] The second gate driver circuit 144 can be configured to output a second control signal to the gate terminal of the second power transistor 124 to control whether the second power transistor 124 is turned on or off. In some examples, the second control signal can indicate the frequency of the second power transistor 124, the duty cycle of the second power transistor 124, the gate voltage applied to the second power transistor 124, or any combination thereof. In some examples, the second gate driver circuit 144 can generate the second control signal for output to the second power transistor 124 based on second information received by the second gate driver circuit 144 from the controller 110. That is, the controller 110 can control the second control signal output by the second gate driver circuit 144 to the gate terminal of the second power transistor 124. This means that the controller 110 is configured to control the operation of the second power transistor 124 by outputting the second information to the second gate driver circuit 144.

[0036] The gate driver circuits 142, 144 can be configured to control the power transistors 122, 124 to operate in a non-linear mode to discharge the DC link capacitor 102. The terms "linear mode" and "non-linear mode" can refer to the operating regions of power transistors (including MOSFETs, BJTs, and other types of power transistors). The linear mode and the non-linear mode can refer to the response of the power transistor to changes in the input signal and the behavior of the power transistor in amplification and switching. For example, the linear mode and the non-linear mode can refer to the relationship between the magnitude of the gate voltage applied to the power transistor and one or more parameters of the power signal flowing out across the power transistor.

[0037] In the linear mode, the power transistor can operate as an amplifier. This means that one or more output parameters of the power transistor are linearly proportionally amplified by one or more input parameters. The power transistor operating in the linear mode can be biased in a manner that allows the power transistor to respond to small changes in an input parameter (such as the gate voltage) such that one or more output parameters also change proportionally to the small changes in the input parameter. The linear mode can be used to amplify analog signals and otherwise process analog signals. In some examples, the power transistor can operate in the linear mode when the gate voltage applied to the gate terminal of the power transistor is within a range from a lower limit linear mode gate voltage to an upper limit linear mode gate voltage. When operating in the linear mode, the power transistor is not fully turned on. That is, when operating in the linear mode, the power transistor does not reach the full potential for conduction. The power transistor operating in the linear mode can also exhibit undesirable heating.

[0038] In the non-linear mode, the power transistor can operate as a switch. The power transistor operating in the non-linear mode can operate in the cut-off region where the power transistor is fully off, or can operate in the saturation region where the power transistor is fully on. One or more output parameters of the power transistor operating in the non-linear mode are not linearly proportional to one or more input parameters of the power transistor. That is, the power transistor operating in the non-linear mode can transition between fully off and fully on. This means that the non-linear mode can be used when the power transistor operates as a power switch. In some examples, when the gate voltage applied to the gate terminal of the power transistor is greater than the threshold non-linear mode gate voltage, the power transistor can operate in the non-linear mode. The threshold non-linear mode gate voltage of the power transistor can be greater than or equal to the upper limit linear mode gate voltage of the power transistor.

[0039] For example, a MOSFET can operate according to three operating regions including a cut-off operating region, a saturation operating region, and a linear operating region. When the MOSFET operates in the non-linear mode, the MOSFET can alternate between the cut-off operating region where the MOSFET is fully off and the saturation region where the MOSFET is fully on. In the cut-off operating region, no current or a very small amount of current can flow across the MOSFET. In the saturation region, the MOSFET is fully on, and current flows freely across the MOSFET. When operating in the linear operating region (where the MOSFET acts as an amplifier), the MOSFET operates in the linear mode.

[0040] The controller 110 can be configured to control the first power transistor 122 to execute a first switching cycle sequence. To control the first power transistor 122 to execute the first switching cycle sequence, the controller 110 can cause the first gate driver circuit 142 to apply a first gate voltage to the first gate terminal of the first power transistor 122 for each switching cycle in the first switching cycle sequence. The first gate voltage applied by the first gate driver circuit 142 to the gate terminal of the first power transistor 122 can exceed the threshold non-linear mode gate voltage, such that the first power transistor 122 operates in the non-linear mode. That is, the first power transistor 122 can operate according to a non-linear transfer function. To execute the first switching cycle sequence, the first power transistor 122 can alternate between fully on and fully off.

[0041] The controller 110 may be configured to control the second power transistor 124 to perform a second switching cycle sequence. To control the second power transistor 124 to perform the second switching cycle sequence, the controller 110 may cause the second gate driver circuit 144 to apply a second gate voltage to the second gate terminal of the second power transistor 124 for each switching cycle in the second switching cycle sequence. The second gate voltage applied by the second gate driver circuit 144 to the gate terminal of the second power transistor 124 may exceed the threshold non-linear mode gate voltage, such that the second power transistor 124 operates in the non-linear mode. That is, the second power transistor 124 may operate according to a non-linear transfer function. To perform the second switching cycle sequence, the second power transistor 124 may alternate between fully on and fully off.

[0042] By controlling the first power transistor 122 to perform a first switching cycle sequence and controlling the second power transistor 124 to perform a second switching cycle sequence, the controller 110 causes the DC link capacitor 102 to discharge via the discharge current path 104 according to a discharge phase sequence. In response to the first power transistor 122 performing the first switching cycle sequence and the second power transistor 124 performing the second switching cycle sequence, the first power transistor 122 and the second power transistor 124 may control the discharge phase sequence. That is, one or more parameters of the discharge phase sequence may depend on the first switching cycle sequence and the second switching cycle sequence.

[0043] When the first power transistor 122 operates in the non-linear mode and performs the first switching cycle sequence, the first power transistor 122 may alternate between an active phase and a deactivated phase, wherein during the active phase the first power transistor 122 operates in the saturation region (where the first power transistor 122 is fully on), and during the deactivated phase the first power transistor 122 operates in the cut-off region (where the first power transistor 122 is fully off). Each switching cycle in the first switching cycle sequence may include an active phase and a deactivated phase. When the second power transistor 124 operates in the non-linear mode and performs the second switching cycle sequence, the second power transistor 124 may alternate between an active phase and a deactivated phase, wherein during the active phase the second power transistor 124 operates in the saturation region (where the second power transistor 124 is fully on), and during the deactivated phase the second power transistor 124 operates in the cut-off region (where the second power transistor 124 is fully off). Each switching cycle in the second switching cycle sequence may include an active phase and a deactivated phase.

[0044] In some examples, the discharge phase sequence may correspond to one or more overlapping segments between the activation phase of the first switching cycle sequence and the activation phase of the second switching cycle sequence, and during the discharge phase sequence, the DC link capacitor 102 discharges via the discharge current path 104. That is, when there is an overlapping segment between the activation phase of the first switching cycle sequence and the activation phase of the second switching cycle sequence, both the first power transistor 122 and the second power transistor 124 are fully turned on during the overlapping segment, such that current flows out of the DC link capacitor 102 across the first power transistor 122 and the second power transistor 124 during the overlapping segment. This means that the controller 110 can control the first switching cycle sequence and the second switching cycle sequence to define the discharge phase sequence, with each discharge phase corresponding to an overlapping segment between the activation phase of the first switching cycle sequence and the activation phase of the second switching cycle sequence.

[0045] In some examples, even when there is no overlapping segment between the activation phase of the first switching cycle sequence and the activation phase of the second switching cycle sequence, there may still be a discharge phase sequence, and during the discharge phase sequence, the DC link capacitor 102 discharges via the discharge current path 104. For example, even when there is no time period during which both the first power transistor 122 and the second power transistor 124 are fully turned off, current may still cross the discharge current path 104. This can occur via the parasitic capacitances of the first power transistor 122 and the second power transistor 124. For example, the current from the DC link capacitor 102 can charge the parasitic capacitance of the first power transistor 122. The parasitic capacitance of the first power transistor 122 can discharge to charge the parasitic capacitance of the second power transistor 124. The parasitic capacitance of the second power transistor 124 can discharge to complete the discharge current path 104.

[0046] In some examples, the DC link capacitor 102 can discharge during the overlapping segment between the activation phase of the first switching cycle sequence and the activation phase of the second switching cycle sequence and also according to the charging and discharging of the parasitic capacitances of the power transistors 122, 124. That is, during the time period when both the first power transistor 122 and the second power transistor 124 are present, current can flow freely across both the first power transistor 122 and the second power transistor 124. Additionally, the current from the DC link capacitor 102 can charge the parasitic capacitance of the first power transistor 122, the parasitic capacitance of the first power transistor 122 can discharge to charge the parasitic capacitance of the second power transistor 124, and the parasitic capacitance of the second power transistor 124 can discharge to complete the discharge current path 104.

[0047] In some examples, system 100 may include safety logic 150 separated from controller 110. In some examples, safety logic 150 may be configured to control first gate driver circuit 142 to deliver a first control signal to first power transistor 122 and control second gate driver circuit 144 to deliver a second control signal to second power transistor 124. In some examples, safety logic 150 may perform any function described herein as being performed by controller 110. In some examples, safety logic 150 may control first power transistor 122 and second power transistor 124 to discharge DC link capacitor 102 in response to the occurrence of one or more safety conditions. For example, in response to safety logic 150 determining that DC link capacitor 102 must be discharged, safety logic 150 may initiate the discharge of DC link capacitor 102. Although safety logic 150 is illustrated in Figure 1 as being separated from first gate driver circuit 142 and second gate driver circuit 144, in some cases safety logic 150 may be part of first gate driver circuit 142 and second power transistor 144.

[0048] In some examples, controller 110 controls first gate driver circuit 142 and second gate driver circuit 144 in response to system 100 operating according to a normal operating mode, and safety logic 150 controls first gate driver circuit 142 and second gate driver circuit 144 in response to system 100 operating according to a safety operating mode. In some examples, controller 110 may output a message to safety logic 150 in response to system 100 transitioning from a normal operating mode to a safety operating mode. In response to safety logic 150 receiving the message, safety logic 150 may control first gate driver circuit 142 and second gate driver circuit 144.

[0049] To discharge DC link capacitor 102 according to a discharge phase sequence, controller 110 is configured to cause current to flow out of DC link capacitor 102 via discharge current path 104 for each discharge phase in the discharge phase sequence. For example, during each discharge phase in the discharge phase sequence, current may flow out of DC link capacitor 102, thereby reducing the voltage of DC link capacitor 102. Throughout the discharge phase sequence, DC link capacitor 102 may discharge from a high voltage to a low voltage. In some examples, DC link capacitor 102 may discharge before a period of time has elapsed. In some examples, the period of time is in the range from 0.5 seconds to 3 seconds (e.g., 1 second). That is, DC link capacitor 102 may discharge according to the discharge phase sequence within a period of time in the range from 0.5 seconds to 3 seconds.

[0050] In some examples, to discharge the DC link capacitor 102 according to a discharge phase sequence, the controller 110 is configured to discharge the voltage of the DC link capacitor 102 from a first voltage value to a second voltage value. In some examples, each discharge phase in the discharge phase sequence can reduce the voltage of the DC link capacitor 102 until the voltage of the DC link capacitor 102 is less than or equal to the second voltage value. In some examples, the first voltage can represent a high voltage value similar to the voltage of a high-voltage power source used to power one or more electric motors of an electric vehicle. For example, the first voltage can be in the range from 400 volts (V) to 900 V. In some examples, the second voltage value represents a voltage that does not pose a safety hazard or poses a significantly reduced safety hazard. The second voltage value can be in the range from 0 V to 60 V.

[0051] In some examples, the voltage sensor 152 can be configured to generate a voltage signal indicative of the voltage of the DC link capacitor 102. In some examples, the controller 110 can receive the voltage signal from the voltage sensor 152. The controller 110 can initiate the discharge of the DC link capacitor 102 from a first voltage to a second voltage that is lower than the first voltage. The controller 110 can determine that the voltage of the DC link capacitor 102 is less than or equal to the second voltage value based on the voltage signal received from the voltage sensor 152. In response to determining that the voltage of the DC link capacitor 102 is less than or equal to the second voltage value, the controller 110 can control the first power transistor 122 to stop the first switching cycle sequence. In response to determining that the voltage of the DC link capacitor 102 is less than or equal to the second voltage value, the controller 110 can control the second power transistor 124 to stop the second switching cycle sequence.

[0052] In some examples, system 100 can transition from a normal operating mode to a safe operating mode. In the safe operating mode, safety logic 150 can take over control of the first gate driver circuit 142 and the second gate driver circuit 144 from controller 110. For example, controller 110 can cause system 100 to transition to the safe mode by outputting a message to safety logic 150. When system 100 operates according to the safe operating mode, safety logic 150 can receive a voltage signal from voltage sensor 152. Safety logic 150 can initiate a discharge of DC link capacitor 102 from a first voltage to a second voltage that is lower than the first voltage. Safety logic 150 can determine that the voltage of DC link capacitor 102 is less than or equal to the second voltage value based on the voltage signal received from voltage sensor 152. In response to determining that the voltage of DC link capacitor 102 is less than or equal to the second voltage value, safety logic 150 can control first power transistor 122 to stop the first switching cycle sequence. In response to determining that the voltage of DC link capacitor 102 is less than or equal to the second voltage value, safety logic 150 can control second power transistor 124 to stop the second switching cycle sequence.

[0053] Controller 110 can be configured to automatically stop the discharge of DC link capacitor 102 without an input from voltage sensor 152. For example, controller 110 can initiate a discharge of DC link capacitor 102 by causing first power transistor 122 to begin the first switching cycle sequence and causing second power transistor 124 to begin the second switching cycle sequence. When a period of time has elapsed after the start of the first switching cycle sequence, controller 110 can control first power transistor 122 to stop the first switching cycle sequence. When a period of time has elapsed after the start of the second switching cycle sequence, controller 110 can control second power transistor 124 to stop the second switching cycle sequence.

[0054] The controller 110 can determine whether to initiate the discharge of the DC link capacitor 102, and in response to determining to initiate the discharge, control the first power transistor 122 and the second power transistor 124 to discharge the DC link capacitor 102. For example, the controller 110 can identify one or more fault conditions that cause a discharge operation to discharge the DC link capacitor 102. The one or more fault conditions can include a motor vehicle accident, a hardware failure, a failure of one or more other electrical components, or any combination thereof. The controller 110 can initiate the discharge operation. The discharge operation includes the first power transistor 122 performing a first switching cycle sequence and the second power transistor 124 performing a second switching cycle sequence. The controller 110 is not limited to discharging the DC link capacitor 102 based on detecting a fault condition. In some examples, the controller 110 can identify one or more standard operating modes that cause a discharge operation to discharge the DC link capacitor 102, and initiate the discharge operation based on identifying the one or more normal operating modes. The normal operating modes that cause the DC link capacitor 102 to discharge can include powering down the electric vehicle or one or more other normal operating modes.

[0055] Figure 2 is a circuit diagram illustrating a system 200 for discharging a DC link capacitor 202 through a discharge current path 204 across a first power transistor 222 and a second power transistor 224 according to the present disclosure. For example, the system 200 includes: a DC link capacitor 202; a controller 210 including processing circuitry 212 and a memory 214; a power module 220 including a first power transistor 222 and a second power transistor 224; a first gate driver circuit 242; a second gate driver circuit 244; a safety logic 250; a voltage sensor 252; and a current sensor 254. The DC link capacitor 202 can be discharged via the discharge current path 204 through the first power transistor 222 and the second power transistor 224.

[0056] The system 200 can be Figure 1 an example of the system 100. The DC link capacitor 202 can be Figure 1 an example of the DC link capacitor 102. The controller 210 can be Figure 1 an example of the controller 110. The processing circuitry 212 can be Figure 1 an example of the processing circuitry 112. The memory 214 can be Figure 1 an example of the memory 114. The first power transistor 222 is Figure 1 an example of the first power transistor 122. The second power transistor 224 is Figure 1 an example of the second power transistor 124. The first gate driver circuit 242 can be Figure 1An example of the first gate driver circuit 142. The second gate driver circuit 244 can be Figure 1 An example of the second gate driver circuit 144. The safety logic 250 can be Figure 1 An example of the safety logic 150. The voltage sensor 252 can be Figure 1 An example of the voltage sensor 152.

[0057] System 200 can be substantially the same as Figure 1 System 100, except that system 200 includes a power module 220 that illustrates additional details regarding the first power transistor 222 and the second power transistor 224. For example, the power module 220 includes a first source terminal (S1) of the first power transistor 222, a first drain terminal (D1) of the first power transistor 222, and a first gate terminal (G1) of the first power transistor 222. The power module 220 also includes a second source terminal (S2) of the second power transistor 224, a second drain terminal (D2) of the second power transistor 224, and a second gate terminal (G2) of the second power transistor 224. System 200 also includes a current sensor 254, which is not illustrated as Figure 1 Part of system 100.

[0058] The controller 210 can cause the DC link capacitor 202 to discharge via a discharge current path 204. As Figure 2 seen, the first gate driver circuit 242 is connected to the first gate terminal G1 of the first power transistor 222. The first gate driver circuit 242 is also connected to the first source terminal S1 of the first power transistor 222. In some examples, the first gate driver circuit 242 can deliver a first control signal to the first gate terminal G1 of the first power transistor 222. The first gate driver circuit 242 can be configured to sense one or more parameters of the first source terminal S1 of the first power transistor 222. For example, the first gate driver circuit 242 can sense the voltage at the first source terminal S1 and / or the current at the first source terminal S1. By delivering the first control signal to the first gate terminal G1 of the first power transistor 222, the first gate driver circuit 242 can cause the first power transistor 222 to perform a first switching cycle sequence.

[0059] The second gate driver circuit 244 is connected to the second gate terminal G2 of the second power transistor 224. The second gate driver circuit 244 is also connected to the second source terminal S2 of the second power transistor 224. In some examples, the second gate driver circuit 244 may deliver a second control signal to the second gate terminal G2 of the second power transistor 224. The second gate driver circuit 244 may be configured to sense one or more parameters of the second source terminal S2 of the second power transistor 224. For example, the second gate driver circuit 244 may sense the voltage at the second source terminal S2 and / or the current at the second source terminal S2. By delivering the second control signal to the second gate terminal G2 of the second power transistor 224, the second gate driver circuit 244 may cause the second power transistor 224 to perform a second switching cycle sequence.

[0060] In some examples, the controller 210 may be configured to output first information to the first gate driver circuit 242 to cause the first gate driver circuit 242 to output a first control signal to the first gate terminal G1 of the first power transistor 222. The controller 210 may be configured to output second information to the second gate driver circuit 244 to cause the second gate driver circuit 244 to output a second control signal to the second gate terminal G2 of the second power transistor 224. The controller 210 is not the only component configured to control the first gate driver circuit 242 and the second gate driver circuit 244. The safety logic 250 may be configured to cause the first gate driver circuit 242 to output a first control signal to the first gate terminal G1 of the first power transistor 222. The safety logic 250 may be configured to cause the second gate driver circuit 244 to output a second control signal to the second gate terminal G2 of the second power transistor 224.

[0061] In some examples, the DC link capacitor 202 may discharge from a first voltage to a second voltage. The first voltage may be a high voltage (such as greater than 400V). The second voltage may be a low voltage (such as 60V). The voltage sensor 252 may be configured to sense the voltage of the DC link capacitor 202 and output a voltage signal indicating the voltage of the DC link capacitor 202 to the controller 210. The controller 210 may discharge the DC link capacitor 202 based on the voltage signal. For example, the controller 210 may cause the DC link capacitor 202 to start discharging from the first voltage. The controller 210 may stop discharging the DC link capacitor 202 based on determining that the voltage of the DC link capacitor 202 is less than or equal to the second voltage. In some examples, the controller 210 may discharge the DC link capacitor 202 without determining the voltage of the DC link capacitor 202. For example, the controller 210 may cause the DC link capacitor 202 to start discharging and then stop discharging after a period of time has elapsed since the start of the discharge. The current sensor 254 may be configured to sense the current along the discharge current path 204.

[0062] Figure 3 is a graph showing a first timing curve 300 of a first switching cycle sequence 310, a second switching cycle sequence 320, and a discharge phase sequence 330 according to the present disclosure. As Figure 3 seen, the first switching cycle sequence 310 includes a set of long activation phases 312A to 312N (collectively referred to as "long activation phases 312") and a set of short activation phases 314A to 314N (collectively referred to as "short activation phases 314"). The second switching cycle sequence 320 includes a set of long activation phases 322A to 322N (collectively referred to as "long activation phases 322") and a set of short activation phases 324A to 324N (collectively referred to as "short activation phases 324"). The discharge phase sequence 330 may include discharge phases 336A to 336N (collectively referred to as "discharge phases 336") and discharge phases 338A to 338N (collectively referred to as "discharge phases 338").

[0063] In some examples, Figure 1 the first power transistor 122 of is configured to execute the first switching cycle sequence 310. Figure 1The second power transistor 124 can be configured to perform a second switching cycle sequence 320. In the first switching cycle sequence 310, the first power transistor 122 can conduct during the long activation phase 312 and the short activation phase 314 and operate in the saturation region. The duration of each short activation phase in the short activation phase 314 can be shorter than the duration of each long activation phase in the long activation phase 312. The first power transistor 122 can turn off and operate in the cutoff region during the time period between the activation phases (e.g., between the long activation phase 312A and the short activation phase 314A). In the second switching cycle sequence 320, the second power transistor 124 can conduct during the long activation phase 322 and the short activation phase 324 and operate in the saturation region. The duration of each short activation phase in the short activation phase 324 can be shorter than the duration of each long activation phase in the long activation phase 322. The second power transistor 124 can turn off and operate in the cutoff region during the time period between the activation phases (e.g., between the short activation phase 324A and the long activation phase 322A).

[0064] Since both the first power transistor 122 and the second power transistor 124 switch between the saturation region during the activation phase and the cutoff region during the deactivation phase, both the first power transistor 122 and the second power transistor 124 can operate in a non-linear mode. This means that the first power transistor 122 and the second power transistor 124 can each perform the first switching cycle sequence 310 and the second switching cycle sequence 320 by alternating between fully on and fully off. This means that the first power transistor 122 and the second power transistor 124 can alternate between fully on and fully off without acting as an amplifier. In some examples, the gate voltage (+V) applied to the gate terminal of the first power transistor 122 during the long activation phase 312 and the short activation phase 314 exceeds the threshold gate voltage, such that the first power transistor 122 operates in a non-linear mode. In some examples, the gate voltage (+V) applied to the gate terminal of the second power transistor 124 during the long activation phase 322 and the short activation phase 324 exceeds the threshold gate voltage, such that the second power transistor 124 operates in a non-linear mode.

[0065] As Figure 3As seen in [Figure 0], the long activation phase 312A of the first switching cycle sequence 310 extends from time T1 to time T4. The short activation phase 324A of the second switching cycle sequence 320 extends from time T2 to time T3. This means that between time T2 and time T3, both the first power transistor 122 and the second power transistor 124 are fully turned on and operating in the saturation region. This means that when both the first power transistor 122 and the second power transistor 124 are fully turned on, current can flow out of the DC link capacitor 102 across the first power transistor 122 and the second power transistor 124 between time T2 and time T3. For example, when both the first power transistor 122 and the second power transistor 124 are fully turned on, the discharge phase 336A in the discharge phase 336 can occur between time T2 and time T3. During the time period between time T2 and time T3, the magnitude of the current flowing out across the first power transistor 122 and the second power transistor 124 can increase to the maximum current (+I).

[0066] Each saturation phase of the discharge phase 336 can correspond to an overlapping segment between the long activation phase in the long activation phase 312 performed by the first power transistor 122 and the short activation phase in the short activation phase 324 performed by the second power transistor 124. Each saturation phase in the saturation phase 338 can correspond to an overlapping segment between the short activation phase in the short activation phase 314 performed by the first power transistor 122 and the long activation phase in the long activation phase 322 performed by the second power transistor 124. During each saturation phase of the discharge phases 336, 338, current can flow from the DC link capacitor 102 through the first power transistor 122 and the second power transistor 124, thereby reducing the voltage of the DC link capacitor 102 by a certain amount of voltage. Throughout the discharge phases 336, 338, the voltage of the DC link capacitor 102 can be reduced from the first voltage to a second voltage lower than the first voltage.

[0067] In some examples, the long activation phase 312 and the short activation phase 314 performed by the first power transistor 122 can be interleaved such that the short activation phases in the short activation phase 314 occur between each pair of consecutive long activation phases in the long activation phase 312. The long activation phase 322 and the short activation phase 324 performed by the second power transistor 124 can be interleaved such that the short activation phases in the short activation phase 324 occur between each pair of consecutive long activation phases in the long activation phase 322. The long activation phase 312 can be time-aligned with the short activation phase 324, and the short activation phase 314 can be time-aligned with the long activation phase 322.

[0068] By interleaving the long activation phases and short activation phases performed by each of the first power transistor 122 and the second power transistor 124 such that the short activation phase performed by the first power transistor 122 is aligned with the long activation phase performed by the second power transistor 124, and vice versa, the controller 110 can evenly distribute stress between the first power transistor 122 and the second power transistor 124. For example, during the discharge phase 336, a greater amount of stress can be applied to the second power transistor 124 compared to the stress applied to the first power transistor 122. During the saturation phase 338, a greater amount of stress can be applied to the first power transistor 122 compared to the stress applied to the second power transistor 124. This means that the stress can be evenly distributed between the first power transistor 122 and the second power transistor 124.

[0069] Figure 4 is a graph showing a second timing curve 400 of a first switching cycle sequence 410, a second switching cycle sequence 420, and a discharge phase sequence 430 according to the present disclosure. As Figure 4 seen, the first switching cycle sequence 410 includes a set of activation phases 412A to 412N (collectively referred to as "activation phases 412"). The second switching cycle sequence 420 includes a set of activation phases 422A to 422N (collectively referred to as "activation phases 422"). The discharge phase sequence 430 may include discharge phases 436A to 436N (collectively referred to as "discharge phases 436") and discharge phases 438A to 438N (collectively referred to as "discharge phases 438").

[0070] In some examples, Figure 1 the first power transistor 122 of is configured to perform the first switching cycle sequence 410. Figure 1The second power transistor 124 can be configured to perform a second switching cycle sequence 420. In the first switching cycle sequence 410, the first power transistor 122 can conduct during the activation phase 412 and operate in the saturation region. In some examples, the duration of each activation phase in the activation phase 412 can be substantially the same as the duration of each other activation phase in the activation phase 412. The first power transistor 122 can turn off and operate in the cutoff region during the time period between activation phases (e.g., between activation phase 412A and activation phase 412B). In the second switching cycle sequence 420, the second power transistor 124 can conduct during the activation phase 422 and operate in the saturation region. In some examples, the duration of each activation phase in the activation phase 422 can be substantially the same as the duration of each other activation phase in the activation phase 422. The second power transistor 124 can turn off and operate in the cutoff region during the time period between activation phases (e.g., between activation phase 424A and activation phase 424B).

[0071] When performing the first switching cycle sequence 410 and the second switching cycle sequence 420 respectively, the first power transistor 122 and the second power transistor 124 can operate in a non-linear mode. That is, by alternating between fully conducting and fully turning off, the first power transistor 122 can perform the first switching cycle sequence 410, and the second power transistor 124 can perform the second switching cycle sequence 420. In some examples, the gate voltage (+V) applied to the gate terminal of the first power transistor 122 during the activation phase 412 exceeds the threshold gate voltage, such that the first power transistor 122 operates in a non-linear mode. In some examples, the gate voltage (+V) applied to the gate terminal of the second power transistor 124 during the activation phase 422 exceeds the threshold gate voltage, such that the second power transistor 124 operates in a non-linear mode.

[0072] As Figure 4 seen, the activation phase 412A of the first switching cycle sequence 410 extends from time T1 to time T2. The activation phase 422A of the second switching cycle sequence 420 extends from time T2 to time T4. There is a time period between time T2 and time T3 during which both the first power transistor 122 and the second power transistor 124 are deactivated and operate in the cutoff region. In the example of the second timing curve 400, there is no time period during which both the first power transistor 122 and the second power transistor 124 are activated and operate in the saturation region. This means that there is no time period during which both the first power transistor 122 and the second power transistor 124 are activated to complete the discharge current path 104 through the first power transistor 122 and the second power transistor 124.

[0073] Even in the example of the second timing curve 400, where there is no overlapping segment between the activation phase 412 of the first switching cycle sequence 410 and the activation phase 422 of the second switching cycle sequence 420, the DC link capacitor 102 can still discharge via the parasitic capacitances of the first power transistor 122 and the second power transistor 124 through the discharge current path 104. For example, even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the first power transistor 122 can be charged. Even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the first power transistor 122 can discharge to charge the parasitic capacitance of the second power transistor 124. Even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the second power transistor 124 can discharge to complete the discharge current path 104.

[0074] Since the current output from the DC link capacitor 102 is configured to cross the discharge current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor 124, even when there is no overlapping segment between the activation phase of the first switching cycle sequence 410 and the activation phase of the second switching cycle sequence 420, the first power transistor 122 can execute the first switching cycle sequence 410 and the second power transistor 124 can execute the second switching cycle sequence 420 to discharge the DC link capacitor 102 from the first voltage to the second voltage. For example, the DC link capacitor 102 can discharge during the entire discharge phase 436 and discharge phase 438.

[0075] As Figure 4 seen, each discharge phase in the discharge phase 436 can start when the activation phase in the activation phase 412 starts, and each discharge phase in the discharge phase 438 starts when the activation phase in the activation phase 422 starts. In response to the first power transistor 122 being activated when each activation phase in the activation phase 412 starts, this may cause one or both of the parasitic capacitance of the first power transistor 122 and the parasitic capacitance of the second power transistor 124 to discharge through the discharge current path 104. In response to the second power transistor 124 being activated when each activation phase in the activation phase 422 starts, this can cause one or both of the parasitic capacitance of the first power transistor 122 and the parasitic capacitance of the second power transistor 124 to discharge through the discharge current path 104.

[0076] During a period of time after each activation stage in the activation stage 412, the current through the discharge current path 104 can be increased to a maximum current (+I). For example, after the activation stage 412A at time T1 is started, the current through the discharge current path 104 increases to the maximum current during the discharge stage 436A. After the activation stage 412B at time T5 is started, the current through the discharge current path 104 increases to the maximum current during the discharge stage 436B, and so on. In addition, during a period of time after each activation stage in the activation stage 422, the current through the discharge current path 104 can be increased to the maximum current. For example, after the activation stage 422A at time T3 is started, the current through the discharge current path 104 increases to the maximum current within the discharge stage 438A. After the activation stage 422B is started, the current through the discharge current path 104 increases to the maximum current during the discharge stage 438B, and so on.

[0077] In response to the first power transistor 122 executing the first switching cycle sequence 410 and the second power transistor 124 executing the second switching cycle sequence 420, even when there is no overlapping region between the activation stage 412 and the activation stage 422, the DC link capacitor 102 can be discharged from the first voltage to the second voltage through the discharge current path 104. The current discharged by the DC link capacitor 102 can cross the discharge current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor. Since the activation stage 412 and the activation stage 422 are interleaved, this can equally distribute the stress between the first power transistor 122 and the second power transistor 124.

[0078] In some examples, in an example of the second timing curve 400 where there is no overlapping region between the activation stages of the power transistor 122 and the power transistor 124, the maximum current associated with the discharge stage 436 and the discharge stage 438 is lower than that in Figure 3 an example of the first timing curve 300 where there is an overlapping region between the activation stages of the power transistor 122 and the power transistor 124 and associated with the discharge stage 336 and the discharge stage 338. This is because, compared with an example where one or both of the first power transistor 122 and the second power transistor 124 are deactivated, when both the first power transistor 122 and the second power transistor 124 are simultaneously activated, the current can flow more freely through the discharge current path 104. That is, in an example of the second timing curve 400 where the current depends on the parasitic capacitances of the first power transistor 122 and the second power transistor 124 to cross the discharge current path 104, the amplitude of the current is limited by the capacitance of the parasitic capacitances of the first power transistor 122 and the second power transistor 124.

[0079] Figure 5is a graph showing a third timing curve 500 of a first switching cycle sequence 510, a second switching cycle sequence 520, and a discharge phase sequence 530 according to the present disclosure. As Figure 5 seen, the first switching cycle sequence 510 includes a set of activation phases 512A to 512N (collectively referred to as "activation phase 512"). The second switching cycle sequence 520 includes a set of activation phases 522A to 522N (collectively referred to as "activation phase 522"). The discharge phase sequence 530 may include discharge phases 536A to 536N (collectively referred to as "discharge phase 536") and discharge phases 538A to 538N (collectively referred to as "discharge phase 538").

[0080] In some examples, Figure 1 the first power transistor 122 is configured to perform the first switching cycle sequence 510. Figure 1 the second power transistor 124 may be configured to perform the second switching cycle sequence 520. In the first switching cycle sequence 510, the first power transistor 122 may conduct during the activation phase 512 and operate in the saturation region. In some examples, the duration of each activation phase in the activation phase 512 may be substantially the same as the duration of each other activation phase in the activation phase 512. The first power transistor 122 may turn off and operate in the cutoff region during the time period between the activation phases (e.g., between activation phase 512A and activation phase 512B). In the second switching cycle sequence 520, the second power transistor 124 may conduct during the activation phase 522 and operate in the saturation region. In some examples, the duration of each activation phase in the activation phase 522 may be substantially the same as the duration of each other activation phase in the activation phase 522. The second power transistor 124 may turn off and operate in the cutoff region during the time period between the activation phases (e.g., between activation phase 524A and activation phase 524B).

[0081] When performing the first switching cycle sequence 510 and the second switching cycle sequence 520 respectively, the first power transistor 122 and the second power transistor 124 may operate in a non-linear mode. That is, by alternating between fully conducting and fully turning off, the first power transistor 122 may perform the first switching cycle sequence 510, and the second power transistor 124 may perform the second switching cycle sequence 520. In some examples, the gate voltage (+V) applied to the gate terminal of the first power transistor 122 during the activation phase 512 exceeds the threshold gate voltage, such that the first power transistor 122 operates in a non-linear mode. In some examples, the gate voltage (+V) applied to the gate terminal of the second power transistor 124 during the activation phase 522 exceeds the threshold gate voltage, such that the second power transistor 124 operates in a non-linear mode.

[0082] As Figure 5 seen, the activation phase 512A of the first switching cycle sequence 510 extends from time T1 to time T2. The activation phase 522A of the second switching cycle sequence 520 extends from time T2 to time T3. That is, the activation phase 512A ends at the same time T2 at which the activation phase 522A begins. In some cases, there can be a very brief moment at time T2 when both the first power transistor 122 and the second power transistor 124 are activated. In some cases, at time T2, the first power transistor 122 is in the turn-off process and the second power transistor 124 is in the turn-on process. This means that at time T2, there can be a very brief time period in which both the first power transistor 122 and the second power transistor 124 are at least partially activated to complete the discharge current path 104 through the first power transistor 122 and the second power transistor 124.

[0083] Even in the example of the third timing curve 500, where there is a very brief overlapping segment between the activation phase 512 of the first switching cycle sequence 510 and the activation phase 522 of the second switching cycle sequence 520, the DC link capacitor 102 can still discharge through the discharge current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor 124. For example, even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the first power transistor 122 can be charged. Even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the first power transistor 122 can discharge to charge the parasitic capacitance of the second power transistor 124. Even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the second power transistor 124 can discharge to complete the discharge current path 104.

[0084] Since the current output from the DC link capacitor 102 is configured to traverse the discharge current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor 124, the first power transistor 122 can execute the first switching cycle sequence 510 and the second power transistor 124 can execute the second switching cycle sequence 520 to discharge the DC link capacitor 102 from the first voltage to the second voltage even when there is only a very short overlap segment between the activation phase of the first switching cycle sequence 510 and the activation phase of the second switching cycle sequence 520. In the example of the third timing curve 500, when both the first power transistor 122 and the second power transistor 124 are activated in a very short time period (e.g., at time T1, time T2, time T3, and time T4), the DC link capacitor 102 can be discharged by the current passing through the discharge current path 104 and by the current passing through the discharge current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor 124. The DC link capacitor 102 can be discharged during the entire discharge phase 536 and discharge phase 538.

[0085] During the time period after the start of each activation phase in the activation phase 512, the current passing through the discharge current path 104 can increase to the maximum current (+I). For example, after the start of the activation phase 512A at time T1, the current passing through the discharge current path 104 increases to the maximum current during the discharge phase 536A, after the start of the activation phase 512B at time T3, the current passing through the discharge current path 104 increases to the maximum current during the discharge phase 536B, and so on. In addition, during the time period after the start of each activation phase in the activation phase 522, the current passing through the discharge current path 104 can increase to the maximum current. For example, after the start of the activation phase 522A at time T2, the current passing through the discharge current path 104 increases to the maximum current during the discharge phase 538A, after the start of the activation phase 522B at time T4, the current passing through the discharge current path 104 increases to the maximum current during the discharge phase 538B, and so on.

[0086] In response to the first power transistor 122 executing a first switching cycle sequence 510 and the second power transistor 124 executing a second switching cycle sequence 520, even if there is only a short overlapping region between the activation phase 512 and the activation phase 522, the DC link capacitor 102 can discharge from a first voltage to a second voltage through the discharge current path 104. The current discharged by the DC link capacitor 102 can cross the discharge current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor and during a short time period (e.g., at time T1, time T2, time T3, and time T4) when both the first power transistor 122 and the second power transistor 124 are activated. Since the activation phases 512 and 522 are interleaved, this can equally distribute the stress between the first power transistor 122 and the second power transistor 124.

[0087] In some examples, in the example of the third timing curve 500, the maximum current associated with the discharge phase 536 and the discharge phase 538 is greater than the maximum current associated with the discharge phase 436 and the discharge phase 438 in the example of the Figure 4 curve 400. In the third timing curve 500, there is a very short overlapping region between the activation phases of the power transistor 122 and the power transistor 124. In the Figure 4 curve 400, there is no overlapping region between the activation phases of the power transistor 122 and the power transistor 124. This is because, compared to an example where there is a time gap between the activation phases of the first power transistor 122 and the second power transistor 124, when the activation phase of the first power transistor 122 immediately transitions to the activation phase of the second power transistor 124, the current can flow more freely through the discharge current path 104.

[0088] Figure 6 is a graph showing a fourth timing curve 600 illustrating a first switching cycle sequence 610, a second switching cycle sequence 620, and a discharge phase sequence 630 according to the present disclosure. As Figure 6As seen in, the first switching cycle sequence 610 includes a set of activation phases 612A through 612N (collectively referred to as "activation phases 612"). Each activation phase in the activation phases 612 includes a soft turn-off phase from soft turn-off phase 613A through soft turn-off phase 613N (collectively referred to as "soft turn-off phases 613"). The second switching cycle sequence 620 includes a set of activation phases 622A through 622N (collectively referred to as "activation phases 622"). Each activation phase in the activation phases 622 includes a soft turn-off phase from soft turn-off phase 623A through soft turn-off phase 623N (collectively referred to as "soft turn-off phases 623"). The discharge phase sequence 630 may include discharge phases 636A through 636N (collectively referred to as "discharge phases 636") and discharge phases 638A through 638N (collectively referred to as "discharge phases 638").

[0089] In some examples, Figure 1 the first power transistor 122 is configured to execute the first switching cycle sequence 610. Figure 1 the second power transistor 124 may be configured to execute the second switching cycle sequence 620. In the first switching cycle sequence 610, the first power transistor 122 may conduct during the activation phases 612 and operate in the saturation region. In some examples, the duration of each activation phase in the activation phases 612 may be substantially the same as the duration of each other activation phase in the activation phases 612. The first power transistor 122 may turn off and operate in the cutoff region during the time period between activation phases (e.g., between activation phase 612A and activation phase 612B). In the second switching cycle sequence 620, the second power transistor 124 may conduct during the activation phases 622 and operate in the saturation region. In some examples, the duration of each activation phase in the activation phases 622 may be substantially the same as the duration of each other activation phase in the activation phases 622. The second power transistor 124 may turn off and operate in the cutoff region during the time period between activation phases (e.g., between activation phase 624A and activation phase 624B).

[0090] In some examples, the first power transistor 122 and the second power transistor 124 can be configured to perform soft turn-on or hard turn-on when transitioning from a deactivated stage to an activated stage. Hard turn-on involves a faster transition from the deactivated stage to the activated stage. For example, when the first power transistor 122 transitions from the deactivated stage to the activated stage 612A, hard turn-on occurs at time T1, when the second power transistor 124 transitions from the deactivated stage to the activated stage 622A, hard turn-on occurs at time T2, and so on. Soft turn-on involves a slower transition from the deactivated stage to the activated stage. For example, during soft turn-on, the first power transistor 122 and / or the second power transistor 124 may not be instantaneously activated as occurs during the hard turn-on stages at times T1, T2, T3, and T4. In some examples, the first power transistor 122 and the second power transistor 124 can include two separate gate input pins, one gate input pin for hard turn-on and one gate input pin for soft turn-on.

[0091] The first power transistor 122 and the second power transistor 124 can be configured to perform soft turn-off or hard turn-off when transitioning from the activated stage to the deactivated stage. Hard turn-off involves a faster transition from the activated stage to the deactivated stage. Soft turn-off involves a slower transition from the activated stage to the deactivated stage. For example, during soft turn-off, the first power transistor 122 and / or the second power transistor 124 may not be instantaneously deactivated. For example, during the soft turn-off stage 613A, the first power transistor 122 takes time to transition from the activated stage 612A to the deactivated stage, during the soft turn-off stage 613B, the first power transistor 122 takes time to transition from the activated stage 612B to the deactivated stage, and so on. The first power transistor 122 and the second power transistor 124 can include two separate gate input pins, one gate input pin for hard turn-off and one gate input pin for soft turn-off.

[0092] In some examples, the first power transistor 122 and the second power transistor 124 may each include a single gate input pin for receiving a control signal from a gate driver. In some examples, the first gate driver circuit 142 may include two output pins, one output pin for controlling the first power transistor 122 to perform a hard turn-off and / or a hard turn-on, and one output pin for controlling the first power transistor 122 to perform a soft turn-off and / or a soft turn-on. In some examples, the second gate driver circuit 144 may include two output pins, one output pin for controlling the second power transistor 124 to perform a hard turn-off and / or a hard turn-on, and one output pin for controlling the second power transistor 124 to perform a soft turn-off and / or a soft turn-on. In these examples, the two output pins of the first gate driver circuit 142 may output to the single gate input pin of the first power transistor 122, and the two output pins of the second gate driver circuit 144 may output to the single gate input pin of the second power transistor 124.

[0093] When the first switching cycle sequence 610 and the second switching cycle sequence 620 are respectively executed, the first power transistor 122 and the second power transistor 124 may operate in a non-linear mode. That is, by alternating between full conduction and full turn-off, the first power transistor 122 may execute the first switching cycle sequence 610, and the second power transistor 124 may execute the second switching cycle sequence 620. In some examples, the gate voltage (+V) applied to the gate terminal of the first power transistor 122 during the activation phase 612 exceeds the threshold gate voltage, such that the first power transistor 122 operates in a non-linear mode. In some examples, the gate voltage (+V) applied to the gate terminal of the second power transistor 124 during the activation phase 622 exceeds the threshold gate voltage, such that the second power transistor 124 operates in a non-linear mode.

[0094] As Figure 6As seen in, activation phase 622A starts with a hard turn-on at time T2, and T2 is in the middle of the soft turn-off phase 613A of activation phase 612A. This means that when the second power transistor 124 suddenly turns on, the first power transistor 122 is in the turn-off process. This means that activation phase 622A overlaps with the second half of the soft turn-off phase 613A of activation phase 612A. This means that during the second half of the soft turn-off phase 613A of activation phase 612A, after time T2, the DC link capacitor 102 can discharge through the discharge current path 104 across the first power transistor 122 and the second power transistor 124. During the second half of each of the activation phases 612, there can be a segment during which both the first power transistor 122 and the second power transistor 124 are activated before the first power transistor 122 completes the soft turn-off phase. The same is true for the second power transistor 124. During the second half of each of the activation phases 622, there can be a segment during which both the first power transistor 122 and the second power transistor 124 are activated before the second power transistor 124 completes the soft turn-off phase.

[0095] Even in the example of the fourth timing curve 600, even though there is a brief overlapping segment between the soft turn-off phases 613 of activation phase 612 and activation phase 622, the DC link capacitor 102 can still discharge through the parasitic capacitances of the first power transistor 122 and the second power transistor 124 via the discharge current path 104. For example, even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the first power transistor 122 can be charged. Even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the first power transistor 122 can discharge to charge the parasitic capacitance of the second power transistor 124. Even when one or both of the first power transistor 122 and the second power transistor 124 are disabled, the parasitic capacitance of the second power transistor 124 can discharge to complete the discharge current path 104. That is, the current from the DC link capacitor 102 can flow freely through the discharge current path 104 when both the first power transistor 122 and the second power transistor 124 are turned on, and can cross the discharge current path 104 by being transferred through the parasitic capacitances of the first power transistor 122 and the second power transistor 124.

[0096] During a period of time after each activation phase start in activation phase 612, the current through discharge current path 104 can increase to a maximum current (+I). For example, during discharge phase 636A after activation phase 612A at time T1, the current through discharge current path 104 increases to the maximum current, and during discharge phase 636B after activation phase 612B at time T3, the current through discharge current path 104 increases to the maximum current, and so on. Additionally, during a period of time after each activation phase start in activation phase 622, the current through discharge current path 104 can increase to the maximum current. For example, during discharge phase 638A after activation phase 622A at time T2, the current through discharge current path 104 increases to the maximum current, and during discharge phase 638B after activation phase 622B at time T4, the current through discharge current path 104 increases to the maximum current, and so on.

[0097] By performing a soft turn-off to end the activation phase, the first power transistor 122 and the second power transistor 124 can allow a brief period where both the first power transistor 122 and the second power transistor 124 are activated without placing excessive stress on the first power transistor 122 and the second power transistor 124. The stress can be evenly distributed between the first power transistor 122 and the second power transistor 124 because activation phase 612 and activation phase 622 are interleaved. Additionally, by performing a soft turn-off to end the activation phase, the first power transistor 122 and the second power transistor 124 can prevent overvoltage events that occur when using a hard turn-off.

[0098] Figure 7 is a block diagram illustrating an example system 700 for disconnecting the power of one or more electrical components and discharging a DC link capacitor according to the present disclosure. System 700 includes a capacitor discharge system 701, DC link capacitors 702A to 702C (collectively referred to as "DC link capacitors 702"), a power source 740, a power disconnect unit 750, a traction inverter 762, a DC-DC converter 764, and an air conditioner inverter 766. As Figure 7 seen, the traction inverter 762 includes DC link capacitor 702A, the DC-DC converter 764 includes DC link capacitor 702B, and the air conditioner inverter 766 includes a DC link capacitor.

[0099] The capacitor discharge system 701 can include one or more power transistors, gate driver circuits, a controller, or any combination thereof for discharging the DC link capacitors 702. Figure 1 of the DC link capacitor 102 and Figure 2The DC link capacitor 202 can be an example of any one of the DC link capacitor 702A, the DC link capacitor 702B, and the DC link capacitor 702C. The power supply 7490 can supply power to the traction inverter 762, the DC-DC converter 764, and the air conditioner inverter 766. The power disconnect unit 750 can disconnect the power supply 740 from one or more of the traction inverter 762, the DC-DC converter 764, and the air conditioner inverter 766 in response to one or more fault conditions or one or more normal operating conditions. The capacitor discharge system 701 can discharge one or more of the DC link capacitor 702A, the DC link capacitor 702B, and the DC link capacitor 702C in response to an electrical component corresponding to the DC link capacitor being disconnected by the power disconnect unit 750.

[0100] Figure 8 is a flowchart illustrating an example operation for discharging a DC link capacitor using a power transistor in accordance with one or more techniques of the present disclosure. With respect to Figure 1 system 100 described Figure 8 . However, Figure 8 the techniques can be performed by different components of system 100 or by additional or alternative systems.

[0101] The controller 110 is configured to control the first power transistor 122 to perform a first switching cycle sequence (802) by applying a first gate voltage that exceeds a threshold gate voltage for each switching cycle in the first switching cycle sequence to cause the first power transistor 122 to operate according to a non-linear transfer function. For example, the first power transistor 122 can operate in a non-linear mode such that the first power transistor alternates between an active phase and a deactivated phase, and during the active phase, the first power transistor 122 operates in the saturation operating region, and during the deactivated phase, the first power transistor 122 operates in the cut-off operating region. The first power transistor 122 can be configured to freely conduct current when operating in the saturation operating region.

[0102] The controller 110 is configured to control the second power transistor 124 to perform a second switching cycle sequence (802) by applying a second gate voltage that exceeds a threshold gate voltage for each switching cycle in the second switching cycle sequence to cause the second power transistor 124 to operate according to a non-linear transfer function. For example, the second power transistor 124 can operate in a non-linear mode such that the first power transistor alternates between an active phase and a deactivated phase, and during the active phase, the second power transistor 124 operates in the saturation operating region, and during the deactivated phase, the second power transistor 124 operates in the cut-off operating region. The second power transistor 124 can be configured to freely conduct current when operating in the saturation operating region.

[0103] By controlling the first power transistor 122 to execute a first switching cycle sequence and controlling the second power transistor 124 to execute a second switching cycle sequence, the controller 110 is configured to cause the DC link capacitor 102 to discharge (806) via a discharge current path 104 according to a discharge phase sequence. In some examples, during each discharge phase in the discharge phase sequence, current may discharge from the DC link capacitor 102. When both the first power transistor 122 and the second power transistor 124 are turned on, current may freely discharge through the discharge current path 104. Additionally or alternatively, current may discharge through the current path 104 via the parasitic capacitances of the first power transistor 122 and the second power transistor 124.

[0104] The following numbered clauses may illustrate one or more aspects of the present disclosure.

[0105] Clause 1: A circuit, comprising: a first power transistor, including a first gate terminal; and a second power transistor, including a second gate terminal. The second power transistor is connected in series with the first power transistor. A capacitor, the first power transistor, and the second power transistor are located on a discharge current path. The circuit further includes a controller configured to control the first power transistor to execute a first switching cycle sequence by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence, the first gate voltage exceeding a threshold gate voltage such that the first power transistor operates according to a non-linear transfer function, and to control the second power transistor to execute a second switching cycle sequence by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence, the second gate voltage exceeding a threshold gate voltage such that the second power transistor operates according to a non-linear transfer function. By controlling the first power transistor to execute the first switching cycle sequence and controlling the second power transistor to execute the second switching cycle sequence, the controller is configured to cause the capacitor to discharge via the discharge current path according to a discharge phase sequence.

[0106] Clause 2: The circuit according to clause 1, wherein to cause the capacitor to discharge according to a discharge phase sequence, the controller is configured to cause current to flow out of the capacitor via the discharge current path for each discharge phase in the discharge phase sequence.

[0107] Clause 3: The circuit according to any one of clauses 1 to 2, wherein to cause the capacitor to discharge according to a discharge phase sequence, the controller is configured to discharge the voltage of the capacitor from a first voltage value to a second voltage value, each discharge phase in the discharge phase sequence reducing the voltage of the capacitor until the voltage of the capacitor equals the second voltage value.

[0108] Clause 4: The circuit according to Clause 3 further includes a voltage sensor configured to generate a voltage signal indicative of the voltage of the capacitor, and wherein the controller or the safety logic is configured to: based on the voltage signal, determine that the voltage of the capacitor is equal to a second voltage value; based on determining that the voltage of the capacitor is equal to the second voltage value, control the first power transistor to stop the first switching cycle sequence; and based on determining that the voltage of the capacitor is equal to the second voltage value, control the second power transistor to stop the second switching cycle sequence.

[0109] Clause 5: The circuit according to any one of Clauses 1 to 4, wherein the controller is configured to: when a time period has elapsed, control the first power transistor to stop the first switching cycle sequence; and when the time period has elapsed, control the second power transistor to stop the second switching cycle sequence.

[0110] Clause 6: The circuit according to any one of Clauses 1 to 5, wherein in order to discharge the capacitor according to a discharge phase sequence, the controller is configured for each discharge phase in the discharge phase sequence: in response to both the first transistor and the second transistor being activated, cause current to flow out of the capacitor across the first power transistor and the second power transistor; and in response to one or both of the first power transistor and the second power transistor being deactivated, prevent current from flowing out of the capacitor across the first power transistor and the second power transistor.

[0111] Clause 7: The circuit according to any one of Clauses 1 to 6, wherein in order to discharge the capacitor according to a discharge phase sequence, the controller is configured for each discharge phase in the discharge phase sequence: cause the current from the capacitor to charge the parasitic capacitance of the first power transistor; discharge the parasitic capacitance of the first power transistor to charge the parasitic capacitance of the second power transistor; and discharge the parasitic capacitance of the second power transistor.

[0112] Clause 8: The circuit according to Clause 7, wherein in order to discharge the capacitor according to a discharge phase sequence, the controller is further configured to, in response to both the first power transistor and the second power transistor being activated, cause current to flow out of the capacitor across the first power transistor and the second power transistor for each discharge phase in the discharge phase sequence.

[0113] Clause 9: The circuit according to any one of Clauses 1 to 8, wherein each first switching cycle in the first switching cycle sequence includes a first activation phase and a first deactivation phase, wherein each second switching cycle in the second switching cycle sequence includes a second activation phase and a second deactivation phase, and wherein each discharge phase in the discharge phase sequence corresponds to a combination of the first activation phase of the first switching cycle in the first switching cycle sequence and the second activation phase of the second switching cycle in the second switching cycle sequence.

[0114] Clause 10: A circuit according to any one of Clauses 1 to 9, wherein the first switching cycle sequence includes a first plurality of short activation phases and a first plurality of long activation phases interleaved with the first plurality of short activation phases, wherein the duration of each short activation phase in the first plurality of short activation phases is shorter than the duration of each long activation phase in the first plurality of long activation phases, wherein the second switching cycle sequence includes a second plurality of short activation phases and a second plurality of long activation phases interleaved with the second plurality of short activation phases, wherein the duration of each short activation phase in the second plurality of short activation phases is shorter than the duration of each long activation phase in the second plurality of long activation phases, and wherein each discharge phase in the discharge phase sequence corresponds to: an overlapping segment between a short activation phase in the first plurality of short activation phases and a long activation phase in the second plurality of long activation phases; or an overlapping segment between a short activation phase in the second plurality of short activation phases and a long activation phase in the first plurality of long activation phases.

[0115] Clause 11: A circuit according to any one of Clauses 1 to 10, wherein the first switching cycle sequence includes a first plurality of activation phases, wherein the second switching cycle sequence includes a second plurality of activation phases interleaved with the first plurality of activation phases such that each activation phase in the second plurality of activation phases does not overlap with any of the first plurality of activation phases, and wherein each discharge phase in the discharge phase sequence corresponds to: a time period after the start of an activation phase in the first plurality of activation phases; or a time period after the start of an activation phase in the second plurality of activation phases.

[0116] Clause 12: A circuit according to any one of Clauses 1 to 11, wherein the first switching cycle sequence includes a first plurality of activation phases, each activation phase in the first plurality of activation phases ending in a first soft turn-off phase, wherein the first gate voltage decreases during the first soft turn-off phase, wherein the second switching cycle sequence includes a second plurality of activation phases, each activation phase in the second plurality of activation phases ending in a second soft turn-off phase, wherein the second gate voltage decreases during the second soft turn-off phase, and wherein each discharge phase in the discharge phase sequence corresponds to: an overlapping segment between the first soft turn-off phase of an activation phase in the first plurality of activation phases and an activation phase in the second plurality of activation phases; or an overlapping segment between the second soft turn-off phase of an activation phase in the second plurality of activation phases and an activation phase in the first plurality of activation phases.

[0117] Clause 13: A circuit according to any one of Clauses 1 to 12, wherein the controller is configured to: identify one or more fault conditions that cause a discharge operation to discharge a capacitor; and initiate the discharge operation based on the identified one or more fault conditions, wherein the discharge operation includes the first power transistor performing the first switching cycle sequence and the second power transistor performing the second switching cycle sequence.

[0118] Clause 14: A circuit according to any one of Clauses 1 to 13, wherein the controller is configured to: identify one or more standard operating modes that cause a discharge operation to discharge a capacitor; and initiate the discharge operation based on the identified one or more standard operating modes, wherein the discharge operation includes a first power transistor performing a first switching cycle sequence and a second power transistor performing a second switching cycle sequence.

[0119] Clause 15: A circuit according to any one of Clauses 1 to 14, wherein the capacitor includes a DC link capacitor connected to an inverter circuit for an electric motor of a vehicle.

[0120] Clause 16: A method, comprising: controlling, by a controller, a first power transistor including a first gate terminal to perform a first switching cycle sequence by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence, the first gate voltage exceeding a threshold gate voltage such that the first power transistor operates according to a non-linear transfer function; and controlling, by the controller, a second power transistor including a second gate terminal to perform a second switching cycle sequence by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence, the second gate voltage exceeding the threshold gate voltage such that the second power transistor operates according to a non-linear transfer function, wherein the second power transistor is connected in series with the first power transistor, and wherein the capacitor, the first power transistor, and the second power transistor are located on a discharge current path. By controlling the first power transistor to perform the first switching cycle sequence and controlling the second power transistor to perform the second switching cycle sequence, the method includes discharging the capacitor via the discharge current path according to a discharge phase sequence.

[0121] Clause 17: The method according to Clause 16, wherein discharging the capacitor according to the discharge phase sequence includes causing current to flow out of the capacitor via the discharge current path for each discharge phase in the discharge phase sequence.

[0122] Clause 18: The method according to any one of Clauses 16 to 17, wherein discharging the capacitor according to the discharge phase sequence includes discharging the voltage of the capacitor from a first voltage value to a second voltage value, each discharge phase in the discharge phase sequence reducing the voltage of the capacitor until the voltage of the capacitor equals the second voltage value.

[0123] Item 19: A method according to any one of Items 16 to 18, wherein discharging the capacitor according to a sequence of discharge phases includes, for each discharge phase in the sequence of discharge phases: in response to both the first transistor and the second transistor being activated, causing, by a controller, current to flow out of the capacitor across the first power transistor and the second power transistor; and in response to one or both of the first power transistor and the second power transistor being deactivated, preventing, by the controller, current from flowing out of the capacitor across the first power transistor and the second power transistor.

[0124] Item 20: A method according to any one of Items 16 to 19, wherein discharging the capacitor according to a sequence of discharge phases includes, for each discharge phase in the sequence of discharge phases: causing, by a controller, current from the capacitor to charge a parasitic capacitance of the first power transistor; discharging, by the controller, the parasitic capacitance of the first power transistor to charge a parasitic capacitance of the second power transistor; and discharging, by the controller, the parasitic capacitance of the second power transistor.

[0125] Item 21: A method according to Item 20, wherein discharging the capacitor according to a sequence of discharge phases includes, in response to both the first power transistor and the second power transistor being activated, causing, by a controller, for each discharge phase in the sequence of discharge phases, current to flow out of the capacitor across the first power transistor and the second power transistor.

[0126] Item 22: A system, comprising: a capacitor; a first power transistor including a first gate terminal; and a second power transistor including a second gate terminal. The second power transistor is connected in series with the first power transistor. The capacitor, the first power transistor, and the second power transistor are located on a discharge current path. The system further includes a controller configured to: control the first power transistor to perform a first sequence of switching cycles by applying a first gate voltage to the first gate terminal for each switching cycle in a first sequence of switching cycles, the first gate voltage exceeding a threshold gate voltage such that the first power transistor operates according to a non-linear transfer function; and control the second power transistor to perform a second sequence of switching cycles by applying a second gate voltage to the second gate terminal for each switching cycle in a second sequence of switching cycles, the second gate voltage exceeding a threshold gate voltage such that the second power transistor operates according to a non-linear transfer function. By controlling the first power transistor to perform the first sequence of switching cycles and controlling the second power transistor to perform the second sequence of switching cycles, the system is configured to discharge the capacitor according to a sequence of discharge phases via the discharge current path.

[0127] Clause 23: The system according to Clause 22 further includes: a first gate driver circuit; and a second gate driver circuit, wherein, in order to control the first power transistor to execute a first switching cycle sequence, the controller is configured to output a first control signal to the first gate driver circuit to cause the first gate driver circuit to execute the first switching cycle sequence, and wherein, in order to control the second power transistor to execute a second switching cycle sequence, the controller is configured to output a second control signal to the second gate driver circuit to cause the second gate driver circuit to execute the second switching cycle sequence.

[0128] The techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, aspects of the techniques described may be implemented within one or more processors, which include one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuitry, as well as any combination of such components. The term "processor" or "processing circuitry" may generally refer to any one of the foregoing logic circuitry or any other equivalent circuitry, either alone or in combination with other logic circuitry. A control unit including hardware may also perform one or more of the techniques of this disclosure.

[0129] Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various operations and functions described in this disclosure. Additionally, any of the units, modules, or components described may be implemented together or separately as discrete but interoperable logic devices. The depiction of different features as modules or units is intended to highlight different functional aspects and does not necessarily imply that such modules or units must be implemented by separate hardware or software components. Instead, the functionality associated with one or more modules or units may be performed by separate hardware or software components, or integrated within common or separate hardware or software components.

[0130] The techniques described in this disclosure may also be embodied or encoded in a computer-readable medium, such as a computer-readable storage medium, that contains instructions. For example, when executed, the instructions embedded or encoded in the computer-readable storage medium may cause a programmable processor or other processor to perform a method. The computer-readable storage medium may include RAM, ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), EEPROM, flash memory, a hard disk, a compact disc read-only memory (CD-ROM), a floppy disk, magnetic tape, magnetic media, optical media, or other computer-readable media.

[0131] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A circuit comprising: A first power transistor (122, 222) comprising a first gate terminal; as well as a second power transistor (124, 224) comprising a second gate terminal, the second power transistor (124, 224) being connected in series with the first power transistor (122, 222), wherein a capacitor, the first power transistor (122, 222) and the second power transistor (124, 224) are located in a discharge current path; and The controller (110, 210) is configured to: controlling the first power transistor (122, 222) to perform the first switching cycle sequence (310, 410, 510, 610) by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence (310, 410, 510, 610), the first gate voltage exceeding a threshold gate voltage causing the first power transistor (122, 222) to operate according to a nonlinear transfer function; controlling the second power transistor (124, 224) to perform the second switching cycle sequence (320, 420, 520, 620) by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence (320, 420, 520, 620), the second gate voltage exceeding the threshold gate voltage causing the second power transistor (124, 224) to operate according to the nonlinear transfer function; as well as The capacitor is discharged according to a discharge phase sequence via the discharge current path by controlling the first power transistor (122, 222) to perform the first switching cycle sequence (310, 410, 510, 610) and controlling the second power transistor (124, 224) to perform the second switching cycle sequence (320, 420, 520, 620).

2. The circuit according to claim 1, wherein in order to discharge the capacitor according to the discharge phase sequence, the controller (110, 210) is configured to cause current to flow from the capacitor via the discharge current path for each discharge phase in the discharge phase sequence.

3. The circuit according to any one of claims 1 to 2, wherein in order to discharge the capacitor according to the discharge phase sequence, the controller (110, 210) is configured to discharge the voltage of the capacitor from a first voltage value to a second voltage value, each discharge phase in the discharge phase sequence reducing the voltage of the capacitor until the voltage of the capacitor is equal to the second voltage value.

4. The circuit of claim 3, further comprising a voltage sensor (152, 252) configured to generate a voltage signal indicative of the voltage of the capacitor, and wherein the controller (110, 210) or the safety logic (150, 250) is configured to: Based on the voltage signal, determining that the voltage of the capacitor is equal to the second voltage value; Based on determining that the voltage of the capacitor is equal to the second voltage value, controlling the first power transistor (122, 222) to stop the first switching cycle sequence (310, 410, 510, 610); and Based on determining that the voltage of the capacitor is equal to the second voltage value, the second power transistor (124, 224) is controlled to stop the second switching cycle sequence (320, 420, 520, 620).

5. The circuit according to any one of claims 1 to 4, wherein the controller (110, 210) is configured to: When the time period has passed, controlling the first power transistor (122, 222) to stop the first switching cycle sequence (310, 410, 510, 610); and When the time period has elapsed, the second power transistor (124, 224) is controlled to stop the second switching cycle sequence (320, 420, 520, 620).

6. The circuit according to any one of claims 1 to 5, wherein in order to discharge the capacitor according to the discharge phase sequence, the controller (110, 210) is configured to, for each discharge phase in the discharge phase sequence: causing current to flow from the capacitor across the first power transistor (122, 222) and the second power transistor (124, 224) in response to both the first power transistor (122, 222) and the second power transistor (124, 224) being activated; and In response to one or both of the first power transistor (122, 222) and the second power transistor (124, 224) being disabled, current is prevented from flowing from the capacitor across the first power transistor (122, 222) and the second power transistor (124, 224).

7. The circuit according to any one of claims 1 to 6, wherein in order to discharge the capacitor according to the discharge phase sequence, the controller (110, 210) is configured to, for each discharge phase in the discharge phase sequence: allowing current from the capacitor to charge a parasitic capacitance of the first power transistor (122, 222); discharging the parasitic capacitance of the first power transistor (122, 222) to charge the parasitic capacitance of the second power transistor (124, 224); and The parasitic capacitance of the second power transistor (124, 224) is discharged.

8. The circuit of claim 7, wherein in order to discharge the capacitor according to the discharge phase sequence, the controller (110, 210) is further configured to cause current to flow from the capacitor across the first power transistor (122, 222) and the second power transistor (124, 224) for each discharge phase in the discharge phase sequence in response to both the first power transistor (122, 222) and the second power transistor (124, 224) being activated.

9. The circuit according to any one of claims 1 to 8, Each first switching cycle (310, 410, 510, 610) in the first switching cycle sequence (310, 410, 510, 610) includes a first activation phase and a first deactivation phase, wherein each second switching cycle (320, 420, 520, 620) in the second switching cycle sequence (320, 420, 520, 620) comprises a second activation phase and a second deactivation phase, and Each discharge phase in the discharge phase sequence corresponds to a combination of a first activation phase of a first switching cycle (310, 410, 510, 610) in the first switching cycle sequence (310, 410, 510, 610) and a second activation phase of a second switching cycle (320, 420, 520, 620) in the second switching cycle sequence (320, 420, 520, 620).

10. The circuit according to any one of claims 1 to 9, wherein the first switching cycle sequence (310, 410, 510, 610) includes a first plurality of short activation phases (314, 314A, 324, 324A) and a first plurality of long activation phases (312, 312A, 322, 322A) interleaved with the first plurality of short activation phases (314, 314A, 324, 324A), wherein the duration of each short activation phase (314, 314A, 324, 324A) in the first plurality of short activation phases (314, 314A, 324, 324A) is shorter than the duration of each long activation phase (312, 312A, 322, 322A) in the first plurality of long activation phases (312, 312A, 322, 322A), wherein the second switching cycle sequence (320, 420, 520, 620) comprises a second plurality of short activation phases (314, 314A, 324, 324A) and a second plurality of long activation phases (312, 312A, 322, 322A) interleaved with the second plurality of short activation phases (314, 314A, 324, 324A), wherein the duration of each short activation phase (314, 314A, 324, 324A) in the second plurality of short activation phases (314, 314A, 324, 324A) is shorter than the duration of each long activation phase (312, 312A, 322, 322A) in the second plurality of long activation phases (312, 312A, 322, 322A), and Each discharge phase in the discharge phase sequence corresponds to: an overlapping segment between a short activation phase (314, 314A, 324, 324A) of the first plurality of short activation phases (314, 314A, 324, 324A) and a long activation phase (312, 312A, 322, 322A) of the second plurality of long activation phases (312, 312A, 322, 322A); or An overlapping segment between a short activation phase (314, 314A, 324, 324A) of the second plurality of short activation phases (314, 314A, 324, 324A) and a long activation phase (312, 312A, 322, 322A) of the first plurality of long activation phases (312, 312A, 322, 322A).

11. The circuit according to any one of claims 1 to 10, wherein the first switching cycle sequence (310, 410, 510, 610) includes a first plurality of activation phases, wherein the second switching cycle sequence (320, 420, 520, 620) comprises a second plurality of activation phases interleaved with the first plurality of activation phases such that each activation phase of the second plurality of activation phases does not overlap with any of the first plurality of activation phases, and Each discharge phase in the discharge phase sequence corresponds to: a period of time after the start of an activation phase of the first plurality of activation phases; or A time period after initiation of an activation phase of the second plurality of activation phases.

12. The circuit according to any one of claims 1 to 11, wherein the first switching cycle sequence (310, 410, 510, 610) includes a first plurality of activation phases, each of the first plurality of activation phases ends in a first soft turn-off phase, wherein the first gate voltage decreases with the first soft turn-off phase, wherein the second switching cycle sequence (320, 420, 520, 620) includes a second plurality of activation phases, each of the second plurality of activation phases ends in a second soft turn-off phase, wherein the second gate voltage decreases with the second soft turn-off phase, and Each discharge phase in the discharge phase sequence corresponds to: An overlapping section between the first soft-off phase of an activation phase in the first plurality of activation phases and an activation phase in the second plurality of activation phases; or An overlapping section between the second soft-off phase of an activation phase in the second plurality of activation phases and an activation phase in the first plurality of activation phases.

13. The circuit according to any one of claims 1 to 12, wherein the controller (110, 210) is configured to: identifying one or more fault conditions that result in a discharge operation to discharge the capacitor; and The discharge operation is initiated based on identifying the one or more fault conditions, wherein the discharge operation includes the first power transistor (122, 222) performing the first switching cycle sequence (310, 410, 510, 610) and the second power transistor (124, 224) performing the second switching cycle sequence (320, 420, 520, 620).

14. The circuit according to any one of claims 1 to 13, wherein the controller (110, 210) is configured to: identifying one or more standard operating modes that result in a discharge operation to discharge the capacitor; and The discharge operation is initiated based on identifying the one or more standard operating modes, wherein the discharge operation includes the first power transistor (122, 222) performing the first switching cycle sequence (310, 410, 510, 610) and the second power transistor (124, 224) performing the second switching cycle sequence (320, 420, 520, 620).

15. The circuit of any one of claims 1 to 14, wherein the capacitor comprises a direct current (DC) link capacitor connected to an inverter circuit for an electric motor of a vehicle.

16. A method comprising: Controlling a first power transistor (122, 222) including the first gate terminal by a controller (110, 210) to perform the first switching cycle sequence (310, 410, 510, 610) by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence (310, 410, 510, 610), the first gate voltage exceeding a threshold gate voltage causing the first power transistor (122, 222) to operate according to a nonlinear transfer function; as well as The controller (110, 210) controls a second power transistor (124, 224) including the second gate terminal to perform the second switching cycle sequence (320, 420, 520, 620) by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence (320, 420, 520, 620), the second gate voltage exceeding the threshold gate voltage causing the second power transistor (124, 224) to operate according to the nonlinear transfer function, wherein the second power transistor (124, 224) is connected in series with the first power transistor (122, 222), and wherein a capacitor, the first power transistor (122, 222) and the second power transistor (124, 224) are located on a discharge current path; and The capacitor is discharged according to a discharge phase sequence via the discharge current path by controlling the first power transistor (122, 222) to perform the first switching cycle sequence (310, 410, 510, 610) and controlling the second power transistor (124, 224) to perform the second switching cycle sequence (320, 420, 520, 620). 17 . The method of claim 16 , wherein causing the capacitor to discharge according to the sequence of discharge phases comprises causing current to flow from the capacitor via the discharge current path for each discharge phase in the sequence of discharge phases.

18. The method of any one of claims 16 to 17, wherein discharging the capacitor according to the sequence of discharge phases comprises discharging the voltage of the capacitor from a first voltage value to a second voltage value, each discharge phase in the sequence of discharge phases reducing the voltage of the capacitor until the voltage of the capacitor is equal to the second voltage value.

19. The method according to any one of claims 16 to 18, wherein discharging the capacitor according to the sequence of discharge phases comprises, for each discharge phase in the sequence of discharge phases: causing, by the controller (110, 210), current to flow from the capacitor across the first power transistor (122, 222) and the second power transistor (124, 224) in response to both the first power transistor (122, 222) and the second power transistor (124, 224) being activated; and In response to one or both of the first power transistor (122, 222) and the second power transistor (124, 224) being disabled, current is prevented by the controller (110, 210) from flowing from the capacitor across the first power transistor (122, 222) and the second power transistor (124, 224).

20. The method according to any one of claims 16 to 19, wherein discharging the capacitor according to the sequence of discharge phases comprises, for each discharge phase in the sequence of discharge phases: The controller (110, 210) causes the current from the capacitor to charge the parasitic capacitance of the first power transistor (122, 222); Discharging the parasitic capacitance of the first power transistor (122, 222) by the controller (110, 210) to charge the parasitic capacitance of the second power transistor (124, 224); and The parasitic capacitance of the second power transistor (124, 224) is discharged by the controller (110, 210).

21. The method of claim 20, wherein causing the capacitor to discharge according to the discharge phase sequence comprises causing, by the controller (110, 210), current to flow from the capacitor across the first power transistor (122, 222) and the second power transistor (124, 224) for each discharge phase in the discharge phase sequence in response to both the first power transistor (122, 222) and the second power transistor (124, 224) being activated.

22. A system (100, 200, 700), comprising: Capacitors; A first power transistor (122, 222) comprising a first gate terminal; as well as a second power transistor (124, 224) comprising a second gate terminal, the second power transistor (124, 224) being connected in series with the first power transistor (122, 222), wherein the capacitor, the first power transistor (122, 222) and the second power transistor (124, 224) are located in a discharge current path; and The controller (110, 210) is configured to: controlling the first power transistor (122, 222) to perform the first switching cycle sequence (310, 410, 510, 610) by applying a first gate voltage to the first gate terminal for each switching cycle in the first switching cycle sequence (310, 410, 510, 610), the first gate voltage exceeding a threshold gate voltage causing the first power transistor (122, 222) to operate according to a nonlinear transfer function; controlling the second power transistor (124, 224) to perform the second switching cycle sequence (320, 420, 520, 620) by applying a second gate voltage to the second gate terminal for each switching cycle in the second switching cycle sequence (320, 420, 520, 620), the second gate voltage exceeding the threshold gate voltage causing the second power transistor (124, 224) to operate according to the nonlinear transfer function; as well as The first switching cycle sequence (310, 410, 510, 610) is executed by controlling the first power transistor (122, 222) and the second switching cycle sequence (320, 420, 520, 610) is executed by controlling the second power transistor (124, 224). 620) so that the capacitor is discharged via the discharge current path according to a discharge phase sequence.

23. The system (100, 200, 700) of claim 22, further comprising: a first gate driver circuit (132, 142, 242); as well as a second gate driver circuit (144, 244), wherein in order to control the first power transistor (122, 222) to execute the first switching cycle sequence (310, 410, 510, 610), the controller (110, 210) is configured to output a first control signal to the first gate driver circuit (132, 142, 242) so that the first gate driver circuit (132, 142, 242) executes the first switching cycle sequence (310, 410, 510, 610), and In order to control the second power transistor (124, 224) to execute the second switching cycle sequence (320, 420, 520, 620), the controller (110, 210) is configured to output a second control signal to the second gate driver circuit (144, 244) so ​​that the second gate driver circuit (144, 244) executes the second switching cycle sequence (320, 420, 520, 620).

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