Electric vehicle and motor controller thereof

Abstract

The invention discloses an electric vehicle and a motor controller thereof, the motor controller comprises a control circuit, an interlocking circuit and a driving circuit, the interlocking circuit is used for obtaining state signals of an upper bridge switch tube and a lower bridge switch tube, and outputting a first fault signal when the state signals represent that the upper bridge switch tube has a fault; and a second fault signal is output when the state signal represents that the lower bridge switch tube has a fault, the driving circuit comprises a first driving module and a second driving module, the first driving module is used for controlling the upper bridge switch tube to be disconnected when the second fault signal is received, and the second driving module is used for controlling the lower bridge switch tube to be disconnected when the first fault signal is received. In other words, when the lower bridge switch tube breaks down, the first driving module directly controls the upper bridge switch tube to be disconnected, and when the upper bridge switch tube breaks down, the second driving module directly controls the lower bridge switch tube to be disconnected, so that the two switch tubes of the same bridge arm are effectively prevented from being directly connected, and the reliability of the motor controller is improved.

Description

Technical Field

[0001] The present application relates to the technical field of vehicles, and particularly relates to an electric vehicle and its motor controller. Background Art

[0002] As one of the core components of an electric vehicle (electric two-wheeler, electric four-wheeler, and electric motorcycle), the motor controller has relatively high safety performance requirements. The core device of the motor controller is the IGBT (Insulated Gate Bipolar Transistor) power module. The IGBT power module will bear large electrical stresses during use and is prone to failure. Therefore, it is necessary to provide drive protection and fault protection for it. Currently, generally, interlock control is added to the drive side of the IGBT power module, that is, when the upper-bridge switch tube of the same bridge arm is driven to conduct, the lower-bridge switch tube is forced to turn off. However, if a short-circuit fault has occurred in the lower-bridge switch tube when the upper-bridge switch tube is driven, and the control chip fails to handle the short-circuit fault in time, if the upper-bridge switch tube is continuously driven to conduct at this time, there will be a risk of direct connection between the upper-bridge switch tube and the lower-bridge switch tube, resulting in low reliability of the IGBT power module. Summary of the Invention

[0003] In view of this, the present application provides an electric vehicle, and its motor controller can effectively prevent direct connection between two switch tubes of the same bridge arm, improving the reliability of the motor controller. The technical solution of the present application is as follows:

[0004] In a first aspect, the present application provides an electric vehicle, including a vehicle body and a power system. The power system is disposed on the vehicle body and includes a motor controller and a motor. The motor controller includes a series-connected upper-bridge switching tube and a lower-bridge switching tube, and the upper-bridge switching tube and the lower-bridge switching tube are used to drive the motor to operate. The motor controller further includes: a control circuit for outputting a first control signal and a second control signal; an interlock circuit for obtaining status signals of the upper-bridge switching tube and the lower-bridge switching tube, and outputting a first fault signal when the status signal indicates a fault of the upper-bridge switching tube, and outputting a second fault signal when the status signal indicates a fault of the lower-bridge switching tube; and a driving circuit including: a first driving module, the input end of the first driving module is connected to the control circuit and the interlock circuit to receive the first control signal and the second fault signal, and the output end of the first driving module is connected to the control end of the upper-bridge switching tube. The first driving module is configured to: when receiving the second fault signal, control the upper-bridge switching tube to turn off; when not receiving the second fault signal, drive the upper-bridge switching tube to turn on and off according to the first control signal; a second driving module, the input end of the second driving module is connected to the control circuit and the interlock circuit to receive the second control signal and the first fault signal, and the output end of the second driving module is connected to the control end of the lower-bridge switching tube. The second driving module is configured to: when receiving the first fault signal, control the lower-bridge switching tube to turn off; when not receiving the first fault signal, drive the lower-bridge switching tube to turn on and off according to the second control signal.

[0005] In a possible implementation manner of the first aspect, the interlock circuit is further connected to the control circuit to send the status signal to the control circuit, and the control circuit is further configured to: when the status signal indicates a fault of the upper-bridge switching tube or the lower-bridge switching tube, stop outputting the first control signal and the second control signal.

[0006] In a possible implementation manner of the first aspect, the interlock circuit includes: a first interlock module, the first interlock module is connected to the first driving module, the second driving module and the control circuit. The first interlock module is configured to obtain the first status signal of the upper-bridge switching tube through the first driving module and send the first status signal to the control circuit, and send the first fault signal to the second driving module when the first status signal indicates a fault of the upper-bridge switching tube; a second interlock module, the second interlock module is connected to the first driving module, the second driving module and the control circuit. The second interlock module is configured to obtain the second status signal of the lower-bridge switching tube through the second driving module and send the second status signal to the control circuit, and send the second fault signal to the first driving module when the second status signal indicates a fault of the lower-bridge switching tube.

[0007] In a possible implementation of the first aspect, the first interlock module includes a first switching transistor. The control terminal of the first switching transistor is connected to the first driving module to receive a first status signal. The first terminal of the first switching transistor is connected to a power supply terminal, and the second terminal of the first switching transistor is connected to the second driving module. When the first status signal indicates a fault of the upper-bridge switching transistor, the first switching transistor conducts to form a first fault signal at the second terminal of the first switching transistor. The second interlock module includes a second switching transistor. The control terminal of the second switching transistor is connected to the second driving module to receive a second status signal. The first terminal of the second switching transistor is connected to the power supply terminal, and the second terminal of the second switching transistor is connected to the first driving module. When the second status signal indicates a fault of the lower-bridge switching transistor, the second switching transistor conducts to form a second fault signal at the second terminal of the second switching transistor.

[0008] In a possible implementation of the first aspect, the status output terminal of the first driving module is connected to the control terminal of the first switching transistor and is used to send the first status signal. The first input terminal of the first driving module is used to connect to a control circuit to receive a first control signal. The second input terminal of the first driving module is used to connect to the second terminal of the second switching transistor to receive a second fault signal. The driving output terminal of the first driving module is used to connect to the control terminal of the upper-bridge switching transistor. The status output terminal of the second driving module is connected to the control terminal of the second switching transistor and is used to send the second status signal. The first input terminal of the second driving module is used to connect to the control circuit to receive a second control signal. The second input terminal of the second driving module is used to connect to the second terminal of the first switching transistor to receive a first fault signal. The driving output terminal of the second driving module is used to connect to the control terminal of the lower-bridge switching transistor.

[0009] Further, the first interlock module further includes a first pull-up resistor and a first pull-down resistor. The first pull-up resistor is connected between the power supply terminal and the status output terminal of the first driving module. One end of the first pull-down resistor is connected to the second input terminal of the second driving module, and the other end of the first pull-down resistor is grounded. The second interlock module further includes a second pull-up resistor and a second pull-down resistor. The second pull-up resistor is connected between the power supply terminal and the status output terminal of the second driving module. One end of the second pull-down resistor is connected to the second input terminal of the first driving module, and the other end of the second pull-down resistor is grounded.

[0010] In a possible implementation of the first aspect, the interlock circuit further includes a first diode and a second diode. The anode of the first diode is connected to the control circuit to receive a first control signal, and the cathode of the first diode is connected to the second terminal of the first switching transistor and the second input terminal of the second driving module. The anode of the second diode is connected to the control circuit to receive a second control signal, and the cathode of the second diode is connected to the second terminal of the second switching transistor and the second input terminal of the first driving module.

[0011] In a possible implementation of the first aspect, when the upper-bridge switching transistor fails, the first status signal output by the status output terminal of the first driving module is a low-level signal, the first switching transistor conducts, and the first fault signal formed at the second terminal of the first switching transistor is a high-level signal. The second driving module controls the lower-bridge switching transistor to turn off according to the first fault signal received by its second input terminal, and the control circuit stops outputting the first control signal and the second control signal according to the first status signal. When the lower-bridge switching transistor fails, the second status signal output by the status output terminal of the second driving module is a low-level signal, the second switching transistor conducts, and the second fault signal formed at the second terminal of the second switching transistor is a high-level signal. The first driving module controls the upper-bridge switching transistor to turn off according to the second fault signal received by its second input terminal, and the control circuit stops outputting the first control signal and the second control signal according to the second status signal.

[0012] In a second aspect, the present application further provides a motor controller. The motor controller includes an upper-bridge switching transistor and a lower-bridge switching transistor connected in series, and the upper-bridge switching transistor and the lower-bridge switching transistor are used to drive the motor to operate. The motor controller further includes: a control circuit for outputting a first control signal and a second control signal; an interlock circuit for obtaining the status signals of the upper-bridge switching transistor and the lower-bridge switching transistor, and outputting a first fault signal when the status signal indicates that the upper-bridge switching transistor fails, and outputting a second fault signal when the status signal indicates that the lower-bridge switching transistor fails; and a driving circuit including: a first driving module, the input terminal of the first driving module is connected to the control circuit and the interlock circuit to receive the first control signal and the second fault signal, and the output terminal of the first driving module is connected to the control terminal of the upper-bridge switching transistor. The first driving module is configured to: control the upper-bridge switching transistor to turn off when receiving the second fault signal; drive the upper-bridge switching transistor to turn on and off according to the first control signal when not receiving the second fault signal; a second driving module, the input terminal of the second driving module is connected to the control circuit and the interlock circuit to receive the second control signal and the first fault signal, and the output terminal of the second driving module is connected to the control terminal of the lower-bridge switching transistor. The second driving module is configured to: control the lower-bridge switching transistor to turn off when receiving the first fault signal; drive the lower-bridge switching transistor to turn on and off according to the second control signal when not receiving the first fault signal.

[0013] In a possible implementation of the second aspect, the interlock circuit is further connected to the control circuit to send the status signal to the control circuit, and the control circuit is further configured to: stop outputting the first control signal and the second control signal when the status signal indicates that the upper-bridge switching transistor fails or the lower-bridge switching transistor fails.

[0014] In the electric vehicle and motor controller of the present application, the motor controller includes a control circuit, an interlock circuit, and a drive circuit. The interlock circuit is used to obtain the status signals of the upper-bridge switching transistor and the lower-bridge switching transistor, and output a first fault signal when the status signal indicates a fault of the upper-bridge switching transistor, and output a second fault signal when the status signal indicates a fault of the lower-bridge switching transistor. The drive circuit includes a first drive module and a second drive module. The first drive module is used to control the upper-bridge switching transistor to turn off when receiving the second fault signal, and the second drive module is used to control the lower-bridge switching transistor to turn off when receiving the first fault signal. That is to say, when the lower-bridge switching transistor fails, the first drive module directly controls the upper-bridge switching transistor to turn off, and when the upper-bridge switching transistor fails, the second drive module directly controls the lower-bridge switching transistor to turn off. Thus, when one of the switching transistors fails, the other switching transistor is directly turned off through the interlock circuit and the drive circuit, effectively preventing the two switching transistors of the same bridge arm from being short-circuited and improving the reliability of the motor controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of the electric vehicle provided by the embodiment of the present application.

[0016] Figure 2 is a schematic diagram of the module of the motor controller provided by the embodiment of the present application.

[0017] Figure 3 is a schematic diagram of the module of the motor controller provided by another embodiment of the present application.

[0018] Figure 4 is a schematic diagram of the circuit principle of the motor controller provided by the embodiment of the present application.

[0019] DESCRIPTION OF THE MAIN ELEMENT SYMBOLS

[0020] Electric vehicle 100

[0021] Power system 10

[0022] Motor controller 110

[0023] Upper-bridge switching transistor Q1

[0024] Lower-bridge switching transistor Q2

[0025] Control circuit 111

[0026] Control chip U1

[0027] Interlock circuit 112

[0028] First interlock module 1120

[0029] First switch S1

[0030] First pull-up resistor R1

[0031] The first pull-down resistor R2

[0032] The first current-limiting resistor R5

[0033] The second interlock module 1121

[0034] The second switching transistor S2

[0035] The second pull-up resistor R3

[0036] The second pull-down resistor R4

[0037] The second current-limiting resistor R6

[0038] The first diode D1

[0039] The second diode D2

[0040] The driving circuit 113

[0041] The first driving module 1130

[0042] The second driving module 1131

[0043] The vehicle body 20 Detailed implementation manners

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0046] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0047] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0048] Please refer to Figure 1 and Figure 2, an electric vehicle 100 provided by an embodiment of the present application includes a power system 10 and a vehicle body 20. The power system 10 is disposed on the vehicle body 20, and the power system 10 includes a motor controller 110 and a motor (not shown in the figure). The motor controller 110 includes an upper bridge switching tube Q1 and a lower bridge switching tube Q2 connected in series, and the upper bridge switching tube Q1 and the lower bridge switching tube Q2 are used to drive the motor controller to work.

[0049] Among them, the motor controller 110 further includes a control circuit 111, an interlock circuit 112, and a drive circuit 113. The control circuit 111 is used to output a first control signal and a second control signal. It can be understood that the first control signal and the second control signal are PWM (Pulse Width Modulation) signals.

[0050] The interlock circuit 112 is used to obtain the status signals of the upper bridge switching tube Q1 and the lower bridge switching tube Q2, and output a first fault signal when the status signal indicates a fault of the upper bridge switching tube Q1, and output a second fault signal when the status signal indicates a fault of the lower bridge switching tube Q2.

[0051] The drive circuit 113 includes a first drive module 1130 and a second drive module 1131. The input end of the first drive module 1130 is connected to the control circuit 111 and the interlock circuit 112 to receive the first control signal and the second fault signal. The output end of the first drive module 1130 is connected to the control end of the upper bridge switching tube Q1. The first drive module 1130 is used to: when receiving the second fault signal, control the upper bridge switching tube Q1 to turn off; when not receiving the second fault signal, drive the upper bridge switching tube Q1 to turn on and off according to the first control signal. The input end of the second drive module 1131 is connected to the control circuit 111 and the interlock circuit 112 to receive the second control signal and the first fault signal. The output end of the second drive module 1131 is connected to the control end of the lower bridge switching tube Q2. The second drive module 1131 is used to: when receiving the first fault signal, control the lower bridge switching tube Q2 to turn off; when not receiving the first fault signal, drive the lower bridge switching tube Q2 to turn on and off according to the second control signal.

[0052] Based on this, when the lower bridge switching tube Q2 fails, the first drive module 1130 directly controls the upper bridge switching tube Q1 to turn off, and when the upper bridge switching tube Q1 fails, the second drive module 1131 directly controls the lower bridge switching tube Q2 to turn off. Thus, directly through the interlock circuit 112 and the drive circuit 113, when one of the switching tubes fails, the other switching tube is turned off, thereby effectively preventing the two switching tubes on the same bridge arm from being directly connected, and improving the reliability of the motor controller 110.

[0053] It can be understood that the motor controller 110 may include multiple bridge arms, each bridge arm includes an upper bridge switching transistor Q1 and a lower bridge switching transistor Q2 connected in series, and each bridge arm may be respectively provided with a corresponding control circuit 111, an interlock circuit 112, and a drive circuit 113. The upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 may be Insulated-Gate Bipolar Transistors (IGBTs).

[0054] In some embodiments, the interlock circuit 112 may obtain the status signals of the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 through a detection circuit (not shown in the figure). The detection circuit is used to detect whether the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 are faulty and output status signals according to the detection results. Among them, the detection circuit may respectively detect the voltage difference between the first end and the second end of the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2. When the voltage difference between the first end and the second end of the upper bridge switching transistor Q1 or the lower bridge switching transistor Q2 is greater than a preset threshold, it indicates that the upper bridge switching transistor Q1 or the lower bridge switching transistor Q2 is faulty. Specifically, the detection circuit respectively detects the voltage difference between the collector and the emitter of the upper bridge switching transistor Q1 and the voltage difference between the collector and the emitter of the lower bridge switching transistor Q2, and outputs corresponding status signals according to the detection results. Among them, the circuit for detecting the voltage difference between the first end and the second end of the switching transistor and comparing the voltage difference with the preset threshold is a prior art, and the present application does not limit the specific circuit form of the detection circuit.

[0055] As Figure 2 shown, the interlock circuit 112 may also be connected to the control circuit 111 to send status signals to the control circuit 111. The control circuit 111 may also be used to: when the status signal indicates that the upper bridge switching transistor Q1 is faulty or the lower bridge switching transistor Q2 is faulty, stop outputting the first control signal and the second control signal. That is to say, when the upper bridge switching transistor Q1 is faulty or the lower bridge switching transistor Q2 is faulty, the control circuit 111 no longer sends the first control signal and the second control signal to the first drive module 1130 and the second drive module 1131, thereby further preventing the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 from being directly connected.

[0056] It can be understood that since the status signal needs to be able to indicate that the upper bridge switching transistor Q1 is faulty and also be able to indicate that the lower bridge switching transistor Q2 is faulty, in some embodiments, the status signal may include a first status signal and a second status signal. The first status signal indicates the status of the upper bridge switching transistor Q1, and the second status signal indicates the status of the lower bridge switching transistor Q2, which is convenient for distinguishing whether it is the upper bridge switching transistor Q1 that is faulty or the lower bridge switching transistor Q2 that is faulty.

[0057] Please refer to Figure 3, in some embodiments, the interlock circuit 112 may include a first interlock module 1120 and a second interlock module 1121. The first interlock module 1120 is connected to the first drive module 1130, the second drive module 1131, and the control circuit 111. The first interlock module 1120 is configured to obtain a first status signal of the high-side switch Q1 through the first drive module 1130, send the first status signal to the control circuit 111, and send a first fault signal to the second drive module 1131 when the first status signal indicates a fault of the high-side switch Q1. The second interlock module 1121 is connected to the first drive module 1130, the second drive module 1131, and the control circuit 111. The second interlock module 1121 is configured to obtain a second status signal of the low-side switch Q2 through the second drive module 1131, send the second status signal to the control circuit 111, and send a second fault signal to the first drive module 1130 when the second status signal indicates a fault of the low-side switch Q2.

[0058] In this embodiment, the first drive module 1130 and the second drive module 1131 may be connected to a detection circuit (the same as the foregoing), and output a first status signal to the first interlock module 1120 according to the detection result, and output a second status signal to the second interlock module 1121 according to the detection result.

[0059] In some other embodiments, detection circuits (not shown in the figure) may be respectively integrated inside the first drive module 1130 and the second drive module 1131. The detection circuit inside the first drive module 1130 is configured to detect the voltage difference between the first end and the second end of the high-side switch Q1, compare whether the voltage difference is greater than a preset threshold, and output a first status signal according to the comparison result. When the voltage difference is greater than the threshold, the output first status signal indicates a fault of the high-side switch Q1. The detection circuit inside the second drive module 1131 is configured to detect the voltage difference between the first end and the second end of the low-side switch Q2, compare whether the voltage difference is greater than a preset threshold, and output a second status signal according to the comparison result. When the voltage difference is greater than the preset threshold, the output second status signal indicates a fault of the low-side switch Q2. Wherein, the detection circuit may include a detection module and a comparison module. The detection module is configured to detect the voltage difference between the first end and the second end of the switch tube, and the comparison module is configured to compare the voltage difference with the preset threshold. The preset threshold may be determined according to the characteristics of the high-side switch Q1 and the low-side switch Q2. For example, when the high-side switch Q1 and the low-side switch Q2 are IGBT transistors, the preset threshold may be set to the saturation voltage value of the IGBT transistor, such as 7V, 10V, etc.

[0060] Further, as Figure 4As shown, the first interlock module 1120 includes a first switching transistor S1. The control terminal of the first switching transistor S1 is connected to the first driving module 1130 to receive a first status signal. The first terminal of the first switching transistor S1 is connected to the power supply terminal VCC, and the second terminal of the first switching transistor S1 is connected to the second driving module 1131. When the first status signal indicates a fault in the upper-bridge switching transistor Q1, the first switching transistor S1 conducts to cause a first fault signal to be formed at the second terminal of the first switching transistor S1.

[0061] The second interlock module 1121 includes a second switching transistor S2. The control terminal of the second switching transistor S2 is connected to the second driving module 1131 to receive a second status signal. The first terminal of the second switching transistor S2 is connected to the power supply terminal VCC, and the second terminal of the second switching transistor S2 is connected to the first driving module 1130. When the second status signal indicates a fault in the lower-bridge switching transistor Q2, the second switching transistor S2 conducts to cause a second fault signal to be formed at the second terminal of the second switching transistor S2.

[0062] Specifically, the first status signal can represent the status of the upper-bridge switching transistor Q1 in different level states, and the second status signal can also represent the status of the lower-bridge switching transistor Q2 in different level states. For example, when the first status signal is at a low level, it indicates a fault in the upper-bridge switching transistor Q1. The low-level first status signal is provided to the control terminal of the first switching transistor S1, causing the first switching transistor S1 to conduct. As a result, the second terminal of the first switching transistor S1 is at a high level, that is, the first fault signal is a high-level signal. When the first status signal is at a high level or there is no signal, it indicates that the upper-bridge switching transistor Q1 has no fault. The high-level first status signal or no signal is provided to the control terminal of the first switching transistor S1, and the first switching transistor S1 is in an off state. Thus, the second terminal of the first switching transistor S1 is not at a high level, that is, the first interlock module 1120 does not output the first fault signal. Of course, in some other embodiments, it can also be that the first status signal being at a high level indicates a fault in the upper-bridge switching transistor Q1, and the first fault signal is a low-level signal.

[0063] When the second status signal is at a low level, it indicates a fault in the lower-bridge switching transistor Q2. The low-level second status signal is provided to the control terminal of the second switching transistor S2, causing the second switching transistor S2 to conduct. As a result, the second terminal of the second switching transistor S2 is at a high level, that is, the second fault signal is a high-level signal. When the second status signal is at a high level or there is no signal, it indicates that the lower-bridge switching transistor Q2 has no fault. The high-level second status signal or no signal is provided to the control terminal of the second switching transistor S2, and the second switching transistor S2 is in an off state. Thus, the second terminal of the second switching transistor S2 is not at a high level, that is, the second interlock module 1121 does not output the second fault signal. Of course, in some other embodiments, it can also be that the second status signal being at a high level indicates a fault in the lower-bridge switching transistor Q2, and the second fault signal is a low-level signal.

[0064] Among them, the first switching transistor S1 and the second switching transistor S2 can be PNP bipolar transistors, NPN bipolar transistors, PMOS transistors, NMOS transistors, and so on. The embodiments of the present application do not limit the specific device types of the first switching transistor S1 and the second switching transistor S2, as long as the first switching transistor S1 and the second switching transistor S2 can implement the corresponding functions.

[0065] Please continue to refer to Figure 4 , in some embodiments, both the first driving module 1130 and the second driving module 1131 may be provided with a status output terminal FLT, a first input terminal IN+, a second input terminal IN−, and a driving output terminal OUT.

[0066] The status output terminal FLT of the first driving module 1130 is connected to the control terminal of the first switching transistor S1 and is used to send a first status signal. The first input terminal IN+ of the first driving module 1130 is used to connect to the control circuit 111 to receive a first control signal. The second input terminal IN− of the first driving module 1130 is used to connect to the second terminal of the second switching transistor S2 to receive a second fault signal. The driving output terminal OUT of the first driving module 1130 is used to connect to the control terminal of the high-side switching transistor Q1.

[0067] The status output terminal FLT of the second driving module 1131 is connected to the control terminal of the second switching transistor S2 and is used to send a second status signal. The first input terminal IN+ of the second driving module 1131 is used to connect to the control circuit 111 to receive a second control signal. The second input terminal IN− of the second driving module 1131 is used to connect to the second terminal of the first switching transistor S1 to receive a first fault signal. The driving output terminal OUT of the second driving module 1131 is used to connect to the control terminal of the low-side switching transistor Q2.

[0068] That is to say, the first driving module 1130 obtains the status of the high-side switching transistor Q1 and outputs a first status signal through its status output terminal FLT according to the status of the high-side switching transistor Q1. The second driving module 1131 obtains the status of the low-side switching transistor Q2 and outputs a second status signal through its status output terminal FLT according to the status of the low-side switching transistor Q2.

[0069] The first driving module 1130 and the second driving module 1131 respectively control the on and off of the high-side switching transistor Q1 and the low-side switching transistor Q2 in combination with the signals of their respective first input terminals IN+ and second input terminals IN−.

[0070] Specifically, the first driving module 1130 and the second driving module 1131 can be driving optocouplers. When the second input terminal IN- of the driving optocoupler is at a high level, regardless of how the level of the first input terminal IN+ of the driving optocoupler changes, the driving output terminal OUT of the driving optocoupler outputs a signal for controlling the corresponding switching tube to turn off. When the second input terminal IN- of the driving optocoupler is at a low level, the driving output terminal OUT of the driving optocoupler outputs a signal for controlling the corresponding switching tube to turn on or off according to the signal of the first input terminal IN+. Among them, the detection circuit described above can be integrated inside the driving optocoupler, so that the first driving module 1130 can detect the voltage difference between the first end and the second end of the upper bridge switching tube Q1 and output a first status signal according to the voltage difference, and the second driving module 1131 can detect the voltage difference between the first end and the second end of the lower bridge switching tube Q2 and output a second status signal according to the voltage difference. When the upper bridge switching tube Q1 and the lower bridge switching tube Q2 are IGBT transistors, the detection circuits inside the first driving module 1130 and the second driving module 1131 can detect the saturation voltages of the upper bridge switching tube Q1 and the lower bridge switching tube Q2, and determine whether the upper bridge switching tube Q1 and the lower bridge switching tube Q2 are faulty according to the detected saturation voltages, and then output corresponding first status signals and second status signals.

[0071] It should be noted that the circuit for integrating the detection of the saturation voltage of the IGBY transistor inside the driving optocoupler is a prior art and will not be elaborated here.

[0072] Please refer to again Figure 4 In some embodiments, the first interlock module 1120 further includes a first pull-up resistor R1 and a first pull-down resistor R2. The first pull-up resistor R1 is connected between the power supply terminal VCC and the status output terminal FLT of the first driving module 1130. One end of the first pull-down resistor R2 is connected to the second input terminal IN- of the second driving module 1131, and the other end of the first pull-down resistor R2 is grounded. Thus, when the upper bridge switching tube Q1 is faulty, the first status signal output by the status output terminal FLT of the first driving module 1130 is at a low level. When the upper bridge switching tube Q1 is normal, the status output terminal FLT of the first driving module 1130 does not output a signal, and the status output terminal FLT of the first driving module 1130 is pulled high to a high level through the first pull-up resistor R1, so that the first status signal being at a high level indicates that the upper bridge switching tube Q1 is normal. Among them, both the first pull-up resistor R1 and the first pull-down resistor R2 can be set to at least one.

[0073] When the upper-bridge switching transistor Q1 fails, the first switching transistor S1 is turned on under the control of the first state signal at a low level. The second terminal of the first switching transistor S1 is at a high level, forming a first fault signal and inputting it to the second input terminal IN- of the second driving module 1131. When the upper-bridge switching transistor Q1 is normal, the first switching transistor S1 is turned off, and the second input terminal IN- of the second driving module 1131 is at a low level under the pulling-down action of the first pull-down resistor R2, that is, the second input terminal IN- of the second driving module 1131 does not receive the first fault signal.

[0074] Correspondingly, the second interlock module 1121 further includes a second pull-up resistor R3 and a second pull-down resistor R4. The second pull-up resistor R3 is connected between the power supply terminal VCC and the status output terminal FLT of the second driving module 1131. One end of the second pull-down resistor R4 is connected to the second input terminal IN- of the first driving module 1130, and the other end of the second pull-down resistor R4 is grounded. Thus, when the lower-bridge switching transistor Q2 fails, the second status signal output by the status output terminal FLT of the second driving module 1131 is at a low level. When the lower-bridge switching transistor Q2 is normal, the status output terminal FLT of the second driving module 1131 does not output a signal, and the status output terminal FLT of the second driving module 1131 is pulled up to a high level through the second pull-up resistor R3, so that when the second status signal is at a high level, it indicates that the lower-bridge switching transistor Q2 is normal. Among them, both the second pull-up resistor R3 and the second pull-down resistor R4 can be set to at least one.

[0075] When the lower-bridge switching transistor Q2 fails, the second switching transistor S2 is turned on under the control of the second state signal at a low level. The second terminal of the second switching transistor S2 is at a high level, forming a second fault signal and inputting it to the second input terminal IN- of the first driving module 1130. When the lower-bridge switching transistor Q2 is normal, the first switching transistor S1 is turned off, and the second input terminal IN- of the first driving module 1130 is at a low level under the pulling-down action of the second pull-down resistor R4, that is, the second input terminal IN- of the first driving module 1130 does not receive the second fault signal.

[0076] Further, the first interlock module 1120 may further include a first current-limiting resistor R5, and the second interlock module 1121 may further include a second current-limiting resistor R6. One end of the first current-limiting resistor R5 is connected to the end of the first pull-up resistor R1 far from the power supply terminal VCC, and the other end of the first current-limiting resistor R5 is connected to the status output terminal FLT of the first driving module 1130. One end of the second current-limiting resistor R6 is connected to the end of the second pull-up resistor R3 far from the power supply terminal VCC, and the other end of the second current-limiting resistor R6 is connected to the status output terminal FLT of the second driving module 1131.

[0077] Please continue to refer to Figure 4, in some embodiments, the control circuit 111 may include a control chip U1. The control chip U1 includes a first control output terminal IO1, a second control output terminal IO2, a first status input terminal IN1, and a second status input terminal IN2. The first control output terminal IO1 is connected to the first input terminal IN+ of the first driving module 1130. The first control output terminal IO1 is used to output a first control signal. The first status input terminal IN1 is connected to the control terminal of the first switching transistor S1 to receive a first status signal. The second control output terminal IO2 is connected to the first input terminal IN+ of the second driving module 1131. The second control output terminal IO2 is used to output a second control signal. The second status input terminal IN2 is connected to the control terminal of the second switching transistor S2 to receive a second status signal.

[0078] Furthermore, the interlock circuit 112 may further include a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the first control output terminal IO1. The cathode of the first diode D1 is connected to the second terminal of the first switching transistor S1 and the second input terminal IN- of the second driving module 1131. The anode of the second diode D2 is connected to the second control output terminal IO2. The cathode of the second diode D2 is connected to the second terminal of the second switching transistor S2 and the second input terminal IN- of the first driving module 1130. Thus, the first diode D1 can prevent the voltage signal of the power supply terminal VCC from flowing into the first control output terminal IO1 of the control chip U1 when the first switching transistor S1 is turned on. The second diode D2 can prevent the voltage signal of the power supply terminal VCC from flowing into the second control output terminal IO2 of the control chip U1 when the second switching transistor S2 is turned on, thereby preventing the control chip U1 from being damaged.

[0079] In addition, the first diode D1 and the second diode D2 can also achieve interlocking of control signals. When the first control output terminal IO1 of the control chip U1 outputs a first control signal for controlling the upper bridge switching transistor Q1 to conduct, the first control signal can be transmitted to the second input terminal IN- of the second driving module 1131 through the first diode D1. The second driving module 1131 controls the lower bridge switching transistor Q2 to turn off regardless of the signal input to its first input terminal IN+. When the second control output terminal IO2 of the control chip U1 outputs a second control signal for controlling the lower bridge switching transistor Q2 to conduct, the second control signal can be transmitted to the second input terminal IN- of the first driving module 1130 through the second diode D2. The first driving module 1130 controls the upper bridge switching transistor Q1 to turn off regardless of the signal input to its first input terminal IN+. Thus, when the control chip U1 has a problem and outputs a first control signal for controlling the upper bridge switching transistor Q1 to conduct and a second control signal for controlling the lower bridge switching transistor Q2 to conduct simultaneously, it can prevent the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 from conducting simultaneously.

[0080] As Figure 4 shown, the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 are IGBT transistors, the first switching transistor S1 and the second switching transistor S2 are PNP triodes, and the first driving module 1130 and the second driving module 1131 are driving optocouplers. The working process of the motor controller 110 will be described below by taking Figure 4 as an example:

[0081] When the upper bridge switching transistor Q1 fails, the state output terminal FLT of the first driving module 1130 outputs a low-level signal (the first state signal indicating the failure of the upper bridge switching transistor Q1) to the control terminal of the first switching transistor S1. The first switching transistor S1 conducts, and the second terminal of the first switching transistor S1 outputs a high-level signal (the first fault signal) to the second input terminal IN- of the second driving module 1131. According to the high-level signal at the second input terminal IN- of the second driving module 1131, the driving output terminal OUT of the second driving module 1131 outputs a low-level signal to turn off the lower bridge switching transistor Q2. At the same time, the first state input terminal IN1 of the control chip U1 can also receive a low-level signal, causing the first control output terminal IO1 and the second control output terminal IO2 to stop outputting the first control signal and the second control signal.

[0082] When the lower bridge switching transistor Q2 fails, the state output terminal FLT of the second driving module 1131 outputs a low-level signal (the second state signal indicating the failure of the lower bridge switching transistor Q2) to the control terminal of the second switching transistor S2. The second switching transistor S2 conducts, and the second terminal of the second switching transistor S2 outputs a high-level signal (the second fault signal) to the second input terminal IN- of the first driving module 1130. According to the high-level signal at the second input terminal IN- of the first driving module 1130, the driving output terminal OUT of the first driving module 1130 outputs a low-level signal to turn off the upper bridge switching transistor Q1. At the same time, the second state input terminal IN2 of the control chip U1 can also receive a low-level signal, causing the first control output terminal IO1 and the second control output terminal IO2 to stop outputting the first control signal and the second control signal.

[0083] Therefore, when the upper bridge switching transistor Q1 fails, the first driving module 1130 can turn off the lower bridge switching transistor Q2, and when the lower bridge switching transistor Q2 fails, the second driving module 1131 can turn off the upper bridge switching transistor Q1, preventing the upper bridge switching transistor Q1 and the lower bridge switching transistor Q2 from directly conducting due to the short-circuit fault of the upper bridge switching transistor Q1 or the short-circuit fault of the lower bridge switching transistor Q2.

[0084] When both the upper-bridge switching transistor Q1 and the lower-bridge switching transistor Q2 are normal, the status output terminals FLT of the first driving module 1130 and the second driving module 1131 do not output signals. However, the status output terminals FLT of the first driving module 1130 and the second driving module 1131 are pulled up to a high level through the first pull-up resistor R1 and the second pull-up resistor R3 respectively (the first status signal and the second status signal respectively indicate that the upper-bridge switching transistor Q1 and the lower-bridge switching transistor Q2 are normal), and the first status input terminal IN1 and the second status input terminal IN2 of the control chip U1 both receive high-level signals, so that the control chip U1 normally outputs the first control signal and the second control signal. The second input terminals IN- of the first driving module 1130 and the second driving module 1131 are pulled down to a low level through the first pull-down resistor R2 and the second pull-down resistor R4 respectively. Thus, the first driving module 1130 controls the on / off of the upper-bridge switching transistor Q1 according to the first control signal received by its first input terminal IN+, and the second driving module 1131 controls the on / off of the lower-bridge switching transistor Q2 according to the second control signal received by its first input terminal IN+.

[0085] Among them, the upper-bridge switching transistor Q1 and the lower-bridge switching transistor Q2 cannot be conducted simultaneously. The first control output terminal IO1 of the control chip U1 can be connected to the second input terminal IN- of the second driving module 1131 through the first diode D1, and the second control output terminal IO2 of the control chip U1 can be connected to the second input terminal IN- of the first driving module 1130 through the second diode D2. Thus, when the first control signal output by the control chip U1 is a high-level signal, the first driving module 1130 controls the upper-bridge switching transistor Q1 to conduct according to the first control signal, and the first control signal is also transmitted to the second input terminal IN- of the second driving module 1131. Whether the second control signal output by the control chip U1 is a high-level signal or a low-level signal, the second driving module 1131 controls the lower-bridge switching transistor Q2 to disconnect according to the high-level signal of its second input terminal IN-.

[0086] When the second control signal output by the control chip U1 is a high-level signal, the second driving module 1131 controls the lower-bridge switching transistor Q2 to conduct according to the second control signal, and the second control signal is also transmitted to the second input terminal IN- of the first driving module 1130. Whether the first control signal output by the control chip U1 is a high-level signal or a low-level signal, the first driving module 1130 controls the upper-bridge switching transistor Q1 to disconnect according to the high-level signal of its second input terminal IN-. Based on this, the interlock circuit 112 of the embodiment of the present application can also implement the interlock of the first control signal and the second control signal. When the first control signal controls the upper-bridge switching transistor Q1 to conduct, the second driving module 1131 forcibly disconnects the lower-bridge switching transistor Q2 according to the first control signal; when the second control signal controls the lower-bridge switching transistor Q2 to conduct, the first driving module 1130 controls the upper-bridge switching transistor Q1 to disconnect according to the second control signal.

[0087] In summary, the control circuit 111, the interlock circuit 112, and the drive circuit 113 in the motor controller 110 according to the embodiments of the present application can not only achieve fault interlock between the upper bridge switch tube Q1 and the lower bridge switch tube Q2, but also achieve interlock of control signals, effectively preventing the upper bridge switch tube Q1 and the lower bridge switch tube Q2 from conducting simultaneously, and improving the reliability of the motor controller 110.

[0088] The above embodiments are described in the preferred embodiment mode of the present application, and do not limit the scope of the present application. Without departing from the design spirit of the present application, various deformations and improvements made by those of ordinary skill in the art to the technical solution of the present application should fall within the protection scope determined by the claims of the present application.

Claims

1. An electric vehicle, comprising: a vehicle body; a power system, which is arranged on the vehicle body, the power system includes a motor controller and a motor, the motor controller includes a series-connected upper-bridge switching tube and a lower-bridge switching tube, and the upper-bridge switching tube and the lower-bridge switching tube are used to drive the motor to work; It is characterized in that the motor controller further includes: a control circuit, which is used to output a first control signal and a second control signal; an interlock circuit, which is used to obtain the state signals of the upper-bridge switching tube and the lower-bridge switching tube, and output a first fault signal when the state signal indicates a fault of the upper-bridge switching tube, and output a second fault signal when the state signal indicates a fault of the lower-bridge switching tube; and a drive circuit, the drive circuit includes: a first drive module, the input end of the first drive module is connected to the control circuit and the interlock circuit to receive the first control signal and the second fault signal, the output end of the first drive module is connected to the control end of the upper-bridge switching tube, and the first drive module is used for: when receiving the second fault signal, controlling the upper-bridge switching tube to turn off; when not receiving the second fault signal, driving the upper-bridge switching tube to turn on and off according to the first control signal; a second drive module, the input end of the second drive module is connected to the control circuit and the interlock circuit to receive the second control signal and the first fault signal, the output end of the second drive module is connected to the control end of the lower-bridge switching tube, and the second drive module is used for: when receiving the first fault signal, controlling the lower-bridge switching tube to turn off; when not receiving the first fault signal, driving the lower-bridge switching tube to turn on and off according to the second control signal.

2. The electric vehicle according to claim 1, characterized in that, The interlock circuit is further connected to the control circuit to send the state signal to the control circuit, and the control circuit is further used for: when the state signal indicates a fault of the upper-bridge switching tube or the lower-bridge switching tube, stopping outputting the first control signal and the second control signal.

3. The electric vehicle according to claim 2, characterized in that, The interlock circuit includes: a first interlock module, the first interlock module is connected to the first drive module, the second drive module and the control circuit, the first interlock module is used to obtain the first state signal of the upper-bridge switching tube through the first drive module and send the first state signal to the control circuit, and send the first fault signal to the second drive module when the first state signal indicates a fault of the upper-bridge switching tube; a second interlock module, the second interlock module is connected to the first drive module, the second drive module and the control circuit, the second interlock module is used to obtain the second state signal of the lower-bridge switching tube through the second drive module and send the second state signal to the control circuit, and send the second fault signal to the first drive module when the second state signal indicates a fault of the lower-bridge switching tube.

4. The electric vehicle according to claim 3, characterized in that, The first interlock module includes a first switching transistor. The control terminal of the first switching transistor is connected to the first driving module to receive the first status signal. The first terminal of the first switching transistor is connected to the power supply terminal, and the second terminal of the first switching transistor is connected to the second driving module. When the first status signal indicates a fault in the upper-bridge switching transistor, the first switching transistor is turned on so that the second terminal of the first switching transistor forms the first fault signal. The second interlock module includes a second switching transistor. The control terminal of the second switching transistor is connected to the second driving module to receive the second status signal. The first terminal of the second switching transistor is connected to the power supply terminal, and the second terminal of the second switching transistor is connected to the first driving module. When the second status signal indicates a fault in the lower-bridge switching transistor, the second switching transistor is turned on so that the second terminal of the second switching transistor forms the second fault signal.

5. The electric vehicle according to claim 4, wherein, The status output terminal of the first driving module is connected to the control terminal of the first switching transistor and is used to send the first status signal. The first input terminal of the first driving module is used to connect to the control circuit to receive the first control signal. The second input terminal of the first driving module is used to connect to the second terminal of the second switching transistor to receive the second fault signal. The driving output terminal of the first driving module is used to connect to the control terminal of the upper-bridge switching transistor. The status output terminal of the second driving module is connected to the control terminal of the second switching transistor and is used to send the second status signal. The first input terminal of the second driving module is used to connect to the control circuit to receive the second control signal. The second input terminal of the second driving module is used to connect to the second terminal of the first switching transistor to receive the first fault signal. The driving output terminal of the second driving module is used to connect to the control terminal of the lower-bridge switching transistor.

6. The electric vehicle according to claim 5, wherein, The first interlock module further includes a first pull-up resistor and a first pull-down resistor. The first pull-up resistor is connected between the power supply terminal and the status output terminal of the first driving module. One end of the first pull-down resistor is connected to the second input terminal of the second driving module, and the other end of the first pull-down resistor is grounded. The second interlock module further includes a second pull-up resistor and a second pull-down resistor. The second pull-up resistor is connected between the power supply terminal and the status output terminal of the second driving module. One end of the second pull-down resistor is connected to the second input terminal of the first driving module, and the other end of the second pull-down resistor is grounded.

7. The electric vehicle according to claim 5 or 6, characterized in that, The interlock circuit further includes a first diode and a second diode. The anode of the first diode is connected to the control circuit to receive the first control signal, and the cathode of the first diode is connected to the second terminal of the first switching transistor and the second input terminal of the second driving module. The anode of the second diode is connected to the control circuit to receive the second control signal, and the cathode of the second diode is connected to the second terminal of the second switching transistor and the second input terminal of the first driving module.

8. The electric vehicle according to claim 5 or 6, characterized in that, When the upper-bridge switching transistor fails, the first status signal output by the status output terminal of the first driving module is a low-level signal, the first switching transistor conducts, and the first fault signal formed at the second terminal of the first switching transistor is a high-level signal. The second driving module controls the lower-bridge switching transistor to turn off according to the first fault signal received by its second input terminal, and the control circuit stops outputting the first control signal and the second control signal according to the first status signal; When the lower-bridge switching transistor fails, the second status signal output by the status output terminal of the second driving module is a low-level signal, the second switching transistor conducts, and the second fault signal formed at the second terminal of the second switching transistor is a high-level signal. The first driving module controls the upper-bridge switching transistor to turn off according to the second fault signal received by its second input terminal, and the control circuit stops outputting the first control signal and the second control signal according to the second status signal.

9. A motor controller, which includes a series-connected upper-bridge switching transistor and a lower-bridge switching transistor, and the upper-bridge switching transistor and the lower-bridge switching transistor are used to drive a motor to operate; It is characterized in that The motor controller further includes: A control circuit, which is used to output a first control signal and a second control signal; An interlock circuit, which is used to obtain the status signals of the upper-bridge switching transistor and the lower-bridge switching transistor, and output a first fault signal when the status signals indicate that the upper-bridge switching transistor fails, and output a second fault signal when the status signals indicate that the lower-bridge switching transistor fails; and A driving circuit, which includes: A first driving module, the input terminal of the first driving module is connected to the control circuit and the interlock circuit to receive the first control signal and the second fault signal, the output terminal of the first driving module is connected to the control terminal of the upper-bridge switching transistor, and the first driving module is used to: when receiving the second fault signal, control the upper-bridge switching transistor to turn off; when not receiving the second fault signal, drive the upper-bridge switching transistor to turn on and off according to the first control signal; A second driving module, the input terminal of the second driving module is connected to the control circuit and the interlock circuit to receive the second control signal and the first fault signal, the output terminal of the second driving module is connected to the control terminal of the lower-bridge switching transistor, and the second driving module is used to: when receiving the first fault signal, control the lower-bridge switching transistor to turn off; when not receiving the first fault signal, drive the lower-bridge switching transistor to turn on and off according to the second control signal.

10. The motor controller according to claim 9, characterized in that, The interlock circuit is further connected to the control circuit to send the status signal to the control circuit, and the control circuit is further used to: when the status signal indicates that the upper-bridge switching transistor fails or the lower-bridge switching transistor fails, stop outputting the first control signal and the second control signal.

Images