Control device and micro-control circuit
By designing a control device containing multiple logic circuits and coupling the oscillation circuit, the problem of unstable clock signal output and susceptible to noise interference in the analog circuit is solved, and stable clock signal output and noise immunity are improved.
Patent Information
- Application Number
- CN202411701492.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-22
- Filing Date
- 2024-11-26
- Publication Date
- 2025-06-24
AI Technical Summary
The clock signal output by the analog circuit is unstable when it is turned on, and directly provided to the digital circuit may cause malfunction. The analog circuit is susceptible to noise interference or glitches, causing shutdown, and cannot provide a clock signal.
A control device is designed to couple the oscillation circuit, including a first output circuit, a synchronization circuit, a hysteresis circuit, a stabilization circuit and a second output circuit, and ensures the stability and reliability of the output clock signal through logic control such as enable signal, synchronization signal, a hysteresis signal and a transmission signal.
It effectively solves the problems of unstable clock signals and susceptible to noise interference, ensures that the digital circuit receives stable clock signals, avoids malfunctions, and improves the noise immunity and stability of the control device.
Smart Images
Figure CN120200587A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a control device and a micro-control circuit, and particularly to a control device for controlling an oscillation circuit. Background Art
[0002] Digital circuits require a clock signal as a driving source, and the clock signal is usually generated by an analog circuit. When the analog circuit is just turned on, the output clock signal is not very stable. If an unstable clock signal is directly provided to the digital circuit, it will cause the digital circuit to malfunction. Moreover, the analog circuit usually starts generating the clock signal according to a driving signal. When the driving signal is interfered by noise or has glitches, the analog circuit may be turned off and cannot provide the clock signal to the digital circuit properly. Summary of the Invention
[0003] An embodiment of this application provides a control device, coupled to an oscillation circuit, and includes a first output circuit, a synchronization circuit, a hysteresis circuit, a stabilization circuit, and a second output circuit. When an enable signal is at a first level, the first output circuit enables a driving signal. When a first clear signal is enabled, the first output circuit disables the driving signal. The synchronization circuit synchronizes the first enable signal to generate a synchronization signal. The synchronization signal is synchronized with an input clock. When the synchronization signal conforms to a first preset state, the hysteresis circuit enables the first clear signal. When the synchronization signal conforms to a second preset state, the hysteresis circuit enables a second clear signal. The stabilization circuit enables a transmission signal according to the input clock. When the transmission signal is enabled, the second output circuit uses the input clock as an output clock. When the second clear signal is enabled, the second output circuit stops using the input clock as the output clock. When the driving signal is enabled, the oscillation circuit provides the input clock. When the driving signal is disabled, the oscillation circuit stops providing the input clock.
[0004] The present application further provides a micro-control circuit, including an oscillation circuit and a control device. When a driving signal is enabled, the oscillation circuit provides an input clock. When the driving signal is disabled, the oscillation circuit stops providing the input clock. The control device is coupled to the oscillation circuit and includes a first output circuit, a synchronization circuit, a hysteresis circuit, a stabilization circuit, and a second output circuit. When an enable signal is at a first level, the first output circuit enables the driving signal. When a first clear signal is enabled, the first output circuit disables the driving signal. The synchronization circuit synchronizes the first enable signal to generate a synchronization signal. The synchronization signal is synchronized with the input clock. When the synchronization signal conforms to a first preset state, the hysteresis circuit enables the first clear signal. When the synchronization signal conforms to a second preset state, the hysteresis circuit enables a second clear signal. The stabilization circuit enables a transmission signal according to the input clock. When the transmission signal is enabled, the second output circuit uses the input clock as a first output clock. When the second clear signal is enabled, the second output circuit stops using the input clock as the first output clock. Description of the Drawings
[0005] Figure 1 It is a schematic diagram of the micro-control circuit of the present application.
[0006] Figure 2 It is a schematic diagram of the control device of the present application.
[0007] Figure 3 It is a schematic diagram of the architectures of the synchronization circuit, the hysteresis circuit, and the output circuit of the present application.
[0008] Figure 4 It is a schematic diagram of the architectures of the stabilization circuit and the output circuit of the present application.
[0009] Figure 5 It is a signal waveform diagram of the micro-control circuit of the present application when the enable signal is enabled.
[0010] Figure 6 It is a signal waveform diagram of the micro-control circuit of the present application when the enable signal is disabled.
[0011] Figure 7 It is a waveform diagram of the micro-control circuit of the present application when the enable signal has low glitches.
[0012] Symbol Explanation
[0013] 100: Micro-control circuit
[0014] 110: Control device
[0015] 120: Oscillation circuit
[0016] 130: Logic circuit
[0017] clk_en: Enable signal
[0018] en_latch: Drive signal
[0019] clk_in: Input clock
[0020] clk_out, clk_outn: Output clock
[0021] IP0_clk_req ~ IP2_clk_req: Clock requirement
[0022] 210: Stabilization circuit
[0023] 220, 250: Output circuit
[0024] 230: Synchronization circuit
[0025] 240: Hysteresis circuit
[0026] 260: Processing circuit
[0027] 261: Inverter
[0028] 262, 225, 226: Integrated clock gating circuit
[0029] stb_cnt_clr, en_latch_clr: Clear signal
[0030] clk_in_n_g: Gated clock signal
[0031] ST: Transfer signal
[0032] clk_in_n: Inverted signal
[0033] clk_en_hd1: Synchronization signal
[0034] icg_en: Control signal
[0035] DFF1 ~ DFF5: D-type flip-flop
[0036] clk_en_hd0, SO1 ~ SO3: Output signal
[0037] SPOR: Power-on reset signal
[0038] 241, 211: Counter
[0039] 242, 243, 215: Comparator
[0040] CV1, CV2: Count value
[0041] en_cnt_tar, en_cnt_tar - 1 preset value
[0042] cnt_tar: target value
[0043] 244, 223, 252: OR gate
[0044] 222, 255: AND gate
[0045] 245, 211: adder
[0046] 246, 247, 212, 213, 224: multiplexer
[0047] 261, 251, 254, 221: inverter
[0048] 510 - 550, 610 - 650, 710 - 730: time points
[0049] 660, 680: falling edge
[0050] 670: rising edge
[0051] 700: glitch Detailed implementation manners
[0052] To make the objectives, features, and advantages of this application more obvious and understandable, specific embodiments are given below and detailed descriptions are provided in conjunction with the accompanying drawings. This application specification provides different embodiments to illustrate the technical features of different implementation manners of this application. Among them, the configuration of each component in the embodiments is for illustrative purposes and is not intended to limit this application. In addition, the partial repetition of the figure reference numerals in the embodiments is for simplifying the description and does not imply the relevance between different embodiments.
[0053] Figure 1 It is a schematic diagram of the micro - control circuit of this application. As shown in the figure, the micro - control circuit 100 includes a control device 110 and an oscillation circuit 120. The control device 110 is coupled to the oscillation circuit 120 and generates a driving signal en_latch according to an enable signal clk_en (or the first enable signal). In a possible embodiment, when the enable signal clk_en is enabled, the control device 110 enables the driving signal en_latch, and when the enable signal clk_en is disabled, the control device 110 disables the driving signal en_latch.
[0054] In addition, the control device 110 generates an output clock clk_out based on an input clock clk_in. In a possible embodiment, after the input clock clk_in is stable, the control device 110 uses the input clock clk_in as the output clock clk_out. In another possible embodiment, the control device 110 uses the inverted signal of the input clock clk_in (not shown) as the output clock clk_out. The present application does not limit the number of output clocks. In some embodiments, the control device 110 further generates an output clock clk_outn. The phase of the output clock clk_outn is inverted relative to the output clock clk_out.
[0055] In other embodiments, when the enable signal clk_en is enabled, the control device 110 sets the output clock clk_out equal to the inverted signal of the input clock clk_in, and sets the output clock clk_outn equal to the input clock clk_in. In this example, when the enable signal clk_en is disabled, the control device 110 sets the output clocks clk_out and clk_outn to a specific level, such as a low level.
[0056] The oscillation circuit 120 generates the input clock clk_in according to the drive signal en_latch. For example, when the drive signal en_latch is enabled, the oscillation circuit 120 provides the input clock clk_in. When the drive signal en_latch is disabled, the provision of the input clock clk_in is stopped. In this embodiment, the drive signal en_latch provided by the control device 110 does not have glitches, so the oscillation circuit 120 will not malfunction due to glitches, such as stopping the generation of the input clock clk_in. The present application does not limit the architecture of the oscillation circuit 120. In a possible embodiment, the oscillation circuit 120 is a resistor-capacitor (RC) oscillator.
[0057] The present application does not limit the source of the enable signal clk_en. In other embodiments, the micro control circuit 100 further includes a logic circuit 130. The logic circuit 130 generates the enable signal clk_en according to the clock requirements IP0_clk_req, IP1_clk_req, and IP2_clk_req. For example, when one of the clock requirements IP0_clk_req, IP1_clk_req, and IP2_clk_req is enabled, the logic circuit 130 enables the enable signal clk_en. When the clock requirements IP0_clk_req, IP1_clk_req, and IP2_clk_req are all disabled, the logic circuit 130 disables the enable signal clk_en. The present application does not limit the architecture of the logic circuit 130. In a possible embodiment, the logic circuit 130 is an OR gate.
[0058] The present application does not limit the sources of the clock requirements IP0_clk_req, IP1_clk_req, and IP2_clk_req. In a possible embodiment, the clock requirements IP0_clk_req, IP1_clk_req, and IP2_clk_req are generated by different devices (IPs). For example, when a first specific device (not shown) needs to use the output clock clk_out, the first specific device enables the clock requirement IP0_clk_req. Therefore, the logic circuit 130 enables the enable signal clk_en, requesting the control device 110 to generate the output clock clk_out. In this example, when the first specific device does not need to use the output clock clk_out, the first specific device disables the clock requirement IP0_clk_req. At this time, if both the clock requirements IP1_clk_req and IP2_clk_req are disabled, the logic circuit 130 disables the enable signal clk_en. However, if the clock requirement IP1_clk_req or IP2_clk_req is enabled, it means that other specific devices need the output clock clk_out. Therefore, the logic circuit 130 continues to enable the enable signal clk_en.
[0059] Figure 2 It is a schematic diagram of the control device of the present application. As shown in the figure, the control device 110 includes a stabilization circuit 210, an output circuit 220, an output circuit 250, a synchronization circuit 230, and a hysteresis circuit 240. The stabilization circuit 210 adjusts a count value according to the input clock clk_in. When the count value reaches a target value, it indicates that the input clock clk_in is stable. Therefore, the stabilization circuit 210 notifies the output circuit 220. In some embodiments, if the target value is set lower, the output circuit 220 can provide the output clock clk_out to the external load faster. However, if the external load requires a more accurate output clock clk_out, the target value can be increased.
[0060] In this embodiment, the stabilization circuit 210 enables a transmission signal ST according to a clear signal stb_cnt_clr and a gated clock signal clk_in_n_g. In a possible embodiment, the stabilization circuit 210 performs a counting operation according to the gated clock signal clk_in_n_g. Since the gated clock signal clk_in_n_g is related to the input clock clk_in, it is equivalent to the stabilization circuit 210 performing a counting operation according to the input clock clk_in. When the count value of the stabilization circuit 210 reaches a target value, the stabilization circuit 210 enables the transmission signal ST to notify the output circuit 220 to provide the output clock clk_out. In a possible embodiment, when the clear signal stb_cnt_clr is enabled, it indicates that the enable signal clk_en is disabled. Therefore, the stabilization circuit 210 resets its own count value.
[0061] The output circuit 220 is used to provide the output clock clk_out. In other embodiments, the output circuit 220 further provides another output clock clk_outn. When the phase of the output clock clk_out is inverted with respect to the phase of the output clock clk_outn, the output clocks clk_out and clk_outn can be applied to devices that require positive and negative edge triggering.
[0062] In some embodiments, the output circuit 220 uses an inverted signal clk_in_n (or the first inverted signal) as the output clock clk_out and uses the input clock clk_in as the output clock clk_outn. In this example, the phase of the inverted signal clk_in_n is inverted with respect to the phase of the input clock clk_in. When the enable signal clk_en is disabled, the output clocks clk_out and clk_outn stay at the same level, such as a low level. For a retention D-type flip-flop with an advanced process, when the retention D-type flip-flop performs a restore operation, the clock terminal of the retention D-type flip-flop needs to be at a low level. Since the output clocks clk_out and clk_outn may both stay at a low level, the retention D-type flip-flop can be applied.
[0063] In this embodiment, the output circuit 220 receives a clear signal stb_cnt_clr, a gated clock signal clk_in_n_g, and a transfer signal ST. When the transfer signal ST is enabled, it indicates that the input clock clk_in has stabilized. Therefore, the output circuit 220 uses the inverted signal clk_in_n or the input clock clk_in as the output clock clk_out. When the clear signal stb_cnt_clr is enabled, it indicates that the enable signal clk_en is disabled. Therefore, the output circuit 220 stops using the inverted signal clk_in_n or the input clock clk_in as the output clock clk_out. At this time, the output clock clk_out may be at a low level.
[0064] In other embodiments, the output circuit 220 further provides an output clock clk_outn. When the transfer signal ST is enabled, the output circuit 220 uses the inverted signal clk_in_n as the output clock clk_out and the input clock clk_in as the output clock clk_outn. In another possible embodiment, when the transfer signal ST is enabled, the output circuit 220 uses the input clock clk_in as the output clock clk_out and the inverted signal clk_in_n as the output clock clk_outn.
[0065] The synchronization circuit 230 synchronizes the enable signal clk_en to generate a synchronization signal clk_en_hd1. The synchronization signal clk_en_hd1 is synchronized with the input clock clk_in. In some embodiments, the enable signal clk_en and the input clock clk_in may belong to different clock domains. When the control device 110 uses the enable signal clk_en and the input clock clk_in, since the transition time point of the enable signal clk_en may be very close to the transition time point of the input clock clk_in, the output clock clk_out may be in a metastable state. However, by means of the synchronization circuit 230, adjusting the level change time point of the enable signal clk_en so that the enable signal clk_en is synchronized with the input clock clk_in can avoid the output clock clk_out being in a metastable state.
[0066] In other embodiments, the control device 110 further includes a processing circuit 260. The processing circuit 260 may be integrated into the synchronization circuit 230 or independent of the synchronization circuit 230. The processing circuit 260 processes the input clock clk_in to generate an inverted signal clk_in_n (or a first inverted signal) and generates a gated clock signal clk_in_n_g according to a control signal icg_en.
[0067] In a possible embodiment, the processing circuit 260 includes an inverter 261 and an integrated clock gating cell 262. The inverter 261 inverts the input clock clk_in to generate an inverted signal clk_in_n. In a possible embodiment, the synchronization circuit 230 generates a synchronization signal clk_en_hd1 according to the input clock clk_in, the inverted signal clk_in_n, and the enable signal clk_en. In another possible embodiment, the inverter 261 can be omitted. When the inverter 261 is omitted, the synchronization circuit 230 generates a synchronization signal clk_en_hd1 according to the input clock clk_in and the enable signal clk_en.
[0068] The integrated clock gating cell 262 generates a gated clock signal clk_in_n_g according to the inverted signal clk_in_n and the control signal icg_en. When the inverter 261 is omitted, the integrated clock gating cell 262 generates a gated clock signal clk_in_n_g according to the input clock clk_in and the control signal icg_en.
[0069] Taking the inverted signal clk_in_n as an example, when the control signal icg_en is at a first level (such as a high level), the integrated clock gating cell 262 uses the inverted signal clk_in_n as the gated clock signal clk_in_n_g. When the control signal icg_en is at a second level (such as a low level), the integrated clock gating cell 262 sets the gated clock signal clk_in_n_g to the second level.
[0070] In this embodiment, the integrated clock gating cell 262 provides the gated clock signal clk_in_n_g to the stabilization circuit 210, the output circuit 220, the output circuit 250, and the hysteresis circuit 240. Therefore, the operations of the stabilization circuit 210, the output circuit 220, the output circuit 250, and the hysteresis circuit 240 are all synchronized with the input clock clk_in. Furthermore, when the input clock clk_in is stable, the integrated clock gating cell 262 may set the gated clock signal clk_in_n_g to the second level. Therefore, the stabilization circuit 210, the output circuit 220, the output circuit 250, and the hysteresis circuit 240 stop operating, reducing the power consumption of the control device 110. When the enable signal clk_en is disabled, the integrated clock gating cell 262 uses the inverted clk_in_n as the gated clock signal clk_in_n_g. Therefore, the stabilization circuit 210, the output circuit 220, the output circuit 250, and the hysteresis circuit 240 start operating.
[0071] The hysteresis circuit 240 is used to determine the duration for which the enable signal clk_en is disabled. When the duration for which the enable signal clk_en is disabled does not reach a preset value, it indicates that the enable signal clk_en has a short glitch or is affected by noise. Therefore, the hysteresis circuit 240 ignores the level change of the enable signal clk_en and treats the enable signal clk_en as still being enabled.
[0072] In addition, when a first specific device does not need to use the output clock clk_out, the first specific device may disable the clock request IP0_clk_req. At this time, the enable signal clk_en may be disabled. However, a second specific device may need to use the output clock clk_out, so the enable clock request IP1_clk_req is enabled. Therefore, the enable signal clk_en is immediately enabled. Since the duration for which the enable signal clk_en is disabled does not reach a preset value, the hysteresis circuit 240 still treats the enable signal clk_en as being enabled, does not require the output circuit 220 to stop providing the output clock clk_out, and does not require the output circuit 250 to disable the drive signal en_latch. Therefore, the output circuit 220 and the output circuit 250 are not frequently turned off. Furthermore, since it takes a certain amount of stabilization time for the output circuit 250 to provide the enable drive signal en_latch again after being turned off and then on, so that the output circuit 220 can provide the output clock clk_out again. If the output circuit 220 and the output circuit 250 are frequently switched on and off, it not only increases the power consumption of the control device 110, but also significantly reduces the efficiency of the external specific device (the device that requires the output clocks clk_out and clk_outn) due to the stable circuit 210 re - counting. Therefore, by appropriately adjusting the preset value, the benefits of power saving and high efficiency can be achieved.
[0073] In this embodiment, the hysteresis circuit 240 receives the synchronization signal clk_en_hd1 and the gated clock signal clk_in_n_g. When the synchronization signal clk_en_hd1 conforms to a first preset state, it indicates that the duration for which the enable signal clk_en is disabled has reached a preset value. Therefore, the hysteresis circuit 240 enables a clear signal en_latch_clr to reset the stable circuit 210 and requires the output circuit 220 to stop providing the output clocks clk_out and clk_outn. At this time, at least one of the output clocks clk_out and clk_outn is at a low level.
[0074] When the synchronization signal clk_en_hd1 conforms to a second preset state, the hysteresis circuit 240 enables another clear signal stb_cnt_clr. In this embodiment, the first preset state refers to the duration that the synchronization signal clk_en_hd1 maintains at a specific level (such as a low level) reaching a first preset value, and the second preset state refers to the duration that the synchronization signal clk_en_hd1 maintains at the specific level reaching a second preset value. In this example, the second preset value is less than the first preset value. Therefore, before the clear signal en_latch_clr is enabled, the clear signal stb_cnt_clr will be enabled first.
[0075] The output circuit 250 determines whether to enable the drive signal en_latch according to the enable signal clk_en. After the enabling is completed, the output circuit 250 determines whether to disable the drive signal en_latch according to the clear signal en_latch_clr. Therefore, since the clear signal en_latch_clr is synchronized with the input clock clk_in, the metastable state phenomenon caused by the clock domain crossing problem can be avoided.
[0076] In this embodiment, the output circuit 250 receives the enable signal clk_en, the clear signal en_latch_clr, and the gated clock signal clk_in_n_g. When the enable signal clk_en is at a specific level (such as a high level), the output circuit 250 enables the drive signal en_latch. When the clear signal en_latch_clr is enabled, the output circuit 250 disables the drive signal en_latch. In this embodiment, when the drive signal en_latch is enabled, it is not synchronized with the input clock clk_in, and when the drive signal en_latch is disabled, it is synchronized with the clear signal en_latch_clr and the input clock clk_in.
[0077] Figure 3Schematic diagram of the architecture of the synchronization circuit 230, hysteresis circuit 240, and output circuit 250 of the present application. In this embodiment, the synchronization circuit 230 includes D flip-flops DFF1 and DFF2. The input terminal D of the D flip-flop DFF1 receives the enable signal clk_en. The clock terminal CLK of the D flip-flop DFF1 receives the input clock clk_in. The output terminal Q of the D flip-flop DFF1 provides an output signal clk_en_hd0 (or the first output signal). The input terminal D of the D flip-flop DFF2 receives the output signal clk_en_hd0. The clock terminal CLK of the D flip-flop DFF2 receives the inverted signal clk_in_n. The output terminal Q of the D flip-flop DFF2 provides the synchronization signal clk_en_hd1. In some embodiments, since the clock terminal CLK of the D flip-flop DFF2 receives the inverted signal clk_in_n, the speed of synchronizing the enable signal clk_en by the synchronization circuit 230 can be increased.
[0078] In other embodiments, the reset terminals R of the D flip-flops DFF1 and DFF2 receive a power-on reset signal SPOR. When the power-on reset signal SPOR is at a low level, the D flip-flop DFF1 resets the output signal clk_en_hd0, and the D flip-flop DFF2 resets the synchronization signal clk_en_hd1. At this time, both the output signal clk_en_hd0 and the synchronization signal clk_en_hd1 may be at a low level.
[0079] The hysteresis circuit 240 includes a counter 241, a comparator 242, and a comparator 243. The counter 241 adjusts a count value CV1 according to the gated clock signal clk_in_n_g. The comparator 243 determines whether the count value CV1 reaches a preset value en_cnt_tar (or the first preset value). When the count value CV1 reaches the preset value en_cnt_tar, the comparator 243 enables the clear signal en_latch_clr. The comparator 242 determines whether the count value CV1 reaches a preset value en_cnt_tar - 1 (or the second preset value). When the count value CV1 reaches the preset value en_cnt_tar - 1, the comparator 242 enables the clear signal stb_cnt_clr. In this embodiment, the preset value en_cnt_tar - 1 is less than the preset value en_cnt_tar.
[0080] In other embodiments, the hysteresis circuit 240 further includes an OR gate 244, an adder 245, multiplexers 246 and 247. The OR gate 244 provides a selection signal SS1 (or a first selection signal) according to the clear signal stb_cnt_clr and the synchronization signal clk_en_hd1. The adder 245 adds the count value CV1 to a preset value (such as the value 1) to generate an adjusted value AV1. The multiplexer 246 outputs the count value CV1 or the adjusted value AV1 according to an enable signal clk_outn_en (or a third enable signal).
[0081] The multiplexer 247 outputs the output of the multiplexer 246 or outputs an initial value (such as the value 0) to the counter 241 according to the selection signal SS1. The counter 241 sets the count value CV1 according to the output of the multiplexer 247. For example, when the multiplexer 247 outputs the output of the multiplexer 246, the counter 241 sets the count value CV1 equal to the output of the multiplexer 246. When the multiplexer 247 outputs the initial value, the counter 241 sets the count value CV1 equal to the initial value.
[0082] The output circuit 250 includes a D flip-flop DFF3, an inverter 251 and an OR gate 252. The input terminal D of the D flip-flop DFF3 receives an output signal SO1 (or a second output signal). The clock terminal of the D flip-flop DFF3 receives the gated clock signal clk_in_n_g. The output terminal Q of the D flip-flop DFF3 provides a drive signal en_latch. The set terminal S of the D flip-flop DFF3 receives an output signal SO2 (or a third output signal). In other embodiments, the reset terminal R of the D flip-flop DFF3 receives a power-on reset signal SPOR. When the power-on reset signal SPOR is at a low level, the D flip-flop DFF3 resets the drive signal en_latch to a low level.
[0083] The inverter 251 (or a third inverter) inverts the enable signal clk_en to generate an inverted signal SIV1 (or a third inverted signal). The OR gate 252 generates the output signal SO2 according to the inverted signal SIV1 and the drive signal en_latch. In some embodiments, the output circuit 250 further includes a delay element 253. The delay element 253 delays the drive signal en_latch to allow sufficient time for the D flip-flop DFF3 to enable the drive signal en_latch. In this example, the OR gate 252 generates the output signal SO2 according to the output of the delay element 253 and the inverted signal SIV1. When the output signal SO2 is at a low level, the D flip-flop DFF3 is allowed to enable the drive signal en_latch.
[0084] In other embodiments, the output circuit 250 further includes an inverter 254 and an AND gate 255. The inverter 254 inverts the clear signal en_latch_clr to generate an inverted signal SIV2 (or the second inverted signal). The AND gate 255 generates an output signal SO1 based on the inverted signal SIV2 and the drive signal en_latch. When the output signal SO1 is at a low level and the level of the gated clock signal clk_in_n_g changes (such as from a low level to a high level), the D flip-flop DFF3 sets the drive signal en_latch to a low level (equivalent to disabling the drive signal en_latch).
[0085] When the drive signal en_latch is enabled, the oscillation circuit 120 has not provided a stable input clock clk_in, so the D flip-flop DFF3 is allowed to operate according to an asynchronous signal (such as clk_en). However, after the oscillation circuit 120 provides a stable input clock clk_in, the D flip-flop DFF3 disables the drive signal en_latch through a synchronous signal (such as en_latch_clr). Therefore, cross-domain clocking (CDC) problems can be avoided.
[0086] In addition, the output circuit 250 disables the drive signal en_latch according to the clear signal en_latch_clr of the hysteresis circuit 240, and the hysteresis circuit 240 enables the clear signal en_latch_clr only when the duration for which the enable signal clk_en remains at a low level conforms to a first preset state, so high-level glitches on the enable signal clk_en can be prevented from erroneously disabling the drive signal en_latch.
[0087] In other embodiments, after the output circuit 250 enables the drive signal en_latch, the integrated clock gating circuit 262 sets the gated clock signal clk_in_n_g to a low level. Therefore, the hysteresis circuit 240 pauses the counting operation, and the output circuit 250 does not disable the drive signal en_latch temporarily, so the power consumption of the control device 110 can be reduced.
[0088] Figure 4Schematic diagram of the architecture of the stabilization circuit 210 and the output circuit 220 of the present application. In this embodiment, the stabilization circuit 210 includes an adder 211, a multiplexer 212, a multiplexer 213, a counter 214, and a comparator 215. The adder 211 adds the count value CV2 to a preset value (such as the value 1) to generate an adjustment value AV2. The multiplexer 212 outputs the adjustment value AV2 or the count value CV2 according to the transmission signal ST. The multiplexer 213 outputs the output of the multiplexer 212 or outputs an initial value (such as the value 0) to the counter 214 according to the clear signal stb_cnt_clr. The counter 214 uses the output of the multiplexer 213 as the count value CV2 according to the gated clock signal clk_in_n_g. For example, when the multiplexer 213 outputs the output of the multiplexer 212, the counter 214 sets the count value CV2 equal to the output of the multiplexer 212. When the multiplexer 213 outputs the initial value, the counter 214 sets the count value CV2 equal to the initial value.
[0089] The comparator 215 compares the count value CV2 with a target value cnt_tar. In a possible embodiment, when the count value CV2 reaches the target value cnt_tar, the comparator 215 enables the transmission signal ST, such as setting the transmission signal ST to a high level. In this example, when the count value CV2 does not reach the target value cnt_tar, the comparator 215 disables the transmission signal ST, such as setting the transmission signal ST to a low level.
[0090] The output circuit 220 includes an inverter 221, an AND gate 222, an OR gate 223, a multiplexer 224, a D-type flip-flop DFF4, and an integrated clock gating circuit 225. The inverter 221 inverts the clear signal stb_cnt_clr to generate an inverted signal SIV3 (or the fourth inverted signal). The AND gate 222 generates an output signal SO3 (or the fifth output signal) according to the transmission signal ST and the inverted signal SIV3. The OR gate 223 generates a selection signal SS2 (or the second selection signal) according to the transmission signal ST and the clear signal stb_cnt_clr. The multiplexer 224 outputs the enable signal clk_out_en (or the second enable signal) or the output signal SO3 according to the selection signal SS2.
[0091] The input terminal D of the D flip-flop DFF4 receives the output of the multiplexer 224 (or the fourth output signal). The clock terminal of the D flip-flop DFF4 receives the gated clock signal clk_in_n_g. The output terminal Q of the D flip-flop DFF4 provides the enable signal clk_out_en. In some embodiments, the reset terminal (not shown) of the D flip-flop DFF4 receives the power-on reset signal SPOR. When the power-on reset signal SPOR is at a low level, the D flip-flop DFF4 resets the enable signal clk_out_en to a low level.
[0092] The integrated clock gating circuit 225 determines whether to use the inverted signal clk_in_n as the output clock clk_out according to the enable signal clk_out_en. For example, when the enable signal clk_out_en is at a high level, the integrated clock gating circuit 225 uses the inverted signal clk_in_n as the output clock clk_out. When the enable signal clk_out_en is at a low level, the integrated clock gating circuit 225 stops using the inverted signal clk_in_n as the output clock clk_out. At this time, the integrated clock gating circuit 225 sets the output clock clk_out to a low level.
[0093] In other embodiments, the output circuit 220 further includes a D flip-flop DFF5 and an integrated clock gating circuit 226. The input terminal D of the D flip-flop DFF5 receives the enable signal clk_out_en. The inverted clock terminal of the D flip-flop DFF5 receives the gated clock signal clk_in_n_g. The output terminal Q of the D flip-flop DFF5 provides the enable signal clk_outn_en. In some embodiments, the reset terminal (not shown) of the D flip-flop DFF5 receives the power-on reset signal SPOR. When the power-on reset signal SPOR is at a low level, the D flip-flop DFF5 resets the enable signal clk_outn_en to a low level.
[0094] The integrated clock gating circuit 226 determines whether to use the input clock clk_in as the output clock clk_outn according to the enable signal clk_outn_en. Since the operation of the integrated clock gating circuit 226 is similar to that of the integrated clock gating circuit 225, it will not be described in detail.
[0095] After the output circuit 220 generates the output clocks clk_out and clk_outn, the integrated clock gating circuit 262 sets the gated clock signal clk_in_n_g to a low level. Therefore, the stable circuit 210 pauses the counting operation, and the D flip-flops DFF4 and DFF5 of the output circuit 250 do not change the enable signals clk_out_en and clk_outn_en, so the power consumption can be saved and the purpose of power saving can be achieved.
[0096] Figure 5 This is the signal waveform diagram of the micro - control circuit of the present application when the enable signal clk_en is enabled. At time point 510, the enable signal clk_en is enabled to a high level, so the output circuit 250 enables the drive signal en_latch to a high level. Therefore, at time point 520, the oscillation circuit 120 starts to generate the input clock clk_in.
[0097] At time point 530, since the control signal icg_en is at a high level, the integrated clock gating circuit 262 of the processing circuit 260 uses the inverted signal clk_in_n as the gated clock signal clk_in_n_g. Therefore, the stabilization circuit 210 starts to count.
[0098] At time point 540, the count value CV2 of the stabilization circuit 210 reaches the target value cnt_tar, so the transfer enable signal ST is enabled. The D - type flip - flop DFF4 of the output circuit 220 provides a high - level enable signal clk_out_en.
[0099] At time point 550, the output circuit 220 uses the inverted signal clk_in_n as the output clock clk_out. Therefore, the phase of the output clock clk_out is inverted with respect to the input clock clk_in. At this time, the D - type flip - flop DFF5 of the output circuit 220 sets the enable signal clk_outn_en to a high level. Therefore, after half a cycle of the input clock clk_in, the output circuit 220 uses the input clock clk_in as the output clock clk_outn.
[0100] Figure 6 This is the signal waveform diagram of the micro - control circuit of the present application when the enable signal clk_en is disabled. Before time point 610, the enable signal clk_en is at a high level, so the output circuit 250 enables the drive signal en_latch, causing the oscillation circuit 120 to generate the input clock clk_in. At time point 610, the enable signal clk_en is disabled, changing from a high level to a low level.
[0101] At time point 620, since the control signal icg_en is at a high level, the hysteresis circuit 240 starts to count. Assume that the first preset value en_cnt_tar is the value 3, and the second preset value en_cnt_tar - 1 is the value 2 (i.e., the first preset value minus 1). At time point 630, the count value CV1 of the hysteresis circuit 240 is the value 2, reaching the preset value en_cnt_tar - 1, so the clear signal stb_cnt_clr is enabled. Therefore, the D - type flip - flop DFF4 of the output circuit 220 sets the enable signal clk_out_en to a low level.
[0102] At time point 640, the output circuit 220 stops providing the output clock clk_out and sets the output clock clk_out to a low level. At this time, the enable signal clk_outn_en of the output circuit 220 is at a low level.
[0103] At time point 650, the output circuit 220 stops providing the output clock clk_outn and sets the output clock clk_outn to a low level. At this time, the count value of the hysteresis circuit 240 is the value 3, reaching the preset value en_cnt_tar. Therefore, the clear signal en_latch_clr is enabled. The output circuit 250 sets the drive signal en_latch to a low level. In this embodiment, since the output circuit 250 sets the drive signal en_latch to a low level when the phase of the input clock clk_in changes from a high level to a low level (i.e., the falling edge 660), to prevent a high glitch from occurring in the drive signal en_latch. In this embodiment, the output clocks clk_out, clk_outn, and the drive signal en_latch are turned off (disabled) in sequence.
[0104] Figure 7 This is the waveform diagram when the microcontrol circuit of this application encounters a low glitch in the enable signal clk_en. At time point 710, the enable signal clk_en has a low glitch 700. Therefore, the output signal clk_en_hd0 of the synchronization circuit 230 is at a low level. After half a cycle, the synchronization signal clk_en_hd1 changes from a high level to a low level.
[0105] At time point 720, since the enable signal clk_outn_en is at a high level, the hysteresis circuit 240 starts counting. At time point 730, since the synchronization signal clk_en_hd1 is at a high level, the hysteresis circuit 240 stops counting and resets the count value. Since the count value CV1 of the hysteresis circuit 240 does not reach the preset value en_cnt_tar, the hysteresis circuit 240 disables the clear signal en_latch_clr. Therefore, the output circuit 250 continues to enable the drive signal en_latch, and the output circuit 220 continues to provide the output clocks clk_out and clk_outn. By using the hysteresis circuit 240 to judge the duration during which the enable signal clk_en is disabled, it is possible to prevent the output circuit 250 from being frequently turned on and off, greatly improving the efficiency of the microcontrol circuit 100.
[0106] It must be understood that when an element is referred to as being “coupled” to another element, it can be directly coupled or connected to the other element, or there can be other elements intervening therebetween. Conversely, when an element is “connected” to another element, there are no other elements intervening therebetween. Additionally, “enable” shall mean changing the state of a Boolean signal. The Boolean signal can be enabled to be high or have a higher voltage, and the Boolean signal can be enabled to be low or have a lower voltage at the discretion of the circuit designer. Similarly, “disable” shall mean changing the state of the Boolean signal to a voltage level opposite to the enabled state.
[0107] Unless otherwise defined, all terms herein (including technical and scientific terms) shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application pertains. Additionally, unless explicitly stated, the definitions of terms in an ordinary dictionary shall be interpreted as being consistent with their meanings in the context of the articles of their relevant technical fields, and shall not be interpreted in an idealized or overly formal sense. Although terms such as “first,” “second,” etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
[0108] Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person of ordinary skill in the art to which this application pertains, without departing from the spirit and scope of the present application, may make some modifications and refinements. For example, the systems, devices, or methods described in the embodiments of the present application can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present application shall be determined by the scope defined by the claims.
Claims
1. A control device coupled to an oscillating circuit, characterized in that: include: a first output circuit, which enables a driving signal when a first enable signal is at a first level, and disables the driving signal when a first clear signal is enabled; a synchronization circuit, synchronizing the first enable signal to generate a synchronization signal, wherein the synchronization signal is synchronized with an input clock; a hysteresis circuit, which enables the first clear signal when the synchronization signal meets a first preset state, and enables a second clear signal when the synchronization signal meets a second preset state; a stabilization circuit, enabling a transmission signal according to the input clock; as well as a second output circuit, which uses the input clock as a first output clock when the transfer signal is enabled, and stops using the input clock as the first output clock when the second clear signal is enabled, When the driving signal is enabled, the oscillation circuit provides the input clock, and when the driving signal is disabled, the oscillation circuit stops providing the input clock.
2. The control device according to claim 1, characterized in that The synchronization circuit comprises: A first D-type flip-flop, comprising: a first input terminal, receiving the first enable signal; a first output terminal, providing a first output signal; a first clock terminal, receiving the input clock; A second D-type flip-flop, comprising: a second input terminal, receiving the first output signal; a second output terminal, providing the synchronization signal; A second clock terminal, receiving a first inverted signal; a first inverter, inverting the input clock to generate the first inverted signal; A first integrated clock gating circuit determines whether to use the first inverted signal as a gated clock signal according to a control signal.
3. The control device according to claim 2, characterized in that The first output circuit comprises: A third D-type flip-flop, comprising: a third input terminal, receiving a second output signal; a third output terminal, providing the driving signal; a third clock terminal, receiving the gated clock signal; A setting terminal, receiving a third output signal; a second inverter, inverting the first clear signal to generate a second inverted signal; A first AND gate generates the second output signal according to the second inverted signal and the driving signal.
4. The control device according to claim 3, characterized in that: The first output circuit further comprises: a third inverter, inverting the first enable signal to generate a third inverted signal; a delayer, delaying the driving signal to generate a delayed signal; and A first OR gate generates the third output signal according to the third inverted signal and the delayed signal.
5. The control device according to claim 3, characterized in that: The second output circuit comprises: A fourth D-type flip-flop, comprising: a fourth input terminal, receiving a fourth output signal; a fourth output terminal, providing a second enable signal; a fourth clock terminal, receiving the gated clock signal; a fourth inverter, inverting the second clear signal to generate a fourth inverted signal; a second AND gate, generating a fifth output signal according to the transmission signal and the fourth inverted signal; a second OR gate, generating a selection signal according to the transmission signal and the second clear signal; a multiplexer, which uses the second enable signal or the fifth output signal as the fourth output signal according to the selection signal; and A second integrated clock gating circuit determines whether to use the first inverted signal as the first output clock according to the second enable signal.
6. A microcontroller circuit, characterized in that: include: an oscillator circuit, which provides an input clock when a driving signal is enabled, and stops providing the input clock when the driving signal is disabled; as well as A control device, coupled to the oscillation circuit, comprising: a first output circuit, which enables the driving signal when a first enable signal is at a first level, and disables the driving signal when a first clear signal is enabled; a synchronization circuit, synchronizing the first enable signal to generate a synchronization signal, wherein the synchronization signal is synchronized with the input clock; a hysteresis circuit, which enables the first clear signal when the synchronization signal meets a first preset state, and enables a second clear signal when the synchronization signal meets a second preset state; a stabilization circuit, enabling a transmission signal according to the input clock; and a second output circuit that uses the input clock as a first output clock when the transfer signal is enabled, and stops using the input clock as the first output clock when the second clear signal is enabled.
7. The microcontroller circuit according to claim 6, characterized in that: Also includes: a first inverter, inverting the input clock to generate a first inverted signal; and a first integrated clock gating circuit, which uses the first inverted signal as a gated clock signal when a control signal is at the first level, and sets the gated clock signal to the second level when the control signal is at a second level, The first integrated clock gating circuit provides the gated clock signal to the hysteresis circuit, the first output circuit, the stabilization circuit and the second output circuit.
8. The microcontroller circuit according to claim 7, characterized in that: The hysteresis circuit comprises: a counter, adjusting a count value according to the gated clock signal; a first comparator, for determining whether the count value reaches a first preset value, and enabling the first clear signal when the count value reaches the first preset value; a second comparator, for determining whether the count value reaches a second preset value, and enabling the second clear signal when the count value reaches the second preset value; The first preset value is greater than the second preset value.
9. The microcontroller circuit according to claim 8, characterized in that: The hysteresis circuit further comprises: an adder, adding the count value and a preset value to generate an adjustment value; a first multiplexer, outputting the count value or the adjustment value according to a third enable signal; a second multiplexer, outputting the output of the first multiplexer or outputting an initial value to the counter according to a first selection signal; a first OR gate, providing the first selection signal according to the first clear signal and the synchronization signal, in: When the second multiplexer outputs the output of the first multiplexer, the counter sets the count value equal to the output of the first multiplexer, When the second multiplexer outputs the initial value, the counter sets the count value equal to the initial value.
10. The microcontroller circuit according to claim 9, characterized in that: The synchronization circuit comprises: A first D-type flip-flop, comprising: a first input terminal, receiving the first enable signal; a first output terminal, providing a first output signal; a first clock terminal, receiving the input clock; A second D-type flip-flop, comprising: a second input terminal, receiving the first output signal; a second output terminal, providing the synchronization signal; A second clock terminal receives the first inverted signal.