Phase locked loop device and method of operating same

Abstract

A phase-locked loop device and a method for operating the same, comprising: a voltage-controlled oscillator configured to generate an output clock signal; a phase splitter configured to split the output clock signal into a first phase split signal; a sampling phase frequency detector configured to: receive a first power supply voltage, a second power supply voltage different from the first power supply voltage, and the first phase split signal, and output a holding voltage and a state signal for a phase difference based on determining that the phase difference between the first phase split signal and a reference clock signal corresponds to a first interval; a transconductance circuit configured to output a first conversion current based on the holding voltage; a charge pump configured to output a second conversion current based on the state signal; and a loop filter configured to provide the voltage control signal to the voltage controlled oscillator.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Korean Patent Application No. 10 - 2023 - 0190072, filed with the Korean Intellectual Property Office on December 22, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a phase - locked loop device and a method of operating the same. Background art

[0004] In the field of fifth - generation (5G) communication technology, there is an increasing demand for phase - locked loops (PLLs) with high data rate (HDR) and high - performance jitter cancellation specifications.

[0005] Generally, for a PLL including a charge pump, it may be difficult to achieve the fast frequency and jitter specifications required by the 5G standard.

[0006] Some methods for achieving the fast frequency and jitter specifications required by the 5G standard may use a sampling PLL, such as a sub - sampling PLL.

[0007] However, in the case of a sampling PLL, the locking range for achieving phase - locking may be relatively narrow, making it difficult to achieve stable phase - locking.

[0008] To ensure a fixed range, in addition to the main loop, a separate loop (such as a frequency - locked loop) may be added to the sampling PLL, which may lead to difficulties in reducing manufacturing costs and achieving integration. Summary of the invention

[0009] A phase - locked loop device and an operation method are provided that ensure a wide fixed range using only the main loop.

[0010] A phase - locked loop device and an operation method are also provided that ensure a proportional gain within a wide range using only the main loop.

[0011] Other aspects will be partially set forth in the following description, will become partially apparent from the description, or may be learned by practice of the presented embodiments.

[0012] According to one aspect of the present disclosure, a phase-locked loop device includes: a voltage-controlled oscillator configured to generate an output clock signal; a phase splitter configured to split the output clock signal into a first phase-divided signal; a sampling phase frequency detector configured to: receive a first power supply voltage, a second power supply voltage different from the first power supply voltage, and the first phase-divided signal, and based on determining that the phase difference between the first phase-divided signal and a reference clock signal corresponds to a first interval, output a holding voltage based on the first power supply voltage or the second power supply voltage, and output a status signal for the phase difference; a transconductance circuit configured to output a first conversion current based on the holding voltage; a charge pump configured to output a second conversion current based on the status signal; and a loop filter configured to provide a voltage control signal corresponding to the first conversion current and the second conversion current to the voltage-controlled oscillator.

[0013] According to one aspect of the present disclosure, a method for operating a phase-locked loop device includes: receiving a reference clock signal and a first phase-divided signal phase-split from an output clock signal; generating a holding voltage based on the phase difference between the first phase-divided signal and the reference clock signal; generating a first conversion current based on the holding voltage; generating a status signal based on whether the phase difference is included within a predetermined interval; generating a second conversion current based on the status signal; providing a voltage control signal based on the conversion current including the first conversion current and the second conversion current; and providing an output clock signal based on the voltage control signal.

[0014] According to one aspect of the present disclosure, a phase-locked loop device includes: a first circuit including: a first flip-flop configured to output a first latch signal as a first selection signal based on a first adjustment clock signal, wherein the phase of the first adjustment clock signal is adjusted according to a reference clock signal; a second flip-flop configured to output a second latch signal as a second selection signal based on a second adjustment clock signal, wherein the phase of the second adjustment clock signal is adjusted according to the reference clock signal; a first AND gate configured to perform an AND operation on the first latch signal and the first selection signal to output a first status signal; a second AND gate configured to perform an AND operation on the second latch signal and the second selection signal to output a second status signal; and a negative OR (NOR) gate configured to perform a NOR operation on the first selection signal and the second selection signal to output a third selection signal; a second circuit including: a sampling phase detection circuit configured to provide a sampling voltage to a holding node based on the third selection signal; an upper switch configured to provide a first power supply voltage to the holding node based on the first selection signal; and a lower switch configured to provide a second power supply voltage different from the first power supply voltage to the holding node based on the second selection signal; and a charge pump configured to output at least a part of a conversion current based on the first status signal and the second status signal. Description of the Drawings

[0015] In the following description with reference to the accompanying drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent, where:

[0016] Figure 1 is a block diagram showing a phase-locked loop device according to an embodiment.

[0017] Figure 2 is a block diagram showing a sampling phase frequency detector according to an embodiment of the present disclosure.

[0018] Figure 3 is a circuit diagram showing a first circuit included in the sampling phase frequency detector according to an embodiment.

[0019] Figure 4 is a circuit diagram showing a second circuit included in the sampling phase frequency detector according to an embodiment.

[0020] Figure 5 is a circuit diagram showing a third circuit included in the sampling phase frequency detector according to an embodiment.

[0021] Figure 6 is a timing diagram of signals that occur in the phase-locked state according to an embodiment.

[0022] Figure 7 and Figure 8 is a timing diagram of signals that occur in the phase-advance state according to an embodiment.

[0023] Figure 9 and Figure 10 is a timing diagram of signals that occur in the phase-lag state according to an embodiment.

[0024] Figure 11 is a diagram showing a transconductance circuit according to an embodiment.

[0025] Figure 12 is a characteristic diagram showing the conversion current versus the phase difference according to an embodiment.

[0026] Figure 13 is a flowchart showing a method of operating a phase-locked loop device according to an embodiment.

[0027] Figure 14 is a flowchart showing the steps of generating a holding voltage at a holding node according to an embodiment.

[0028] Figure 15 is a block diagram showing a phase-locked loop device according to an embodiment.

[0029] Figure 16 is showing Figure 15 a diagram of the transconductance circuit and the pulse generator shown.

[0030] Figure 17 is a block diagram showing a wireless communication system according to an embodiment. Detailed Description

[0031] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure.

[0032] Embodiments of the present disclosure may be implemented in many different forms and are not limited to the embodiments described herein.

[0033] To clearly explain the present disclosure, parts irrelevant to the description are omitted, and throughout the specification, the same or similar components are assigned the same reference numerals.

[0034] In addition, throughout the disclosure, when a component is referred to as "including" a certain component, it means that it may also include other components, rather than excluding other components, unless there is a contrary specific statement.

[0035] In addition, specific numbers described in the claims, even if explicitly cited in the claims, should not be construed as limiting the specific numbers that do not have such a reference in the claims.

[0036] For example, phrases such as "at least one" and "one or more" may be included in subsequent dependent claims to aid understanding.

[0037] However, the use of such phrases should not be construed as a limitation described by the indefinite article "a" for the purpose of example.

[0038] In addition, in the case of using a convention such as "at least one of A, B, or C", those skilled in the art will well understand such phrases (i.e., "a system including at least one of A, B, or C" includes the meanings of only A, only B, only C, A and B, A and C, B and C, and / or A, B, and C together, but is not limited to any one concept).

[0039] Alternatively, letters and / or phrases having two or more separate alternative terms in the specification, claims, or drawings should be considered to possibly include one term, one of the terms, or both terms.

[0040] For example, the phrase "A or B" should be understood to include the possibilities of "A", "B", or "A and B".

[0041] Figure 1 is a block diagram showing a phase-locked loop device according to an embodiment.

[0042] Reference Figure 1, in an embodiment, the phase-locked loop device 1 may be implemented as an integrated circuit manufactured by a semiconductor process, and in an embodiment, at least one semiconductor package includes the integrated circuit and may be included in a circuit board on which the semiconductor package is mounted.

[0043] The phase-locked loop device 1 may be referred to as a phase-locked loop or a phase-locked loop circuit.

[0044] The phase-locked loop device 1 may output an output clock signal CLK_OUT based on a reference clock signal CLK_REF.

[0045] The reference clock signal CLK_REF may oscillate at a constant frequency and may be generated by, for example, a crystal oscillator.

[0046] The phase-locked loop device 1 may generate an output clock signal CLK_OUT having a target frequency used by a functional block. For example, the functional block may be included in a processor (not shown) and perform its own function, and the operation of the functional block may be controlled by a processor (not shown). In some embodiments, the functional block may include a memory controller, a display controller, a graphics processing unit (GPU), an image signal processor, a multi-format codec block, and the like.

[0047] The functional block may process signals based on the output clock signal CLK_OUT, the signal processing speed of the functional block may depend on the frequency of the output clock signal CLK_OUT, and the jitter of the output clock signal CLK_OUT may limit the high-speed operation of the functional block.

[0048] Therefore, the phase-locked loop device 1 may generate a jitter-reduced output clock signal CLK_OUT by blocking the influence of noise that causes jitter.

[0049] The phase-locked loop device 1 may include a sampling phase frequency detector 10 (shown as "SPFD"), a transconductance circuit 20 (shown as "GM circuit"), a charge pump 30, a loop filter 50, a voltage-controlled oscillator 60, and a phase splitter 70.

[0050] The sampling phase frequency detector 10 may receive the reference clock signal CLK_REF from an external source (e.g., from outside the phase-locked loop device 1).

[0051] The sampling phase frequency detector 10 may receive a first phase division signal and a second phase division signal PH2 from the phase splitter 70.

[0052] The first phase division signal PH1 and the second phase division signal PH2 may be referred to as a feedback signal CLK_FB.

[0053] In some embodiments, the first phase - divided signal PH1 may be a signal for sampling a specific voltage in the sampling phase - frequency detector 10.

[0054] In some embodiments, the second phase - divided signal PH2 may be a signal for providing the voltage sampled by the sampling phase - frequency detector 10 as the holding voltage Vhold.

[0055] The phase difference between the first phase - divided signal PH1 and the second phase - divided signal PH2 may be constant.

[0056] In some embodiments, the sampling phase - frequency detector 10 may detect the phase difference between the reference clock signal CLK_REF and the first phase - divided signal PH1, may generate a holding voltage Vhold corresponding to the detected phase difference, and may generate a first status signal UP_SS and a second status signal DN_SS.

[0057] According to an embodiment, the holding voltage Vhold and the first status signal UP_SS and the second status signal DN_SS may be examples of detection signals based on the phase difference output from the sampling phase - frequency detector 10.

[0058] In an embodiment, the sampling phase - frequency detector 10 may sample the voltage generated by the reference clock signal CLK_REF at a specific node based on the first phase - divided signal PH1.

[0059] The sampled voltage may be referred to as a sampling voltage.

[0060] In some embodiments, the sampling may be performed between a first power supply voltage (e.g., Figure 3 shown as Vdd) and a second power supply voltage (e.g., Figure 3 shown as Vss).

[0061] Based on the falling edge of the first phase - divided signal PH1, the sampling phase - frequency detector 10 may sample the voltage between the first power supply voltage and the second power supply voltage.

[0062] The sampling phase - frequency detector 10 may output one of the sampling voltage, the first power supply voltage, and the second power supply voltage as a detection signal based on the second phase - divided signal PH2.

[0063] In some embodiments, the voltage level of the second power supply voltage may be lower than the voltage level of the first power supply voltage.

[0064] The second power supply voltage may be, for example, a ground voltage.

[0065] The sampling phase frequency detector 10 can detect any one of a sampling voltage, a first power supply voltage, and a second power supply voltage according to the degree of the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1, and can output the detected voltage as a detection signal.

[0066] For example, based on the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 being included in a first phase interval (which may be a specific phase interval), the sampling phase frequency detector 10 can output the sampling voltage as a detection signal.

[0067] Based on the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 being included in a second phase interval different from the first phase interval, the sampling phase frequency detector 10 can output the first power supply voltage as a detection signal.

[0068] Based on the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 being included in a third phase interval different from the first phase interval and the second phase interval, the sampling phase frequency detector 10 can output the second power supply voltage as a detection signal.

[0069] In an embodiment, the sampling phase frequency detector 10 can output a first status signal UP_SS and a second status signal DN_SS according to a phase interval including the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1.

[0070] In some embodiments, the sampling phase frequency detector 10 can operate based on the phase difference between the reference clock signal CLK_REF and a first inverted division signal PH1b in which the first phase division signal PH1 is inverted.

[0071] Based on the phase difference between the reference clock signal CLK_REF and the first inverted division signal PH1b being included within a predetermined phase interval, the sampling phase frequency detector 10 may not output the first status signal UP_SS and the second status signal DN_SS.

[0072] In addition, based on the phase difference being included in a phase interval other than the predetermined phase interval, the sampling phase frequency detector 10 can output the first status signal UP_SS and the second status signal DN_SS.

[0073] In some embodiments, the first status signal UP_SS and the second status signal DN_SS can be output in the form of pulse signals.

[0074] The pulse widths of the first state signal UP_SS and the second state signal DN_SS can correspond to the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1.

[0075] For example, as the phase difference between the first phase division signal PH1 and the reference clock signal CLK_REF increases, the pulse widths of the first state signal UP_SS and the second state signal DN_SS can also increase.

[0076] In some embodiments, the first state signal UP_SS can be referred to as the up selection signal, and the second state signal DN_SS can be referred to as the down selection signal.

[0077] Depending on the lead and lag states between the reference clock signal CLK_REF and the first phase division signal PH1, one of the first state signal UP_SS and the second state signal DN_SS can be output.

[0078] For example, based on determining that the first phase division signal PH1 leads the reference clock signal CLK_REF, the sampling phase frequency detector 10 can output the second state signal DN_SS in the form of a pulse signal, and when the second state signal DN_SS is output, the first state signal UP_SS can be maintained at a constant level.

[0079] As another example, based on determining that the first phase division signal PH1 lags the reference clock signal CLK_REF, the sampling phase frequency detector 10 can output the first state signal UP_SS in the form of a pulse signal, and when the first state signal UP_SS is output, the second state signal DN_SS can be maintained at a constant level.

[0080] The transconductance circuit 20 can convert the holding voltage Vhold into a first conversion current Icp1.

[0081] The transconductance circuit 20 can be referred to as the GM circuit.

[0082] The transconductance circuit 20 can adjust the direction and amplitude of the first conversion current Icp1 according to the difference between the holding voltage and the reference voltage Vref.

[0083] A detailed description of an example of the transconductance circuit 20 is given in the following description of Figure 11 of.

[0084] The charge pump 30 can generate a second conversion current Icp2 based on the first state signal UP_SS and the second state signal DN_SS.

[0085] In some embodiments, the charge pump 30 may provide the current output from the current source as a second conversion current Icp2 to the output terminal based on a first status signal UP_SS and a second status signal DN_SS, or the second conversion current Icp2 may flow from the output terminal to the ground terminal.

[0086] In some embodiments, the charge pump 30 may adjust the direction and magnitude of the second conversion current Icp2 according to the types and pulse widths of the input status signals UP_SS and DN_SS.

[0087] In an embodiment, when the first status signal UP_SS is input, the charge pump 30 may operate to input the second conversion current Icp2 into the loop filter 50. In an embodiment, this may be referred to as the second conversion current Icp2 flowing in the forward or bidirectional (positive) direction.

[0088] In addition, when the second status signal DN_SS is input, the charge pump 30 may operate to output the second conversion current Icp2 from the loop filter 50. In an embodiment, this may refer to the direction in which the second conversion current Icp2 flows being the reverse or backward direction.

[0089] In some embodiments, the charge pump 30 may output the second conversion current Icp2 according to the pulse widths of the first status signal UP_SS and the second status signal DN_SS.

[0090] As an example, the charge pump 30 receives the first status signal UP_SS, and as the pulse width of the provided first status signal UP_SS increases, the magnitude of the output second conversion current Icp2 may also increase.

[0091] In some embodiments, the pulse width of the first status signal UP_SS may correspond to the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1, and the magnitude of the second conversion current Icp2 may linearly increase as the pulse width of the first status signal UP_SS increases.

[0092] As an example, the charge pump 30 may receive the second status signal DN_SS, and as the pulse width of the provided second status signal DN_SS increases, the magnitude of the output second conversion current Icp2 may also increase.

[0093] In some embodiments, the pulse width of the second status signal DN_SS may correspond to the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1, and the magnitude of the second conversion current Icp2 may linearly increase as the pulse width of the second status signal DN_SS increases.

[0094] The loop filter 50 can generate a voltage control signal VCTRL based on the conversion current Icp, and the conversion current Icp can be the sum of a first conversion current Icp1 and a second conversion current Icp2. The loop filter 50 can generate the voltage control signal VCTRL so as to output it to the voltage controlled oscillator 60.

[0095] In an embodiment, the loop filter 50 can be implemented as a low-pass filter, but the embodiment is not limited thereto.

[0096] The voltage controlled oscillator 60 can generate an output clock signal CLK_OUT based on the voltage control signal VCTRL.

[0097] The generated output clock signal CLK_OUT can be output to the outside of the phase-locked loop device 1 and can be provided to the phase splitter 70.

[0098] In some embodiments, the voltage controlled oscillator 60 can generate an output clock signal CLK_OUT having a frequency adjusted based on the voltage control signal VCTRL within the voltage variable range of the input voltage control signal VCTRL.

[0099] According to the frequency adjustment of the output clock signal CLK_OUT, the waveform and phase of the output clock signal CLK_OUT can be changed, and the waveform and phase of the first phase-divided signal PH1 obtained by phase division can be changed accordingly.

[0100] In some embodiments, the voltage controlled oscillator 60 can perform frequency adjustment on the output clock signal CLK_OUT until the output clock signal CLK_OUT is phase-locked.

[0101] The phase splitter 70 can receive the output clock signal CLK_OUT.

[0102] The phase splitter 70 can divide the output clock signal CLK_OUT into a first phase-divided signal PH1 and a second phase-divided signal PH2.

[0103] In some embodiments, the first phase-divided signal PH1 and the second phase-divided signal PH2 can be signals obtained by dividing the frequency of the output clock signal CLK_OUT by M according to a desired division ratio (where M is a natural number greater than or equal to one (“1”)). The frequencies of the first phase-divided signal PH1 and the second phase-divided signal PH2 can be closer to the frequency of the reference clock signal CLK_REF than the frequency of the output clock signal CLK_OUT.

[0104] In some embodiments, the sampling phase frequency detector 10, the transconductance circuit 20, the charge pump 30, the loop filter 50, the voltage controlled oscillator 60, and the phase splitter 70 can be referred to as the main loop.

[0105] The sampling phase frequency detector 10 can detect whether the main loop is fixed or synchronized.

[0106] If the output clock signal CLK_OUT has a constant target frequency, the main loop can be called fixed.

[0107] In some embodiments, when the phase of the first phase division signal PH1 based on the output clock signal CLK_OUT leads or lags the phase of the reference clock signal CLK_REF, fixing the main loop may cause the frequency and phase of the output clock signal CLK_OUT to change.

[0108] The phase-locked loop device 1 according to an embodiment can lock the phase and frequency using only the main loop without using a separate frequency-locking loop.

[0109] Therefore, the degree of integration can be increased, and the reliability and performance of the device can be improved.

[0110] Figure 2 is a block diagram showing a sampling phase frequency detector according to an embodiment.

[0111] Reference Figure 2 , the sampling phase frequency detector 10 can include a first circuit 11, a second circuit 12, and a third circuit 13.

[0112] The first circuit 11 can receive the reference clock signal CLK_REF and the first phase division signal PH1.

[0113] The first circuit 11 can generate a sampled voltage by sampling the voltage in response to the edge of the first phase division signal PH1. In some embodiments, the phrase "in response to" can also mean, for example, "based on".

[0114] The sampled voltage can be the voltage generated at a specific node according to the reference clock signal CLK_REF and the first phase division signal PH1.

[0115] The first circuit 11 can receive a first switch signal PH2_UP, a second switch signal PH2_DN, and a third switch signal PH2_SPD, and can output a holding voltage Vhold.

[0116] The first to third switch signals PH2_UP, PH2_DN, and PH2_SPD can be signals for selecting one of a first power supply voltage, a second power supply voltage, and the sampled voltage as the holding voltage Vhold.

[0117] For example, during a period when the first switching signal PH2_UP has a first logic level and the second switching signal PH2_DN and the third switching signal PH2_SPD have a second logic level, the first power supply voltage can be output as the holding voltage Vhold.

[0118] Here, the first logic level can indicate a logic high, and the second logic level can indicate a logic low. However, the embodiments are not limited thereto.

[0119] As another example, during a period when the second switching signal PH2_DN has a first logic level and the first switching signal PH2_UP and the third switching signal PH2_SPD have a second logic level, the second power supply voltage can be output as the holding voltage Vhold.

[0120] As yet another example, during a period when the third switching signal PH2_SPD has a first logic level and the first switching signal PH2_UP and the second switching signal PH2_DN have a second logic level, the sampling voltage can be output as the holding voltage Vhold.

[0121] Examples of the first to third switching signals PH2_UP, PH2_DN, and PH2_SPD are referenced Figures 6 to 10 described below.

[0122] The second circuit 12 can receive the first inverted divided signal PH1b, the reference clock signal CLK_REF, and the inverted reference clock signal CLK_REFb.

[0123] The first inverted divided signal PH1b can be the inverted signal of the first phase divided signal PH1. For example, the first inverted divided signal PH1b can be the inversion of the first phase divided signal PH1.

[0124] The inverted reference clock signal CLK_REFb can be the inverted signal of the reference clock signal CLK_REF. For example, the inverted reference clock signal CLK_REFb can be the inversion of the reference clock signal CLK_REF.

[0125] The second circuit 12 can output the first selection signal UP_FLL, the second selection signal DN_FLL, and the third selection signal SPD to the third circuit 13.

[0126] In addition, the second circuit 12 can output the first status signal UP_SS and the second status signal DN_SS to Figure 1 the charge pump 30.

[0127] The first selection signal UP_FLL may be referred to as the upper selection signal, the second selection signal DN_FLL may be referred to as the lower selection signal, and the third selection signal SPD may be referred to as the sampling selection signal.

[0128] Examples of the first to third selection signals UP_FLL, DN_FLL, and SPD, and the first status signal UP_SS and the second status signal DN_SS are referred to Figures 6 to 10 and are described below.

[0129] The third circuit 13 may receive the first to third selection signals (UP_FLL, DN_FLL, SPD) and the second phase division signal PH2, and may output the first to third switch signals PH2_UP, PH2_DN, and PH2_SPD to the first circuit 11.

[0130] The first to third selection signals UP_FLL, DN_FLL, and SPD may be signals for matching the phase of one of the first to third switch signals PH2_UP, PH2_DN, and PH2_SPD with the phase of the second phase division signal PH2.

[0131] For example, if the first selection signal UP_FLL has a first logic level and the second selection signal DN_FLL and the third selection signal SPD have a second logic level, the phase of the first switch signal PH2_UP may correspond to the phase of the second phase division signal PH2.

[0132] As another example, when the second selection signal DN_FLL has a first logic level and the first selection signal UP_FLL and the third selection signal SPD have a second logic level, the phase of the second switch signal PH2_DN may correspond to the phase of the second phase division signal PH2.

[0133] As another example, when the third selection signal SPD_FLL has a first logic level and the first selection signal UP_FLL and the second selection signal DN_FLL have a second logic level, the phase of the third switch signal PH2_SPD may correspond to the phase of the second phase division signal PH2.

[0134] The first switch signal PH2_UP may be referred to as the upper switch signal, the second switch signal PH2_DN may be referred to as the lower switch signal, and the third switch signal PH2_SPD may be referred to as the sampling switch signal.

[0135] Examples of the first to third switch signals PH2_UP, PH2_DN, and PH2_SPD are referred to Figures 6 to 10 and are described below.

[0136] Figure 3 FIG. 1 is a circuit diagram showing a first circuit included in a sampling phase frequency detector according to an embodiment.

[0137] Reference Figures 1 to 3 , the first circuit 11 may be implemented as an integrated circuit chip including an input terminal and an output terminal, a reference clock signal CLK_REF is input through the input terminal, and a hold voltage Vhold is output through the output terminal.

[0138] The first circuit 11 may include a sampling phase detection circuit SPDC, an upper switch USW, and a lower switch DSW.

[0139] The sampling phase detection circuit SPDC may be disposed between an input node IN and a hold node HN.

[0140] The sampling phase detection circuit SPDC may sample the voltage generated at a sampling node SN based on a first phase division signal PH1.

[0141] The voltage sampled at the sampling node SN may be referred to as a sampling voltage.

[0142] In addition, the sampling phase detection circuit SPDC may transfer the sampling voltage as a hold voltage Vhold to the hold node HN based on a third switch signal PH2_SPD.

[0143] The sampling phase detection circuit SPDC may include a first transistor Tr1, a second transistor Tr2, a resistor R, a first switch SW1, a first capacitor C1, a second switch SW2, and a second capacitor C2.

[0144] The first transistor Tr1 may transfer a first power supply voltage Vdd to the sampling node SN in response to the reference clock signal CLK_REF.

[0145] The first transistor Tr1 may be connected between a node to which the first power supply voltage Vdd is applied and the sampling node SN at which the sampling voltage is generated.

[0146] For example, a first end of the first transistor Tr1 may be connected to the node to which the first power supply voltage Vdd is applied, a second end of the first transistor Tr1 may be connected to the resistor R, and a gate terminal of the first transistor Tr1 may be connected to the input node IN for inputting the reference clock signal CLK_REF.

[0147] When the first transistor Tr1 is turned on, the first power supply voltage Vdd may be transferred to the sampling node SN, and the level of the sampling voltage may increase. In an embodiment, a turned-on transistor may be referred to as an active transistor, and a turned-off transistor may be referred to as a deactivated transistor.

[0148] The second transistor Tr2 can transfer the second power supply voltage Vss to the sampling node SN in response to the reference clock signal CLK_REF.

[0149] The second transistor Tr2 can be connected between the node to which the second power supply voltage Vss is applied and the sampling node SN.

[0150] For example, the first end of the second transistor Tr2 can be connected to the node to which the second power supply voltage Vss is applied, the second end of the second transistor Tr2 can be connected to the sampling node SN, and the gate terminal of the second transistor Tr2 can be connected to the input node IN.

[0151] When the second transistor Tr2 is turned on, the second power supply voltage Vss can be transferred to the sampling node SN, and the level of the sampling voltage can be reduced.

[0152] In an embodiment, the first transistor Tr1 can be implemented as a p-channel metal oxide semiconductor (PMOS) transistor, and the second transistor Tr2 can be implemented as an n-channel metal oxide semiconductor (NMOS) transistor, but the embodiment is not limited thereto.

[0153] In some embodiments, the first end of the first transistor Tr1 implemented as a PMOS transistor and the first end of the second transistor Tr2 implemented as an NMOS transistor can be referred to as the source.

[0154] The second end of the first transistor Tr1 and the second end of the second transistor Tr2 can be referred to as the drain.

[0155] The resistor R can be connected between the second end of the first transistor Tr1 and the sampling node SN.

[0156] When the first transistor Tr1 is turned on, the resistor R can form an edge slope in the sampling voltage.

[0157] In some embodiments, when the sampling voltage increases, it can linearly increase from the second power supply voltage Vss to the first power supply voltage Vdd based on the edge slope.

[0158] The first switch SW1 can be connected between the sampling node SN and the charging node CN, and can connect the sampling node SN and the charging node CN in response to the first phase splitting signal PH1.

[0159] In an embodiment, when the first phase splitting signal PH1 has a first logic level, the first switch SW1 can be turned on, and the sampling voltage can be applied to the charging node CN.

[0160] The first capacitor C1 can be charged with a charge corresponding to the difference between the voltage generated at the charging node CN and the second power supply voltage Vss.

[0161] The first capacitor C1 can be connected between a node to which a second power supply voltage Vss is applied and a charging node CN.

[0162] For example, a first end of the first capacitor C1 can be connected to the charging node CN, and a second end of the first capacitor C1 can be connected to the node to which the second power supply voltage Vss is applied.

[0163] The second switch SW2 is connected between the charging node CN and the holding node HN, and can connect the charging node CN and the holding node HN in response to a third switch signal PH2_SPD.

[0164] In an embodiment, if the third switch signal PH2_SPD has a first logic level, the second switch SW2 can be turned on, and a sampled voltage generated at the charging node CN (or a voltage corresponding to the charge stored in the first capacitor C1) can be applied to the holding node HN.

[0165] In an embodiment, each of the first switch SW1 and the second switch SW2 can be implemented using an NMOS transistor, but the embodiment is not limited thereto.

[0166] The second capacitor C2 can store a charge corresponding to the difference between the voltage generated at the holding node HN (e.g., the holding voltage Vhold) and the second power supply voltage Vss.

[0167] The second capacitor C2 can be connected between the node to which the second power supply voltage Vss is applied and the holding node HN.

[0168] For example, a first end of the second capacitor C2 can be connected to the holding node HN, and a second end of the second capacitor C2 can be connected to the node to which the second power supply voltage Vss is applied.

[0169] The upper switch USW can transfer the first power supply voltage Vdd as the holding voltage Vhold to the holding node HN based on a first switch signal PH2_UP.

[0170] The upper switch USW can be connected between the node to which the first power supply voltage Vdd is applied and the holding node HN, and can connect the node to which the first power supply voltage Vdd is applied and the holding node HN in response to the first switch signal PH2_UP.

[0171] In an embodiment, when the first switch signal PH_UP has a first logic level, the upper switch USW can be turned on, and the first power supply voltage Vdd can be applied to the holding node HN.

[0172] In an embodiment, the upper switch USW can be implemented using an NMOS transistor, but the embodiment is not limited thereto.

[0173] The lower switch DSW can transmit the second power supply voltage Vss as the holding voltage Vhold to the holding node HN based on the second switch signal PH2_DN.

[0174] The lower switch DSW can be connected between the node to which the second power supply voltage Vss is applied and the holding node HN, and can connect the node to which the second power supply voltage Vss is applied and the holding node HN in response to the second switch signal PH2_DN.

[0175] In an embodiment, when the second switch signal PH_DN has a first logic level, the lower switch DSW can be turned on, and the second power supply voltage Vss can be applied to the holding node HN.

[0176] In an embodiment, the lower switch DSW can be implemented using an NMOS transistor, but the embodiment is not limited thereto.

[0177] Figure 4 is a circuit diagram showing a second circuit included in a sampling phase frequency detector according to an embodiment.

[0178] Reference Figures 1 to 4 , the second circuit 12 can be implemented using an integrated circuit chip, which includes an input terminal for inputting the first inverted divided signal PH1, an input terminal for inputting the reference clock signal CLK_REF, an input terminal for inputting the inverted reference clock signal CLK_REFb, a terminal for outputting the first selection signal to the third selection signals UP_FLL, DN_FLL, and SPD, and a terminal for outputting the first status signal UP_SS and the second status signal DN_SS.

[0179] The second circuit 12 can include a first flip-flop FF1, a second flip-flop FF2, a third flip-flop FF3, a fourth flip-flop FF4, a first phase adjustment circuit PA1, a second phase adjustment circuit PA2, a first logical product gate ANDG1, a second logical product gate ANDG2, a third logical product gate ANDG3, and a negative OR gate NORG.

[0180] The first flip-flop FF1 can include a clock terminal for inputting the reference clock signal CLK_REF, an input terminal for inputting the first power supply voltage Vdd, and an output terminal for outputting the first latch signal UP.

[0181] The first flip-flop FF1 can latch the first power supply voltage Vdd in response to the reference clock signal CLK_REF and output the first latch signal UP.

[0182] In an embodiment, the first flip-flop FF1 may output a first latch signal UP having a level of a first power supply voltage Vdd (e.g., a first logic level) in response to a rising edge of a reference clock signal CLK_REF.

[0183] The first latch signal UP may be referred to as an upper latch signal.

[0184] The second flip-flop FF2 may include a clock terminal for inputting a first inverted divided signal PH1b, an input terminal for inputting a first power supply voltage Vdd, and an output terminal for outputting a second latch signal DN.

[0185] The second flip-flop FF2 may latch the first power supply voltage Vdd in response to the first inverted divided signal PH1b and output the second latch signal DN.

[0186] In an embodiment, the second flip-flop FF2 may output a second latch signal DN having a level of a first power supply voltage Vdd (e.g., a first logic level) in response to a rising edge of the first inverted divided signal PH1b.

[0187] The second latch signal DN may be referred to as a lower latch signal.

[0188] The first logic AND gate ANDG1 may have input terminals for inputting the first latch signal UP and the second latch signal DN, and an output terminal connected to a reset terminal of each of the first flip-flop FF1 and the second flip-flop FF2.

[0189] The first ANDG1 may perform an AND operation on the first latch signal UP and the second latch signal DN.

[0190] In addition, the first logic AND gate ANDG1 may transmit an output signal representing a result of the AND operation as a reset signal to the reset terminal of each of the first flip-flop FF1 and the second flip-flop FF2.

[0191] In an embodiment, when both the first latch signal UP and the second latch signal DN have a first logic level (e.g., logic high), the first logic AND gate ANDG1 may output an output signal having a first logic level to the reset terminal of each of the first flip-flop FF1 and the second flip-flop FF2.

[0192] At this time, the first flip-flop FF1 and the second flip-flop FF2 may be reset.

[0193] The first phase adjustment circuit PA1 may include an input terminal and an output terminal, and a reference clock signal CLK_REF is input through the input terminal, and a first adjusted clock signal CLK_A1 is output through the output terminal.

[0194] The first phase adjustment circuit PA1 can delay the output of the reference clock signal CLK_REF, change the phase of the reference clock signal CLK_REF, and output the first adjusted clock signal CLK_A1.

[0195] In some embodiments, the first phase adjustment circuit PA1 may be an inverter chain including a plurality of inverters, but the embodiments are not limited thereto.

[0196] In some embodiments, the first adjusted clock signal CLK_A1 may rise synchronously with the timing at which the sampling phase frequency detector 10 samples the first power supply voltage Vdd.

[0197] For example, the rising edge of the first inverted divided signal PH1b may lag the rising edge of the reference clock signal CLK_REF by a first interval, such that the sampling phase frequency detector 10 detects the level of the first power supply voltage Vdd. When sampling, the first adjusted clock signal CLK_A1 may lag the reference clock signal CLK_REF in phase by the first interval.

[0198] The third flip-flop FF3 may include a clock terminal for inputting the first adjusted clock signal CLK_A1, an input terminal for inputting the first latch signal UP, and an output terminal for outputting the first selection signal UP_FLL.

[0199] The third flip-flop FF3 may latch the first latch signal UP in response to the first adjusted clock signal CLK_A1 and output the latched signal as the first selection signal UP_FLL.

[0200] In an embodiment, the third flip-flop FF3 may latch the first latch signal in response to the rising edge of the first adjusted clock signal CLK_A1.

[0201] The second logical product ANDG2 may include an input terminal for inputting the first latch signal UP and the first selection signal UP_FLL, and an output terminal for outputting the first status signal UP_SS.

[0202] The second logical product gate ANDG2 may perform an AND operation on the first latch signal UP and the first selection signal UP_FLL.

[0203] In addition, the second logical product gate ANDG2 may transmit the first status signal UP_SS indicating the result of the logical product operation to the charge pump 30.

[0204] When the rising edge of the first inverted divided signal PH1b lags the rising edge of the reference clock signal CLK_REF by a first predetermined interval, the first status signal UP_SS may be output in the form of a pulse signal.

[0205] In some embodiments, the pulse width of the first status signal UP_SS may correspond to the time interval between the rising edge of the first inverted division signal PH1b and the rising edge of the reference clock signal CLK_REF.

[0206] The second phase adjustment circuit PA2 may include an input terminal for receiving the inverted reference clock signal CLK_REFb and an output terminal for outputting the second adjusted clock signal CLK_A2.

[0207] The second phase adjustment circuit PA2 may delay the output of the inverted reference clock signal CLK_REFb, change the phase of the inverted reference clock signal CLK_REFb, and output it as the second adjusted clock signal CLK_A2.

[0208] In some embodiments, the second phase adjustment circuit PA2 may be an inverter chain including a plurality of inverters, but the embodiments are not limited thereto.

[0209] In some embodiments, the second adjusted clock signal CLK_A2 may rise synchronously with the timing at which the sampling phase frequency detector 10 samples the second power supply voltage Vss.

[0210] For example, when the rising edge of the first inverted division signal PH1b is advanced by a second interval relative to the rising edge of the reference clock signal CLK_REF, the sampling phase frequency detector 10 may detect the level of the second power supply voltage Vss. When sampling, the second adjusted clock signal CLK_A2 may be advanced by a second interval in phase relative to the reference clock signal CLK_REF.

[0211] The fourth flip-flop FF4 may include a clock terminal for receiving the second adjusted clock signal CLK_A2, an input terminal for receiving the second latch signal DN, and an output terminal for outputting the second selection signal DN_FLL.

[0212] The fourth flip-flop FF4 may latch the second latch signal DN in response to the second adjusted clock signal CLK_A2 and output the latched signal as the second selection signal DN_FLL.

[0213] In an embodiment, the fourth flip-flop FF4 may latch the second latch signal DN in response to the rising edge of the second adjusted clock signal CLK_A2.

[0214] The third AND gate ANDG3 may include input terminals for receiving the second latch signal DN and the second selection signal DN_FLL, and an output terminal for outputting the second status signal DN_SS.

[0215] The third AND gate ANDG3 may perform an AND operation on the second latch signal DN and the second selection signal DN_FLL.

[0216] In addition, the third AND gate ANDG3 can transmit a second status signal DN_SS indicating the result of the AND operation to the charge pump 30.

[0217] When the rising edge of the first inverted division signal PH1b is advanced by a second predetermined interval relative to the rising edge of the reference clock signal CLK_REF, the second status signal DN_SS can be output in the form of a pulse signal.

[0218] In some embodiments, the pulse width of the second status signal DN_SS can correspond to the time interval between the rising edge of the first inverted division signal PH1b and the rising edge of the reference clock signal CLK_REF.

[0219] The negative OR gate NORG can include an input terminal for inputting a first selection signal UP_FLL and a second selection signal DN_FLL, and an output terminal for outputting a third selection signal SPD.

[0220] The negative OR gate NORG can perform a negative OR operation on the first selection signal UP_FLL and the second selection signal DN_FLL.

[0221] In addition, the negative OR gate NORG can output an output signal representing the result of the negative OR operation as the third selection signal SPD.

[0222] In an embodiment, when both the first selection signal UP_FLL and the second selection signal DN_FLL have a second logic level (e.g., logic low), the negative OR gate NORG can output a third selection signal SPD having a first logic level, and when one of the first selection signal UP_FLL and the second selection signal DN_FLL has a first logic level, the negative OR gate NORG can output a third selection signal SPD having a second logic level.

[0223] Figure 5 is a circuit diagram showing a third circuit included in a sampling phase frequency detector according to an embodiment.

[0224] Reference Figures 2 to 5 , the third circuit 13 can include at least one input terminal for inputting a second phase division signal PH2 and inputting the first selection signal to the third selection signal UP_FLL, DN_FLL, and SPD, and can be implemented as an integrated circuit chip including output terminals for outputting a first switch signal to a third switch signal PH2_UP, PH2_DN, and PH2_SPD.

[0225] The third circuit 13 can include a fourth AND gate ANDG4, a fifth AND gate ANDG5, and a sixth AND gate ANDG6.

[0226] The fourth AND gate ANDG4 may include an input terminal for receiving the second phase division signal PH2 and the first selection signal UP_FLL, and an output terminal for outputting the first switching signal PH2_UP.

[0227] The fourth AND gate ANDG4 may logically multiply the second phase division signal PH2 and the first selection signal UP_FLL to output the first switching signal PH2_UP.

[0228] In an embodiment, when the first selection signal UP_FLL is at the first logic level, the fourth AND gate ANDG4 may output the first switching signal PH2_UP equal to the second phase division signal PH2.

[0229] When the first selection signal UP_FLL is at the second logic level, the fourth AND gate ANDG4 may output the first switching signal PH2_UP having the second logic level.

[0230] The fifth AND gate ANDG5 may include an input terminal for receiving the second phase division signal PH2 and the second selection signal DN_FLL, and an output terminal for outputting the second switching signal PH2_DN.

[0231] The fifth AND gate ANDG5 may logically multiply the second phase division signal PH2 and the second selection signal DN_FLL to output the second switching signal PH2_DN.

[0232] In an embodiment, when the second selection signal DN_FLL is at the first logic level, the fifth AND gate ANDG5 may output the second switching signal PH2_DN equal to the second phase division signal PH2.

[0233] When the second selection signal DN_FLL is at the second logic level, the fifth AND gate ANDG5 may output the second switching signal PH2_DN having the second logic level.

[0234] The sixth AND gate ANDG6 may include an input terminal for receiving the second phase division signal PH2 and the third selection signal SPD, and an output terminal for outputting the third switching signal PH2_SPD.

[0235] The sixth AND gate ANDG6 may logically multiply the second phase division signal PH2 and the third selection signal SPD to output the third switching signal PH2_SPD.

[0236] In an embodiment, when the third selection signal SPD is at the first logic level, the sixth AND gate ANDG6 may output the third switching signal PH2_SPD equal to the second phase division signal PH2.

[0237] When the third selection signal SPD is at the second logic level, the sixth logical product gate ANDG6 can output a third switching signal PH2_SPD having the second logic level.

[0238] Figure 6 is a timing diagram of signals that occur in the phase-locked state according to the embodiment.

[0239] Reference Figures 3 to 6 , when the first transistor Tr1 is turned on, the level of the sampling voltage at the sampling node SN can increase to the first power supply voltage Vdd.

[0240] In addition, when the second transistor Tr2 is turned on, the level of the sampling voltage can be reduced to the second power supply voltage Vss.

[0241] In this way, the level of the sampling voltage can increase or decrease in each cycle of the reference clock signal CLK_REF.

[0242] The period of the reference clock signal CLK_REF can be, for example, 2π, but the embodiment is not limited thereto.

[0243] Figure 6 The phase difference between the first phase division signal PH1 and the second phase division signal PH2 shown can be constant and can be the same as Figures 7 to 10 the phase difference between the first phase division signal PH1 and the second phase division signal PH2 shown.

[0244] Figure 6 The period of each of the first phase division signal PH1 and the second phase division signal PH2 shown can be the same as T, and T can be the period of the reference clock signal CLK_REF.

[0245] At time t11, the first phase division signal PH1 can change from the first logic level to the second logic level, and the reference clock signal CLK_REF can change from the second logic level to the first logic level.

[0246] In the embodiment, the first logic level can be logic high, and the second logic level can be logic low.

[0247] In the embodiment, the time when the first logic level changes to the second logic level can be referred to as the falling edge, and the time when the second logic level changes to the first logic level can be referred to as the rising edge.

[0248] The first phase adjustment circuit PA1 can delay the reference clock signal CLK_REF by the first threshold time constant τ1, so that the first adjusted clock signal CLK_A1 can lag behind the first time point t11 by the first threshold time constant τ1 and change from the second logic level to the first logic level.

[0249] The second phase adjustment circuit PA2 can delay the inverted reference clock signal CLK_REFb by π - τ2 in response to the second threshold time constant τ2, such that the second adjusted clock signal CLK_A2 lags behind the first time point t11 by π - τ2, and can change from the first logic level to the second logic level.

[0250] Since the first switch SW1 can be turned off in response to the falling edge of the first phase division signal PH1, the sampling voltage can be sampled at the falling edge of the first phase division signal PH1.

[0251] At this time, the level of the sampling voltage can correspond to the level of the reference voltage Vref, and the reference voltage Vref can be, for example, half of the first power supply voltage Vdd (e.g., the reference voltage Vref can be Vdd / 2).

[0252] In addition, in response to the reference clock signal CLK_REF and the first inverted division signal PH1b, the first latch signal UP and the second latch signal DN can be temporarily increased to the level of the first power supply voltage Vdd. However, they can be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip - flop FF1 and the second flip - flop FF2.

[0253] The reset level of the first latch signal UP and the second latch signal DN can be the second logic level.

[0254] At this time, the first selection signal UP_FLL and the second selection signal DN_FLL can have the second logic level, and the first status signal UP_SS and the second status signal DN_SS can have the second logic level.

[0255] In addition, the third selection signal SPD can have the first logic level.

[0256] The first switch signal PH2_UP and the second switch signal PH2_DN can have the second logic level, and the third switch signal PH2_SPD can be equal to the second phase division signal PH2.

[0257] When the third switch signal PH2_SPD is at the first logic level, the sampling voltage applied to the charging node CN can be transmitted to the holding node HN as the holding voltage Vhold.

[0258] In the drawings, the pulse width of the reference clock signal CLK_REF and the pulse width of the first phase division signal PH1 are shown to be the same, but the embodiments are not limited thereto. In addition, in some embodiments, the pulse width of the first phase division signal PH1 can be different from the pulse width of the reference clock signal CLK_REF.

[0259] At time t12, the first phase division signal PH1 may change from the first logic level to the second logic level, and the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0260] The time point t12 may be one period T after the time point t11, and the period T may be the period of the reference clock signal CLK_REF.

[0261] At time t12, the sampling phase frequency detector 10 may operate in the same manner as at time t11.

[0262] As Figure 6 shown, when the phase difference between the phase of the first inverted division signal PH1b and the phase of the reference clock signal CLK_REF is 0, sampling may be performed in response to the falling edge of the first phase division signal PH1, and the sampling voltage may be equal to the level of the reference voltage Vref.

[0263] For example, when the first phase division signal PH1 changes from the first logic level to the second logic level, if the level of the sampling voltage corresponds to half of the level of the first power supply voltage Vdd at the falling edge, the third switch signal PH2_SPD may correspond to the second phase division signal PH2.

[0264] Therefore, the level of the holding voltage Vhold may be the same as the level of the reference voltage Vref.

[0265] Figure 7 and Figure 8 are timing diagrams of signals that occur in the phase lead state according to an embodiment.

[0266] In some embodiments, the phase lead state may be determined based on the rising edge of the first inverted division signal PH1b and the rising edge of the reference clock signal CLK_REF.

[0267] Specifically, Figure 7 is a timing diagram of signals that occur when the phase difference between the first inverted division signal PH1b and the reference clock signal CLK_REF is less than or equal to the second threshold time constant τ2, Figure 8 is a timing diagram of signals that occur when the phase difference between the first inverted division signal PH1b and the reference clock signal CLK_REF is greater than the second threshold time constant τ2.

[0268] Referring to Figures 1 to 5 and Figure 7 , when the phase of the first inverted division signal PH1b is relatively ahead of the phase of the reference clock signal CLK_REF, the falling edge of the first phase division signal PH1 (the timing for sampling the sampling voltage) may be relatively faster thanFigure 6 The timing shown.

[0269] For example, Figure 7 The period of each of the first phase division signal PH1 and the second phase division signal PH2 shown may be a period T1, and this period T1 may be less than the above period T.

[0270] At time t21, the second adjustment clock signal CLK_A2 may change from the second logic level to the first logic level.

[0271] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN may be latched, such that the first selection signal UP_FLL and the second selection signal DN_FLL have the second logic level, and the third selection signal SPD may have the first logic level.

[0272] At time t22, the first inverted division signal PH1b may change from the second logic level to the first logic level.

[0273] In response to the rising edge of the first inverted division signal PH1b, the first power supply voltage Vdd may be latched, and the second latch signal DN may have the first logic level.

[0274] At time t23, the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0275] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched, and the first latch signal UP may have the first logic level.

[0276] In response to the reference clock signal CLK_REF, the first latch signal UP may temporarily have the level of the first power supply voltage Vdd, but may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0277] The reset levels of the first latch signal UP and the second latch signal DN may be the second logic level.

[0278] After time t23 and before time t24 (which may be the rising edge of the second adjustment clock signal CLK_A2), the first adjustment clock signal CLK_A1 may change from the second logic level to the first logic level.

[0279] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP is latched, the first selection signal UP_FLL and the second selection signal DN_FLL may have the second logic level, and the third selection signal SPD may have the first logic level.

[0280] At time t24, the second adjustment clock signal CLK_A2 may change from a second logic level to a first logic level.

[0281] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN may be latched, such that the first selection signal UP_FLL and the second selection signal DN_FLL have a second logic level, and the third selection signal SPD may have a first logic level.

[0282] At time t25, the first inverted divided signal PH1b may change from a second logic level to a first logic level.

[0283] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd may be latched, and the second latch signal DN may have a first logic level.

[0284] The period between time t22 and time t25 may be a period T1, which may be the period of the first inverted divided signal PH1b at the interval of the rising edge of the first inverted divided signal PH1b.

[0285] During the period between time t22 and time t25, the first selection signal UP_FLL and the second selection signal DN_FLL may have a second logic level, and the third selection signal SPD may have a first logic level.

[0286] The first switch signal PH2_UP and the second switch signal PH2_DN may have a second logic level, and the third switch signal PH2_SPD may be equal to the second phase division signal PH2.

[0287] When the third switch signal PH2_SPD is at a first logic level, the sampled voltage applied to the charging node CN may be transferred to the holding node HN as the holding voltage Vhold.

[0288] At time t26, the reference clock signal CLK_REF may change from a second logic level to a first logic level.

[0289] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched, and the first latch signal UP may have a first logic level.

[0290] In response to the reference clock signal CLK_REF, the first latch signal UP may temporarily have the level of the first power supply voltage Vdd, but may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0291] The reset levels of the first latch signal UP and the second latch signal DN may be the second logic level.

[0292] After time t26 and before time t27 (which may be the rising edge of the second adjusted clock signal CLK_A2), the first adjusted clock signal CLK_A1 may change from the second logic level to the first logic level.

[0293] In response to the rising edge of the first adjusted clock signal CLK_A1, the first latch signal UP may be latched such that the first selection signal UP_FLL and the second selection signal DN_FLL have the second logic level, and the third selection signal SPD may have the first logic level.

[0294] At time t27, the second adjusted clock signal CLK_A2 may change from the second logic level to the first logic level.

[0295] In response to the rising edge of the second adjusted clock signal CLK_A2, the second latch signal DN may be latched such that the first selection signal UP_FLL and the second selection signal DN_FLL have the second logic level, and the third selection signal SPD may have the first logic level.

[0296] At time t28, the first inverted divided signal PH1b may change from the second logic level to the first logic level.

[0297] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd may be latched and the second latch signal DN may have the first logic level.

[0298] At time t29, the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0299] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched and the first latch signal UP may have the first logic level.

[0300] In response to the reference clock signal CLK_REF, the first latch signal UP may temporarily have the level of the first power supply voltage Vdd, but may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0301] The reset levels of the first latch signal UP and the second latch signal DN may be the second logic level.

[0302] When the phase of the first inverted divided signal PH1b is relatively advanced with respect to the phase of the reference clock signal CLK_REF, the second latch signal can be generated according to the feedback operation of the main loop in the phase-locked loop device 1 and the repetition of the signal period, where the length of the interval in which DN has the first logic level can be reduced, and the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF can also be reduced.

[0303] In addition, according to the repetition of the signal period and the feedback operation of the main loop in the phase-locked loop device 1, the period of the output clock signal CLK_OUT can be increased, and the period T1 of the first inverted divided signal PH1b can be increased.

[0304] The holding voltage Vhold can rise close to the reference voltage Vref.

[0305] In some embodiments, if the sampling phase detection circuit SPDC performs a sampling operation at the rising edge of the second adjustment clock signal CLK_A2, the sampling voltage can be the second power supply voltage Vss.

[0306] Reference Figure 8 , the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF can be greater than the second threshold time constant τ2 of the reference clock signal CLK_REF.

[0307] For example, Figure 8 the period of each of the first phase divided signal PH1 and the second phase divided signal PH2 shown can be the period T2, and this period T2 can be less than Figure 7 the period T1 shown.

[0308] At time t31, the first inverted divided signal PH1b can change from the second logic level to the first logic level.

[0309] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd can be latched, and the second latch signal DN can have the first logic level.

[0310] At time t32, the second adjustment clock signal CLK_A2 can change from the second logic level to the first logic level.

[0311] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN is latched, such that the second selection signal DN_FLL has the first logic level, and the first selection signal UP_FLL and the third selection signal SPD can have the second logic level.

[0312] In addition, due to the second latch signal DN and the second selection signal DN_FLL, the second status signal DN_SS can have the first logic level.

[0313] At time t33, the reference clock signal CLK_REF can change from a second logic level to a first logic level.

[0314] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd can be latched, and the first latch signal UP can have a first logic level.

[0315] In response to the reference clock signal CLK_REF, the first latch signal UP can temporarily have the level of the first power supply voltage Vdd, but can be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0316] The reset levels of the first latch signal UP and the second latch signal DN can be a second logic level.

[0317] By resetting the second latch signal DN, the second status signal DN_SS can have a second logic level.

[0318] After time t33 and before time t34 (which can be the rising edge of the first inverted division signal PH1b), the first adjustment clock signal CLK_A1 can change from a second logic level to a first logic level.

[0319] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP is latched, such that the first selection signal UP_FLL and the third selection signal SPD have a second logic level, and the second selection signal DN_FLL can have a first logic level.

[0320] At time t34, the first inverted division signal PH1b can change from a second logic level to a first logic level.

[0321] In response to the rising edge of the first inverted division signal PH1b, the first power supply voltage Vdd can be latched, and the second latch signal DN can have a first logic level.

[0322] In addition, since the second latch signal DN and the second selection signal DN_FLL are latched at time t32, the second status signal DN_SS can have a first logic level.

[0323] The period between time t31 and time t34 can be a period T2, which can be the period of the first inverted division signal PH1b at the interval of the rising edge of the first inverted division signal PH1b.

[0324] During the period between time t32 and time t35, the first selection signal UP_FLL and the third selection signal SPD may have a second logic level, and the second selection signal DN_FLL may have a first logic level.

[0325] The first switch signal PH2_UP and the third switch signal PH2_SPD may have a second logic level, and the second switch signal PH2_DN may be equal to the second phase splitting signal PH2.

[0326] When the second switch signal PH2_DN is at the first logic level, the second power supply voltage Vss may be transmitted as the holding voltage Vhold to the holding node HN.

[0327] At time t35, the second adjustment clock signal CLK_A2 may change from the second logic level to the first logic level.

[0328] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN may be latched, such that the second selection signal DN_FLL has a first logic level, and the first selection signal UP_FLL and the third selection signal SPD may have a second logic level.

[0329] At time t36, the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0330] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched, and the first latch signal UP may have a first logic level.

[0331] In response to the reference clock signal CLK_REF, the first latch signal UP may temporarily have the level of the first power supply voltage Vdd, but may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0332] The reset levels of the first latch signal UP and the second latch signal DN may be the second logic level.

[0333] By resetting the second latch signal DN, the second status signal DN_SS may have a second logic level.

[0334] After time t36 and before time t37 (which may be the rising edge of the first inverted splitting signal PH1b), the first adjustment clock signal CLK_A1 may change from the second logic level to the first logic level.

[0335] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP can be latched, such that the first selection signal UP_FLL and the third selection signal SPD can have a second logic level, and the second selection signal DN_FLL can have a first logic level.

[0336] At time t37, the first inverted division signal PH1b can change from the second logic level to the first logic level.

[0337] In response to the rising edge of the first inverted division signal PH1b, the first power supply voltage Vdd is latched, and the second latch signal DN can have a first logic level.

[0338] In addition, since the second latch signal DN and the second selection signal DN_FLL are latched at time t32, the second status signal DN_SS can have a first logic level.

[0339] At time t38, the second adjustment clock signal CLK_A2 can change from the second logic level to the first logic level.

[0340] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN is latched, such that the second selection signal DN_FLL has a first logic level, and the first selection signal UP_FLL and the third selection signal SPD can have a second logic level.

[0341] At time t39, the reference clock signal CLK_REF can change from the second logic level to the first logic level.

[0342] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd is latched, and the first latch signal UP can have a first logic level.

[0343] In response to the reference clock signal CLK_REF, the first latch signal UP can temporarily have the level of the first power supply voltage Vdd, but it can be reset by the output of the first logic gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0344] The reset levels of the first latch signal UP and the second latch signal DN can be the second logic level.

[0345] By resetting the second latch signal DN, the second status signal DN_SS can have a second logic level.

[0346] And Figure 7Similarly, when the phase of the first inverted divided signal PH1b is relatively advanced with respect to the phase of the reference clock signal CLK_REF, based on the feedback operation of the main loop in the phase-locked loop device 1 and the repetition of the signal period, the length of the interval in which the second latch signal DN has the first logic level can be reduced, and the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF can also be reduced.

[0347] As the phase difference decreases, the second state interval Td (which can be the pulse width of the second state signal DN_SS) can also be reduced.

[0348] In addition, according to the repetition of the signal period and the feedback operation of the main loop in the phase-locked loop device 1, the period of the output clock signal CLK_OUT can be increased, and the period T2 of the first inverted divided signal PH1b can be increased.

[0349] After time t32, the second selection signal DN_FLL can have the first logic level, the first selection signal UP_FLL and the third selection signal SPD can have the second logic level, so that the second power supply voltage Vss can be transmitted to the holding node HN as the holding voltage Vhold and maintained at the holding node HN.

[0350] Figure 9 and Figure 10 is a timing diagram of the signals that appear in the phase lag state according to the embodiment.

[0351] In some embodiments, the phase lag state can be determined based on the rising edge of the first inverted divided signal PH1b and the rising edge of the reference clock signal CLK_REF.

[0352] Specifically, Figure 9 is a timing diagram of the signals that appear when the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF is less than or equal to the first threshold time constant τ1, Figure 10 is a timing diagram of the signals that appear when the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF is greater than the first threshold time constant τ1.

[0353] Refer to Figures 1 to 5 and Figure 9 , when the phase of the first inverted divided signal PH1b is relatively lagging behind the phase of the reference clock signal CLK_REF, the timing of sampling the sampling voltage at the falling edge of the first phase divided signal PH1 may be relatively delayed compared to the timing shown in Figure 6 shown.

[0354] For example, Figure 9The period of each of the first phase division signal PH1 and the second phase division signal PH2 shown may be a period T3, and this period T3 may be greater than the above-mentioned period T.

[0355] At time t41, the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0356] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched, and the first latch signal UP may have the first logic level.

[0357] At time t42, the first inverted division signal PH1b may change from the second logic level to the first logic level.

[0358] In response to the rising edge of the first inverted division signal PH1b, the first power supply voltage Vdd may be latched, and the second latch signal DN may have the first logic level.

[0359] In response to the first inverted division signal PH1b, the second latch signal DN may temporarily have the level of the first power supply voltage Vdd, but may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0360] The reset levels of the first latch signal UP and the second latch signal DN may be the second logic level.

[0361] At time t43, the first adjustment clock signal CLK_A1 may change from the second logic level to the first logic level.

[0362] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP may be latched so that the first selection signal UP_FLL and the second selection signal DN_FLL have the second logic level, and the third selection signal SPD may have the first logic level.

[0363] After time t43 and before time t44 (which may be the rising edge of the reference clock signal CLK_REF), the second adjustment clock signal CLK_A2 may change from the second logic level to the first logic level.

[0364] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN may be latched so that the first selection signal UP_FLL and the second selection signal DN_FLL have the second logic level, and the third selection signal SPD may have the first logic level.

[0365] At time t44, the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0366] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd is latched, and the first latch signal UP can have a first logic level.

[0367] At time t45, the first inverted divided signal PH1b can change from a second logic level to a first logic level.

[0368] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd can be latched, and the second latch signal DN can have a first logic level.

[0369] In response to the first inverted divided signal PH1b, the second latch signal DN can temporarily have the level of the first power supply voltage Vdd, but can be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0370] The reset levels of the first latch signal UP and the second latch signal DN can be a second logic level.

[0371] The period between time t42 and time t45 can be T3, which can be the period of the first inverted divided signal PH1b at the interval of the rising edge of the first inverted divided signal PH1b.

[0372] During the period between time t42 and time t45, the first selection signal UP_FLL and the second selection signal DN_FLL can have a second logic level, and the third selection signal SPD can have a first logic level.

[0373] The first switch signal PH2_UP and the second switch signal PH2_DN can have a second logic level, and the third switch signal PH2_SPD can be equal to the second phase divided signal PH2.

[0374] When the third switch signal PH2_SPD is at a first logic level, the sampled voltage applied to the charging node CN can be transmitted to the holding node HN as the holding voltage Vhold.

[0375] At time t46, the first adjustment clock signal CLK_A1 can change from a second logic level to a first logic level.

[0376] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP can be latched so that the first selection signal UP_FLL and the second selection signal DN_FLL have a second logic level, and the third selection signal SPD can have a first logic level.

[0377] After time t46 and before time t47, which may be the rising edge of the reference clock signal CLK_REF, the second adjusted clock signal CLK_A2 may change from a second logic level to a first logic level.

[0378] In response to the rising edge of the second adjusted clock signal CLK_A2, the second latch signal DN may be latched such that the first selection signal UP_FLL and the second selection signal DN_FLL have a second logic level and the third selection signal SPD may have a first logic level.

[0379] At time t47, the reference clock signal CLK_REF may change from a second logic level to a first logic level.

[0380] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched and the first latch signal UP may have a first logic level.

[0381] At time t48, the first inverted divided signal PH1b may change from a second logic level to a first logic level.

[0382] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd may be latched and the second latch signal DN may have a first logic level.

[0383] In response to the first inverted divided signal PH1b, the second latch signal DN may temporarily have the level of the first power supply voltage Vdd but may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0384] The reset level of the first latch signal UP and the second latch signal DN may be a second logic level.

[0385] At time t49, the first adjusted clock signal CLK_A1 may change from a second logic level to a first logic level.

[0386] In response to the rising edge of the first adjusted clock signal CLK_A1, the first latch signal UP may be latched such that the first selection signal UP_FLL and the second selection signal DN_FLL have a second logic level and the third selection signal SPD has a first logic level.

[0387] When the phase of the first inverted divided signal PH1b is relatively lagging behind the phase of the reference clock signal CLK_REF, the length of the interval during which the first latch signal UP has a first logic level may be reduced based on the feedback operation of the main loop in the phase-locked loop device 1 and the repetition of the signal period, and the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF may also be reduced.

[0388] In addition, according to the repetition of the signal period in the phase-locked loop device 1 and the feedback operation of the main loop, the period of the output clock signal CLK_OUT can be reduced, and the period T3 of the first inverted divided signal PH1b can be reduced.

[0389] The holding voltage Vhold can be reduced to be close to the reference voltage Vref.

[0390] In some embodiments, if the sampling phase detection circuit SPDC performs a sampling operation at the rising edge of the first adjustment clock signal CLK_A1, the sampling voltage can be the first power supply voltage Vdd.

[0391] Reference Figure 10 , the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF can be greater than the first threshold time constant τ1 of the reference clock signal CLK_REF.

[0392] For example, Figure 10 the period of each of the first phase divided signal PH1 and the second phase divided signal PH2 shown can be the period T, which can be greater than Figure 9 the shown T3.

[0393] At time t51, the reference clock signal CLK_REF can change from the second logic level to the first logic level.

[0394] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd is latched, and the first latch signal UP can have the first logic level.

[0395] At time t52, the first adjustment clock signal CLK_A1 can change from the second logic level to the first logic level.

[0396] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP can be latched, so that the first selection signal UP_FLL has the first logic level, and the second selection signal DN_FLL and the third selection signal SPD can have the second logic level.

[0397] In addition, due to the second latch signal DN and the second selection signal DN_FLL, the second state signal DN_SS can have the second logic level.

[0398] At time t53, the first inverted divided signal PH1b can change from the second logic level to the first logic level.

[0399] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd can be latched, and the second latch signal DN can have the first logic level.

[0400] In response to the first inverted division signal PH1b, the second latch signal DN may temporarily have the level of the first power supply voltage Vdd, but the first flip-flop FF1 and the second flip-flop FF2 may be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0401] The reset levels of the first latch signal UP and the second latch signal DN may be the second logic level.

[0402] By resetting the first latch signal UP, the first status signal UP_SS may have the second logic level.

[0403] After time t53 and before time t54 (which is the rising edge of the reference clock signal CLK_REF), the second adjustment clock signal CLK_A2 may change from the second logic level to the first logic level.

[0404] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN may be latched such that the second selection signal DN_FLL and the third selection signal SPD have the second logic level, and the first selection signal UP_FLL may have the first logic level.

[0405] At time t54, the reference clock signal CLK_REF may change from the second logic level to the first logic level.

[0406] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd may be latched and the first latch signal UP may have the first logic level.

[0407] In addition, since the first latch signal UP and the first selection signal UP_FLL are latched at time t52, the first status signal UP_SS may have the first logic level.

[0408] At time t55, the first adjustment clock signal CLK_A1 may change from the second logic level to the first logic level.

[0409] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP may be latched such that the first selection signal UP_FLL has the first logic level, and the second selection signal DN_FLL and the third selection signal SPD may have the second logic level.

[0410] At time t56, the first inverted division signal PH1b may change from the second logic level to the first logic level.

[0411] In response to the rising edge of the first inverted division signal PH1b, the first power supply voltage Vdd can be latched, and the second latch signal DN can have a first logic level.

[0412] In response to the first inverted division signal PH1b, the second latch signal DN can temporarily have the level of the first power supply voltage Vdd, but it can be reset by the output of the first logical product gate ANDG1 connected to the reset terminals of the first flip-flop FF1 and the second flip-flop FF2.

[0413] The reset levels of the first latch signal UP and the second latch signal DN can be a second logic level.

[0414] By resetting the first latch signal UP, the first status signal UP_SS can have a second logic level.

[0415] The period between time t53 and time t56 can be a period T4, which can be the period of the first inverted division signal PH1b at the interval of the rising edge of the first inverted division signal PH1b.

[0416] During the period between time t53 and time t56, the second selection signal DN_FLL and the third selection signal SPD can have a second logic level, and the first selection signal UP_FLL can have a first logic level.

[0417] The second switch signal PH2_DN and the third switch signal PH2_SPD can have a second logic level, and the first switch signal PH2_UP can be equal to the second phase division signal PH2.

[0418] When the first switch signal PH2_UP is at a first logic level, the first power supply voltage Vdd can be transmitted to the hold node HN as the hold voltage Vhold.

[0419] After time t56 and before time t57 (which is the rising edge of the reference clock signal CLK_REF), the second adjustment clock signal CLK_A2 can change from a second logic level to a first logic level.

[0420] In response to the rising edge of the second adjustment clock signal CLK_A2, the second latch signal DN can be latched, such that the second selection signal DN_FLL and the third selection signal SPD have a second logic level, and the first selection signal UP_FLL can have a first logic level.

[0421] At time t57, the reference clock signal CLK_REF can change from a second logic level to a first logic level.

[0422] In response to the rising edge of the reference clock signal CLK_REF, the first power supply voltage Vdd can be latched, and the first latch signal UP can have a first logic level.

[0423] In addition, since the first latch signal UP and the first selection signal UP_FLL are latched at time t52, the first status signal UP_SS can have a first logic level.

[0424] At time t58, the first adjustment clock signal CLK_A1 can change from a second logic level to a first logic level.

[0425] In response to the rising edge of the first adjustment clock signal CLK_A1, the first latch signal UP can be latched, such that the first selection signal UP_FLL has a first logic level, and the second selection signal DN_FLL and the third selection signal SPD can have a second logic level.

[0426] At time t59, the first inverted divided signal PH1b can change from a second logic level to a first logic level.

[0427] In response to the rising edge of the first inverted divided signal PH1b, the first power supply voltage Vdd can be latched, and the second latch signal DN can have a first logic level.

[0428] In response to the first inverted divided signal PH1b, the second latch signal DN can temporarily have the level of the first power supply voltage Vdd, but the first flip-flop FF1 and the second flip-flop can be reset by the output of the first AND gate ANDG1 connected to the reset terminal of FF2.

[0429] The reset levels of the first latch signal UP and the second latch signal DN can be a second logic level.

[0430] By resetting the first latch signal UP, the first status signal UP_SS can have a second logic level.

[0431] As Figure 10 shown, when the phase of the first inverted distribution signal PH1b lags relative to the phase of the reference clock signal CLK_REF, due to the feedback operation of the main loop and the repetition of the signal period in the phase-locked loop device 1, the length of the interval during which the first latch signal UP has a first logic level can be reduced, and the phase difference between the first inverted distribution signal PH1b and the reference clock signal CLK_REF can also be reduced.

[0432] As the phase difference decreases, the first status interval Tu (which can be the pulse width of the first status signal UP_SS) also decreases.

[0433] In addition, according to the repetition of the signal period in the phase-locked loop device 1 and the feedback operation of the main loop, the period of the output clock signal CLK_OUT can be reduced, and the period T4 of the first inverted divided signal PH1b can be reduced.

[0434] After t52, the first selection signal UP_FLL has a first logic level, and the second selection signal DN_FLL and the third selection signal SPD can have a second logic level, such that the first power supply voltage Vdd is a holding voltage and can be transmitted to and maintained at Vhold at the holding node HN.

[0435] As Figures 6 to 10 shown, the level of any one of the first selection signal to the third selection signal UP_FLL, DN_FLL, and SPD can be the first logic level, and the levels of the remaining selection signals can be the second logic level.

[0436] Among the first switch signal to the third switch signal PH2_UP, PH2_DN, and PH2_SPD, the switch signal corresponding to the selection signal having the first logic level can correspond to the second divided signal.

[0437] As Figure 8 and Figure 10 shown, even if the phase of the first inverted divided signal PH1b is excessively advanced or delayed with respect to the phase of the reference clock signal CLK_REF, it is not affected by the sampling voltage.

[0438] If the phase difference between the first inverted divided signal PH1b and the reference clock signal CLK_REF exceeds a predetermined interval, the first power supply voltage Vdd or the second power supply voltage Vss can be provided as the holding voltage Vhold, and the phase and frequency of the output clock signal CLK_OUT can be easily tracked through the first status signal UP_SS and the second status signal DN_SS corresponding to the phase difference.

[0439] Later, during the feedback control performed by the transconductance circuit 20, the charge pump 30, and the loop filter 50, the frequency of the output clock signal CLK_OUT can be tracked, thereby controlling the frequency of the output clock signal CLK_OUT. Therefore, the embodiment has the advantage of being able to set the frequency to a target frequency.

[0440] Figure 11 is a diagram showing a transconductance circuit according to an embodiment.

[0441] Referring Figure 1 and Figure 11 the transconductance circuit 20 may include a bias circuit 21, a current control circuit 22, and a current supply circuit 23.

[0442] The bias circuit 21 can provide a constant bias current (Ib) to the current control circuit 22.

[0443] Figure 11 An example where the number of bias circuits 21 is one is shown, but the embodiment is not limited thereto. For example, in some embodiments, in order to increase the magnitude of the bias current Ib, multiple bias circuits 21 may be included in the transconductance circuit 20.

[0444] The current control circuit 22 can compare the magnitude of the holding voltage Vhold and the magnitude of the reference voltage Vref.

[0445] The reference voltage Vref can be, for example, half of the first power supply voltage Vdd (e.g., the reference voltage can be Vdd / 2), but the embodiment is not limited thereto.

[0446] In some embodiments, the reference voltage Vref can be generated within the current control circuit 22.

[0447] In other embodiments, the current control circuit 22 can receive the reference voltage Vref from an external source.

[0448] The current control circuit 22 can control the current supply circuit 23 to adjust the first conversion current Icp1 output from the current supply circuit 23 depending on the result of comparing the magnitude of the holding voltage Vhold with the magnitude of the reference voltage Vref.

[0449] For example, if the magnitude (or level) of the holding voltage Vhold is the same as the magnitude of the reference voltage Vref (e.g., if the holding voltage Vhold is phase - locked with the reference voltage Vref), the current control circuit 22 can control the current supply circuit 23 such that the first conversion current Icp1 is not output.

[0450] As another example, when the magnitude (or level) of the holding voltage Vhold is less than the magnitude of the reference voltage Vref (i.e., when the phase of the voltage Vhold leads the phase of the reference voltage Vref), the current control circuit 22 can control the first conversion current Icp1 to be output from the loop filter 50 (this can be referred to as the direction of the first conversion current Icp1 flowing in the reverse or backward direction).

[0451] As yet another example, when the magnitude (or level) of the holding voltage Vhold is greater than the magnitude of the reference voltage Vref (e.g., when the phase of the voltage Vhold lags the phase of the reference voltage Vref), the current control circuit 22 can control the current supply circuit 23 such that the first conversion current Icp1 is input to the loop filter 50 (this can be referred to as the first conversion current Icp1 flowing in the forward or bidirectional direction).

[0452] In an embodiment, the number of current control circuits 22 may be one, but the embodiment is not limited thereto. In another embodiment, the transconductance circuit 20 may include a plurality of current control circuits 22.

[0453] The current supply circuit 23 may include a first current source CS1 and a second current source CS2.

[0454] The first current source CS1 may be connected between the first power supply voltage Vdd and the supply line and the node N.

[0455] The first current source CS1 may supply a first current (or an up current) to the node N.

[0456] The first current may flow from the line supplied with the first power supply voltage Vdd to the node N.

[0457] The second current source CS2 may be connected between the second power supply voltage Vss and the supply line and the node N.

[0458] The second current source CS2 may supply a second current (or a down current) from the node N to the line supplied with the second power supply voltage Vss.

[0459] As Figure 11 shown, according to Kirchhoff's current law, the sum of the first current of the first current source CS1, the second current of the second current source CS2, and the first conversion current Icp1 at the node N may be 0.

[0460] In an embodiment, based on the comparison result between the magnitudes of the hold voltage Vhold and the reference voltage Vref, the current control circuit 22 may supply a first current control signal CC1 and a second current control signal CC2 to the first current source CS1 and the second current source CS2, respectively.

[0461] The first current control signal CC1 and the second current control signal CC2 may be signals for controlling the currents generated by each of the first current source CS1 and the second current source CS2.

[0462] In some embodiments, the first current control signal CC1 and the second current control signal CC2 may be signals indicating the magnitudes of the currents generated by each of the first current source CS1 and the second current source CS2.

[0463] The sum of the current amplitude according to the first current control signal CC1 and the current amplitude according to the second current control signal CC2 corresponds to the bias current Ib, and if the current amplitude according to the first current control signal CC1 increases, the current amplitude according to the second current control signal CC2 may decrease, or if the current amplitude according to the first current control signal CC1 decreases, the current amplitude according to the second current control signal CC2 may increase.

[0464] For example, when the bias current Ib is 400 μA, the sum of the current amplitude according to the first current control signal CC1 and the current amplitude according to the second current control signal CC2 is 400 μA, and the change amount of the current according to the first current control signal CC1 and the change amount of the current according to the second current control signal CC2 can be opposite to each other. However, the embodiments are not limited thereto.

[0465] In the above example, the bias current Ib may be, for example, 400 μA, but the embodiments are not limited thereto.

[0466] If the amplitude of the holding voltage Vhold is the same as the amplitude of the reference voltage Vref, the current control circuit 22 may output the first current control signal CC1 and the second current control signal CC2 such that both the first current and the second current are 200 μA.

[0467] At this time, the first conversion current Icp1 may be 0 A.

[0468] In an embodiment, when the amplitude of the holding voltage Vhold is greater than the amplitude of the reference voltage Vref, the current control circuit 22 applies the first current control signal CC1 to the first current source CS1 such that the first current has a value greater than 200 μA, and applies the second current control signal CC2 to the second current source CS2 such that the second current has a value less than 200 μA.

[0469] At this time, according to Kirchhoff's current law, the first conversion current Icp1 may flow from the node N to the input terminal of the loop filter 50.

[0470] On the other hand, when the amplitude of the holding voltage Vhold is less than the amplitude of the reference voltage Vref, the current control circuit 22 may apply the first current control signal CC1 to the first current source CS1 such that the first current has a value less than 200 μA, and apply the second current control signal CC2 to the second current source CS2 such that the second current has a value greater than 200 μA.

[0471] At this time, according to Kirchhoff's current law, the first conversion current Icp1 may flow from the input terminal of the loop filter 50 to the node N.

[0472] When the first conversion current Icp1 flows from the node N to the input terminal of the loop filter 50, the loop filter 50 can increase the amplitude of the voltage control signal VCTRL.

[0473] When the increased voltage control signal VCTRL is input to the voltage controlled oscillator 60, the phase of the output clock signal CLK_OUT may become faster.

[0474] When the first conversion current Icp1 flows from the input terminal of the loop filter 50 to the node N, the loop filter 50 can decrease the amplitude of the voltage control signal VCTRL.

[0475] When the decreased voltage control signal VCTRL is input to the voltage controlled oscillator 60, the phase of the output clock signal CLK_OUT may slow down.

[0476] Figure 12 It is a diagram for explaining the characteristics of the conversion current according to an embodiment with respect to the phase difference.

[0477] Reference Figure 1 and Figure 12 , hereinafter, the conversion current Icp is described for each phase interval divided based on the phase difference (Δφ) between the reference clock signal CLK_REF and the first inverted divided signal PH1b.

[0478] Hereinafter, [-2π, 2π] (which may be the entire interval of the phase difference Δφ) may include a first phase interval PI1 and a second phase interval PI2.

[0479] In some embodiments, the first phase interval PI1 may be defined by a first threshold time constant τa and a second threshold time constant τb.

[0480] The second threshold time constant τb is less than 0, and the magnitude of the second threshold time constant τb may correspond to Figures 6 to 10 the second threshold time constant τ2.

[0481] The first threshold time constant τa may be greater than 0, and the magnitude of the first threshold time constant τa may correspond to Figures 6 to 10 the first threshold time constant τ1.

[0482] The second phase interval PI2 may be the interval in [-2π, 2π] different from the first phase interval PI1.

[0483] The second phase interval PI2 may include a 2_1 phase interval PI21 and a 2_2 phase interval PI22.

[0484] When the phase difference Δφ in the second phase interval PI2 is greater than 0, the 2_1 phase interval PI21 may correspond to phase lag.

[0485] In some embodiments, the 2_1 phase interval PI21 may be [τ1, 2π].

[0486] When the phase difference Δφ in the second phase interval PI2 is less than 0, the 2_2 phase interval PI22 may correspond to phase lead.

[0487] In some embodiments, the 2_2 phase interval (PI22) may be [-2π, τ2].

[0488] If the phase difference Δφ between the reference clock signal CLK_REF and the first inverted divided signal PH1b is 0, the amplitude of the conversion current Icp may be 0, and the magnitude of the sampling voltage in the sampling phase frequency detector 10 may be Figure 6 matched with the reference voltage Vref in

[0489] At this time, the main loop can be phase-locked.

[0490] In some embodiments, according to Equation 1 below, the conversion current Icp in the first phase interval PI1 may vary according to the first slope (m1).

[0491] m1 = K·gm Equation 1

[0492] In Equation 1, m1 is the slope of the conversion current Icp that varies depending on the phase difference Δφ in the first phase interval PI1, K is the edge slope of the sampling voltage in the sampling phase frequency detector 10, and gm is the transconductance coefficient in the transconductance circuit 20.

[0493] In the first phase interval PI1, the conversion current Icp may vary linearly depending on the amplitude of the sampling voltage and the transconductance coefficient in the transconductance circuit 20.

[0494] In the first phase interval PI1, the conversion current Icp may be determined by the first conversion current Icp1 output from the transconductance circuit 20.

[0495] In some embodiments, the first conversion current Icp1 may vary linearly with the conversion current Icp.

[0496] In the first phase interval PI1, if the phase difference Δφ between the reference clock signal CLK_REF and the first inverted divided signal PH1b is greater than 0, the conversion current Icp may be greater than 0.

[0497] If the phase difference Δφ between the reference clock signal CLK_REF and the first inverted divided signal PH1b is less than 0, the conversion current Icp may be less than 0.

[0498] At this time, the fact that the conversion current Icp is less than 0 may mean that the conversion current Icp flows in the opposite direction.

[0499] In some embodiments, according to Equation 2 below, the conversion current Icp in the second phase interval PI2 may vary according to the second slope m2.

[0500]

[0501] In Equation 2, where m2 is the slope of the conversion current Icp that varies with the change in the phase difference Δφ in the second phase interval PI2, is the phase difference Δφ between the reference clock signal CLK_REF and the first inverted divided signal PH1b, and Icp2 is the second conversion current Icp2 output from the charge pump 30.

[0502] In the second phase interval PI2, the conversion current Icp can be changed by the second conversion current Icp2 output from the charge pump 30.

[0503] In the second phase interval PI2, the conversion current Icp is input to the charge pump 30, and the first state signal UP_SS and the second state signal DN_SS, whose pulse widths vary depending on the phase difference Δφ, are output from the sampling phase frequency detector 10.

[0504] In the 2_1 phase interval PI21, the sampling phase frequency detector 10 may output the first power supply voltage Vdd, the transconductance circuit 20 may output a voltage greater than 0 based on the first power supply voltage Vdd, and the first conversion current Icp1 may be output.

[0505] In addition, in the 2_1 phase interval PI21, the sampling phase frequency detector 10 outputs the first state signal UP_SS, and the charge pump 30 outputs a second conversion current Icp2 greater than zero based on the first state signal UP_SS.

[0506] In the 2_2 phase interval PI22, the sampling phase frequency detector 10 may output the second power supply voltage Vss, the transconductance circuit 20 may output a voltage less than 0 based on the second power supply voltage Vss, and the first conversion current Icp1 may be output.

[0507] In addition, in the 2_2 phase interval PI22, the sampling phase frequency detector 10 outputs the second state signal DN_SS, and the charge pump 30 outputs a second conversion current Icp2 greater than zero based on the first state signal DN_SS.

[0508] At this time, the fact that the first conversion current Icp1 and the second conversion current Icp2 are less than 0 may mean that the first conversion current Icp1 and the second conversion current Icp2 flow in the opposite direction.

[0509] In the second phase interval PI2, by sampling the phase frequency detector 10 and the charge pump 30, as the phase difference Δφ changes, the conversion current Icp can be changed to a proportional gain.

[0510] The conversion current Icp can have a proportional gain in [-2π, 2π].

[0511] Through the proportional gain, the phase-locked loop device 1 can have the same fast lock time in the second phase interval PI2 as in the first phase interval PI1.

[0512] In some embodiments, in [-2π, 2π] of the phase difference Δφ, the phase difference Δφ and the conversion current Icp can correspond to each other one by one.

[0513] Figure 13 is a flowchart showing a method of operating a phase-locked loop device according to an embodiment.

[0514] Refer to Figures 1 to 5 and Figure 13 , the operating method of the phase-locked loop device 1 can be a method for synchronizing the output clock signal CLK_OUT to a desired target frequency and phase.

[0515] In operation S110, the sampling phase frequency detector 10 receives the reference clock signal CLK_REF and the first phase division signal PH1 and the second phase division signal PH2 divided from the output clock signal CLK_OUT.

[0516] In operation S120, the sampling phase frequency detector 10 generates a holding voltage Vhold based on the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1.

[0517] An example of operation S120 is described below in the description of Figure 14 .

[0518] In operation S130, the transconductance circuit 20 generates a first conversion current Icp1 based on the holding voltage Vhold.

[0519] According to some embodiments, operation S130 can correspond to the description referred to above in Figure 11 .

[0520] In operation S140, the sampling phase frequency detector 10 checks whether the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is within a predetermined interval.

[0521] The predetermined interval can correspond to Figure 12 the first phase interval PI1 of

[0522] In some embodiments, in operation S140, the sampling phase frequency detector 10 may check whether the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is included in a predetermined first phase interval PI1.

[0523] In an embodiment, operation S140 may correspond to the description referred to above Figures 6 to 10 and correspond to the falling edge of the first phase division signal PH1. This may be confirmed by comparing the falling edge of the first phase division signal PH1 with the rising edges of the first adjustment clock signal CLK_A1 and the second adjustment clock signal CLK_A2.

[0524] In some embodiments, the falling edge of the first phase division signal PH1 may be a sampling point of the sampling phase detection circuit SPDC, and may be between the rising edge of the second adjustment clock signal CLK_A2 and the rising edge of the first adjustment clock signal CLK_A1. When the falling edge of the first phase division signal PH1 is formed between the rising edge of the second adjustment clock signal CLK_A2 and the rising edge of the first adjustment clock signal CLK_A1, this may mean that the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is included in the predetermined first phase interval PI1.

[0525] In an embodiment, this may mean that when the falling edge of the first phase division signal PH1 is ahead of the rising edge of the second adjustment clock signal CLK_A2, or when the falling edge of the first phase division signal PH1 lags behind the rising edge of the first adjustment clock signal CLK_A1, the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is included in a second phase interval PI2 outside the predetermined first phase interval PI1.

[0526] Depending on the result of operation S140, it may be determined whether to output the first status signal UP_SS and the second status signal DN_SS of the sampling phase frequency detector 10.

[0527] If the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is not included in the predetermined interval, then in operation S150, the sampling phase frequency detector 10 generates status signals corresponding to the phase difference (e.g., the first status signal UP_SS and the second status signal DN_SS).

[0528] In an embodiment, operation S150 may correspond to the description referred to above Figure 8 and Figure 10 the description.

[0529] In some embodiments, when the falling edge of the first phase division signal PH1 precedes the rising edge of the second adjustment clock signal CLK_A2, the sampling phase frequency detector 10 may generate a second state signal DN_SS.

[0530] In some embodiments, when the falling edge of the first phase division signal PH1 lags behind the rising edge of the first adjustment clock signal CLK_A1, the sampling phase frequency detector 10 generates a first state signal UP_SS.

[0531] In operation S160, the charge pump 30 generates a second conversion current Icp2 based on the first state signal UP_SS and the second state signal DN_SS.

[0532] The charge pump 30 may adjust the direction and magnitude of the second conversion current Icp2 according to the types and pulse widths of the input state signals UP_SS and DN_SS.

[0533] In the drawings, operation S130 is shown before operations S140 to S160, but in some embodiments, operations S140 and step S150 may be performed together with operation S120 before operation S130.

[0534] In addition, in some embodiments, operations S130 and S160 may be performed simultaneously.

[0535] In operation S170, the loop filter 50 provides a voltage control signal VCTRL to the voltage controlled oscillator 60 based on the conversion current Icp, where the conversion current Icp is the sum of the first conversion current Icp1 and the second conversion current Icp2.

[0536] In some embodiments, if it is confirmed in operation S140 that the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is included in Figure 12 the first phase interval PI1, the loop filter 50 may provide the voltage control signal VCTRL to the voltage controlled oscillator 60 based on the first conversion current Icp1.

[0537] In some embodiments, if it is confirmed in operation S140 that the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is included in Figure 12 the first phase interval PI1, the magnitude of the second conversion current Icp2 may be 0.

[0538] In operation S180, the voltage controlled oscillator 60 provides an output clock signal CLK_OUT to the phase splitter 70 according to the voltage control signal VCTRL.

[0539] In operation S190, the phase splitter 70 splits the output clock signal CLK_OUT into a first phase-divided signal PH1 and a second phase-divided signal PH2.

[0540] Thereafter, the sampling phase frequency detector 10 can receive the first phase-divided signal PH1 and the second phase-divided signal PH2 from the phase splitter 70 as feedback signals.

[0541] The phase-locked loop device 1 can repeatedly execute operations S110 to S190 in one cycle.

[0542] Through the above operations of the sampling phase frequency detector 10, the transconductance circuit 20, the charge pump 30, the loop filter 50, the voltage-controlled oscillator 60, and the phase splitter 70, the output clock signal CLK_OUT can be synchronized with the target frequency and phase.

[0543] In some embodiments, the phase-locked loop device 1 can repeatedly execute operations S110 to S190 until the holding voltage Vhold generated by the sampling phase frequency detector 10 matches the reference voltage Vref.

[0544] Figure 14 is a flowchart showing the steps of generating a holding voltage at the holding node according to an embodiment.

[0545] Reference Figures 1 to 5 and Figure 13 and Figure 14 , step S120 according to an embodiment may include operations S121 to S125.

[0546] In operation S121, the sampling phase detection circuit SPDC samples the voltage based on the first phase-divided signal PH1.

[0547] In operation S121, the first switch SW1 of the sampling phase detection circuit SPDC connects the sampling node SN and the charging node CN in response to the first phase-divided signal PH1.

[0548] When the first phase-divided signal PH1 has a first logic level, the first switch SW1 is turned on, and the sampling voltage generated at the sampling node SN is applied to the charging node CN.

[0549] In operation S122, the sampling phase frequency detector 10 checks whether the phase difference between the reference clock signal CLK_REF and the first phase-divided signal PH1 is within a predetermined interval.

[0550] In some embodiments, operation S122 can be performed similarly to Figure 13 S140 of Figure 13 and can be performed simultaneously with S140 of

[0551] In some embodiments, operation S122 may be replaced by operation S140.

[0552] The predetermined interval may correspond to Figure 12 the first phase interval PI1 of

[0553] Depending on the confirmation result of operation S122, it may be determined whether to output the first selection signal UP_FLL and the second selection signal DN_FLL of the first logic level of the sampling phase frequency detector 10.

[0554] Depending on whether the first selection signal UP_FLL and the second selection signal DN_FLL are output at the first logic level, it may also be determined the output of the first logic level of the third selection signal SPD.

[0555] The level of one of the first selection signal to the third selection signal UP_FLL, DN_FLL, and SPD may be the first logic level, and the levels of the remaining selection signals may be the second logic level.

[0556] When it is confirmed that the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is within the predetermined interval, a sampling voltage is provided as the holding voltage Vhold in operation S123.

[0557] When it is confirmed that the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is within the predetermined interval, the first selection signal UP_FLL and the second selection signal DN_FLL may have the second logic level.

[0558] Therefore, the third selection signal SPD may have the first logic level.

[0559] According to the third switching signal PH2_SPD based on the third selection signal SPD, the sampling phase frequency detector 10 may provide a sampling voltage as the holding voltage Vhold.

[0560] When the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 is not within the predetermined interval, in operation S124, the sampling phase frequency detector 10 generates the first selection signal UP_FLL and the second selection signal DN_FLL.

[0561] In an embodiment, operation S124 may correspond to Figure 8 and Figure 10 the description of

[0562] In some embodiments, when the falling edge of the first phase division signal PH1 precedes the rising edge of the second adjustment clock signal CLK_A2, the second selection signal DN_FLL may have the first logic level.

[0563] In an embodiment, if the falling edge of the first phase division signal PH1 is delayed compared to the rising edge of the first adjustment clock signal CLK_A1, the sampling phase frequency detector 10 may set the first selection signal UP_FLL to a first logic level.

[0564] In operation S125, the sampling phase frequency detector 10 provides the power supply voltages (Vdd, Vss) as the holding voltage Vhold according to the phase lead state and the phase lag state.

[0565] In some embodiments, when the falling edge of the first phase division signal PH1 precedes the rising edge of the second adjustment clock signal CLK_A2, the phase is in a phase lead state and the second selection signal DN_FLL has a first logic level.

[0566] According to the second switching signal PH2_DN based on the second selection signal DN_FLL, the second power supply voltage Vss may be transmitted to the holding node HN as the holding voltage Vhold.

[0567] In some embodiments, when the falling edge of the first phase division signal PH1 lags behind the rising edge of the first adjustment clock signal CLK_A1, the phase is in a phase lag state and the first selection signal UP_FLL has a first logic level.

[0568] According to the first switching signal PH2_UP based on the first selection signal UP_FLL, the first power supply voltage Vdd may be transmitted to the holding node HN as the holding voltage Vhold.

[0569] The phase-locked loop device 1 may operate as described above Figure 13 and Figure 14 to have a proportional gain for the phase difference between the reference clock signal CLK_REF and the first phase division signal PH1 over the entire [-2π, 2π] interval.

[0570] Therefore, the phase-locked loop device 1 can have a fast lock time over the entire [-2π, 2π] interval using only the main loop without a separate loop.

[0571] Figure 15 is a block diagram showing a phase-locked loop device according to an embodiment.

[0572] Figure 16 is for explaining Figure 15 the transconductance circuit and the pulse generator shown.

[0573] As Figure 15 and Figure 16As shown, the phase-locked loop device 1' may include a sampling phase frequency detector 10' (shown as "SPFD"), a transconductance circuit 20' (shown as "GM circuit"), a charge pump 30' (shown as "CP"), a loop filter 50' (shown as "LF"), a voltage-controlled oscillator 60', a phase splitter 70', an automatic frequency calibrator (AFC) 80', and a pulser 90'.

[0574] The sampling phase frequency detector 10', the transconductance circuit 20', the charge pump 30', the loop filter 50', the voltage-controlled oscillator 60', and the phase splitter 70' may respectively correspond to the sampling phase frequency detector 10, the transconductance circuit 20, the charge pump 30, the loop filter 50, the voltage-controlled oscillator 60, and the phase splitter 70 as described above Figures 1 to 10 described, and redundant or repetitive descriptions may be omitted.

[0575] For ease of description below, the description of the components of Figure 15 and Figure 16 will focus on the differences from Figures 1 to 10 .

[0576] The sampling phase frequency detector 10', the transconductance circuit 20', the charge pump 30', the loop filter 50', the voltage-controlled oscillator 60', the phase splitter 70', the AFC 80', and the pulser 90' may operate as a main loop.

[0577] The AFC 80' may generate a target signal TGT for adjusting the frequency of the output clock signal CLK_OUT based on a reference clock signal CLK_REF and a feedback signal FDB.

[0578] In an embodiment, the feedback signal FDB output from the phase splitter 70' may correspond to Figures 1 to 10 the first phase division signal PH1 and the second phase division signal PH2 in

[0579] In an embodiment, the feedback signal FDB output from the phase splitter 70' may be a signal obtained by dividing the frequency of the output clock signal CLK_OUT by N. The frequency of the feedback signal FDB may be closer to the frequency of the reference clock signal CLK_REF than the frequency of the output clock signal CLK_OUT.

[0580] The pulser 90' may provide a pulse signal PLS to the transconductance circuit 20' and the charge pump 30', the pulse width of which is based on the output clock signal CLK_OUT.

[0581] The pulser 90' may also be referred to as a pulse generator.

[0582] The transconductance circuit 20' and the charge pump 30' can respectively output a first conversion current Icp1 and a second conversion current Icp2 during an interval corresponding to the pulse width of the pulse signal PLS.

[0583] The first conversion current Icp1 and the second conversion current Icp2 can be adjusted according to the pulse signal PLS of the pulser 90'.

[0584] When the pulser 90' is included in the phase-locked loop device 1', it has the advantages of ensuring a desired bandwidth and phase margin and reducing phase noise.

[0585] Regarding the transconductance circuit 20' and the charge pump 30', these elements can also include switches. For example, compared with the transconductance circuit 20 described above with reference to Figures 1 to 10 the transconductance circuit 20' can further include a switch 24.

[0586] The switch 24 can be connected between the node N and the output terminal that outputs the first conversion current Icp1, and the switch 24 can connect the node N and the output terminal in response to the pulse signal PLS output from the pulser 90'.

[0587] In an embodiment, the switch 24 is turned on only when the pulse signal PLS has a pulse width of a specific logic level, and the first conversion current Icp1 is output.

[0588] The switch 24 can be implemented using a transistor, but the embodiment is not limited thereto.

[0589] Similarly, the charge pump 30' according to an embodiment can further include a switch connected to the output terminal and receiving the pulse signal PLS from the pulser 90'.

[0590] This switch can output the second conversion current Icp2 to the output terminal in response to the pulse signal PLS.

[0591] This switch can be implemented using a transistor, but the embodiment is not limited thereto.

[0592] Figure 17 is a block diagram showing a wireless communication system according to an embodiment.

[0593] Specifically, Figure 17 shows an embodiment in which the base station 101 and the user equipment 102 perform wireless communication in the wireless communication system 100 using a cellular network.

[0594] According to the above embodiment, the wireless communication system 100 can define a high carrier frequency, and the base station 101 and the user equipment 102 can include a phase-locked loop device.

[0595] The base station 101 and the user equipment 102 may include a phase-locked loop device to improve the area overhead while providing a wide locking range and improved locking time for signals including high carrier frequencies and the like.

[0596] The base station 101 may be a fixed station that communicates with the user equipment and / or other base stations.

[0597] For example, the base station 101 may be or may include at least one of a Node B, an evolved Node B (eNB), a sector, a site, a base transceiver system (BTS), an access point (AP), and a relay node, and may be referred to as a remote radio head (RRH), a radio unit (RU), a small cell, etc.

[0598] The user equipment 102 may be fixed or mobile and may communicate with the base station to transmit and receive data and / or control information.

[0599] For example, the user equipment 102 may be or may include a terminal device, a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS), a wireless device, or a portable device, and may also be referred to as a handheld device, etc.

[0600] As Figure 17 shown, the base station 101 and the user equipment 102 may each include multiple antennas and may perform wireless communication through a multiple-input multiple-output (MIMO) channel 103.

[0601] Although some embodiments have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art may also be included within the scope of the present disclosure.

Claims

1. A phase-locked loop device, comprising: a voltage controlled oscillator configured to generate an output clock signal; A phase splitter configured to phase-split the output clock signal into a first phase division signal; Sampling phase frequency detector, configured as: receiving a first power supply voltage, a second power supply voltage different from the first power supply voltage, and the first phase division signal, and outputting a hold voltage based on the first power supply voltage or the second power supply voltage based on determining that a phase difference between the first phase division signal and the reference clock signal corresponds to a first interval, and outputting a status signal for the phase difference; a transconductance circuit configured to output a first switching current based on the holding voltage; a charge pump configured to output a second conversion current based on the state signal; as well as The loop filter is configured to provide a voltage control signal corresponding to the first switching current and the second switching current to the voltage controlled oscillator.

2. The phase-locked loop device according to claim 1, wherein: The state signal includes a first state signal and a second state signal, and Wherein, the sampling phase frequency detector is further configured as: converting the first state signal into a pulse signal based on determining that the phase difference corresponds to the first interval and a falling edge of the first phase division signal lags behind a rising edge of the reference clock signal, and The second state signal is converted into the pulse signal based on determining that the phase difference corresponds to the first interval and a falling edge of the first phase division signal precedes a rising edge of the reference clock signal.

3. The phase-locked loop device according to claim 2, wherein: Based on the sampling phase frequency detector outputting the first state signal, the sampling phase frequency detector is further configured to output the holding voltage based on the first power supply voltage, and Wherein, a voltage level of the first power supply voltage is higher than a voltage level of the second power supply voltage.

4. The phase-locked loop device according to claim 2, wherein: Based on the sampling phase frequency detector outputting the second state signal, the sampling phase frequency detector is further configured to output the holding voltage based on the second power supply voltage, and Wherein, a voltage level of the second power supply voltage is lower than a voltage level of the first power supply voltage.

5. The phase-locked loop device according to claim 2, wherein: Within the interval [-2π, 2π] of the phase difference, the phase difference corresponds one-to-one to the sum of the first switching current and the second switching current.

6. The phase-locked loop device according to claim 1, wherein: A second interval different from the first interval is defined by a first threshold time constant and a second threshold time constant at both ends, Wherein, the first threshold time constant is greater than 0, and Wherein, the second threshold time constant is less than 0.

7. The phase-locked loop device according to claim 6, wherein: The phase difference corresponds to an interval between a falling edge of the first phase division signal and a rising edge of the reference clock signal, and Wherein, based on the phase difference being within the second interval, the sampling phase frequency detector is further configured to output a voltage between the first power supply voltage and the second power supply voltage as a sampling voltage based on the phase difference.

8. The phase-locked loop device according to claim 7, wherein: The sampling phase frequency detector is further configured to: output the first power supply voltage as the sampled voltage based on determining that the phase difference corresponds to the first threshold time constant, and Based on determining that the phase difference corresponds to the second threshold time constant, the second power supply voltage is output as the sampled voltage.

9. The phase-locked loop device according to claim 8, wherein: The second power supply voltage includes a ground voltage, and Wherein, a voltage level of the first power supply voltage is higher than a voltage level of the second power supply voltage.

10. The phase-locked loop device according to claim 7, wherein: Based on determining that the phase difference corresponds to the second interval, the sampling phase frequency detector is further configured not to output the state signal and provide the sampled voltage as the hold voltage to the transconductance circuit, and the first switching current changes linearly according to the phase difference.

11. The phase-locked loop device according to claim 1, wherein: The transconductance circuit comprises: a current supply circuit including a first current source and a second current source connected to a node at which the first switching current is output; and The current control circuit is configured as: comparing the magnitude of the hold voltage with the magnitude of a reference voltage to generate a comparison result; and A first current control signal for controlling the first current source and a second current control signal for controlling the second current source are generated based on the comparison result.

12. The phase-locked loop device according to claim 11, further comprising a pulse generator configured to provide a pulse signal having a pulse width based on the output clock signal to the transconductance circuit, and in, The transconductance circuit is further configured to output the first switching current in an interval corresponding to the pulse width.

13. A method for operating a phase-locked loop device, the method comprising: receiving a reference clock signal and a first phase division signal phase-divided from an output clock signal; generating a holding voltage based on a phase difference between the first phase division signal and the reference clock signal; generating a first switching current based on the holding voltage; generating a status signal based on whether the phase difference is included within a predetermined interval; generating a second switching current based on the state signal; providing a voltage control signal based on a switching current including the first switching current and the second switching current; as well as The output clock signal is provided based on the voltage control signal.

14. The method according to claim 13, wherein: Generating the holding voltage comprises: generating a selection signal based on whether the phase difference is included in the predetermined interval; and Based on the selection signal, a power supply voltage is provided or a sampling operation is performed to provide a sampling voltage.

15. The method according to claim 14, wherein: Based on the phase difference being included in the predetermined interval, the sampling voltage is provided as the hold voltage, and the state signal is not output.

16. The method according to claim 14, wherein: Based on the phase difference not being included in the predetermined interval, the power supply voltage is provided as the hold voltage based on the selection signal, and the second conversion current is generated according to the state signal.

17. A phase-locked loop device, comprising: The first circuit comprises: a first flip-flop configured to output a first latch signal as a first selection signal based on a first adjustment clock signal, wherein a phase of the first adjustment clock signal is adjusted according to a reference clock signal, a second flip-flop, configured to output a second latch signal as a second selection signal based on a second adjustment clock signal, wherein the phase of the second adjustment clock signal is adjusted according to the reference clock signal, a first AND gate configured to perform an AND operation on the first latch signal and the first selection signal to output a first state signal; a second AND gate configured to perform an AND operation on the second latch signal and the second selection signal to output a second state signal; and a negative OR NOR gate configured to perform a NOR operation on the first selection signal and the second selection signal to output a third selection signal; The second circuit comprises: a sampling phase detection circuit configured to provide a sampling voltage to a holding node based on the third selection signal, an upper switch configured to provide a first power supply voltage to the holding node based on the first selection signal, and a lower switch configured to provide a second power supply voltage different from the first power supply voltage to the holding node based on the second selection signal; and A charge pump is configured to output at least a portion of a switching current based on the first state signal and the second state signal.

18. The phase-locked loop device according to claim 17, wherein: The first circuit further comprises: a third flip-flop configured to latch the first power supply voltage into the first latch signal based on the reference clock signal; a fourth flip-flop configured to latch the first power supply voltage into the second latch signal according to a falling edge of a phase division signal based on an output clock signal; and The third AND gate is configured to perform an AND operation on the first latch signal and the second latch signal to provide a reset signal to the third flip-flop and the fourth flip-flop.

19. The phase-locked loop device according to claim 17, wherein: The first circuit further comprises: a first phase adjustment circuit, configured to delay the reference clock signal and output the first adjusted clock signal; and The second phase adjustment circuit is configured to delay the inverted signal of the reference clock signal and output the second adjusted clock signal.

20. The phase-locked loop device according to claim 17, wherein: Based on the first selection signal having a first logic level, the second selection signal and the third selection signal have a second logic level different from the first logic level.

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