Digital frequency locking loop and digital frequency locking loop frequency control method
By using phase offset to generate electrical control signals in the digital frequency locking ring, the nonlinear response problem introduced by traditional voltage comparators is solved, and the control accuracy and accuracy of clock frequency is improved.
Patent Information
- Application Number
- CN202510151985.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-11
- Publication Date
- 2025-06-24
AI Technical Summary
When controlling the clock frequency, traditional voltage comparators introduce nonlinear responses due to the input offset voltage, which affects the control accuracy.
By introducing a control unit and a frequency adjustment unit into the digital frequency locking ring, an electrical control signal is generated using phase offset, and the input electrical signal is adjusted to control the output clock frequency to avoid nonlinear response.
The control accuracy of clock frequency is improved, the nonlinear response problem introduced by traditional voltage comparators is avoided, and the time particle size based on phase adjustment is more refined, thereby achieving higher control accuracy.
Smart Images
Figure CN120200610A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of frequency locking, and particularly to a digital frequency locked loop and a digital frequency locked loop frequency control method. Background Art
[0002] In large central processing unit / graphics processing unit (CPU / GPU) chips, due to instantaneous current changes and parasitic inductance generated by the package under different loads, power supply voltage droop occurs. The power supply voltage droop will reduce the timing and voltage design margins, affecting system performance and power consumption. Modern processing Device To solve the problem of the current change rate, the impact caused by the power supply voltage droop is reduced by changing the system clock frequency. Usually, multiple power supply voltage droop detectors are placed on the processor to detect the power supply voltage droop, and the detectors quickly respond to the power supply voltage droop and reduce the frequency.
[0003] As shown in the appendix Figure 1 Existing adaptive frequency reduction technologies compare the power supply voltage and the set threshold voltage in parallel through multiple voltage comparators, and directly control the current of the voltage controlled oscillator (VCO) of the frequency locked loop with the output of the voltage comparator, thereby playing a role in changing the clock frequency. However, due to factors such as the manufacturing process, there will be a certain input offset voltage at the two input terminals of the traditional voltage comparator, thus introducing a non-linear response during operation, which may produce incorrect output results, thereby affecting the control accuracy of the clock frequency. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a digital frequency locked loop and a digital frequency locked loop frequency control method, which are convenient for improving the control accuracy of the clock frequency.
[0005] In a first aspect, an embodiment of the present invention provides a digital frequency locked loop, including: A control unit configured to generate an electrical control signal according to the phase offset caused by detecting the change in the power supply voltage; A frequency adjustment unit coupled to the control unit and configured to adjust the input electrical signal according to the electrical control signal to control the output clock frequency.
[0006] Optionally, the control unit includes: a multi-phase delay line configured to generate multiple clock phase signals; A phase comparator, coupled to the multi-phase delay line, configured to compare the phase offsets between the multiple clock phase signals and convert the phase offsets into digital control signals.
[0007] Optionally, the digital control signal is a multi-bit output signal for characterizing the power supply voltage change amount to drive the frequency adjustment unit to adjust the input electrical signal.
[0008] Optionally, the frequency adjustment unit includes: a digital-to-analog converter and a voltage-controlled oscillator coupled to the output end of the digital-to-analog converter; wherein, The digital-to-analog converter is configured to adjust the input current or voltage of the voltage-controlled oscillator according to the electrical control signal; wherein the electrical signal includes: current or voltage; The voltage-controlled oscillator is configured to generate the desired target output clock frequency of the digital frequency-locked loop according to the input current or voltage.
[0009] Optionally, the frequency adjustment unit further includes: a frequency discriminator and a digital loop filter, and the signal feedback end of the frequency discriminator is connected to the output end of the voltage-controlled oscillator; wherein, The frequency discriminator is configured to detect the change of the output clock frequency and generate a feedback signal; The digital loop filter is used to filter the feedback signal to stabilize the output frequency.
[0010] Optionally, the frequency adjustment unit further includes: a loop frequency divider, and the loop frequency divider is coupled to the output end of the phase comparator of the control unit; The digital control signal is further configured to adjust the frequency division ratio of the loop frequency divider to dynamically reduce the target frequency of the frequency-locked loop.
[0011] Optionally, the frequency adjustment unit further includes: a voltage regulator and a current pull-down module; the voltage regulator is coupled to the digital-to-analog converter of the frequency adjustment unit, and the voltage regulator is configured to provide a regulated voltage source and reduce the power supply noise; The current pull-down module is coupled to the output end of the phase comparator of the control unit; the current pull-down module is configured to reduce the clock frequency according to the electrical control signal.
[0012] Optionally, the control unit further includes a phase selector, and the phase selector is configured to automatically adjust the threshold ratio of the power supply voltage change detection based on the phase offset.
[0013] In a second aspect, an embodiment of the present invention further provides a digital frequency-locked loop frequency control method, including: Generating an electrical control signal according to the detected phase offset caused by the power supply voltage change; Adjust the input electrical signal according to the electrical control signal to control the output clock frequency.
[0014] Optionally, the generating the electrical control signal according to the phase shift caused by detecting the power supply voltage change includes: Generate a plurality of clock phase signals; Compare the phase shift amounts between the plurality of clock phase signals and convert the phase shift amounts into digital control signals.
[0015] The digital frequency-locked loop and the digital frequency-locked loop frequency control method provided by the embodiments of the present invention generate an electrical control signal according to the phase shift caused by detecting the power supply voltage change through a control unit, so as to control the output frequency of the digital frequency-locked loop by adjusting the output clock frequency through a frequency adjustment unit, avoiding the problems brought by the non-linear response introduced by the traditional voltage comparator, and since the time granularity based on phase adjustment is finer than that based on voltage adjustment, it is convenient to improve the control accuracy of the clock frequency. Description of the Drawings
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings.
[0017] Figure 1 It is a schematic block diagram of an existing frequency-locked loop architecture based on a voltage comparator; Figure 2 It is a schematic diagram of the clock frequency and the processor power supply voltage change in the existing adaptive frequency reduction technology; Figure 3 It is a corresponding relationship diagram of voltage and frequency in the existing adaptive frequency reduction technology; Figure 4 It is a schematic block diagram of a digital frequency-locked loop architecture provided by an embodiment of the present invention; Figure 5 It is a schematic block diagram of a digital frequency-locked loop architecture provided by another embodiment of the present invention; Figure 6 It is a schematic structural diagram of a structure including a multi-phase delay line provided by an embodiment of the present invention; Figure 7 It is a structural diagram of a phase comparator provided by an embodiment of the present invention; Figure 8 It is a schematic flow diagram of a digital frequency-locked loop frequency control method provided by an embodiment of the present invention. Detailed Embodiments
[0018] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0019] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative work belong to the scope of protection of the present invention.
[0020] As Figure 1 shown, the existing adaptive frequency reduction technology uses multiple voltage comparators connected in parallel to compare the power supply voltage VDDCS and the set threshold voltage vref, obtains the voltage droop amount Droop[7:0], and directly controls the current of the voltage controlled oscillator (VCO) of the frequency locked loop with the output of the voltage comparator, thereby changing the clock frequency. As shown in the attached Figure 2 shown, the existing adaptive frequency reduction technology compares the power supply voltage VDD of the processor and the set Droop threshold voltage, quickly reduces the clock frequency after detecting the power supply voltage droop, and restores the clock frequency after the voltage recovers, thereby avoiding the timing convergence failure caused by the power supply voltage droop; the attached Figure 3 is the corresponding relationship between the power supply voltage and frequency of a typical existing frequency reduction and frequency locked loop of a processor. The clock frequency can be reduced along with the power supply voltage droop. However, the input voltage range of the traditional voltage comparator is limited, and the voltage comparator will introduce input offset.
[0021] To avoid the problems caused by the non-linearity of the traditional voltage comparator, the embodiments of the present invention provide a digital frequency locked loop and a digital frequency locked loop frequency control method. The control unit generates an electrical control signal according to the phase shift caused by detecting the change of the power supply voltage, and adjusts the output clock frequency through the frequency adjustment unit to control the output frequency of the digital frequency locked loop, avoiding the problems brought by the non-linear response introduced by the traditional voltage comparator.
[0022] Embodiment 1 Combined with the attached Figures 4 - 7 , the technical solution provided by the embodiment of the present invention will be described in detail. Figure 4 This is a block diagram showing the architecture of the digital frequency locked loop provided by the embodiment of the present invention. As shown in Figure 4 shown, the digital frequency locked loop provided in this embodiment includes a control unit 10 and a frequency adjustment unit 20, and the frequency adjustment unit 20 is coupled to the control unit 10.
[0023] A control unit 10, configured to generate an electrical control signal according to a phase shift caused by detecting a change in the power supply voltage; A frequency adjustment unit 20, coupled to the control unit, configured to adjust an input electrical signal according to the electrical control signal to control the output clock frequency.
[0024] This application improves the existing method of controlling the current of a voltage-controlled oscillator in a frequency-locked loop by comparing the power supply voltage with a set threshold voltage through a voltage comparator to change the clock frequency. By setting a control unit in the phase domain, voltage droop detection is performed in the phase domain and the output clock frequency of the frequency-locked loop is reduced, thereby avoiding the problems brought by the non-linear response introduced by the traditional voltage comparator. And since the time granularity based on phase adjustment is finer than that based on voltage adjustment, it is convenient to improve the control accuracy of the clock frequency.
[0025] In this embodiment, the output end of the control unit is coupled to the frequency control unit. The control unit operates in the phase domain. By performing voltage droop detection on the power supply voltage, an electrical control signal is generated according to the phase shift amount caused by the detected change in the power supply voltage, and is used to control the frequency adjustment unit to adjust the input electrical signal according to the electrical control signal to control the output clock frequency.
[0026] Refer to Figure 5 As shown, in an embodiment of the present invention, the control unit 10 includes: A multi-phase delay line, configured to generate a plurality of clock phase signals; A phase comparator, coupled to the multi-phase delay line, configured to compare the phase shift amounts between the plurality of clock phase signals and convert the phase shift amounts into digital control signals.
[0027] In this embodiment, the multi-phase delay line generates a plurality of clock phases with the same phase, phase[0]~phase
[40] , where N = 40 in the figure, and phase[0] is the reference clock phase; when the power supply voltage VDD has no droop, phase[0] and phase
[40] are phase-aligned. When the power supply voltage VDD has a voltage droop, phase
[40] generates a phase shift relative to phase[0], and the more the voltage droop amount, the more the number of phases that generate a phase shift relative to the reference phase phase[0]. Therefore, the phase comparator can compare a plurality of clock phases with the reference phase phase[0] to obtain the number of generated phase shifts (phase shift amounts), and convert the phase shift amounts into digital control signals to control the frequency adjustment unit to adjust the input electrical signal according to the electrical control signal to control the output clock frequency.
[0028] In some embodiments, refer toFigure 6 As shown Figure 6 FIG. is a schematic structural diagram of a structure including a multi-phase delay line provided by an embodiment of the present invention. In the figure, it is a complete delay lock loop, including a multi-phase voltage-controlled delay line, a loop filter, and a phase detector. Among them, Figure 6 the multi-phase delay line in is a common 4-phase delay line, which is used to input a clock signal CK in and then output a 90° shifted 4-phase clock CK out [0]~CK out [3].
[0029] In some embodiments, as shown in Figure 7 FIG., Figure 7 is a structural diagram of a phase comparator according to an embodiment of the present invention. The phase comparator can adopt a D flip-flop (DFF). P0 is the reference phase, and P33~P40 are the phases to be compared. The phase comparator outputs to indicate whether the phase lags or leads the reference phase P0. When the phase comparator detects a voltage droop, it quantifies the magnitude of the power supply voltage droop to obtain a set of digital control signals OUT[7:0] (Droop[7:0]=OUT[7:0]). This set of digital control signals is used to drive the frequency adjustment unit to adjust the input electrical signal. Compared with the traditional voltage comparator, the phase comparator working in the phase domain in this embodiment has a wide working range (multi-phase comparison), and the non-ideal effects introduced are small, which can basically ensure linear operation.
[0030] Furthermore, a D flip-flop (DFF) can be used as the phase comparator to detect the power supply voltage droop. The area of the phase comparator is small, and the phase comparator and the frequency adjustment unit can be separated. The phase comparator can be placed at various positions on the chip to detect the power supply voltage droop.
[0031] In an embodiment of the present invention, the digital control signal is a multi-bit output signal, which is used to characterize the change in the power supply voltage to drive the frequency adjustment unit to adjust the input electrical signal.
[0032] In this embodiment, the phase comparator compares multiple clock phases with the reference phase phase[0], obtains the phase offset when detecting a droop, and converts the phase offset into a digital control signal OUT[7:0], which is used to represent the change in the power supply voltage.
[0033] In one embodiment of the present invention, the control unit further includes a phase selector configured to automatically adjust a threshold ratio for detecting a change in the power supply voltage based on a phase shift.
[0034] In this embodiment, the amplitude of the power supply voltage droop detection can be adjusted by adjusting the threshold gear of the phase selector. The larger the threshold gear of the phase selector, the larger the amount of phase shift detected, which represents a larger power supply voltage droop. An 8-bit phase selector is used in this embodiment, and phases P33 to P40 are selected for phase comparison. During the operation of the control unit, when detecting the power supply voltage droop by comparing the phase changes of the multi-phase delay line (the changes of phases P33 to P40) through a phase comparator, the phase selector can automatically adjust the threshold ratio for detecting the change in the power supply voltage based on the phase shift and adjust the threshold gear.
[0035] In one embodiment of the present invention, the frequency adjustment unit includes: a digital-to-analog converter (Digital Analog Converter, DAC) and a voltage-controlled oscillator (Voltage Controlled Oscillator, VCO) coupled to the output terminal of the digital-to-analog converter; wherein, The digital-to-analog converter is configured to adjust the input current or voltage of the voltage-controlled oscillator according to the electrical control signal; wherein, the electrical signal includes: current or voltage; The voltage-controlled oscillator is configured to generate a desired target output clock frequency of the digital frequency-locked loop according to the input current or voltage.
[0036] In one embodiment of the present invention, the frequency adjustment unit further includes: a frequency discriminator and a digital loop filter (Digital Loop Filter, DLF), and the signal feedback terminal of the frequency discriminator is connected to the output terminal of the voltage-controlled oscillator; wherein, the frequency discriminator is configured to detect a change in the output clock frequency and generate a feedback signal; the digital loop filter is used to filter the feedback signal to stabilize the output frequency.
[0037] In one embodiment of the present invention, the frequency adjustment unit further includes: a loop frequency divider, and the loop frequency divider is coupled to the output terminal of the phase comparator of the control unit; the digital control signal is further configured to adjust the frequency division ratio of the loop frequency divider to dynamically reduce the target frequency of the frequency-locked loop.
[0038] In an embodiment of the present invention, the frequency adjustment unit further includes: a voltage regulator and a current pull-down module; the voltage regulator is coupled to the digital-to-analog converter of the frequency adjustment unit, and the voltage regulator is configured to provide a regulated voltage source and reduce power supply noise; the current pull-down module is coupled to the output of the phase comparator of the control unit; the current pull-down module is configured to reduce the clock frequency according to the electrical control signal.
[0039] In the frequency adjustment unit of this embodiment, after the control unit detects a change in the power supply voltage and obtains the amount of change in the power supply voltage, a part of the power supply voltage droop amount OUT[7:0] output by the control unit is shunted to the current pull-down module to ground, thereby reducing the clock frequency F. fb At the same time, the voltage droop amount is output to the loop frequency divider to reduce the division ratio (N.F), so that the frequency-locked loop is locked to a lower frequency.
[0040] Among them, the frequency adjustment unit maintains frequency locking throughout the process and satisfies the following frequency formula: ; Among them, F ref represents the reference frequency; F fb represents the clock frequency; N.F is the division ratio of the loop frequency divider, N is the integer component, and.F is the fractional component.
[0041] Specifically, the phase comparator of the control unit outputs a digital control signal OUT[7:0] representing the amount of change in the power supply voltage according to the offset between the clock phase and the reference clock, filters and processes it through a digital filter, outputs a smooth digital control signal to the digital-to-analog converter, converts the digital control signal into a voltage or current signal and inputs it to the voltage-controlled oscillator, so that the voltage-controlled oscillator adjusts the output clock frequency of the voltage-controlled oscillator according to the input current or voltage. Then, the clock frequency output by the voltage-controlled oscillator is input to the loop frequency divider for frequency division, and the generated feedback clock is input to the frequency discriminator. In this way, the output clock frequency will be detected and a feedback signal will be generated and fed back to the digital filter to form a closed-loop control system. In this way, by using a phase comparator, the frequency-locked loop is downshifted by detecting the power supply voltage droop in the phase domain, with fast speed and high accuracy.
[0042] Embodiment 2 Refer to Figure 8 As shown, the present invention also provides a digital frequency-locked loop frequency control method, including: S10. Generate an electrical control signal according to the phase offset caused by detecting a change in the power supply voltage; S20. Adjust the input electrical signal according to the electrical control signal to control the output clock frequency.
[0043] The digital frequency-locked loop frequency control method provided by this embodiment detects voltage droop in the phase domain, generates an electrical control signal based on the phase shift caused by the detected power supply voltage change to control the operating current of the voltage-controlled oscillator of the frequency-locked loop, so as to reduce the output clock frequency of the frequency-locked loop, thereby avoiding the problems brought by the non-linear response introduced by the traditional voltage comparator. And because the time granularity based on phase adjustment is finer than that based on voltage adjustment, it is convenient to improve the control accuracy of the clock frequency.
[0044] Optionally, in some embodiments, generating the electrical control signal according to the phase shift caused by detecting the power supply voltage change includes: generating a plurality of clock phase signals; comparing the phase shift amounts between the plurality of clock phase signals, and converting the phase shift amounts into digital control signals.
[0045] Optionally, in some embodiments, the digital control signal is a multi-bit output signal for characterizing the power supply voltage change amount.
[0046] The digital frequency-locked loop frequency control method provided by this embodiment detects the voltage droop of the power supply by comparing the changes in the clock phases generated by the multi-phase delay lines through the phase comparator of the control unit, generates an electrical control signal based on the phase shift amount obtained from the detected changes in the clock phase signals, and adjusts the output clock frequency of the voltage-controlled oscillator according to the electrical control signal through the frequency adjustment unit to achieve the control of the output frequency of the digital frequency-locked loop.
[0047] Specifically, when the power supply voltage VDD changes, the phase comparator set in the phase domain compares a plurality of clock phases generated by the multi-phase delay lines, compares the number of phases that change and the phase shift amount, and quantifies the magnitude of the voltage droop to obtain a set of digital control signals OUT[7:0]. A part of this set of digital control signals is output to the current pull-down module to ground, thereby reducing the clock frequency. At the same time, the digital control signals OUT[7:0] are also output to the loop frequency divider of the frequency adjustment unit to reduce the division ratio (N.F), so that the frequency-locked loop is locked to a lower frequency. In this way, the power supply voltage droop detection and the frequency-locked loop frequency reduction work in the phase domain, which is a linear process, avoiding the problems brought by the non-linear response introduced by the traditional voltage comparator. And because the time granularity based on phase adjustment is finer than that based on voltage adjustment, it is convenient to improve the control accuracy of the clock frequency.
[0048] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.
[0049] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized.
[0050] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. A digital frequency locked loop, characterized in that: include: a control unit configured to generate an electrical control signal according to a phase shift caused by a change in the detected power supply voltage; The frequency adjustment unit is coupled to the control unit and is configured to adjust the input electrical signal according to the electrical control signal to control the output clock frequency.
2. The digital frequency locked loop according to claim 1, characterized in that: The control unit comprises: a multi-phase delay line configured to generate a plurality of clock phase signals; The phase comparator is coupled to the multi-phase delay line and configured to compare the phase offsets between the multiple clock phase signals and convert the phase offsets into a digital control signal.
3. The digital frequency locked loop according to claim 2, characterized in that: The digital control signal is a multi-bit output signal used to characterize the change in power supply voltage so as to drive the frequency adjustment unit to adjust the input electrical signal.
4. The digital frequency locked loop according to claim 1, characterized in that: The frequency adjustment unit includes: a digital-to-analog converter and a voltage-controlled oscillator coupled to the output terminal of the digital-to-analog converter; wherein, The digital-to-analog converter is configured to adjust an input current or voltage of a voltage-controlled oscillator according to the electrical control signal; wherein the electrical signal comprises: a current or a voltage; The voltage controlled oscillator is configured to generate a desired target output clock frequency of a digital frequency locked loop according to an input current or voltage.
5. The digital frequency locked loop according to claim 1, characterized in that: The frequency adjustment unit further includes: a frequency discriminator and a digital loop filter, wherein the signal feedback end of the frequency discriminator is connected to the output end of the voltage controlled oscillator; wherein, The frequency discriminator is configured to detect the frequency change of the output clock and generate a feedback signal; The digital loop filter is used for filtering the feedback signal to stabilize the output frequency.
6. The digital frequency locked loop according to claim 1, characterized in that: The frequency adjustment unit further includes: a loop frequency divider, the loop frequency divider being coupled to an output end of the phase comparator of the control unit; The digital control signal is further configured to adjust a division ratio of the loop frequency divider to dynamically reduce a target frequency of the frequency locked loop.
7. The digital frequency locked loop according to claim 1, characterized in that: The frequency adjustment unit further includes: a voltage regulator and a current pull-down module; the voltage regulator is coupled to the digital-to-analog converter of the frequency adjustment unit, and the voltage regulator is configured to provide a regulated voltage source and reduce power supply noise; The current pull-down module is coupled to the output end of the phase comparator of the control unit; the current pull-down module is configured to reduce the clock frequency according to the electrical control signal.
8. The digital frequency locked loop according to claim 1, characterized in that: The control unit further includes a phase selector configured to automatically adjust a threshold ratio of power supply voltage variation detection based on the phase shift.
9. A digital frequency locked loop frequency control method, characterized in that: The method comprises: generating an electrical control signal based on a phase shift caused by a change in the detected power supply voltage; The input electrical signal is adjusted according to the electrical control signal to control the output clock frequency.
10. The digital frequency locked loop frequency control method according to claim 9, characterized in that: The step of generating an electrical control signal according to the phase shift caused by the change in the power supply voltage comprises: generating a plurality of clock phase signals; Phase offsets between the plurality of clock phase signals are compared, and the phase offsets are converted into digital control signals.