Quantized extraction for phase-locked loop oscillators

Abstract

The invention relates to quantization extraction for a phase-locked loop oscillator. An example apparatus includes quantized feedback circuitry (QFC) (216) including an input terminal coupled to an output terminal of voltage controlled oscillator (VCO) circuitry (210) and an input terminal coupled to an output terminal of a first frequency divider circuitry (FDC) (212). The example apparatus also includes a second FDC (214) including an output terminal coupled to an input terminal of a phase frequency detector (PFD) circuitry (202) and an input terminal coupled to an output terminal of the first FDC (212). Moreover, the example apparatus includes masking logic circuitry (218) including an output terminal coupled to an input terminal of the QFC (216), an input terminal coupled to the output terminal of the VCO circuitry (210), and an input terminal coupled to the output terminal of the second FDC (214).

Description

Technical Field

[0001] This specification generally relates to oscillators, and more particularly to methods, apparatus, and articles of manufacture for using quantization extraction in a phase-locked loop oscillator. Background Art

[0002] Many electronic devices, such as transmitters, receivers, televisions, computers, computer peripherals, mobile devices, etc., include electronic oscillators. An electronic oscillator is a circuit that generates a periodic, oscillating, or alternating current (AC) signal powered by a direct current (DC) source. An electronic oscillator can be implemented as at least one of a linear (e.g., harmonic) oscillator or a nonlinear (e.g., relaxation) oscillator. A linear oscillator can be implemented by a crystal oscillator. A nonlinear oscillator can be implemented by at least one of a multivibrator, a Pearson-Anson oscillator, a ring oscillator, a delay line oscillator, or a Royer oscillator. A voltage-controlled oscillator (VCO) can be implemented by at least one of a linear oscillator or a nonlinear oscillator. A VCO is used in a phase-locked loop (PLL) oscillator. Summary of the Invention

[0003] For methods, apparatus, and articles of manufacture for using quantization extraction in a phase-locked loop oscillator, an example apparatus includes a voltage-controlled oscillator (VCO) circuit system that includes an output terminal and an input terminal; and a first divider circuit system that includes a first output terminal, a second output terminal, and an input terminal coupled to the output terminal of the VCO circuit system. Also, the example apparatus includes a quantization feedback circuit system that includes an output terminal, a first input terminal, a second input terminal, and a third input terminal, where the first input terminal of the quantization feedback circuit system is coupled to the output terminal of the VCO circuit system and the second input terminal of the quantization feedback circuit system is coupled to the first output terminal of the first divider circuit system. The example apparatus further includes a second divider circuit system that includes an output terminal and an input terminal coupled to the second output terminal of the first divider circuit system; and a phase frequency detector (PFD) circuit system that includes an output terminal and an input terminal coupled to the output terminal of the second divider circuit system. Also, the example apparatus includes a masking logic circuit system that includes an output terminal coupled to the third input terminal of the quantization feedback circuit system, a first input terminal coupled to the output terminal of the VCO circuit system, and a second input terminal coupled to the output terminal of the second divider circuit system. The example apparatus further includes an adder circuit system that includes an output terminal coupled to the input terminal of the VCO circuit system, a first input terminal coupled to the output terminal of the PFD circuit system, and a second input terminal coupled to the output terminal of the quantization feedback circuit system.

[0004] For methods, apparatuses, and articles of manufacture using quantization extraction in a phase-locked loop oscillator, an example apparatus includes a voltage-controlled oscillator (VCO) circuit system that includes an output terminal and an input terminal; and a multi-mode frequency divider (MMFD) circuit system that includes an output terminal and an input terminal coupled to the output terminal of the VCO circuit system. Also, the example apparatus includes a second frequency divider circuit system that includes an output terminal and an input terminal coupled to the output terminal of the MMFD circuit system; and a first phase frequency detector (PFD) circuit system that includes an output terminal and an input terminal coupled to the output terminal of the second frequency divider circuit system. The example apparatus further includes a quantization extraction circuit system that includes an output terminal, a first input terminal coupled to the output terminal of the VCO circuit system, and a second input terminal coupled to the output terminal of the MMFD circuit system. Also, the example apparatus includes a switching circuit system that includes an output terminal, a first input terminal, and a second input terminal, where the first input terminal of the switching circuit system is coupled to the output terminal of the quantization extraction circuit system. The example apparatus further includes a second PFD circuit system that includes an output terminal and an input terminal coupled to the output terminal of the switching circuit system; and a masking logic circuit system that includes an output terminal coupled to the second input terminal of the switching circuit system, a first input terminal coupled to the output terminal of the VCO circuit system, and a second input terminal coupled to the output terminal of the second frequency divider circuit system. Also, the example apparatus includes an adder circuit system that includes an output terminal coupled to the input terminal of the VCO circuit system, a first input terminal coupled to the output terminal of the first PFD circuit system, and a second input terminal coupled to the output terminal of the second PFD circuit system.

[0005] For a method, apparatus, and article of manufacture using quantization extraction in a phase-locked loop oscillator, an example apparatus includes a voltage-controlled oscillator (VCO) circuit system that includes an output terminal and an input terminal; and a multi-mode frequency divider (MMFD) circuit system that includes an output terminal, a first input terminal, and a second input terminal, where the first input terminal of the MMFD circuit system is coupled to the output terminal of the VCO circuit system. Also, the example apparatus includes a second frequency divider circuit system that includes an output terminal and an input terminal coupled to the output terminal of the MMFD circuit system; and a phase frequency detector (PFD) circuit system that includes an output terminal and an input terminal coupled to the output terminal of the second frequency divider circuit system. The example apparatus further includes a delta-sigma modulator (DSM) circuit system that includes an output terminal coupled to the second input terminal of the MMFD circuit system and an input terminal coupled to the output terminal of the MMFD circuit system. Also, the example apparatus includes a quantization extraction circuit system that includes an output terminal, a first input terminal coupled to the output terminal of the VCO circuit system, and a second input terminal coupled to the output terminal of the DSM circuit system. The example apparatus further includes a switching circuit system that includes an output terminal, a first input terminal, and a second input terminal, where the first input terminal of the switching circuit system is coupled to the output terminal of the quantization extraction circuit system. Also, the example apparatus includes a masking logic circuit system that includes an output terminal coupled to the second input terminal of the switching circuit system, a first input terminal coupled to the output terminal of the VCO circuit system, and a second input terminal coupled to the output terminal of the second frequency divider circuit system. The example apparatus further includes an adder circuit system that includes an output terminal coupled to the input terminal of the VCO circuit system, a first input terminal coupled to the output terminal of the PFD circuit system, and a second input terminal coupled to the output terminal of the switching circuit system.

[0006] For a method, apparatus, and article of manufacture using quantization extraction in a phase-locked loop oscillator, an example method includes generating a first quantization feedback signal and a second quantization feedback signal based on a masking signal, the first quantization feedback signal and the second quantization feedback signal for capturing quantization information present in a frequency divider output signal. The example method further includes generating the masking signal based on a feedback signal, the masking signal for masking redundant information present in the quantization information, the feedback signal based on the frequency divider output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram of an example integrated circuit (IC) for deserializing an input data stream that includes serialized data via a flat panel display (FDP) link interface.

[0008] Figure 2 For Figure 1 a block diagram of an example implementation of a clock generation circuit system of

[0009] Figure 3 A flowchart of example machine-readable instructions or example operations that are executed, instantiated, or performed by an example programmable circuit system implementation of a clock generation circuit system that can be used Figure 2 to execute, instantiate, or perform the example machine-readable instructions or example operations of an example programmable circuit system implementation of a clock generation circuit system that can be used

[0010] Figure 4 An illustrative diagram depicting an example first frequency response of a clock generation circuit system compared to an example second frequency response of other clock generation circuit systems Figure 2 to an example second frequency response of other clock generation circuit systems

[0011] Figure 5 An illustrative diagram depicting an example first frequency response of a clock generation circuit system compared to an example second frequency response of other clock generation circuit systems Figure 2 to an example second frequency response of other clock generation circuit systems

[0012] Figure 6A An illustrative diagram depicting an example output signal of an adder circuit system of a clock generation circuit system compared to an example output signal of other clock generation circuit systems Figure 2 to an example output signal of other clock generation circuit systems

[0013] Figure 6B An illustrative diagram depicting an example output signal of an adder circuit system of a clock generation circuit system compared to an example output signal of other clock generation circuit systems Figure 2 to an example output signal of other clock generation circuit systems

[0014] Figure 7 A block diagram of a clock generation circuit system of a first example implementation that includes Figure 2 a first frequency divider circuit system and a quantization feedback circuit system Figure 2 to a first frequency divider circuit system and a quantization feedback circuit system

[0015] Figure 8 A block diagram of a clock generation circuit system of an example implementation that includes Figure 7 a quantization extraction circuit system, a switching circuit system, and a masking logic circuit system Figure 7 to a quantization extraction circuit system, a switching circuit system, and a masking logic circuit system

[0016] Figure 9 A flowchart of example machine-readable instructions or example operations that are executed, instantiated, or performed by an example programmable circuit system implementation of a clock generation circuit system that can be used Figure 7 to execute, instantiate, or perform the example machine-readable instructions or example operations of an example programmable circuit system implementation of a clock generation circuit system that can be used

[0017] Figure 10 An illustrative diagram depicting example operations of a clock generation circuit system Figure 7 to a clock generation circuit system

[0018] Figure 11 An illustrative diagram depicting a clock generation circuit system having a matched PFD circuit system Figure 7Example first frequency response of a clock generation circuit system and of a PFD circuit system having a first delay mismatch Figure 7 Graphical illustration of an example second frequency response of a clock generation circuit system

[0019] Figure 12 For depicting an example first frequency response of a clock generation circuit system having a matched PFD circuit system Figure 7 Example first frequency response of a clock generation circuit system and of a PFD circuit system having a first delay mismatch Figure 7 Example second frequency response of a clock generation circuit system and of a PFD circuit system having a second delay mismatch Figure 7 Graphical illustration of an example third frequency response of a clock generation circuit system having a PFD circuit system with a second delay mismatch

[0020] Figure 13 For including Figure 2 Block diagram of a clock generation circuit system of a second example implementation of a first frequency divider circuit system and a quantization feedback circuit system Figure 2 Block diagram of a clock generation circuit system

[0021] Figure 14 For including Figure 13 Block diagram of a clock generation circuit system of an example implementation of a quantization extraction circuit system, a switching circuit system, and a masking logic circuit system Figure 13 Block diagram of a clock generation circuit system

[0022] Figure 15 For representing example machine-readable instructions or example operations that may be executed, instantiated, or performed by an example programmable circuit system implementation of a clock generation circuit system Figure 13 Flowchart of example machine-readable instructions or example operations that may be executed, instantiated, or performed by an example programmable circuit system implementation of a clock generation circuit system

[0023] Figure 16 Block diagram of an example processing platform that includes a programmable circuit system that is structured to execute, instantiate, or perform example machine-readable instructions or perform Figure 3 , 9 or at least one of 15 to implement Figure 2 , 7 a clock generation circuit system of at least one of 8, 13, or 14

[0024] The same reference numerals or other reference designators are used in the drawings to denote the same or similar (functionally, structurally, or both structurally and functionally) features Detailed Description

[0025] The drawings are not necessarily to scale. In general, like reference numerals in the drawings and the specification refer to like or similar parts. Although the drawings show regions having clear lines and boundaries, some or all of these lines or boundaries may be idealized. In reality, the boundaries and lines may be unobservable, blended, or irregular.

[0026] A phase-locked loop (PLL) oscillator is implemented with a voltage-controlled oscillator (VCO). For example, a PLL oscillator (sometimes referred to as a PLL) can be implemented by a phase frequency detector (PFD) and a VCO. In an example operation of a PLL, the VCO generates a periodic output signal having a specific frequency in response to an input voltage, and the PFD compares the phase of the output signal with the phase of a reference input signal and generates an output signal representing the comparison. The VCO adjusts the output signal to match the phase in response to the output signal from the PFD. PLLs are used for computer clock synchronization, demodulation, and frequency synthesis in various electronic applications such as radios, telecommunications, computers, and other electronic applications.

[0027] For example, a PLL is used to generate one or more clock signals for a graphics processing unit of an electronic device such as a laptop computer, a tablet computer, a flat panel display (e.g., in a motor vehicle), or a television. In some instances, a timing controller of a display device communicates with a graphics processing unit of the display device using a standard such as a flat panel display (FPD) link (FPD link). FPD links are commonly used in navigation systems, in-vehicle entertainment, rearview cameras, and driver assistance systems in motor vehicles. For example, an FPD link provides a framework for transmitting clock, data, and control signals between a parent device and one or more child devices.

[0028] In some instances, a transmitter and a receiver communicate through an FPD link interface operating at different rates to reduce crosstalk. Crosstalk can include interference caused by unintentional coupling to another communication channel. For example, the transmitter and the receiver operate at non-integer rates. In these instances, the transmitter and the receiver utilize a fractional PLL having a reference frequency of about 25 megahertz (MHz) and an output frequency between six gigahertz (GHz) and 12 GHz. The fractional PLL generates an output signal having a frequency that is a non-integer multiple of the frequency of the reference signal. To enable the device to track drift in the received data, the PLL has a relatively large bandwidth (e.g., 5 - 10 MHz).

[0029] Phase noise and reference spurs (e.g., harmonics in the frequency response on a PLL) can be amplified by frequency multiplication in a PLL. To counteract noise amplification, some PLLs include a delta-sigma modulator (DSM) to "shape" the noise by moving the noise to a higher frequency range outside the range of interest of the PLL. Consequently, the noise can be removed by low-pass filtering. However, such filtering is difficult to implement when operating in the gigahertz frequency range.

[0030] A first technique for addressing quantization noise present in a PLL output signal utilizes a multi-stage architecture that includes an integer PLL that generates an intermediate signal and provides the intermediate signal to a fractional PLL before generating the output signal. Since the DSM operates at a higher frequency, the first technique achieves sufficient quantization noise shaping for gigahertz operation. However, the multi-stage nature of the first technique consumes more semiconductor die area and more power than other techniques.

[0031] A second technique for addressing quantization noise present in a PLL output signal utilizes multiple phase detectors implemented by multiple exclusive-OR (XOR) gates that process feedback signals in parallel. In the second technique, the number of XOR gates utilized is proportional to the multiplication factor of the PLL. However, if there is a delay mismatch in the transmission path to the multiple XOR gates, the second technique cannot shape the quantization noise because the multiple phase detectors will operate on corrupted data (e.g., due to mismatched delays). Also, because multiple XOR gates are utilized, the charge pump of the second technique can operate in a non-linear region, which reduces the impact of quantization noise shaping.

[0032] Examples described herein include a fractional PLL that shapes quantization noise without consuming more semiconductor die area or more power than other techniques. Also, examples described herein maintain the charge pump operating in a linear region, independent of the multiplication factor of the PLL. Additionally, examples described herein maintain quantization noise shaping even when there is a delay mismatch in the transmission path between circuit systems.

[0033] Figure 1 A block diagram of an example integrated circuit (IC) 100 for deserializing an input data stream that includes serialized data via an FDP link interface. In Figure 1In an example, IC 100 includes an example input buffer 102, an example equalizer circuit system 104, an example clock data recovery (CDR) circuit system 106, an example deserialization circuit system 108, an example decoder circuit system 110, an example first encoder circuit system 112, an example data output circuit system 114, an example clock generation circuit system 116, an example timing and control circuit system 118, an example communication controller circuit system 120, an example queue circuit system 122, an example second encoder circuit system 124, and an example output buffer 126. In Figure 1 In an example, IC 100 is a deserialization device capable of receiving serialized sensor data from a source via an FPD link interface. When paired with a serializer, IC 100 receives data from imagers, support cameras, satellite radio detection and ranging (RADAR) sensors, and other sensors (such as time-of-flight (ToF) sensors and light detection and ranging (LIDAR) sensors).

[0034] In Figure 1 In the illustrated example, input buffer 102 buffers the serialized sensor data received across the differential input / output (I / O) terminals (such as I / O+ and I / O-) of IC 100. In Figure 1 In an example, input buffer 102 is implemented by combinational logic circuit system, sequential logic circuit system, or a combination of combinational logic circuit system and sequential logic circuit system. Also, a first input terminal of input buffer 102 is coupled to a first capacitor 128. In Figure 1 In an example, a second input terminal of input buffer 102 is coupled to a second capacitor 130. Also, an output terminal of input buffer 102 is coupled to equalizer circuit system 104.

[0035] In Figure 1 In the illustrated example, equalizer circuit system 104 equalizes the input signal to compensate for signal degradation (such as from a communication channel, from an interconnect circuit system, etc.). In Figure 1 In an example, equalizer circuit system 104 is implemented by combinational logic circuit system, sequential logic circuit system, or a combination of combinational logic circuit system and sequential logic circuit system. Also, an input terminal of equalizer circuit system 104 is coupled to the output terminal of input buffer 102. In Figure 1 In an example, an output terminal of equalizer circuit system 104 is coupled to an input terminal of CDR circuit system 106 and a first input terminal of deserialization circuit system 108.

[0036] In Figure 1 In the illustrated example, CDR circuit system 106 extracts timing information from the received serialized sensor data, thereby allowing the timing of the serialized sensor data to be accurately determined without separate clock information.Figure 1 In an example, the CDR circuit system 106 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, an input terminal of the CDR circuit system 106 is coupled to an output terminal of the equalizer circuit system 104. In Figure 1 an example, an output terminal of the CDR circuit system 106 is coupled to a second input terminal of the deserialization circuit system 108.

[0037] In Figure 1 the illustrated example, the deserialization circuit system 108 deserializes the serialized sensor data to format the sensor data into a data structure. In Figure 1 an example, the deserialization circuit system 108 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, a first input terminal of the deserialization circuit system 108 is coupled to an output terminal of the equalizer circuit system 104. In Figure 1 an example, a second input terminal of the deserialization circuit system 108 is coupled to an output terminal of the CDR circuit system 106. Also, an output terminal of the deserialization circuit system 108 is coupled to an input terminal of the decoder circuit system 110.

[0038] In Figure 1 the illustrated example, the decoder circuit system 110 decodes the deserialized sensor data to determine a target of the deserialized sensor data. In Figure 1 an example, the decoder circuit system 110 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, an input terminal of the decoder circuit system 110 is coupled to an output terminal of the deserialization circuit system 108. In Figure 1 an example, an output terminal of the decoder circuit system 110 is coupled to a first input terminal of the encoder circuit system 112.

[0039] In Figure 1 the illustrated example, the encoder circuit system 112 encodes the deserialized sensor data into an internal bus format for transmission to a target. In Figure 1 an example, the encoder circuit system 112 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, a first input terminal of the encoder circuit system 112 is coupled to an output terminal of the decoder circuit system 110. In Figure 1 an example, a second input terminal of the encoder circuit system 112 is coupled to a first output terminal of the clock generation circuit system 116. Also, an output terminal of the encoder circuit system 112 is coupled to a first input terminal of the data output circuit system 114.

[0040] In Figure 1 the illustrated example of, data output circuitry 114 transmits encoded sensor data to a destination. In Figure 1 the example of, data output circuitry 114 implements a physical layer circuitry. Also, a first input terminal of data output circuitry 114 is coupled to an output terminal of encoder circuitry 112. In Figure 1 the example of, a second input terminal of data output circuitry 114 is coupled to a second output terminal of clock generation circuitry 116. Also, a first output terminal of data output circuitry 114 is coupled to an internal bus (e.g., to transmit clock data). In Figure 1 the example of, a second output terminal of data output circuitry 114 is coupled to an internal bus (e.g., to transmit encoded sensor data). Also, general-purpose I / O (GPIO) terminals of data output circuitry 114 are coupled to the internal bus.

[0041] In Figure 1 the illustrated example of, clock generation circuitry 116 generates a clock signal for IC 100. In Figure 1 the example of, clock generation circuitry 116 is implemented by the example fractional PLL described herein. Also, a first output terminal of clock generation circuitry 116 is coupled to a second input terminal of encoder circuitry 112. In Figure 1 the example of, a second output terminal of clock generation circuitry 116 is coupled to a second input terminal of data output circuitry 114. Also, a third output terminal of clock generation circuitry 116 is coupled to an input terminal of timing and control circuitry 118. In Figure 1 the example of, an input terminal of clock generation circuitry 116 is coupled to an oscillator (e.g., a crystal oscillator) to receive a reference clock signal (e.g., REFCLK).

[0042] In Figure 1 the illustrated example of, in response to the clock signal, timing and control circuitry 118 generates timing and control signals for communication controller circuitry 120, queue circuitry 122, and encoder circuitry 124. In Figure 1 the example of, timing and control circuitry 118 is implemented by combinational logic circuitry, sequential logic circuitry, or a combination of combinational logic circuitry and sequential logic circuitry. Also, an input terminal of timing and control circuitry 118 is coupled to the third output terminal of clock generation circuitry 116. In Figure 1 the example of, a first output terminal of timing and control circuitry 118 is coupled to a first input terminal of communication controller circuitry 120. In Figure 1In the example, the second output terminal of the timing and control circuit system 118 is coupled to the first input terminal of the queue circuit system 122. Also, the third output terminal of the timing and control circuit system 118 is coupled to the first input terminal of the encoder circuit system 124.

[0043] In Figure 1 the illustrated example, the communication controller circuit system 120 controls communication between the internal bus control IC 100 and other devices via an internal bus. In Figure 1 the example, the communication controller circuit system 120 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, the first input terminal of the communication controller circuit system 120 is coupled to the first output terminal of the timing and control circuit system 118. In Figure 1 the example, the second input terminal of the communication controller circuit system 120 is coupled to the internal bus to receive an identifier (ID) of device communication via the internal bus. Also, the first I / O terminal of the communication controller circuit system 120 is coupled to the internal bus to receive data from and transmit data to a device via the internal bus. In Figure 1 the example, the second I / O terminal of the communication controller circuit system 120 is coupled to the internal bus to receive a clock signal from and transmit a clock signal to a device via the internal bus. Also, the output terminal of the communication controller circuit system 120 is coupled to the second input terminal of the queue circuit system 122.

[0044] In Figure 1 the illustrated example, the queue circuit system 122 queues data received from a device via the internal bus. In Figure 1 the example, the queue circuit system 122 is implemented by a first-in-first-out (FIFO) queue. Also, the first input terminal of the queue circuit system 122 is coupled to the second output terminal of the timing and control circuit system 118. In Figure 1 the example, the second input terminal of the queue circuit system 122 is coupled to the output terminal of the communication controller circuit system 120. Also, the output terminal of the queue circuit system 122 is coupled to the second input terminal of the encoder circuit system 124.

[0045] In Figure 1 the illustrated example, the encoder circuit system 124 encodes data into a serialized format for transmission to a serializer via an FPD link interface. In Figure 1 the example, the encoder circuit system 124 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, the first input terminal of the encoder circuit system 124 is coupled to the third output terminal of the timing and control circuit system 118. In Figure 1In an example, a second input terminal of the encoder circuitry 124 is coupled to an output terminal of the queue circuitry 122. Also, an output terminal of the encoder circuitry 124 is coupled to an input terminal of the output buffer 126.

[0046] In Figure 1 the illustrated example, the output buffer 126 buffers the serialized data received from the encoder circuitry 124 and transmits the serialized data across differential I / O terminals (e.g., I / O+ and I / O−) of the IC 100. In Figure 1 an example, the output buffer 126 is implemented by combinational logic circuitry, sequential logic circuitry, or a combination of combinational logic circuitry and sequential logic circuitry. Also, an input terminal of the output buffer 126 is coupled to an output terminal of the encoder circuitry 124. In Figure 1 an example, a first output terminal of the output buffer 126 is coupled to the capacitor 128. Also, a second output terminal of the output buffer 126 is coupled to the capacitor 130.

[0047] As described above, the IC 100 deserializes serialized sensor data. For example, the IC 100 is implemented as a camera, a satellite RADAR sensor, a ToF sensor, and a LIDAR sensor. In some examples, the IC 100 is implemented as a driver assistance system, such as those in autonomous vehicles (e.g., a camera monitoring system, a front view camera, a surround view system, a rear view camera, a driver monitoring system, an outside rearview mirror display, etc.). In some examples, the IC 100 is implemented as a safety sensor, a monitoring sensor, an industrial sensor, and a medical imaging sensor.

[0048] Figure 2 For Figure 1 a block diagram of an example implementation of the clock generation circuitry 116. In Figure 2 an example, the clock generation circuitry 116 includes an example phase frequency detector (PFD) circuitry 202, an example adder circuitry 204, an example charge pump circuitry 206, an example low pass filter circuitry 208, an example voltage controlled oscillator (VCO) circuitry 210, an example first divider circuitry 212, an example second divider circuitry 214, an example quantization feedback circuitry 216, and an example masking logic circuitry 218. In Figure 2 an example, the clock generation circuitry 116 generates an output signal having shaped quantization noise and having a frequency in the range of several gigahertz (e.g., 6 - 12 GHz).

[0049] In Figure 2In the illustrated example, the clock generation circuitry 116 includes a frequency extraction loop and a quantization extraction loop nested within the frequency extraction loop. For example, the frequency extraction loop includes a PFD circuitry 202, an adder circuitry 204, a charge pump circuitry 206, a low pass filter circuitry 208, a VCO circuitry 210, a divider circuitry 212, and a divider circuitry 214. And, for example, the quantization extraction loop includes a quantization feedback circuitry 216 and an example masking logic circuitry 218. In Figure 2 the example, the circuitry of the feedback extraction loop is configured to sample the output signal and compare at least one of the phase, frequency, or both the phase and frequency of the output signal with at least one of the phase, frequency, or both the phase and frequency of the reference signal. In Figure 2 the example, the circuitry of the quantization extraction loop extracts and retains quantization information (e.g., one or more rising edges in the output signal) not retained in the frequency extraction loop.

[0050] In Figure 2 the illustrated example, the PFD circuitry 202 compares a reference clock signal with a feedback signal based on the output signal of the clock generation circuitry 116. For example, the reference clock signal has a reference frequency (F REF ) of 500 MHz. In Figure 2 the example, the PFD circuitry 202 is implemented by combinational logic circuitry, sequential logic circuitry, or both combinational logic circuitry and sequential logic circuitry. And, a first input terminal of the PFD circuitry 202 is coupled to an oscillator (e.g., a crystal oscillator) to receive the reference clock signal (e.g., REFCLK). In Figure 2 the example, a second input terminal of the PFD circuitry 202 is coupled to an output terminal of the divider circuitry 214. And, a first output terminal and a second output terminal of the PFD circuitry 202 are coupled to a first input terminal and a second input terminal of the adder circuitry 204, respectively.

[0051] In Figure 2 the illustrated example, the PFD circuitry 202 determines earlier or more frequently which of the reference clock signal and the feedback signal has a zero crossing. For example, when the PFD circuitry 202 detects that the reference clock signal has a zero crossing before the feedback signal, the PFD circuitry 202 generates a signal with a positive voltage at the first output terminal. And, when the PFD circuitry 202 detects that the feedback signal has a zero crossing before the reference clock signal, the PFD circuitry 202 generates a signal with a negative voltage at the second output terminal. In one example, the PFD circuitry 202 operates in a different manner.

[0052] In Figure 2In the illustrated example, the adder circuit system 204 adds the voltages of the signals output by the PFD circuit system 202 and the quantization feedback circuit system 216 to generate a charge pump control signal. In Figure 2 the example, the adder circuit system 204 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. Also, a first input terminal and a second input terminal of the adder circuit system 204 are respectively coupled to a first output terminal and a second output terminal of the PFD circuit system 202. In Figure 2 the example, a third input terminal and a fourth input terminal of the adder circuit system 204 are respectively coupled to a first output terminal and a second output terminal of the quantization feedback circuit system 216. Also, an output terminal of the adder circuit system 204 is coupled to an input terminal of the charge pump circuit system 206.

[0053] In Figure 2 the illustrated example, the charge pump circuit system 206 generates a control signal for the VCO circuit system 210 in response to the charge pump control signal generated by the adder circuit system 204. In Figure 2 the example, the charge pump circuit system 206 is implemented by a bipolar switched current source. Also, an input terminal of the charge pump circuit system 206 is coupled to an output terminal of the adder circuit system 204. In Figure 2 the example, an output terminal of the charge pump circuit system 206 is coupled to an input terminal of the low pass filter circuit system 208.

[0054] In Figure 2 the illustrated example, the low pass filter circuit system 208 filters out (e.g., removes) frequencies higher than a cut-off frequency determined by the electronic components of the low pass filter circuit system 208. In Figure 2 the example, the low pass filter circuit system 208 is implemented by a resistor-capacitor (RC) circuit. Also, an input terminal of the low pass filter circuit system 208 is coupled to an output terminal of the charge pump circuit system 206. In Figure 2 the example, an output terminal of the low pass filter circuit system 208 is coupled to an input terminal of the VCO circuit system 210. In an example operation, the low pass filter circuit system 208 filters the control signal generated by the charge pump circuit system 206 to generate a filtered control signal. In Figure 2 the example, the cut-off frequency of the low pass filter circuit system 208 is in the GHz range.

[0055] In Figure 2 the illustrated example, the VCO circuit system 210 generates a VCO output signal in response to the filtered control signal. For example, the output frequency (F OUT ) of the VCO output signal is k times the reference frequency (F REF ). InFigure 2 In an example, k is 18.3. Thus, the output frequency of the VCO output signal is 9.15 GHz (e.g., 18.3 * 500 MHz = 9.15 GHz). In Figure 2 In an example, the VCO circuit system 210 is implemented by a linear oscillator, a non-linear oscillator, or a linear oscillator and a non-linear oscillator. Also, the input terminal of the VCO circuit system 210 is coupled to the output terminal of the low-pass filter circuit system 208. In Figure 2 In an example, the output terminal of the VCO circuit system 210 is coupled to the input terminal of the frequency divider circuit system 212, the first input terminal of the quantization feedback circuit system 216, and the first input terminal of the masking logic circuit system 218. Also, the output terminal of the VCO circuit system 210 serves as the output terminal of the clock generation circuit system 116. In an example operation, when the voltage of the filtered control signal increases, the VCO circuit system 210 increases the frequency of the VCO output signal. And when the voltage of the filtered control signal decreases, the VCO circuit system 210 decreases the frequency of the VCO output signal. In an example, the VCO circuit system 210 operates in another relationship (e.g., an inverse relationship) with the voltage of the filtered control signal.

[0056] In Figure 2 In the illustrated example, the frequency divider circuit system 212 divides the frequency of the VCO output signal to generate a frequency divider output signal. In Figure 2 In an example, the frequency divider circuit system 212 is implemented by a circuit system such as a multi-mode frequency divider (MMFD) circuit system and a DSM circuit system. The MMFD circuit system and the DSM circuit system are described in further detail below. In Figure 2 In an example, the input terminal of the frequency divider circuit system 212 is coupled to the output terminal of the VCO circuit system 210. Also, the first output terminal of the frequency divider circuit system 212 is coupled to the second input terminal of the quantization feedback circuit system 216. In Figure 2 In an example, the second output terminal of the frequency divider circuit system 212 is coupled to the input terminal of the frequency divider circuit system 214. In some examples, the frequency divider circuit system 212 is referred to as the first frequency divider circuit system (FDC).

[0057] In Figure 2 In the illustrated example, the frequency divider circuit system 212 switches between multiple moduli to divide the frequency of the VCO output signal. For example, the frequency divider circuit system 212 switches between m and m + 1 to divide the frequency of the VCO output signal. In Figure 2 In an example, m is set to the largest integer value less than or equal to k / N (e.g., m = floor(k / N)). For example, N is the modulus of the frequency divider circuit system 214. In Figure 2In an example, N is six. Thus, m is 3 and the frequency divider circuit system 212 switches between 3 and 4 to divide the frequency of the VCO output signal.

[0058] In Figure 2 the illustrated example, the frequency divider circuit system 212 changes the amount of time the frequency divider circuit system 212 divides the frequency of the VCO output signal by m and m + 1 (e.g., 3 and 4) based on the DSM output signal. For example, the DSM circuit system of the frequency divider circuit system 212 receives an MMFD output signal having an MMFD output frequency and samples the MMFD output signal based on a fractional input. In Figure 2 the example, the MMFD output frequency is N times the frequency of the feedback signal (e.g., F MMFD = 6 * 500 MHz = 3 GHz). And, in Figure 2 the example, the fractional input of the DSM circuit system is set to the difference between k / N and the largest integer value less than or equal to k / N. Thus, the fractional input of the DSM circuit system is set to 0.05 (e.g., DSM IN = (18.3 / 6) - floor(18.3 / 6) = 3.05 – 3 = 0.05).

[0059] In Figure 2 the illustrated example, the frequency divider circuit system 214 divides the frequency of the frequency divider output signal to generate a feedback signal. As described above, the frequency divider circuit system 214 divides the frequency of the frequency divider output signal by a single modulus N, which is six in Figure 2 the example. In Figure 2 the example, the frequency divider circuit system 214 is implemented by an analog or digital frequency divider. For example, an analog frequency divider includes a regenerative frequency divider, an injection-locked frequency divider, etc. And, for example, a digital frequency divider is implemented by one or more flip-flops, one or more Johnson counters, etc. In Figure 2 the example, the input terminal of the frequency divider circuit system 214 is coupled to the second output terminal of the frequency divider circuit system 212. And, the output terminal of the frequency divider circuit system 214 is coupled to the second input terminal of the PFD circuit system 202 and the second input terminal of the masking logic circuit system 218. In some examples, the frequency divider circuit system 214 is referred to as a second frequency divider circuit system (FDC).

[0060] In Figure 2 the illustrated example, the quantization feedback circuit system 216 extracts quantization information present in the frequency divider output signal before the quantization information is removed by the frequency divider circuit system 214. For example, the quantization information indicates a rising edge present in the frequency divider output signal. In Figure 2In an example, the quantization feedback circuit system 216 is implemented by one or more switches (such as transistors, diodes, etc.) and combinational logic circuit systems, sequential logic circuit systems, or a combination of combinational logic circuit systems and sequential logic circuit systems, as further described herein. Also, a first input terminal of the quantization feedback circuit system 216 is coupled to an output terminal of the VCO circuit system 210. In Figure 2 an example, a second input terminal of the quantization feedback circuit system 216 is coupled to a first output terminal of the frequency divider circuit system 212. Also, a third input terminal of the quantization feedback circuit system 216 is coupled to an output terminal of the masking logic circuit system 218. In Figure 2 an example, a first output terminal and a second output terminal of the quantization feedback circuit system 216 are respectively coupled to a third input terminal and a fourth input terminal of the adder circuit system 204. In some examples, the quantization feedback circuit system 216 is referred to as a quantization feedback circuit system (QFC).

[0061] In Figure 2 the illustrated example, the quantization feedback circuit system 216 generates a first quantization feedback signal at the first output terminal based on a masking signal generated by the masking logic circuit system 218. For example, the first quantization feedback signal has a positive voltage. In some examples, the quantization feedback circuit system 216 generates a second quantization feedback signal at the second output terminal based on the masking signal generated by the masking logic circuit system 218. For example, the second quantization feedback signal has a negative voltage.

[0062] In Figure 2 the illustrated example, the masking logic circuit system 218 determines whether to generate a masking signal based on a feedback signal. For example, the masking signal masks redundant information present in the quantization information. In Figure 2 an example, the masking logic circuit system 218 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of combinational logic circuit systems and sequential logic circuit systems, as further described herein. Also, a first input terminal of the masking logic circuit system 218 is coupled to an output terminal of the VCO circuit system 210. In Figure 2 an example, a second input terminal of the masking logic circuit system 218 is coupled to an output terminal of the frequency divider circuit system 214. Also, an output terminal of the masking logic circuit system 218 is coupled to a third input terminal of the quantization feedback circuit system 216. In an example operation, when there is the same rising edge in the feedback signal and the frequency divider output signal, the masking logic circuit system 218 generates a masking signal. As further described herein, the masking signal causes the quantization feedback circuit system 216 not to output at least one of the first quantization feedback signal or the second quantization feedback signal.

[0063] Although Figure 2 illustrates the implementation inFigure 1 An example manner of the clock generation circuit system 116, but Figure 2 one or more of the elements, processes, or devices shown may be combined, divided, rearranged, omitted, eliminated, or otherwise implemented at least. In addition, Figure 2 the example PFD circuit system 202, the example adder circuit system 204, the example charge pump circuit system 206, the example low-pass filter circuit system 208, the example VCO circuit system 210, the example frequency divider circuit system 212, the example frequency divider circuit system 214, the example quantization feedback circuit system 216, the example masking logic circuit system 218, or more generally the example clock generation circuit system 116 may be implemented by hardware alone or by a combination of hardware with at least one of software or firmware.

[0064] Thus, for example, Figure 2 the example PFD circuit system 202, the example adder circuit system 204, the example charge pump circuit system 206, the example low-pass filter circuit system 208, the example VCO circuit system 210, the example frequency divider circuit system 212, the example frequency divider circuit system 214, the example quantization feedback circuit system 216, the example masking logic circuit system 218, or more generally any one of the example clock generation circuit system 116 may be implemented by at least one of a combination of a programmable circuit system and machine-readable instructions (such as firmware or software), a processor circuit system, an analog circuit, a digital circuit, a logic circuit, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), or a field programmable logic device (FPLD) (such as an FPGA).

[0065] Additionally, Figure 2 the example clock generation circuit system 116 may include one or more elements, processes, or devices as Figure 2 a supplement or replacement for those elements, processes, or devices shown, and may include more than one of any or all of the elements, processes, and devices shown.

[0066] Figure 3 To represent an example flowchart of example machine-readable instructions or example operations 300 that may be executed, instantiated, or performed by an example programmable circuit system implementation of the clock generation circuit system 116 that may be used Figure 2 . Figure 3An example machine-readable instruction or example operation 300 begins at block 302, where the PFD circuit system 202 compares the phase of a reference signal with the phase of a feedback signal to generate a PFD output signal having a first voltage. At block 304, the adder circuit system 204 adds the PFD output signal to at least one of a first quantized feedback signal having a second voltage or a second quantized feedback signal having a third voltage. For example, the adder circuit system adds the PFD output signal to at least one of the first quantized feedback signal or the second quantized feedback signal to generate a charge pump control signal having a fourth voltage.

[0067] In Figure 3 the illustrated example, at block 306, the charge pump circuit system 206 increases or decreases a fifth voltage of a control signal based on the fourth voltage of the charge pump control signal. At block 308, the low-pass filter circuit system 208 filters the control signal to generate a filtered control signal having a fifth voltage. In Figure 3 the example, at block 310, the VCO circuit system 210 generates a VCO output signal based on the filtered control signal. At block 312, based on the VCO output signal, the divider circuit system 212 generates a divider output signal that includes quantization information. For example, the quantization information indicates a rising edge present in the divider output signal.

[0068] In Figure 3 the illustrated example, at block 314, the divider circuit system 214 generates a feedback signal based on the divider output signal. In Figure 3 the example, after block 314, the PFD circuit system 202 compares the phase of the reference signal with the phase of the feedback signal at block 302 to generate a PFD output signal having a first voltage. And, after block 314, the masking logic circuit system 218 determines whether to generate a masking signal at block 316 based on the feedback signal. In Figure 3 the example, at block 318, the masking logic circuit system 218 generates a masking logic signal to mask redundant information present in the quantization information. For example, at block 318, the masking logic circuit system 218 generates a delayed feedback signal based on the feedback signal and compares the feedback signal with the delayed feedback signal to generate a masking signal. In some examples, at block 318, the masking logic circuit system 218 generates an inverted delayed feedback signal based on the feedback signal and compares the feedback signal with the inverted delayed feedback signal to generate a masking signal.

[0069] For example, the redundancy information indicates rising edges present in the frequency divider output signal and the feedback signal. At block 320, based on the masking signal, the quantization feedback circuit system 216 generates a first quantization feedback signal and a second quantization feedback signal to capture the quantization information present in the frequency divider output signal. After block 320, the adder circuit system 204 adds the PFD output signal to at least one of the first quantization feedback signal having a second voltage or the second quantization feedback signal having a third voltage to generate a charge pump control signal having a fourth voltage.

[0070] Figure 4 To depict compared to an example second frequency response 404 of other clock generation circuit systems Figure 2 Diagram illustration 400 of an example first frequency response 402 of the clock generation circuit system 116. In Figure 4 the example, the clock generation circuit system 116 utilizes a reference clock signal having a reference frequency (F REF ) of 500 MHz and generates an output signal having an output frequency (F OUT ) of 9.25 GHz. Thus, the ratio (e.g., k) between the reference frequency and the output frequency is 18.5. And, the frequency divider circuit system 212 of the clock generation circuit system 116 switches between 18 and 19 to divide the frequency of the VCO output signal to achieve a fractional modulus of 18.5.

[0071] In Figure 4 the shown example, the DSM circuit system of the frequency divider circuit system 212 receives an MMFD output signal having an MMFD output frequency. For example, the MMFD output frequency is N times the frequency of the feedback signal (e.g., F MMFD = 6 * 500 MHz = 3 GHz). And, the modulus of the frequency divider circuit system 214 of the clock generation circuit system 116 is six (e.g., N = 6). In Figure 4 the example, the bandwidth of the clock generation circuit system 116 is 1.1 GHz. For example, since the PFD circuit system 202 serves as a frequency detector, the clock generation circuit system 116 maintains a relatively large frequency range similar to that of an integer PLL. There is a very low least common multiple (LCM) reference spur (e.g., about -93 decibels (dB)) present in the frequency response 402. In Figure 4 the example, compared to the frequency response 404 of other clock generation circuit systems, the frequency response 402 of the clock generation circuit system 116 is reduced by about 40 dB.

[0072] Figure 5 To depict compared to an example second frequency response 504 of other clock generation circuit systems Figure 2Another illustrative diagram 500 of an example first frequency response 502 of the clock generation circuit system 116. In Figure 5 the example, the clock generation circuit system 116 utilizes a reference clock signal having a reference frequency (F REF ) of 500 MHz and generates an output signal having an output frequency (F OUT ) of 9.165 GHz. Thus, the ratio (e.g., k) between the reference frequency and the output frequency is 18.33. And, the divider circuit system 212 of the clock generation circuit system 116 switches between 18 and 19 to divide the frequency of the VCO output signal to achieve a fractional modulus of 18.33.

[0073] In Figure 5 the illustrated example, the DSM circuit system of the divider circuit system 212 receives an MMFD output signal having an MMFD output frequency. For example, the MMFD output frequency is N times the frequency of the feedback signal (e.g., F MMFD = 6 * 500 MHz = 3 GHz). And, the modulus of the divider circuit system 214 of the clock generation circuit system 116 is six (e.g., N = 6). In Figure 5 the example, the bandwidth of the clock generation circuit system 116 is 1.1 GHz. For example, since the PFD circuit system 202 serves as a frequency detector, the clock generation circuit system 116 maintains a relatively large frequency range similar to that of an integer PLL. There are very low LCM reference spurs (e.g., about -94 dB and -110 dB) in the frequency response 502. In Figure 5 the example, the frequency response 502 of the clock generation circuit system 116 is reduced by about 50 dB compared to the frequency response 504 of other clock generation circuit systems.

[0074] Figure 6A A diagrammatic illustration 600 depicting the example output signal 602 of the adder circuit system 204 of the clock generation circuit system 116 compared to the example output signal 604 of other clock generation circuit systems. In Figure 2 the example, the integer modulus (e.g., N) of the clock generation circuit system 116 and the integer modulus of other clock generation circuit systems are 3. As Figure 6A shown in Figure 6A , the peak-to-peak amplitude of the output signal 602 of the adder circuit system 204 is two volts (e.g., 2V), while the peak-to-peak amplitude of the output signal 604 of other clock generation circuit systems is six volts (e.g., 6V).

[0075] Figure 6B A diagrammatic illustration depicting the example output signal 602 of the adder circuit system 204 of the clock generation circuit system 116 compared to the example output signal 610 of other clock generation circuit systems. In Figure 2Diagrammatic illustration 606 of an example output signal 608 of adder circuit system 204 of clock generation circuit system 116. In Figure 6B the example, the integer modulus (e.g., N) of clock generation circuit system 116 and the integer modulus of other clock generation circuit systems is 4. As Figure 6B shown, the peak-to-peak amplitude of output signal 608 of adder circuit system 204 is two volts (e.g., 2V), while the peak-to-peak amplitude of output signal 610 of other clock generation circuit systems is eight volts (e.g., 8V).

[0076] As Figure 6A and Figure 6B shown, regardless of the division factor in the frequency extraction loop of clock generation circuit system 116, clock generation circuit system 116 maintains the same peak-to-peak amplitude for the signal at the output terminal of adder circuit system 204. Thus, clock generation circuit system 116 facilitates the operation of charge pump circuit system 206 in the linear region, regardless of the division factor in the frequency extraction loop of clock generation circuit system 116. Independent of the division factor, the output terminal of adder circuit system 204 maintains the same peak-to-peak amplitude (e.g., -1 to +1), while in other clock generation circuit systems, the peak-to-peak amplitude varies based on the division factor (e.g., -N to +N).

[0077] Figure 7 is a block diagram of clock generation circuit system 116 for a first example implementation including Figure 2 a frequency divider circuit system 212 and a quantization feedback circuit system 216. In Figure 2 the example, frequency divider circuit system 212 includes an example multi-mode frequency divider (MMFD) circuit system 702, an example delta-sigma modulator (DSM) circuit system 704, and an example delta-sigma modulator (DSM) input generation circuit system 706. And, PFD circuit system 202 is an example first PFD circuit system 202. In Figure 7 the example, quantization feedback circuit system 216 includes an example quantization extraction circuit system 708, an example switching circuit system 710, and an example second phase frequency detector (PFD) circuit system 712. Figure 7

[0078] Figure 7 In Figure 7 the example shown, MMFD circuit system 702 generates an MMFD output signal in response to the DSM output signal and the VCO output signal. In Figure 7 the example, MMFD circuit system 702 is implemented by at least two analog frequency dividers, at least two digital frequency dividers, or at least one analog frequency divider and at least one digital frequency divider. And, the first input terminal of MMFD circuit system 702 is coupled to the output terminal of VCO circuit system 210.Figure 7 In an example, the second input terminal of the MMFD circuit system 702 is coupled to the output terminal of the DSM circuit system 704. Also, the output terminal of the MMFD circuit system 702 is coupled to the first input terminal of the DSM circuit system 704, the second input terminal of the quantization extraction circuit system 708, and the input terminal of the frequency divider circuit system 214.

[0079] In Figure 7 the illustrated example, the MMFD circuit system 702 switches between multiple moduli to divide the frequency of the VCO output signal. For example, the MMFD circuit system 702 switches between m and m + 1 to divide the frequency of the VCO output signal. In Figure 7 the example, m is set to the largest integer value less than or equal to k / N (e.g., m = floor(k / N)). For example, N is the modulus of the frequency divider circuit system 214. In Figure 7 the example, N is six and k is 18.3. Thus, m is three and the MMFD circuit system 702 switches between 3 and 4 as the modulus to divide the frequency of the VCO output signal. In Figure 7 the example, when the MMFD circuit system 702 divides the frequency of the VCO output signal by m, one period of the MMFD output signal includes m periods of the VCO output signal. Also, when the MMFD circuit system 702 divides the frequency of the VCO output signal by m + 1, one period of the MMFD output signal includes m + 1 periods of the VCO output signal.

[0080] In Figure 7 the illustrated example, the DSM circuit system 704 generates a DSM output signal in response to the MMFD output signal and the DSM reference signal. In Figure 7 the example, the DSM circuit system 704 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combinational logic circuit system and a sequential logic circuit system. Also, the first input terminal of the DSM circuit system 704 is coupled to the output terminal of the MMFD circuit system 702. In Figure 7 the example, the second input terminal of the DSM circuit system 704 is coupled to the output terminal of the DSM input generation circuit system 706. Also, the output terminal of the DSM circuit system 704 is coupled to the second input terminal of the MMFD circuit system 702.

[0081] In Figure 7 the illustrated example, the DSM circuit system 704 is a first-order DSM. For example, the oversampling factor of the DSM circuit system 704 corresponds to the order of the DSM circuit system 704. In Figure 7In an example, the DSM circuit system 704 controls the MMFD circuit system 702 to use which modulus to divide the frequency of the VCO output signal. For example, the DSM circuit system 704 samples the MMFD output signal in response to a DSM reference signal generated by the DSM input generation circuit system 706. In Figure 7 In an example, the DSM circuit system 704 is time-controlled at the frequency of the MMFD output signal. For example, the frequency of the MMFD output signal is N times the frequency of the feedback signal (e.g., F MMFD = 6 * 500 MHz = 3 GHz) to suppress quantization noise. In Figure 7 In an example, the DSM circuit system 704 generates an oversampled representation of the MMFD output signal to generate a DSM output signal as a bit stream.

[0082] In Figure 7 In the illustrated example, the DSM input generation circuit system 706 generates a DSM reference signal. In Figure 7 In an example, the DSM input generation circuit system 706 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combinational logic circuit system and a sequential logic circuit system. And, the output terminal of the DSM input generation circuit system 706 is coupled to the second input terminal of the DSM circuit system 704. In Figure 7 In an example, the DSM input generation circuit system 706 generates a DSM reference signal as a fractional number. For example, the fractional number is set to the difference between k / N and the largest integer value less than or equal to k / N. Thus, the fractional number is set to 0.05 (e.g., DSM IN = (18.3 / 6) - floor(18.3 / 6) = 3.05 - 3 = 0.05).

[0083] In Figure 7 In the illustrated example, the quantization extraction circuit system 708 samples the MMFD output signal to generate a first delayed MMFD output signal and a second delayed MMFD output signal that contain quantization information present in the MMFD output signal. In Figure 7 In an example, the quantization extraction circuit system 708 is implemented by a delay circuit system, as further described herein. And, the first input terminal of the quantization extraction circuit system 708 is coupled to the output terminal of the VCO circuit system 210. In Figure 7 In an example, the second input terminal of the quantization extraction circuit system 708 is coupled to the output terminal of the MMFD circuit system 702. In Figure 7 In an example, the first output terminal and the second output terminal of the quantization extraction circuit system 708 are respectively coupled to the first input terminal and the second input terminal of the switching circuit system 710.

[0084] In Figure 7In the illustrated example, the quantization extraction circuitry 708 preserves the noise shaping present at the output terminals of the MMFD circuitry 702. For example, the rising edge of the MMD output signal contains quantization information determined by the DSM output signal. However, after the frequency divider circuitry 214 divides the frequency of the MMFD output signal, some of the rising edges of the MMD output signal are removed. Accordingly, the quantization extraction circuitry 708 preserves (e.g., extracts) the quantization information before the frequency of the MMFD output signal is divided (e.g., lost) by the frequency divider circuitry 214. The quantization extraction circuitry 708 adds the quantization information as feedback to the clock generation circuitry 116 by providing the quantization information to the PFD circuitry 712 via the switching circuitry 710.

[0085] In Figure 7 the illustrated example, the switching circuitry 710 couples, decouples, or couples and decouples the quantization extraction circuitry 708 from the PFD circuitry 712 based on a masking signal generated by the masking logic circuitry 218. In Figure 7 the example, the switching circuitry 710 is implemented by one or more switches (e.g., transistors, diodes, etc.) and combinational logic circuitry, sequential logic circuitry, or combinational logic circuitry and sequential logic circuitry, as further described herein. Also, a first input terminal and a second input terminal of the switching circuitry 710 are coupled to a first output terminal and a second output terminal of the quantization extraction circuitry 708, respectively. In Figure 7 the example, a third input terminal of the switching circuitry 710 is coupled to an output terminal of the masking logic circuitry 218. Also, a first output terminal and a second output terminal of the switching circuitry 710 are coupled to a first input terminal and a second input terminal of the PFD circuitry 712, respectively. In Figure 7 the example, the switching circuitry 710 is coupled to the example ground terminal 714.

[0086] In Figure 7 the illustrated example, the PFD circuitry 712 compares a first signal at a first input terminal with a second signal at a second input terminal. In Figure 7 the example, the PFD circuitry 712 is implemented by combinational logic circuitry, sequential logic circuitry, or combinational logic circuitry and sequential logic circuitry. Also, a first input terminal and a second input terminal of the PFD circuitry 712 are coupled to a first output terminal and a second output terminal of the switching circuitry 710, respectively. In Figure 7 the example, a first output terminal and a second output terminal of the PFD circuitry 712 are coupled to a third input terminal and a fourth input terminal of the adder circuitry 204, respectively.

[0087] InFigure 7 In the illustrated example, when the first input terminal and the second input terminal of the PFD circuit system 712 are respectively coupled to the first output terminal and the second output terminal of the quantization extraction circuit system 708, the PFD circuit system 712 compares the rising edge of the MMFD output signal with the rising edge of the MMFD output signal that is shifted by m and m + 1 VCO clock cycles (e.g., m + 0.5 VCO clock cycles). For example, the PFD circuit system 712 determines earlier or more frequently which of the first signal at the first input terminal and the second signal at the second input terminal has a zero crossing. In Figure 7 the example, when the PFD circuit system 712 detects that the first signal has a zero crossing before the second signal, the PFD circuit system 712 generates a signal with a positive voltage at the first output terminal. And, when the PFD circuit system 712 detects that the second signal has a zero crossing before the first clock signal, the PFD circuit system 712 generates a signal with a negative voltage at the second output terminal. In one example, the PFD circuit system 712 operates in a different manner.

[0088] Figure 8 For an example implementation of Figure 7 the quantization extraction circuit system 708, the switching circuit system 710, and the masking logic circuit system 218 Figure 7 is a block diagram of the clock generation circuit system 116. In Figure 8 the example, the quantization extraction circuit system 708 includes an example first delay circuit system 802 and an example second delay circuit system 804. And, the switching circuit system 710 includes an example first switch 806, an example second switch 808, an example third switch 810, an example fourth switch 812, an example first NOT gate 814, an example second NOT gate 816, and an example OR gate 818. In Figure 8 the example, the masking logic circuit system 218 includes an example third delay circuit system 820 and an example AND gate 822.

[0089] In Figure 8 the illustrated example, the delay circuit system 802 delays the MMFD output signal by 0.5 clock cycles of the VCO output signal. In Figure 8 the example, the delay circuit system 802 is implemented by a D flip - flop that is time - controlled by the falling edge of the VCO output signal. And, the first input terminal of the delay circuit system 802 is coupled to the output terminal of the VCO circuit system 210. In Figure 8 the example, the second input terminal of the delay circuit system 802 is coupled to the output terminal of the MMFD circuit system 702. In Figure 8 the example, the output terminal of the delay circuit system 802 is coupled to the first terminal of the switch 806.

[0090] In Figure 8 the illustrated example, the delay circuit system 804 delays the MMFD output signal by m + 1 clock cycles of the VCO output signal. For example, the delay circuit system 804 delays the MMFD output signal by 4 VCO clock cycles. In Figure 8 the example, the delay circuit system 804 is implemented by D flip - flops controlled by the falling edge of the VCO output signal. Also, the first input terminal of the delay circuit system 804 is coupled to the output terminal of the VCO circuit system 210. In Figure 8 the example, the second input terminal of the delay circuit system 804 is coupled to the output terminal of the MMFD circuit system 702. In Figure 8 the example, the output terminal of the delay circuit system 804 is coupled to the first terminal of the switch 810.

[0091] In Figure 8 the illustrated example, the switch 806 is implemented by a transistor. In Figure 8 the example, the first terminal of the switch 806 is coupled to the output terminal of the delay circuit system 802. Also, the second terminal of the switch 806 is coupled to the first input terminal of the PFD circuit system 712. In Figure 8 the example, the control terminal of the switch 806 is coupled to the output terminal of the NOT gate 816.

[0092] In Figure 8 the illustrated example, the switch 808 is implemented by a transistor. In Figure 8 the example, the first terminal of the switch 808 is coupled to the output terminal of the delay circuit system 804. Also, the second terminal of the switch 808 is coupled to the first input terminal of the PFD circuit system 712. In Figure 8 the example, the control terminal of the switch 808 is coupled to the output terminal of the AND gate 822.

[0093] In Figure 8 the illustrated example, the switch 810 is implemented by a transistor. In Figure 8 the example, the first terminal of the switch 810 is coupled to the output terminal of the delay circuit system 804. Also, the second terminal of the switch 810 is coupled to the second input terminal of the PFD circuit system 712. In Figure 8 the example, the control terminal of the switch 810 is coupled to the output terminal of the OR gate 818.

[0094] In Figure 8 the illustrated example, the switch 812 is implemented by a transistor. In Figure 8 the example, the first terminal of the switch 812 is coupled to the ground terminal 714. Also, the second terminal of the switch 812 is coupled to the second input terminal of the PFD circuit system 712. In Figure 8In an example, the control terminal of switch 812 is coupled to the output terminal of NOT gate 814.

[0095] In Figure 8 the illustrated example, NOT gate 814 is implemented by one or more transistors. In Figure 8 an example, the input terminal of NOT gate 814 is coupled to the output terminal of OR gate 818. Also, the output terminal of NOT gate 814 is coupled to the control terminal of switch 812. In Figure 8 an example, NOT gate 816 is implemented by one or more transistors. In Figure 8 an example, the input terminal of NOT gate 816 is coupled to the output terminal of AND gate 822. Also, the output terminal of NOT gate 816 is coupled to the first input terminal of OR gate 818 and the control terminal of switch 806.

[0096] In Figure 8 the illustrated example, OR gate 818 is implemented by one or more transistors. In Figure 8 an example, the first input terminal of OR gate 818 is coupled to the output terminal of NOT gate 816. Also, the second input terminal of OR gate 818 is coupled to the output terminal of AND gate 822. In Figure 8 an example, the output terminal of OR gate 818 is coupled to the control terminal of switch 810 and the input terminal of NOT gate 814.

[0097] In Figure 8 the illustrated example, delay circuit system 820 delays the feedback signal by one clock cycle of the VCO output signal. In Figure 8 an example, delay circuit system 820 is implemented by a D flip-flop controlled by the rising edge of the VCO output signal. Also, the first input terminal of delay circuit system 820 is coupled to the output terminal of VCO circuit system 210. In Figure 8 an example, the second input terminal of delay circuit system 820 is coupled to the output terminal of divider circuit system 214. Also, the output terminal of delay circuit system 820 is coupled to the second input terminal of AND gate 822.

[0098] In Figure 8 the illustrated example, AND gate 822 is implemented by one or more transistors. In Figure 8 an example, the first input terminal of AND gate 822 is coupled to the output terminal of divider circuit system 214. Also, the second input terminal of AND gate 822 is coupled to the output terminal of delay circuit system 820. In Figure 8 an example, the output terminal of AND gate 822 is coupled to the control terminal of switch 808, the input terminal of NOT gate 816, and the second input terminal of OR gate 818.

[0099] In Figure 8In the illustrated example, the masking logic circuit system 218 generates a masking signal based on the rising edge of the feedback signal generated by the frequency divider circuit system 214. For example, for each rising edge of the feedback signal, the AND gate 822 generates a masking signal pulse that is one VCO clock cycle wide (e.g., a logical high value (e.g., 5V) on the masking signal). In these examples, the NOT gate 816 generates a logical low value for one VCO clock cycle, the OR gate 818 generates a logical high value for one VCO clock cycle, and the NOT gate 814 generates a logical low value for one VCO clock cycle. Thus, when the AND gate 822 generates a masking signal pulse that is one VCO clock cycle wide, the switch 806 is open for one VCO clock cycle, the switch 808 is closed for one VCO clock cycle, the switch 810 is closed for one VCO clock cycle, and the switch 812 is open for one VCO clock cycle.

[0100] Accordingly, when the AND gate 822 generates a masking signal pulse that is one VCO clock cycle wide, the switching circuit system 710 couples the first input terminal and the second input terminal of the PFD circuit system 712 to the output terminal of the delay circuit system 804. Accordingly, the PFD circuit system 712 detects the same signal at the first input terminal and the second input terminal. Thus, the PFD circuit system 712 does not detect a phase difference and does not output a positive or negative voltage.

[0101] In Figure 8 the illustrated example, when the output of the AND gate 822 is a logical low value (e.g., 0V), the NOT gate 816 generates a logical high value, the OR gate 818 generates a logical high value, and the NOT gate 814 generates a logical low value. Thus, when the AND gate 822 generates a logical low value, the switch 806 is closed, the switch 808 is open, the switch 810 is closed, and the switch 812 is open. Accordingly, when the AND gate 822 generates a logical low value, the switching circuit system 710 couples the first input terminal of the PFD circuit system 712 to the output terminal of the delay circuit system 802. And, when the AND gate 822 generates a logical low value, the switching circuit system 710 couples the second input terminal of the PFD circuit system 712 to the output terminal of the delay circuit system 804.

[0102] In Figure 8 the illustrated example, since one period of the MMFD output signal includes m or m + 1 periods of the VCO output signal (e.g., the VCO clock signal), the PFD circuit system 712 can determine the MMFD modulus by comparing the rising edge of the MMFD output signal with the previous rising edge of the MMFD output signal that is shifted by the average of m and m + 1 VCO clock cycles (e.g., m + 0.5 VCO clock cycles). In Figure 8In the example, by comparing the MMFD output signal shifted by 0.5 VCO clock cycles with the MMFD output signal shifted by m + 1 VCO clock cycles, the PFD circuit system 712 retains a shift of m + 0.5 VCO clock cycles between the two input terminals. In Figure 8 In the example, when one cycle of the MMFD output signal contains m cycles of the VCO output signal, the PFD circuit system 712 generates a positive voltage that is 0.5 VCO clock cycles wide. Also, when one cycle of the MMFD output signal contains m + 1 cycles of the VCO output signal, the PFD circuit system 712 generates a negative voltage that is 0.5 VCO clock cycles wide. In the examples described herein, the shift of m + 0.5 VCO clock cycles is independent of the fractional divider value of the MMFD circuit system 702.

[0103] Although Figure 7 and 8 illustrate example ways of implementing the divider circuit system 212, the quantization feedback circuit system 216, and the masking logic circuit system 218 of Figure 2 , one or more of the elements, processes, or devices illustrated in Figure 7 and 8 can be combined, divided, rearranged, omitted, eliminated, or implemented in any other way, at least. Additionally, Figure 7 and 8 's example MMFD circuit system 702, example DSM circuit system 704, example DSM input generation circuit system 706, or more generally example divider circuit system 212, or Figure 8 's example delay circuit system 802, example delay circuit system 804, or more generally example quantization extraction circuit system 708, or Figure 8 's example switches 806, 808, 810, 812, example NOT gates 814, 816, example OR gate 818, or more generally example switching circuit system 710, Figure 7 and 8 's example PFD circuit system 712, or more generally quantization feedback circuit system 216, or Figure 8 's example delay circuit system 820, example AND gate 822, or more generally example masking logic circuit system 218 can be implemented by hardware alone or by a combination of hardware with at least one of software or firmware.

[0104] Thus, for example, Figure 7 and 8 's example MMFD circuit system 702, example DSM circuit system 704, example DSM input generation circuit system 706, or more generally example divider circuit system 212, or Figure 8The example delay circuit system 802, the example delay circuit system 804, or more generally the example quantization extraction circuit system 708, or Figure 8 the example switches 806, 808, 810, 812, the example NOT gates 814, 816, the example OR gate 818, or more generally the example switching circuit system 710, Figure 7 and 8 the example PFD circuit system 712 or more generally the quantization feedback circuit system 216, or Figure 8 any one of the example delay circuit system 820, the example AND gate 822, or more generally the example masking logic circuit system 218 can be implemented by at least one of a combination of a programmable circuit system and machine-readable instructions (such as firmware or software), a processor circuit system, an analog circuit, a digital circuit, a logic circuit, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), or a field programmable logic device (FPLD) (such as an FPGA).

[0105] Additionally, Figure 7 and 8 the example frequency divider circuit system 212, Figure 7 and 8 the example quantization extraction circuit system 708, Figure 7 and 8 the example switching circuit system 710, Figure 7 and 8 the example PFD circuit system 712, or more generally Figure 7 and 8 the example quantization feedback circuit system 216 or Figure 8 the example masking logic circuit system 218 can include one or more elements, processes, or devices to supplement or replace those shown as Figure 7 and 8 shown, and can include more than one of any or all of the shown elements, processes, and devices.

[0106] Figure 9 To represent an example flowchart of example machine-readable instructions or example operations 900 that can be executed, instantiated, or performed by an example programmable circuit system implementation using Figure 7 the clock generation circuit system 116. Figure 9An example machine-readable instruction or example operation 900 begins at block 902, where the PFD circuit system 202 compares the phase of a reference signal with the phase of a feedback signal to generate a first PFD output signal having a first voltage. At block 904, an adder circuit system 204 adds the first PFD output signal to a second PFD output signal having a second voltage to generate a charge pump control signal having a third voltage.

[0107] In Figure 9 the illustrated example, at block 906, a charge pump circuit system 206 increases or decreases a fourth voltage of a control signal based on the third voltage of the charge pump control signal. At block 908, a low-pass filter circuit system 208 filters the control signal to generate a filtered control signal having a fourth voltage. In Figure 9 the example, at block 910, a VCO circuit system 210 generates a VCO output signal based on the filtered control signal. At block 912, an MMFD circuit system 702 generates an MMFD output signal based on the DSM output signal and the VCO output signal.

[0108] In Figure 9 the illustrated example, at block 914, a DSM circuit system 704 generates a DSM output signal based on the MMFD output signal and a DSM reference signal. After block 914, the MMFD circuit system 702 generates an MMFD output signal at block 912 based on the DSM output signal and the VCO output signal. In Figure 9 the example, at block 916, a divider circuit system 214 generates a feedback signal based on the MMFD output signal. After block 916, the PFD circuit system 202 compares the phase of the reference signal with the phase of the feedback signal at block 902 to generate a first PFD output signal having a first voltage. Also, after block 916, a masking logic circuit system 218 determines at block 918 whether to generate a masking signal based on the feedback signal.

[0109] In Figure 9 the illustrated example, at block 920, a quantization extraction circuit system 708 generates a first delayed MMFD output signal and a second delayed MMFD output signal that contain quantization information present in the MMFD output signal. At block 922, a masking logic circuit system 218 generates a masking logic signal to mask redundant information present in the quantization information. For example, the redundant information indicates rising edges present in the MMFD output signal and the feedback signal.

[0110] In Figure 9In the illustrated example, at block 924, based on the masking signal, switching circuitry 710 couples at least one of a first delayed MMFD output signal or a second delayed MMFD output signal to PFD circuitry 712. At block 926, PFD circuitry 712 compares the phase of the output signal of switching circuitry 710 to generate a second PFD output signal having a second voltage. After block 926, adder circuitry 204 adds the first PFD output signal and the second PFD output signal having the second voltage to generate a charge pump control signal having a third voltage.

[0111] Figure 10 For illustration Figure 7 FIG. 1000 is a graphical illustration of an example operation of clock generation circuitry 116. Figure 10 Graphical illustration 1000 includes example first plot 1002, example second plot 1004, example third plot 1006, example fourth plot 1008, example fifth plot 1010, example sixth plot 1012, and example seventh plot 1014. In Figure 10 the example, plot 1002 shows the VCO output signal (VCO OUT ). Also, plot 1004 shows the DSM output signal (DSM OUT ). In Figure 10 the example, plot 1006 shows the MMFD output signal (MMFD OUT ). For example, one period of the MMFD output signal includes three periods or four periods of the VCO output signal, depending on the value of the DSM output signal of plot 1004.

[0112] In Figure 10 the illustrated example, plot 1008 shows the feedback signal (FB signal). Also, plot 1010 shows the first delayed MMFD output signal (first delayed MMFD OUT ). For example, the first delayed MMFD output signal represents the MMFD output signal delayed by 0.5 periods of the VCO output signal. In Figure 10 the example, plot 1012 shows the second delayed MMFD output signal (second delayed MMFD OUT ). For example, the second delayed MMFD output signal represents the MMFD output signal delayed by 4 periods of the VCO output signal. In Figure 10 the example, plot 1014 shows the second PFD output signal (second PFD OUT ) without masking logic circuitry 218.

[0113] In Figure 10In the illustrated example, example first edge 1016 A , example second edge 1016 B and example third edge 1016 C are retained in the feedback signal of plot 1008. Also, example fourth edge 1018 A , example fifth edge 1018 B and example sixth edge 1018 C are not present in the feedback signal of plot 1008. Thus, masking logic circuit system 218 masks example first pulse 1020 B and example second pulse 1020 C of the second PFD output signal corresponding to edge 1016 A and edge 1016 B respectively. For example, masking logic circuit system 218 can generate a masking signal pulse before or after the rising edge of the feedback signal. Also, masking logic circuit system 218 does not mask example third pulse 1022 A , example fourth pulse 1022 B and example fifth pulse 1022 C of the second PFD output signal corresponding to edge 1018 A , edge 1018 B and edge 1018 C respectively.

[0114] In Figure 10 the illustrated example, PFD circuit system 712 compares the MMFD output signal shifted by 0.5 cycles of the VCO output signal with the MMFD output signal shifted by 4 cycles of the VCO output signal to extract the sequence of the DSM output signal. For example, PFD circuit system 712 represents the modulo three of MMFD circuit system 702 as a positive voltage pulse 0.5 cycles wide of the VCO output signal. And PFD circuit system 712 represents the modulo four of MMFD circuit system 702 as a negative voltage pulse 0.5 cycles wide of the VCO output signal.

[0115] In Figure 10 the illustrated example, in addition to the edge information present in the rising edge of the feedback signal of plot 1008, the information on other edges is removed by divider circuit system 214. Thus, quantization extraction circuit system 708 extracts the quantization information present in the MMFD output signal. And masking logic circuit system 218 masks the redundant information (such as the rising edge) already present in the feedback signal. For example, masking logic circuit system 218 generates a masking signal pulse to mask the second PFD output signal pulse containing the information present in the feedback signal.

[0116] Figure 11To depict a clock generation circuit system 116 having a matched PFD circuit system Figure 7 Example first frequency response 1102 of the clock generation circuit system 116 of Figure 7 and an illustration 1100 of an example second frequency response 1104 of the clock generation circuit system 116 having a PFD circuit system with a first delay mismatch. In Figure 11 the example, the frequency response 1102 depicts the frequency response of the clock generation circuit system 116 when there is no delay mismatch (or the delay mismatch is negligible) between (1) the transmission path between the output terminal of the PFD circuit system 202 and the input terminal of the adder circuit system 204 and (2) the transmission path between the output terminal of the PFD circuit system 712 and the input terminal of the adder circuit system 204. And, the frequency response 1104 depicts the frequency response of the clock generation circuit system 116 when there is a delay mismatch between (1) the transmission path between the output terminal of the PFD circuit system 202 and the input terminal of the adder circuit system 204 and (2) the transmission path between the output terminal of the PFD circuit system 712 and the input terminal of the adder circuit system 204. For example, the delay mismatch is 0.5 cycles of the VCO output signal.

[0117] In Figure 11 the illustrated example, there is no difference (or the difference is negligible) between the frequency response 1102 and the frequency response 1104. Thus, even if there is a mismatch in the transmission paths of the PFD circuit system 202 and the PFD circuit system 712, the performance of the clock generation circuit system 116 is not affected. Therefore, it is easier to implement the clock generation circuit system 116 in a semiconductor die because the clock generation circuit system 116 can flexibly cope with the delay mismatch between circuit systems that can be caused by defects in the semiconductor die.

[0118] Figure 12 To depict an example first frequency response 1202 of the clock generation circuit system 116 having a matched PFD circuit system Figure 7 an example second frequency response 1204 of the clock generation circuit system 116 having a PFD circuit system with a first delay mismatch, and Figure 7[[END an example third frequency response 1206 of the clock generation circuit system 116 having a PFD circuit system with a second delay mismatch ​ and an illustration 1200. In ​In the example, the frequency response 1202 depicts the frequency response of the clock generation circuit system 116 when there is no delay mismatch (or the delay mismatch is negligible) between (1) the transmission path between the output terminal of the PFD circuit system 202 and the input terminal of the adder circuit system 204 and (2) the transmission path between the output terminal of the PFD circuit system 712 and the input terminal of the adder circuit system 204. And, the frequency response 1204 depicts the frequency response of the clock generation circuit system 116 when there is a first delay mismatch between (1) the transmission path between the output terminal of the PFD circuit system 202 and the input terminal of the adder circuit system 204 and (2) the transmission path between the output terminal of the PFD circuit system 712 and the input terminal of the adder circuit system 204. For example, the first delay mismatch is 0.5 cycles of the VCO output signal.

[0119] In ​ the illustrated example, the frequency response 1206 depicts the frequency response of the clock generation circuit system 116 when there is a first delay mismatch and a second delay mismatch in the clock generation circuit system 116. In ​ the example, the first delay mismatch is the delay mismatch between (1) the transmission path between the output terminal of the PFD circuit system 202 and the input terminal of the adder circuit system 204 and (2) the transmission path between the output terminal of the PFD circuit system 712 and the input terminal of the adder circuit system 204. For example, the first delay mismatch is a delay mismatch of 0.5 cycles of the VCO output signal. In ​ the example, the second delay mismatch is the delay mismatch between (1) the transmission path between the first output terminal of the switching circuit system 710 and the first input terminal of the PFD circuit system 712 and (2) the transmission path between the second output terminal of the switching circuit system 710 and the second input terminal of the PFD circuit system 712. In ​ the example, the second delay mismatch is 0.5 cycles of the VCO output signal.

[0120] In ​ the illustrated example, there is no difference (or the difference is negligible) between the frequency response 1202, the frequency response 1204, and the frequency response 1206. Thus, even if there are mismatches in the transmission paths of the PFD circuit system 202 and the PFD circuit system 712, the performance of the clock generation circuit system 116 is not affected. Therefore, it is easier to implement the clock generation circuit system 116 in a semiconductor die than other technologies because the clock generation circuit system 116 can flexibly cope with the delay mismatches between circuit systems that can be caused by defects in the semiconductor die.

[0121] ​ To include ​Second exemplary embodiment of the frequency divider circuit system 212 and the quantization feedback circuit system 216 ​ Block diagram of the clock generation circuit system 116. In ​ the example, the frequency divider circuit system 212 includes an exemplary multi-mode frequency divider (MMFD) circuit system 1302, an exemplary delta-sigma modulator (DSM) circuit system 1304, and an exemplary delta-sigma modulator (DSM) input generation circuit system 1306. In ​ the example, the quantization feedback circuit system 216 includes an exemplary quantization extraction circuit system 1308 and an exemplary switching circuit system 1310.

[0122] In ​ the illustrated example, the MMFD circuit system 1302 generates an MMFD output signal in response to the DSM output signal and the VCO output signal. In ​ the example, the MMFD circuit system 1302 is implemented by at least two analog frequency dividers, at least two digital frequency dividers, or at least one analog frequency divider and at least one digital frequency divider. Also, the first input terminal of the MMFD circuit system 1302 is coupled to the output terminal of the VCO circuit system 210. In ​ the example, the second input terminal of the MMFD circuit system 1302 is coupled to the output terminal of the DSM circuit system 1304. Also, the output terminal of the MMFD circuit system 1302 is coupled to the first input terminal of the DSM circuit system 1304, the second input terminal of the quantization extraction circuit system 1308, and the input terminal of the frequency divider circuit system 214.

[0123] In ​ the illustrated example, the output frequency (F OUT ) of the VCO output signal is k times the reference frequency (F REF ). In ​ the example, k is 18.5. Thus, the output frequency of the VCO output signal is 9.25 GHz (e.g., 18.5 * 500 MHz = 9.25 GHz). In ​ the example, the MMFD circuit system 1302 switches between multiple modulus values to divide the frequency of the VCO output signal. For example, the MMFD circuit system 1302 switches between m and m + 1 to divide the frequency of the VCO output signal. In ​ the example, m is set to the largest integer value less than or equal to k / N (e.g., m = floor(k / N)). For example, N is the modulus of the frequency divider circuit system 214. In ​ the example, N is six. Thus, m is 3 and the MMFD circuit system 1302 switches between 3 and 4 as the modulus to divide the frequency of the VCO output signal. In ​In an example, when the MMFD circuit system 1302 divides the frequency of the VCO output signal by m, one period of the MMFD output signal includes m periods of the VCO output signal. And when the MMFD circuit system 1302 divides the frequency of the VCO output signal by m + 1, one period of the MMFD output signal includes m + 1 periods of the VCO output signal.

[0124] In ​ the illustrated example, the DSM circuit system 1304 generates a DSM output signal in response to the MMFD output signal and the DSM reference signal. In ​ an example, the DSM circuit system 1304 is implemented by a combinational logic circuit system, a sequential logic circuit system, or a combination of a combinational logic circuit system and a sequential logic circuit system. And a first input terminal of the DSM circuit system 1304 is coupled to an output terminal of the MMFD circuit system 1302. In ​ an example, a second input terminal of the DSM circuit system 1304 is coupled to an output terminal of the DSM input generation circuit system 1306. And an output terminal of the DSM circuit system 1304 is coupled to a second input terminal of the MMFD circuit system 1302 and a second input terminal of the quantization extraction circuit system 1308.

[0125] In ​ the illustrated example, the DSM circuit system 1304 is a first-order DSM. For example, the oversampling factor of the DSM circuit system 1304 corresponds to the order of the DSM circuit system 1304. In ​ an example, the DSM circuit system 1304 controls which modulus the MMFD circuit system 1302 uses to divide the frequency of the VCO output signal. For example, the DSM circuit system 1304 samples the MMFD output signal based on the DSM reference signal generated by the DSM input generation circuit system 1306. In ​ an example, the DSM circuit system 1304 is time-controlled at the frequency of the MMFD output signal. For example, the frequency of the MMFD output signal is N times the frequency of the feedback signal (e.g., F MMFD = 6 * 500 MHz = 3 GHz) to suppress quantization noise. In ​ an example, the DSM circuit system 1304 generates an oversampled representation of the MMFD output signal to generate the DSM output signal as a bit stream.

[0126] In ​ the illustrated example, the DSM input generation circuit system 1306 generates the DSM reference signal. In ​In an example, the DSM input generation circuitry 1306 is implemented by combinational logic circuitry, sequential logic circuitry, or a combination of combinational logic circuitry and sequential logic circuitry. Also, an output terminal of the DSM input generation circuitry 1306 is coupled to a second input terminal of the DSM circuitry 1304. In ​ In an example, the DSM input generation circuitry 1306 generates a DSM reference signal as a fractional number. For example, the fractional number is set to the difference between k / N and the largest integer value less than or equal to k / N. Thus, the fractional number is set to 0.0833 (e.g., DSM IN = (18.5 / 6) - floor(18.5 / 6) = 3.0833 - 3 = 0.0833).

[0127] In ​ In the illustrated example, the quantization extraction circuitry 1308 samples the DSM output signal to generate a first quantization output signal and a second quantization output signal that contain quantization information present in the MMFD output signal. In ​ In an example, the quantization extraction circuitry 1308 is implemented by a delay circuitry, as further described herein. Also, a first input terminal of the quantization extraction circuitry 1308 is coupled to an output terminal of the VCO circuitry 210. In ​ In an example, a second input terminal of the quantization extraction circuitry 1308 is coupled to an output terminal of the DSM circuitry 1304. In ​ In an example, a first output terminal and a second output terminal of the quantization extraction circuitry 1308 are coupled to a first input terminal and a second input terminal of the switching circuitry 1310, respectively.

[0128] In ​ In the illustrated example, the quantization extraction circuitry 1308 preserves the noise shaping present at an output terminal of the MMFD circuitry 1302. For example, a rising edge of the MMD output signal contains quantization information determined by the DSM output signal. However, after the frequency divider circuitry 214 divides the frequency of the MMFD output signal, some of the rising edge of the MMD output signal is removed. Thus, the quantization extraction circuitry 1308 preserves (e.g., extracts) the quantization information from the DSM output signal. Accordingly, the quantization extraction circuitry 1308 extracts the quantization information before the quantization information is removed (e.g., lost) by dividing the frequency of the MMFD output signal by the frequency divider circuitry 214. The quantization extraction circuitry 1308 adds the quantization information as feedback to the clock generation circuitry 116 by providing the quantization information to the adder circuitry 204 via the switching circuitry 1310.

[0129] In ​In the illustrated example, the switching circuit system 1310 couples, decouples, or couples and decouples the quantization extraction circuit system 1308 and the adder circuit system 204 based on a masking signal generated by the masking logic circuit system 218. In ​ the example, the switching circuit system 1310 is implemented by one or more switches (such as transistors, diodes, etc.) and combinational logic circuit systems, sequential logic circuit systems, or combinational logic circuit systems and sequential logic circuit systems, as further described herein. Also, the first input terminal and the second input terminal of the switching circuit system 1310 are respectively coupled to the first output terminal and the second output terminal of the quantization extraction circuit system 1308. In ​ the example, the third input terminal of the switching circuit system 1310 is coupled to the output terminal of the masking logic circuit system 218. Also, the first output terminal and the second output terminal of the switching circuit system 1310 are respectively coupled to the third input terminal and the fourth input terminal of the adder circuit system 204.

[0130] In ​ the illustrated example, the quantization extraction circuit system 1308 generates a positive voltage pulse, a negative voltage pulse, or a positive voltage pulse and a negative voltage pulse based on the DSM output signal. For example, if the DSM output signal is a logic high value, then the quantization extraction circuit system 1308 generates a positive voltage pulse that is 0.5 cycles wide of the VCO output signal. Also, for example, if the DSM output signal is a logic low value, then the quantization extraction circuit system 1308 generates a negative voltage pulse that is 0.5 cycles wide of the VCO output signal. In ​ the example, when there is a rising edge on the feedback signal, the masking logic circuit system 218 causes the switching circuit system 1310 to couple the third input terminal and the fourth input terminal of the adder circuit system 204 to ground for one cycle of the VCO output signal.

[0131] ​ is a block diagram of a clock generation circuit system 116 for an example implementation of ​ the quantization extraction circuit system 1308, the switching circuit system 1310, and the masking logic circuit system 218 that includes ​ In ​ the example, the quantization extraction circuit system 1308 includes an example first delay circuit system 1402, an example first NOT gate 1404, an example first AND gate 1406, an example second NOT gate 1408, an example second delay circuit system 1410, an example third NOT gate 1412, and an example second AND gate 1414. Also, the switching circuit system 1310 includes an example first switch 1416, an example second switch 1418, an example third switch 1420, an example fourth switch 1422, an example fourth NOT gate 1424, and an example ground terminal 1426. In ​In the example, the masking logic circuit system 218 includes an exemplary third delay circuit system 1428, an exemplary fifth NOT gate 1430, and an exemplary third AND gate 1432.

[0132] In ​ the illustrated example, the delay circuit system 1402 delays the DSM output signal by 0.5 clock cycles of the VCO output signal. In ​ the example, the delay circuit system 1402 is implemented by a D flip-flop controlled by the falling edge of the VCO output signal. Also, the first input terminal of the delay circuit system 1402 is coupled to the output terminal of the VCO circuit system 210. In ​ the example, the second input terminal of the delay circuit system 1402 is coupled to the output terminal of the DSM circuit system 1304. In ​ the example, the output terminal of the delay circuit system 1402 is coupled to the input terminal of the NOT gate 1404.

[0133] In ​ the illustrated example, the NOT gate 1404 is implemented by one or more transistors. In ​ the example, the input terminal of the NOT gate 1404 is coupled to the output terminal of the delay circuit system 1402. Also, the output terminal of the NOT gate 1404 is coupled to the second input terminal of the AND gate 1406. In ​ the illustrated example, the AND gate 1406 is implemented by one or more transistors. In ​ the example, the first input terminal of the AND gate 1406 is coupled to the output terminal of the DSM circuit system 1304. Also, the second input terminal of the AND gate 1406 is coupled to the output terminal of the NOT gate 1404. In ​ the example, the output terminal of the AND gate 1406 is coupled to the first terminal of the switch 1416.

[0134] In ​ the illustrated example, the NOT gate 1408 is implemented by one or more transistors. In ​ the example, the input terminal of the NOT gate 1408 is coupled to the output terminal of the DSM circuit system 1304. Also, the output terminal of the NOT gate 1408 is coupled to the second input terminal of the delay circuit system 1410 and the first input terminal of the AND gate 1414. In ​ the example, the delay circuit system 1410 delays the DSM output signal by 0.5 clock cycles of the VCO output signal. In ​ the example, the delay circuit system 1410 is implemented by a D flip-flop controlled by the falling edge of the VCO output signal. Also, the first input terminal of the delay circuit system 1410 is coupled to the output terminal of the VCO circuit system 210. In ​In an example, a second input terminal of the delay circuit system 1410 is coupled to an output terminal of the NOT gate 1408. In ​ In an example, an output terminal of the delay circuit system 1410 is coupled to an input terminal of the NOT gate 1412.

[0135] In ​ In the illustrated example, the NOT gate 1412 is implemented by one or more transistors. In ​ In an example, the input terminal of the NOT gate 1412 is coupled to the output terminal of the delay circuit system 1410. Also, the output terminal of the NOT gate 1412 is coupled to a second input terminal of the AND gate 1414. In ​ In the illustrated example, the AND gate 1414 is implemented by one or more transistors. In ​ In an example, a first input terminal of the AND gate 1414 is coupled to the output terminal of the NOT gate 1408. Also, the second input terminal of the AND gate 1414 is coupled to the output terminal of the NOT gate 1412. In ​ In an example, the output terminal of the AND gate 1414 is coupled to a first terminal of the switch 1420.

[0136] In ​ In the illustrated example, the switch 1416 is implemented by a transistor. In ​ In an example, the first terminal of the switch 1416 is coupled to the output terminal of the AND gate 1406. Also, the second terminal of the switch 1416 is coupled to a fourth input terminal of the adder circuit system 204. In ​ In an example, a control terminal of the switch 1416 is coupled to the output terminal of the NOT gate 1424. In ​ In an example, the switch 1418 is implemented by a transistor. Also, the first terminal of the switch 1418 is coupled to the ground terminal 1426. In ​ In an example, the second terminal of the switch 1418 is coupled to a fourth input terminal of the adder circuit system 204. Also, the control terminal of the switch 1418 is coupled to the output terminal of the AND gate 1432.

[0137] In ​ In the illustrated example, the switch 1420 is implemented by a transistor. In ​ In an example, the first terminal of the switch 1420 is coupled to the output terminal of the AND gate 1414. Also, the second terminal of the switch 1420 is coupled to a third input terminal of the adder circuit system 204. In ​ In an example, the control terminal of the switch 1420 is coupled to the output terminal of the NOT gate 1424. Also, the switch 1422 is implemented by a transistor. In ​ In an example, the first terminal of the switch 1422 is coupled to the ground terminal 1426. Also, the second terminal of the switch 1422 is coupled to a third input terminal of the adder circuit system 204. In​ In the example of, the control terminal of switch 1422 is coupled to the output terminal of AND gate 1432. Also, NOT gate 1424 is implemented by one or more transistors. In ​ In the example of, the input terminal of NOT gate 1424 is coupled to the output terminal of AND gate 1432. Also, the output terminal of NOT gate 1424 is coupled to the control terminal of switch 1416 and the control terminal of switch 1420.

[0138] In ​ In the illustrated example of, delay circuit system 1428 delays the feedback signal by one clock cycle of the VCO output signal. In ​ In the example of, delay circuit system 1428 is implemented by a D flip-flop controlled by the rising edge of the VCO output signal. Also, the first input terminal of delay circuit system 1428 is coupled to the output terminal of VCO circuit system 210. In ​ In the example of, the second input terminal of delay circuit system 1428 is coupled to the output terminal of divider circuit system 214. Also, the output terminal of delay circuit system 1428 is coupled to the input terminal of NOT gate 1430.

[0139] In ​ In the illustrated example of, NOT gate 1430 is implemented by one or more transistors. In ​ In the example of, the input terminal of NOT gate 1430 is coupled to the output terminal of delay circuit system 1428. Also, the output terminal of NOT gate 1430 is coupled to the second input terminal of AND gate 1432. In ​ In the example of, AND gate 1432 is implemented by one or more transistors. Also, the first input terminal of AND gate 1432 is coupled to the output terminal of divider circuit system 214. In ​ In the example of, the second input terminal of AND gate 1432 is coupled to the output terminal of NOT gate 1430. Also, the output terminal of AND gate 1432 is coupled to the control terminal of switch 1418, the control terminal of switch 1422, and the input terminal of NOT gate 1424.

[0140] In ​ In the illustrated example of, when the DSM output signal is logic high, AND gate 1406 of quantization extraction circuit system 1308 generates a positive voltage pulse with a width of 0.5 cycles of the VCO output signal. Also, when the DSM output signal is logic low, AND gate 1414 of quantization extraction circuit system 1308 generates a negative voltage pulse with a width of 0.5 cycles of the VCO output signal. In ​In an example, when there is a rising edge on the feedback signal, AND gate 1432 of masking logic circuit system 218 causes switches 1418 and 1422 to couple the fourth input terminal and the third input terminal of adder circuit system 204 to ground respectively for one period of the VCO output signal. Otherwise, switches 1416 and 1420 couple a positive voltage pulse, a negative voltage pulse, or a positive voltage pulse and a negative voltage pulse to the fourth input terminal and the third input terminal of adder circuit system 204 respectively.

[0141] Although ​ and 14 illustrate example ways of implementing divider circuit system 212, quantization feedback circuit system 216, and masking logic circuit system 218, ​ and 14 one or more of the elements, processes, or apparatuses illustrated in ​ and 14 can be implemented at least by combination, division, rearrangement, omission, elimination, or in any other way. Additionally, ​ example MMFD circuit system 1302, example DSM circuit system 1304, example DSM input generation circuit system 1306, or more generally example divider circuit system 212 of ​ example delay circuit system 1402, example NOT gate 1404, example AND gate 1406, example NOT gate 1408, example delay circuit system 1410, example NOT gate 1412, example AND gate 1414, or more generally quantization extraction circuit system 1308 of ​ example switches 1416, example switches 1418, example switches 1420, example switches 1422, example NOT gate 1424, or more generally example switching circuit system 1310 of

[0142] Thus, for example, ​ and 14 example MMFD circuit system 1302, example DSM circuit system 1304, example DSM input generation circuit system 1306, or more generally example divider circuit system 212 of ​ example delay circuit system 1402, example NOT gate 1404, example AND gate 1406, example NOT gate 1408, example delay circuit system 1410, example NOT gate 1412, example AND gate 1414, or more generally quantization extraction circuit system 1308 of ​Example switches 1416, example switches 1418, example switches 1420, example switches 1422, example NOT gate 1424, or more generally example switching circuitry 1310, or ​ any of example delay circuitry 1428, example NOT gate 1430, example AND gate 1432, or more generally example masking logic circuitry 218 may be implemented by at least one of a combination of programmable circuitry and machine-readable instructions (such as firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic device (PLD), or field programmable logic device (FPLD) (such as FPGA).

[0143] Additionally, ​ and 14 example divider circuitry 212, ​ and 14 example quantization extraction circuitry 1308, ​ and 14 example switching circuitry 1310, or more generally ​ and 14 quantization feedback circuitry 216 or ​ example masking logic circuitry 218 may include one or more elements, processes, or devices to supplement or replace those shown as ​ and 14 shown, and may include more than one of any or all of the shown elements, processes, and devices.

[0144] ​ To represent an example machine-readable instruction or example operation 1500 that may be executed, instantiated, or performed by an example programmable circuitry implementation of clock generation circuitry 116 ​ is a flowchart. ​ Example machine-readable instruction or example operation 1500 begins at block 1502 where the PFD circuitry 202 compares the phase of a reference signal with a feedback signal to generate a PFD output signal having a first voltage. At block 1504, adder circuitry 204 adds the PFD output signal to a first quantization output signal having a second voltage and a second quantization output signal having a third voltage. For example, adder circuitry 204 adds the PFD output signal to the first quantization output signal and the second quantization output signal to generate a charge pump control signal having a fourth voltage.

[0145] At ​In the illustrated example, at block 1506, charge pump circuitry 206 increases or decreases a fifth voltage of a control signal based on a fourth voltage of a charge pump control signal. At block 1508, low pass filter circuitry 208 filters the control signal to generate a filtered control signal having the fifth voltage. At ​ the example, at block 1510, VCO circuitry 210 generates a VCO output signal based on the filtered control signal. At block 1512, MMFD circuitry 1302 generates an MMFD output signal based on the DSM output signal and the VCO output signal.

[0146] At ​ the illustrated example, at block 1514, divider circuitry 214 generates a feedback signal based on the MMFD output signal. After block 1514, PFD circuitry 202 compares the phases of a reference signal and the feedback signal at block 1502 to generate a PFD output signal having a first voltage. And, after block 1514, masking logic circuitry 218 determines whether to generate a masking signal at block 1516 based on the feedback signal.

[0147] At ​ the illustrated example, at block 1518, DSM circuitry 1304 generates a DSM output signal based on the MMFD output signal and a DSM reference signal. At block 1520, quantization extraction circuitry 1308 samples the DSM output signal to generate a first quantization output signal and a second quantization output signal that include quantization information present in the MMFD output signal. At ​ the example, at block 1522, masking logic circuitry 218 generates a masking logic signal to mask redundant information present in the quantization information. For example, the redundant information indicates rising edges present in the MMFD output signal and the feedback signal. At block 1524, based on the masking signal, switching circuitry 1310 couples the first quantization output signal and the second quantization output signal to adder circuitry 204. After block 1524, adder circuitry 204 adds the PFD output signal to the first quantization output signal and the second quantization output signal to generate a charge pump control signal having a fourth voltage.

[0148] ​ and 9 15 illustrate example machine-readable instructions (which may be executed by programmable circuitry to implement or instantiate ​ and 7 8, 13, or 14 of at least one of the clock generation circuitry 116) or represent example operations (which may be executed by programmable circuitry to implement or instantiate ​ and 7, flowchart of a clock generation circuit system 116) of at least one of 8, 13, or 14. The machine-readable instructions may be one or more executable programs or portions of one or more executable programs executed by a programmable circuit system (e.g., the programmable circuit system 1612 shown in the example programmable circuit system platform 1600 described below), or may be one or more functions or portions of functions to be executed by an example programmable circuit system (e.g., an FPGA). In some instances, the machine-readable instructions cause operations, tasks, etc. to be carried out or executed in an automated manner in the real world. As used herein, "automated" means without human intervention. ​ The program may be embodied in instructions (e.g., at least one of software or firmware) stored on one or more non-transitory computer-readable or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, compact discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROMs, solid state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memory (RAM), etc.) or any other storage device or storage disk. The instructions of the non-transitory computer-readable or machine-readable media may be programmed, executed or programmed and executed by a programmable circuit system located in one or more hardware devices, but the entire program or portions thereof may alternatively be executed or instantiated by one or more hardware devices other than the programmable circuit system or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that facilitates communication between the server and the endpoint client hardware device. Similarly, the non-transitory computer-readable storage media may include one or more media. Additionally, although reference

[0149] is made ​ , 9The flowcharts depicted in FIGS. 14 and 15 describe example programs, but many other methods of implementing the example clock generation circuit system 116 may alternatively be used. For example, the order of execution of the blocks of the flowchart may be changed, or some of the blocks described may be changed, eliminated, or combined. In some instances, any and all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., at least one of processor circuitry, discrete analog circuitry, discrete digital circuitry, integrated analog circuitry, integrated digital circuitry, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuitry, etc.) structured to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed at different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, the programmable circuitry may be a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., or any combination thereof.

[0150] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.)) or a data structure (e.g., a portion of an instruction, code, a representation of code, etc.), the data being usable to create, manufacture, or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations of a network or network collection (e.g., in the cloud, at an edge device, etc.). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpackaged, distributed, redistributed, compiled, etc. such that the machine-readable instructions are directly readable, interpretable, or executable by a computing device or other machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, or stored on separate computing devices. When these parts are decrypted, decompressed, or combined, they form a set of computer-executable instructions or machine-executable instructions that implement one or more functions or operations, which together may form, for example, a program as described herein.

[0151] In another example, machine-readable instructions may be stored in a state where they are readable by programmable circuitry, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc. may need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, it may be necessary to configure the machine-readable instructions (e.g., stored settings, data inputs, recorded network addresses, etc.) before the machine-readable instructions or corresponding program can be executed in whole or in part. Thus, machine-readable, computer-readable, or machine-readable media as used herein may include instructions or programs regardless of the particular format or state of the machine-readable instructions or programs.

[0152] The machine-readable instructions described herein may be represented in any past, current, or future instruction language, scripting language, programming language, etc. By way of example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0153] As mentioned above, ​ 、 9Example operations of 0 and 15 can be implemented using executable instructions (such as computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device or storage disk, and to exclude propagated signals and to exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and any other storage device or storage disk in which information is stored for any duration (e.g., an extended period of time, permanently, briefly, temporarily buffered, or cached). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (e.g., mechanical, magnetic, electrical, etc.) hardware for retaining information for a period of time, and to exclude propagated signals and to exclude transmission media. Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memories, flash memories, optical disks, magnetic disks, disk drives, and redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical or electrical device, hardware, or circuitry, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., or which is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0154] "Including" and "comprising" (and all of their forms and tenses) are used herein as open terms. Thus, whenever a claim uses any form of "including" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a leading term or is employed within any type of claim recitation, additional elements, terms, etc. may exist without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term in a leading of a claim, for example, it is open in the same manner as the terms "including" and "comprising" are open.

[0155] As used herein, singular references (e.g., "a", "an", "first", "second", etc.) do not exclude pluralities. As used herein, the term "a" or "an" object refers to one or more of the objects. The terms "a" (or "an"), "one or more", and "at least one" are used interchangeably herein. Additionally, although listed separately, multiple components, elements, or acts may be implemented by, for example, the same entity or object. Further, although individual features may be included in different instances or embodiments, these features are capable of being combined, and inclusion in different instances or embodiments does not imply that a combination of the features is not feasible or not advantageous.

[0156] ​ FIG. is a block diagram of an example programmable circuit system platform 1600 that is structured to execute or instantiate ​ , 9 or at least one of 15 example machine-readable instructions or example operations to implement ​ , 7 , 8, 13 or 14, a clock generation circuit system 116. The programmable circuit system platform 1600 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a phone, a smartphone, a tablet computer such as an iPad TM ), a personal digital assistant (PDA), an Internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, headphones (e.g., augmented reality (AR) headphones, virtual reality (VR) headphones, etc.) or other wearable devices, or any other type of computing or electronic device.

[0157] The programmable circuit system platform 1600 of the illustrated example includes a programmable circuit system 1612. The programmable circuit system 1612 of the illustrated example is hardware. For example, the programmable circuit system 1612 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuit system 1612 can be implemented by one or more semiconductor (e.g., silicon-based) devices. In this example, the programmable circuit system 1612 implements ​ an example PFD circuit system 202, an example adder circuit system 204, an example charge pump circuit system 206, an example low-pass filter circuit system 208, an example VCO circuit system 210, an example divider circuit system 212, an example divider circuit system 214, an example quantization feedback circuit system 216, an example masking logic circuit system 218, or more generally an example clock generation circuit system 116.

[0158] The programmable circuit system 1612 of the illustrated example includes a local memory 1613 (e.g., cache memory, registers, etc.). The programmable circuit system 1612 of the illustrated example communicates with main memories 1614, 1616 via a bus 1618, and the main memories include a volatile memory 1614 and a non-volatile memory 1616. The volatile memory 1614 can be implemented by at least one of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), dynamic random access memory or any other type of RAM device. The non-volatile memory 1616 can be implemented by at least one of a flash memory or any other desired type of memory device. Access to the main memories 1614, 1616 of the illustrated example is controlled by a memory controller 1617. In some examples, the memory controller 1617 can be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuit system to manage the data stream to and from the main memories 1614, 1616.

[0159] The programmable circuit system platform 1600 of the illustrated example further includes an interface circuit system 1620. The interface circuit system 1620 can be implemented in hardware using any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, or a peripheral component interconnect express (PCIe) interface.

[0160] In the illustrated example, one or more input devices 1622 are connected to the interface circuit system 1620. The input devices 1622 allow a user (e.g., a human user, a machine user, etc.) to input data or commands into the programmable circuit system 1612. The input devices 1622 can be implemented by, for example, an audio sensor, a microphone, a camera (static or video), a keyboard, a button, a mouse, a touch screen, a track pad, a track ball, an isopoint device, or a voice recognition system.

[0161] One or more output devices 1624 are also connected to the interface circuit system 1620 of the illustrated example. The output devices 1624 can be implemented by, for example, a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, or a speaker. Thus, the interface circuit system 1620 of the illustrated example can include a graphics driver card, a graphics driver chip, or a graphics processor circuit system such as a GPU.

[0162] The interface circuit system 1620 of the illustrated example also includes a communication device, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with an external machine (e.g., any kind of computing device) via a network 1626. The communication can be carried out, for example, via an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a non-line-of-sight wireless system, a cellular phone system, an optical connection, etc.

[0163] The programmable circuit system platform 1600 of the illustrated example also includes one or more mass storage disks or devices 1628 to store at least one of firmware, software, or data. Examples of such mass storage disks or devices 1628 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices or SSDs.

[0164] Can be ​ , 9 or at least one of 15, the machine-readable instructions 1632 can be stored in at least one of the mass storage device 1628, the volatile memory 1614, the non-volatile memory 1616, or stored on at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0165] In this specification, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment that includes any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0166] In this specification, the term "coupled" can cover a connection, communication, or signal path that enables a functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform a certain action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0167] Numeric identifiers such as "first", "second", "third", etc. are only used to distinguish elements of basically the same type in terms of structure or function. These identifiers used in the detailed description do not necessarily match those used in the claims.

[0168] A device “configured to” perform a task or function can be configured (e.g., programmed or hardwired) by the manufacturer at the time of manufacture to perform the function, or can be configured (or reconfigured) by the user after manufacture to perform the function or other additional or alternative functions. The configuration can be performed by at least one of the device's firmware or software programming, by at least one of the construction or layout of the device's hardware components and interconnections, or by a combination thereof.

[0169] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote the interconnection between or the ends of device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0170] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including at least one of one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, inductors, etc.), or one or more sources (e.g., voltage source, current source, etc.) may alternatively include only semiconductor elements within a single physical device (e.g., semiconductor die, integrated circuit (IC) package, etc.), and may be adapted to be coupled to at least some of the passive elements or sources to form the described structure at the time of manufacture or after manufacture, e.g., by a final user or a third party.

[0171] The circuits described herein can be reconfigured to include replacement components to provide functions that are at least partially similar to the functions available prior to the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. Although some elements of the described examples are included within an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be included within the integrated circuit, or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in / on the same printed circuit board.

[0172] The use of the phrase "ground" in the foregoing description encompasses chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, or any other form of ground connection applicable to or suitable for the teachings of this specification. Unless otherwise stated, "about", "substantially", or "essentially" before a value means + / - 10% of that value, or, if the value is zero, a reasonable range of values near zero.

[0173] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

[0174] In accordance with the foregoing, it should be appreciated that example systems, devices, articles, and methods for using quantization extraction in a phase-locked loop oscillator have been described. The described systems, devices, articles, and methods achieve phase noise performance similar to that found in integer PLLs of similar bandwidth and reduce the impact of quantization noise to negligible levels. Additionally, the described examples do not operate the charge pump circuitry of the PLL in a non-linear region. The examples described herein also consume less semiconductor die area and less power compared to other techniques. Also, the examples described herein maintain quantization noise shaping even when there are delay mismatches in the transmission paths between circuits. Further, the examples described herein utilize an integer divider in the feedback path.

[0175] Moreover, the described systems, devices, articles, and methods are resilient to any shape of noise folding. The examples described herein improve the inherent noise performance of the VCO circuitry of the PLL and achieve no LCM reference spurs or very low LCM reference spurs. Also, the examples described herein are not dependent on the duty cycle of the clock signal. The described systems, devices, articles, and methods improve the efficiency of using a computing device by consuming less semiconductor die area and less power than other techniques. The described systems, devices, articles, and methods thus relate to one or more improvements in the operation of machines such as, for example, computers or other electronic or mechanical devices.

[0176] The appended claims are hereby incorporated by reference into this detailed description. Although certain example systems, devices, articles, and methods have been described herein, the scope of this patent is not limited thereto. Instead, this patent covers all systems, devices, articles, and methods that fall entirely within the scope of the claims of this patent.

Claims

1. A device comprising: A voltage controlled oscillator (VCO) circuit system comprising an output terminal and an input terminal; a first frequency divider circuitry comprising a first output terminal, a second output terminal, and an input terminal coupled to the output terminal of the VCO circuitry; a quantized feedback circuit system comprising an output terminal, a first input terminal, a second input terminal, and a third input terminal, the first input terminal of the quantized feedback circuit system being coupled to the output terminal of the VCO circuit system, the second input terminal of the quantized feedback circuit system being coupled to the first output terminal of the first frequency divider circuit system; a second frequency divider circuitry comprising an output terminal and an input terminal coupled to the second output terminal of the first frequency divider circuitry; a phase frequency detector (PFD) circuitry comprising an output terminal and an input terminal coupled to the output terminal of the second frequency divider circuitry; masking logic circuitry including an output terminal coupled to the third input terminal of the quantization feedback circuitry, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the second frequency divider circuitry; as well as Adder circuitry includes an output terminal coupled to the input terminal of the VCO circuitry, a first input terminal coupled to the output terminal of the PFD circuitry, and a second input terminal coupled to the output terminal of the quantization feedback circuitry.

2. The apparatus according to claim 1, wherein: The PFD circuit system is a first PFD circuit system; The quantization feedback circuit system includes a quantization extraction circuit system, a switching circuit system, and a second PFD circuit system; the quantization extraction circuitry comprising an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the first output terminal of the first frequency divider circuitry; The switching circuitry includes an output terminal, a first input terminal coupled to the output terminal of the quantization extraction circuitry, and a second input terminal coupled to the output terminal of the masking logic circuitry; and The second PFD circuitry includes an output terminal coupled to the second input terminal of the adder circuitry and an input terminal coupled to the output terminal of the switching circuitry.

3. The apparatus according to claim 1, wherein: The quantization feedback circuit system includes a quantization extraction circuit system and a switching circuit system; The quantization extraction circuitry includes an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the first output terminal of the first frequency divider circuitry; and The switching circuitry includes an output terminal coupled to the second input terminal of the adder circuitry, a first input terminal coupled to the output terminal of the quantization extraction circuitry, and a second input terminal coupled to the output terminal of the masking logic circuitry.

4. The apparatus of claim 1, further comprising: a charge pump circuitry comprising an output terminal and an input terminal coupled to the output terminal of the adder circuitry; and Low pass filter circuitry includes an output terminal coupled to the input terminal of the VCO circuitry and an input terminal coupled to the output terminal of the charge pump circuitry.

5. The apparatus of claim 1, wherein the input terminal of the PFD circuitry is a first input terminal and the PFD circuitry includes a second input terminal to be coupled to an oscillator.

6. A device comprising: A voltage controlled oscillator (VCO) circuit system comprising an output terminal and an input terminal; a multi-mode frequency divider MMFD circuitry comprising an output terminal and an input terminal coupled to the output terminal of the VCO circuitry; a second frequency divider circuitry comprising an output terminal and an input terminal coupled to the output terminal of the MMFD circuitry; first phase frequency detector PFD circuitry comprising an output terminal and an input terminal coupled to the output terminal of the second frequency divider circuitry; quantization extraction circuitry comprising an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the MMFD circuitry; a switching circuit system comprising an output terminal, a first input terminal, and a second input terminal, the first input terminal of the switching circuit system being coupled to the output terminal of the quantization extraction circuit system; a second PFD circuitry comprising an output terminal and an input terminal coupled to the output terminal of the switching circuitry; masking logic circuitry including an output terminal coupled to the second input terminal of the switching circuitry, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the second divider circuitry; as well as Adder circuitry includes an output terminal coupled to the input terminal of the VCO circuitry, a first input terminal coupled to the output terminal of the first PFD circuitry, and a second input terminal coupled to the output terminal of the second PFD circuitry.

7. The apparatus of claim 6, wherein: The masking logic circuit system includes a delay circuit system and an AND gate; The delay circuitry includes an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the second divider circuitry; and The AND gate includes an output terminal coupled to the second input terminal of the switching circuitry, a first input terminal coupled to the output terminal of the second divider circuitry, and a second input terminal coupled to the output terminal of the delay circuitry.

8. The apparatus of claim 6, wherein: The quantization extraction circuit system includes a first delay circuit system and a second delay circuit system; The first delay circuitry includes a first input terminal coupled to the output terminal of the VCO circuitry and a second input terminal coupled to the output terminal of the MMFD circuitry; and The second delay circuitry includes a first input terminal coupled to the output terminal of the VCO circuitry and a second input terminal coupled to the output terminal of the MMFD circuitry.

9. The apparatus of claim 6, wherein the switching circuitry comprises: a first NOT gate comprising an output terminal and an input terminal coupled to the output terminal of the masking logic circuitry; an OR gate comprising an output terminal, a first input terminal coupled to the output terminal of the first NOT gate, and a second input terminal coupled to the output terminal of the masking logic circuitry; and A second NOT gate includes an output terminal and an input terminal coupled to the output terminal of the OR gate.

10. The apparatus of claim 9, wherein the output terminal of the quantization extraction circuitry is a first output terminal, the input terminal of the second PFD circuitry is a first input terminal, and the switching circuitry comprises: a first switch including a first terminal coupled to the first output terminal of the quantization extraction circuitry, a second terminal coupled to the first input terminal of the second PFD circuitry, and a control terminal coupled to the output terminal of the first NOT gate; a second switch comprising a first terminal coupled to a second output terminal of the quantization extraction circuitry, a second terminal coupled to the first input terminal of the second PFD circuitry, and a control terminal coupled to the output terminal of the masking logic circuitry; a third switch comprising a first terminal coupled to the second output terminal of the quantization extraction circuitry, a second terminal coupled to a second input terminal of the second PFD circuitry, and a control terminal coupled to the output terminal of the OR gate; as well as A fourth switch includes a first terminal coupled to a ground terminal, a second terminal coupled to the second input terminal of the second PFD circuitry, and a control terminal coupled to the output terminal of the second NOT gate.

11. A device comprising: A voltage controlled oscillator (VCO) circuit system comprising an output terminal and an input terminal; a multi-mode frequency divider MMFD circuit system comprising an output terminal, a first input terminal, and a second input terminal, the first input terminal of the MMFD circuit system being coupled to the output terminal of the VCO circuit system; a second frequency divider circuitry comprising an output terminal and an input terminal coupled to the output terminal of the MMFD circuitry; a phase frequency detector (PFD) circuitry comprising an output terminal and an input terminal coupled to the output terminal of the second frequency divider circuitry; a delta-sigma modulator (DSM) circuitry comprising an output terminal coupled to the second input terminal of the MMFD circuitry and an input terminal coupled to the output terminal of the MMFD circuitry; quantization extraction circuitry comprising an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the DSM circuitry; a switching circuit system comprising an output terminal, a first input terminal, and a second input terminal, the first input terminal of the switching circuit system being coupled to the output terminal of the quantization extraction circuit system; masking logic circuitry including an output terminal coupled to the second input terminal of the switching circuitry, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the second divider circuitry; as well as Adder circuitry includes an output terminal coupled to the input terminal of the VCO circuitry, a first input terminal coupled to the output terminal of the PFD circuitry, and a second input terminal coupled to the output terminal of the switching circuitry.

12. The apparatus of claim 11, wherein: The masking logic circuit system includes a delay circuit system, an AND gate and a NOT gate; the delay circuitry comprising an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the second divider circuitry; The NOT gate includes an output terminal and an input terminal coupled to the output terminal of the delay circuitry; and The AND gate includes an output terminal coupled to the second input terminal of the switching circuitry, a first input terminal coupled to the output terminal of the second divider circuitry, and a second input terminal coupled to the output terminal of the NOT gate.

13. The apparatus of claim 11, wherein: The quantization extraction circuit system includes a delay circuit system, a NOT gate and an AND gate; the delay circuitry comprising an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the DSM circuitry; The NOT gate includes an output terminal and an input terminal coupled to the output terminal of the delay circuitry; and The AND gate includes an output terminal coupled to the first input terminal of the switching circuitry, a first input terminal coupled to the output terminal of the DSM circuitry, and a second input terminal coupled to the output terminal of the NOT gate.

14. The apparatus of claim 11, wherein: The quantization extraction circuit system comprises a first NOT gate, a delay circuit system, a second NOT gate and an AND gate; The first NOT gate includes an output terminal and an input terminal coupled to the output terminal of the DSM circuitry; The delay circuitry includes an output terminal, a first input terminal coupled to the output terminal of the VCO circuitry, and a second input terminal coupled to the output terminal of the first NOT gate; The second NOT gate includes an output terminal and an input terminal coupled to the output terminal of the delay circuitry; and The AND gate includes an output terminal coupled to the first input terminal of the switching circuitry, a first input terminal coupled to the output terminal of the first NOT gate, and a second input terminal coupled to the output terminal of the second NOT gate.

15. The apparatus of claim 11, wherein the output terminal of the quantization extraction circuitry is a first output terminal, the adder circuitry includes a third input terminal, and the switching circuitry includes: a NOT gate including an output terminal and an input terminal coupled to the output terminal of the masking logic circuitry; a first switch including a first terminal coupled to the first output terminal of the quantization extraction circuitry, a second terminal coupled to the second input terminal of the adder circuitry, and a control terminal coupled to the output terminal of the NOT gate; a second switch including a first terminal coupled to a ground terminal, a second terminal coupled to the second input terminal of the adder circuitry, and a control terminal coupled to the output terminal of the masking logic circuitry; a third switch including a first terminal coupled to a second output terminal of the quantization extraction circuitry, a second terminal coupled to the third input terminal of the adder circuitry, and a control terminal coupled to the output terminal of the NOT gate; as well as A fourth switch includes a first terminal coupled to a ground terminal, a second terminal coupled to the third input terminal of the adder circuitry, and a control terminal coupled to the output terminal of the masking logic circuitry.

16. A method comprising: generating a first quantization feedback signal and a second quantization feedback signal based on the masking signal, wherein the first quantization feedback signal and the second quantization feedback signal are used to capture quantization information present in the frequency divider output signal; as well as The mask signal is generated based on a feedback signal, the mask signal being used to mask redundant information present in the quantized information, the feedback signal being based on an output signal of the frequency divider. 17 . The method of claim 16 , further comprising comparing the feedback signal to a delayed feedback signal to generate the masking signal, the delayed feedback signal being based on the feedback signal.

18. The method of claim 16, further comprising: generating an anti-phase delayed feedback signal based on the feedback signal; and The feedback signal is compared with the anti-phase delayed feedback signal to generate the masking signal.

19. The method of claim 16, wherein the quantization information indicates a rising edge present in the divider output signal.

20. The method of claim 16, wherein the redundant information indicates rising edges present in the divider output signal and the feedback signal.

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