Analog-to-digital converter and analog-to-digital conversion method

Abstract

Various embodiments of the present disclosure relate to an analog-to-digital conversion device, and the analog-to-digital conversion device may include a comparator having a first input terminal, a second input terminal, and an output terminal, comparing an input signal input to the first input terminal with a reference voltage input to the second input terminal, and outputting a comparison result value to the output terminal, the reference voltage decreases a preset value from a previous value in response to an input of each clock signal; a counter configured to output a digital count value, the digital count value being increased by 1 each time a clock signal is input; a register configured to latch and store a digital count value based on the comparison result value, and generate a digital value corresponding to the input signal based on the latched digital count value; a first blocking capacitor, one end of the first blocking capacitor being connected to the first input terminal, and the first blocking capacitor transmitting an input signal to the first input terminal; and a control circuit configured to generate a clock signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0189407, filed on December 22, 2023, and Korean Patent Application No. 10 - 2024 - 0097902, filed on July 24, 2024. The entire contents of these two Korean patent applications are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to an analog - to - digital converter and an analog - to - digital conversion method, and more particularly, to an analog - to - digital converter and its conversion method that can be provided in a smaller area while improving the operation speed and reducing power consumption. Background art

[0004] An analog - to - digital converter (ADC) is an electronic circuit for converting an analog electrical signal into a digital electrical signal. That is, the ADC can extract the amplitude of an analog signal at a preset period, and quantize and convert the extracted analog signal into a digital signal.

[0005] Recently, with the increase in the amount of data to be processed in an image processing device, a large number of ADCs are required and operated at a high operation speed simultaneously. To have a large number of ADCs, the area may increase significantly, and when operating at a high operation speed, the power consumption may increase. Summary of the invention

[0006] Accordingly, various embodiments of the present disclosure are directed to providing an analog - to - digital converter that can reduce the area and power consumption in an environment where multiple analog - to - digital converters are required.

[0007] The object of the present disclosure is not limited to the above - described object, and other objects not described will be clearly understood by those skilled in the art to which the present disclosure pertains from the following description.

[0008] According to various embodiments of the present disclosure, an analog - to - digital conversion device may include: a comparator having a first input terminal, a second input terminal, and an output terminal, and configured to compare an input signal input to the first input terminal with a reference voltage input to the second input terminal, and output a comparison result value to the output terminal, the reference voltage decreasing by a preset value from a previous value in response to the input of each clock signal; a counter configured to output a digital count value that increases by 1 each time a clock signal is input; a register configured to latch and store the digital count value based on the comparison result value, and generate a digital value corresponding to the input signal based on the latched digital count value; a first blocking capacitor having one end connected to the first input terminal, and the first blocking capacitor transmitting the input signal to the first input terminal; and a control circuit configured to generate a clock signal.

[0009] According to various embodiments of the present disclosure, an analog-to-digital conversion device may include: a reference voltage generator configured to generate a reference voltage that decreases by a preset value from a previous value in response to the input of each clock signal; a counter configured to output a digital count value that increases by 1 each time a clock signal is input; a control circuit configured to generate a clock signal; and a plurality of analog-to-digital conversion circuits. Herein, each of the plurality of analog-to-digital conversion circuits may include: a comparator having a first input terminal, a second input terminal, and an output terminal, and configured to compare an input signal input to the first input terminal with a reference voltage input to the second input terminal and output a comparison result value to the output terminal; a register configured to latch and store the digital count value based on the comparison result value and generate a digital value corresponding to the input signal based on the latched digital count value; and a first blocking capacitor having one end connected to the first input terminal, and the first blocking capacitor transmitting the input signal to the first input terminal.

[0010] According to various embodiments of the present disclosure, a complementary metal-oxide semiconductor (CMOS) image sensor may include: a pixel array including a plurality of pixels formed at contact points of a plurality of rows and a plurality of columns; a row decoding circuit configured to select a row outputting a pixel signal from the pixel array; a reference voltage generator configured to generate a reference voltage that decreases by a preset value from a previous value in response to the input of each clock signal; a counter configured to output a digital count value that increases by 1 each time a clock signal is input; a control circuit configured to generate a clock signal; and a plurality of analog-to-digital conversion circuits provided in each of the plurality of columns and configured to generate a digital value of a pixel signal of each column using the reference voltage.

[0011] Herein, each of the plurality of analog-to-digital conversion circuits may include: a comparator having a first input terminal, a second input terminal, and an output terminal, and configured to compare an input signal input to the first input terminal with a reference voltage input to the second input terminal and output a comparison result value to the output terminal; a register configured to latch and store the digital count value based on the comparison result value and generate a digital value corresponding to the input signal based on the latched digital count value; and a first blocking capacitor having one end connected to the first input terminal, and the first blocking capacitor transmitting the input signal to the first input terminal.

[0012] According to various embodiments of the present disclosure, an analog in-memory computing (ACiM) system may include: a memory array storing weight information of contacts of a plurality of rows and a plurality of columns; a plurality of digital-to-analog converters provided at input ends of each of the plurality of rows and configured to convert digital input signals of each of the plurality of rows into analog input signals; a reference voltage generator configured to generate a reference voltage that decreases by a preset value from a previous value in response to an input of each clock signal; a counter configured to output a digital count value that increases by 1 each time a clock signal is input; a control circuit configured to generate a clock signal; and a plurality of analog-to-digital conversion circuits provided in each of the plurality of columns and configured to convert analog output signals of each of the plurality of columns into digital output signals, where the analog output signals of each of the plurality of columns are generated by physically multiplying the analog input signals of each of the plurality of rows by corresponding weight information and physically adding the multiplication results of all rows of each of the plurality of columns.

[0013] Herein, each of the plurality of analog-to-digital conversion circuits may include: a comparator having a first input end, a second input end, and an output end, and configured to compare an input signal input to the first input end with a reference voltage input to the second input end and output a comparison result value to the output end; a register configured to latch and store the digital count value based on the comparison result value and generate a digital value corresponding to the input signal based on the latched digital count value; and a first blocking capacitor having one end connected to the first input end, and the first blocking capacitor transmits the input signal to the first input end. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing the structure of the analog-to-digital conversion circuit proposed herein.

[0015] Figure 2 is a diagram for conceptually describing the correlated double sampling (CDS) method for sampling an analog input signal IN in the analog-to-digital conversion circuit proposed herein.

[0016] Figure 3 is a signal timing diagram when sampling an analog input signal IN according to the CDS method in the analog-to-digital conversion circuit proposed herein.

[0017] Figure 4 is for describing based on Figure 1 the analog-to-digital conversion circuit to derive a flowchart of the correlated double sampling method for a sampling result.

[0018] Figure 5 is showing Figure 1Diagrams of the input signal IN, the output CNT, and the signal IN1 obtained by removing the DC component from the input signal passing through the DC blocking capacitor.

[0019] Figure 6 It is a diagram showing the structure of an analog-to-digital conversion device provided with a plurality of analog-to-digital conversion circuits proposed herein.

[0020] Figure 7 It is a diagram showing Figure 6 An example of applying a plurality of analog-to-digital conversion circuits to an analog computing in memory (ACiM) system.

[0021] Figure 8 It is a diagram showing Figure 6 An example of applying a plurality of analog-to-digital conversion circuits to a CMOS image sensor. Detailed implementation mode

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure. However, the present disclosure can be implemented in various different forms and is not limited to the embodiments described herein. In addition, in order to clearly describe the present disclosure in the drawings, components irrelevant to the description have been omitted, and throughout the specification, similar components have been denoted by similar reference numerals.

[0023] In addition, when a certain part is described as "including" a certain component, this means further including another component without excluding another component, unless otherwise specifically stated.

[0024] The terms used in the embodiments of the present disclosure are general terms that are currently used as widely as possible when considering the functions in the present disclosure, but these can be changed according to the intentions or circumstances of those skilled in the art, the emergence of new technologies, etc. In addition, in specific cases, there are terms arbitrarily selected by the applicant, and in such cases, the meanings will be described in detail in the description of the corresponding embodiments. Therefore, the terms used in this embodiment should be defined based on the meanings of the terms and the overall content of this embodiment, rather than only based on the names of the terms.

[0025] In the embodiments of the present disclosure, ordinal numbers such as "first" or "second" may be used to describe various components, but the components are not limited by the terms. The terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present disclosure, the second component may be referred to as the first component, and similarly, the first component may also be referred to as the second component. The term "and / or" includes combinations of a plurality of related listed items or any one of a plurality of related listed items.

[0026] In addition, in the embodiments of the present disclosure, unless the context otherwise requires, singular expressions include plural expressions.

[0027] Figure 1 is a diagram showing the structure of the analog-to-digital conversion circuit proposed herein, Figure 2 is a diagram for conceptually describing the correlated double sampling (CDS) method for sampling an analog input signal IN in the analog-to-digital conversion circuit proposed herein, Figure 3 is a signal timing diagram when sampling the analog input signal IN according to the CDS method in the analog-to-digital conversion circuit proposed herein, and Figure 4 is for describing the Figure 1 correlated double sampling method for deriving a sampling result based on the analog-to-digital conversion circuit.

[0028] Referring to Figure 1 , the analog-to-digital conversion circuit 4000 may include a comparator 410, a counter 420, a control circuit 425, a register REG 430, and a switch 440. The analog-to-digital conversion circuit 4000 proposed herein may further include DC blocking capacitors 451 and 453 and switches 461 and 463, and the switches 461 and 463 are used to connect the power supply voltage VDD to the two input terminals of the comparator 410, respectively.

[0029] The DC blocking capacitors 451 and 453 can prevent the DC component from being transmitted to the interior of the analog-to-digital conversion circuit 4000 when the input signal has a DC component, and match the input signal with the input range of the analog-to-digital conversion circuit 4000.

[0030] The switches 461 and 463 can apply the power supply voltage VDD to the input terminals of the comparator 410 during the initialization phase of the comparator 410 to maximize the input range of the comparator 410. The switches 461 and 463 can be connected during the Figure 2 shown auto zeroing (AZ) operation to initialize the comparator 410, and not connected during the reset operation and the determination operation to allow the analog input signal IN to be sampled to be input to the comparator 410.

[0031] Comparator 410 can receive an analog input signal IN 470 to be sampled at one terminal and a ramp signal RAMP 460 applied from a ramp signal generator (not shown) at the other terminal, and compare the values of the two signals to output a comparison result signal CMP. Here, the ramp signal RAMP can be a reference voltage for comparison, and the ramp signal generator can also be referred to as a reference voltage generator. The comparison result signal CMP can be "1" corresponding to a logic high or "0" corresponding to a logic low. In this case, since the ramp signal RAMP 460 is a signal whose voltage level decreases (or increases) over time, there is a time when the values of the two signals input to the comparator 410 match, and as this time point passes, the value of the comparison result signal CMP output from the comparator 410 reverses from a logic low to a logic high or from a logic high to a logic low.

[0032] Counter 420 can start counting the reference clock CLK from the time point when the ramp signal RAMP decreases (or increases) and output count information CNTO. At the time point when the value of the comparison result signal CMP output from the comparator 410 reverses, the switch 440 can be operated, and thus, the count information CNTO output from the counter 420 can be latched and stored in the register 430. In Figure 1 the configuration shown, the comparison result signal CMP output from the comparator 410 is shown to turn the switch 440 on / off, but according to another embodiment, the comparison result signal CMP output from the comparator 410 can be used as an enable signal for the register 430, and the count information output from the counter 420 can be directly input to the input terminal of the register 430. In addition, at the time point when the comparison result signal CMP reverses, the count information CNTO can be temporarily stored in the register 430 through the enable signal of the register 430. The count information stored in the register 430 can be output as a digital signal.

[0033] Control circuit 425 can generate the reference clock CLK and transmit the reference clock CLK to the counter 420. In addition, the control circuit 425 can control the on / off of the switches 461 and 463.

[0034] When multiple analog-to-digital conversion circuits are used, each analog-to-digital conversion circuit may have different characteristics, so unwanted offsets may be added to the sampling results. To compensate for the offsets that may be introduced into the analog-to-digital conversion in this way, the CDS method as Figure 2 shown can be used to sample the analog input signal.

[0035] Refer to Figure 2, the CDS method may be an analog-to-digital conversion method, which includes an auto-zero (AZ) operation 481, a first reset operation 483, a first determination operation 485, a second reset operation 487, and a second determination operation 489.

[0036] In the CDS method, an operation for removing an offset that may exist in the comparator 410 may be performed during the auto-zero operation 481. To this end, the switches 461 and 463 Figure 1 may be turned on to connect the input terminals of the comparator 410 to the power supply voltage VDD.

[0037] During the first reset operation 483, the ramp signal RAMP may be boosted to rise to a preset voltage.

[0038] During the first determination operation 485, the analog input signal IN may be an analog signal in a reset state, and the ramp signal RAMP may be a voltage that decreases from the preset voltage at a constant slope. The analog-to-digital conversion circuit 4000 may count the analog input signal IN in the reset state as a reference for removing the noise included in the analog input signal IN and obtaining accurate data. The analog-to-digital conversion circuit 4000 may use the value counted until the time point when the output CMP of the comparator 410 is inverted as a reference value during the first determination operation 485. The value counted during the first determination operation 485 may change according to the noise or offset included in the input signal IN.

[0039] When the output CMP of the comparator 410 is inverted, the second reset operation 487 may be performed to raise the ramp signal RAMP back to the preset voltage.

[0040] Then, as Figure 2 shown, during the second reset operation 487, the output CMP of the comparator 410 may be inverted back to logic high. During the second reset operation 487, the analog input signal may be released from the reset state and may be an actual measured value.

[0041] During the second determination operation 489, the analog input signal IN may be an actual measured value, and the ramp signal RAMP may be a voltage that decreases from the preset voltage at a constant slope. During the second determination operation 489, the analog-to-digital conversion circuit 4000 may latch the value counted until the time point when the output CMP of the comparator 410 is inverted, where the comparator 410 compares the analog input signal IN with the ramp signal RAMP. In addition, the final result may be a value obtained by subtracting the value counted during the first determination operation 485 from the value counted during the second determination operation 489.

[0042] Referring to Figure 4, the analog-to-digital conversion circuit 4000 can perform an auto-zero operation in operation S610. For the auto-zero operation to remove the possible offset in the comparator 410, the analog-to-digital conversion circuit 4000 can turn on Figure 1 switches 461 and 463 to connect the input terminals of the comparator 410 to the power supply voltage VDD.

[0043] Referring to Figure 3 and Figure 4 , in operation S620, the analog-to-digital conversion circuit 4000 can perform an analog-to-digital (A / D) conversion on the reference signal. To this end, the control circuit 425 of the analog-to-digital conversion circuit 4000 can disconnect Figure 1 switches 461 and 463 and generate an offset detection control signal that controls the application of a preset reference value to the input signal IN. According to one embodiment, the analog-to-digital conversion circuit 4000 can further include a reference value generator (not shown) that provides a preset reference value in response to the offset detection control signal. However, since the preset reference value is determined by the logic for generating the input signal IN provided at the front end of the analog-to-digital conversion circuit 4000, according to another embodiment, the preset reference value can be generated by the logic for generating the input signal IN provided at the front end of the analog-to-digital conversion circuit 4000.

[0044] The analog-to-digital conversion circuit 4000 can perform a first reset operation 483 and a first determination operation 485 to perform an analog-to-digital conversion on the reference signal. During the first reset operation 483, the ramp signal RAMP can be output as the maximum value, and the analog input signal in the reset state, that is, the reference signal, can be input as the analog input signal IN of the comparator. Here, the analog input signal in the reset state can be the maximum value of the analog input signal. During the first reset operation 483, the analog-to-digital conversion circuit 4000 can sample and hold (S&H) the signal input as the analog input signal IN1. The analog-to-digital conversion circuit 4000 can measure and hold the value of the analog input signal IN1 at the time point of performing the first reset operation 483 and use the above value in the first determination operation 485. Therefore, even when the analog input signal IN1 changes after sampling, the changed analog input signal does not affect the digital value to be converted.

[0045] The analog-to-digital conversion circuit 4000 can determine the digital conversion value of the reference signal in the first determination operation 485 of operation S620. During the first determination operation 485, as Figure 3As shown, the counter 420 can output a count value CNT0 that is incremented by 1 based on the reference clock CLK. In addition, the ramp signal RAMP can become a voltage that continuously decreases to a maximum predetermined amplitude dV based on the reference clock CLK. The comparator 410 can output a comparison result signal CMP that compares the ramp signal RAMP with the analog input signal IN1 based on the reference clock CLK. When the ramp signal RAMP is greater than the analog input signal IN1, the comparator 410 can output a logic high as the result value, and when the ramp signal RAMP is less than the analog input signal IN1, the comparator 410 can output a logic low as the result value. The analog-to-digital conversion circuit 4000 can repeat the above operations until the output CMP of the comparator 410 is inverted from logic high to logic low.

[0046] When the result value of the comparator 410 becomes logic low, the analog-to-digital conversion circuit 4000 can latch and temporarily store the count value CNT0 of the counter 420 (e.g., 3), complete the first determination operation 485, and proceed to operation S630.

[0047] In operation S630, the control circuit 425 of the analog-to-digital conversion circuit 4000 can generate a conversion control signal that controls the input signal IN to be converted into a digital value to be applied as the input signal IN. Therefore, the analog-to-digital conversion circuit 4000 can perform a second reset operation 487 and a second determination operation 489 to perform analog-to-digital conversion on the actually acquired analog signal. During the second reset operation 487, the ramp signal RAMP can be output as the maximum value, and the actual analog input signal can be input as the analog input signal IN1 of the comparator. According to one embodiment, the analog input signal IN1 can be a signal obtained by removing the DC component from the actually acquired analog input signal IN by the DC blocking capacitor 451.

[0048] During the second reset operation 487, the analog-to-digital conversion circuit 4000 can sample and hold (S&H) the signal input as the analog input signal IN1. The analog-to-digital conversion circuit 4000 can measure and hold the value of the analog input signal IN1 at the time point when the second reset operation 487 is performed and use the above value in the second determination operation 489. Therefore, even if the analog input signal IN1 changes after sampling, the changed analog input signal does not affect the digital value to be converted. According to one embodiment, the operation of sampling and holding the signal can be performed by an external device for acquiring the analog input signal instead of the analog-to-digital conversion circuit 4000.

[0049] The analog-to-digital conversion circuit 4000 can determine the digital conversion value of the actually measured analog input signal IN1 in the second determination operation 489 of operation S630. As Figure 3As shown, during the second determination operation 489, the counter 420 may output a count value CNT0 that is incremented by 1 based on the reference clock CLK. In addition, the ramp signal RAMP may become a voltage that continuously decreases by up to a predetermined amplitude dV based on the reference clock CLK. The comparator 410 may output a comparison result signal CMP that compares the ramp signal RAMP with the analog input signal IN1 based on the reference clock CLK. When the ramp signal RAMP is greater than the analog input signal IN1, the comparator 410 may output a logic high as the result value, and when the ramp signal RAMP is less than the analog input signal IN1, the comparator 410 may output a logic low as the result value. The analog-to-digital conversion circuit 4000 may repeat the above operations until the output CMP of the comparator 410 is inverted from logic high to logic low. When the result value of the comparator 410 becomes logic low, the analog-to-digital conversion circuit 4000 may latch and temporarily store the count value CNT0 (e.g., 7) of the counter 420, complete the second determination operation 489, and proceed to operation S640.

[0050] In operation S640, the analog-to-digital conversion circuit 4000 may output the difference between the digital value (e.g., 3) of the reference signal obtained and temporarily stored in operation S620 and the digital value of the actually obtained analog signal obtained in operation S630 as the final digital value CNT. In Figure 3 the example of, the analog-to-digital conversion circuit 4000 may output 4 obtained by subtracting 3 from 7 as the final digital value CNT.

[0051] Figure 5 is a diagram showing Figure 1 the input signal IN and the output CNT in, and the signal IN1 that removes the DC component from the input signal passing through the DC blocking capacitor.

[0052] Referring to Figure 5 , the input IN may have a constant DC component Vdc. When such an input passes through the DC blocking capacitor 451, the DC component may be removed, and only the analog signal IN1 may be retained. The analog signal IN1 may have a voltage between 0V and VDD to match the input range of the comparator 410.

[0053] The signal input to the analog-to-digital conversion circuit 4000 may generate the output CNT according to the operating speed of the analog-to-digital conversion circuit 4000. Here, the output CNT may be a digital signal composed of multiple bits. When the operating speed is fast, the output may more accurately follow the analog input signal IN1. In Figure 5 it, based on Figure 3 and Figure 4The described analog-to-digital conversion circuit 4000 can operate in each time period T1, T2, or T19 to provide an output OUT. As described above, the input signal IN can be sampled and held (S&H) at the beginning of each time period T1, T2, or T19 to prevent being affected by changes in the input signal IN during analog-to-digital conversion.

[0054] Figure 6 is a diagram showing the structure of an analog-to-digital conversion device provided with a plurality of analog-to-digital conversion circuits proposed herein.

[0055] Referring to Figure 6 , a plurality of analog-to-digital conversion circuits 630-1 to 630-K can be provided in one chip or one device to process a large amount of data. In this case, the structure of each of the plurality of analog-to-digital conversion circuits 630-1 to 630-K can be obtained by deleting the counter 420 and the control circuit 425 from the Figure 1 analog-to-digital conversion circuit 4000. Optionally, as Figure 6 shown, only one counter 620 can be provided outside the analog-to-digital conversion circuits 630-1 to 630-K, and the counter 620 can be connected to all the analog-to-digital conversion circuits 630-1 to 630-K to transmit the same count value to each of the analog-to-digital conversion circuits 630-1 to 630-K.

[0056] In addition, as Figure 6 shown, only one control circuit 640 can be provided outside the analog-to-digital conversion circuits 630-1 to 630-K to provide a reference clock CLK to the counter 620 and can additionally control the ramp signal generator 610.

[0057] In addition, as Figure 6 shown, the ramp signal generator 610 can be provided outside to provide the same ramp signal to all the analog-to-digital conversion circuits 630-1 to 630-K.

[0058] Figure 6 The configuration of the plurality of analog-to-digital conversion circuits shown can be applied to an analog in-memory computing (ACiM) system, a CMOS image sensor, etc.

[0059] Figure 7 is a diagram showing an example of applying the Figure 6 plurality of analog-to-digital conversion circuits to an ACiM system.

[0060] Referring to Figure 7 , the ACiM system can include a digital-to-analog converter (DAC) for converting digital input signals X1 to X4 into analog input signals V1 to V4, and an analog-to-digital converter (ADC) for converting internal calculation results A1 to A4 into digital output signals D1 to D4.

[0061] In addition, the weights g11 to g44 can be stored as analog values in the memory or register of the node where each row and each column intersect within the ACiM system. The weights g11 to g44 can be conductances and can perform a multiplication calculation on the applied analog input signals V1 to V4 to output currents. In addition, the currents output from the nodes in the same column can be added together to become the internal calculation results A1 to A4 and input to the ADC block 710. Here, the ADC block 710 can be composed of multiple analog-to-digital conversion circuits as shown in Figure 6 . According to one embodiment, the internal calculation results A1 to A4 can be converted to voltages before being input to the ADC block 710.

[0062] Figure 8 is a diagram showing an example of applying multiple analog-to-digital conversion circuits of Figure 6 to a CMOS image sensor.

[0063] Referring to Figure 8 , the CMOS image sensor 1000 can include a pixel array 110, a row decoding circuit 120, a ramp signal generator 130, an ADC block 140, a data output circuit 150, and a control unit 160. Here, the ramp signal generator 130 can be the same as the ramp signal generator 610 of Figure 6 , and the ADC block 140 can include the counter 620 and multiple analog-to-digital conversion circuits 630-1 to 630-K of Figure 6 . In addition, the control unit 160 can include the control circuit 640 of Figure 6 .

[0064] The pixel array 110 can include multiple pixels arranged in a matrix structure. The pixel array 110 can output an analog pixel signal POUT to the ADC block 140, and the analog pixel signal POUT converts the incident light signal into an electrical signal. Here, the pixel array 100 can be driven by drive signals such as a reset signal RX, a transfer signal TX, and a selection signal SX applied from the row decoding circuit 120.

[0065] The row decoding circuit 120 selects the rows of the pixel array 110. That is, the row decoding circuit 120 can select each of the pixels in the pixel array 110 row by row according to the control signal CON applied from the control unit 160 and control its operation.

[0066] The ramp signal generator 130 can generate a ramp signal RAMP according to the control signal CON applied from the control unit 160. The ramp signal generated from the ramp signal generator 130 can be input to all the analog-to-digital conversion circuits 630-1 to 630-K in the ADC block 140.

[0067] According to one embodiment, when each clock is input synchronously with the reference clock CLK, the ramp signal generator 130 may output a ramp signal RAMP whose voltage decreases by a predetermined value from a previous value. For example, a voltage VDD - dV may be output during the clock cycle of the first clock, and a voltage VDD - 2dV may be output during the clock cycle of the second clock.

[0068] The ADC block 140 may convert the analog pixel signal POUT output from the pixel array 110 into a digital signal. Each of the analog-to-digital conversion circuits 630-1 to 630-K in the ADC block 140 may convert the analog pixel signal POUT into a digital signal according to the method based on Figure 3 or Figure 4 the method described above.

[0069] The ADC block 140 may compare the value of the pixel signal POUT output from the pixel array 110 with the value of the ramp signal RAMP applied from the ramp signal generator 130. The ADC block 140 may count the reference clock CLK applied from the control unit 160 in response to the comparison value of the pixel signal POUT and the ramp signal RAMP, and output digital signals D1 to D of the analog pixel signal POUT for each column K .

[0070] The data output circuit 150 may latch the digital signals D1 to D applied from the ADC block 140 K . The data output circuit 150 may latch the count information and output the pixel data DOUT in digital format in sequence in response to the output control signal OCON and the reference clock CLK.

[0071] The control unit 160 may control the operations of the row decoding circuit 120, the ramp signal generator 130, the ADC block 140, and the data output circuit 150. According to one embodiment, the control unit 160 may include a timing generator, and using the timing generator, the control unit 160 may control all programs from sensing an image to outputting the sensed image data according to time information.

[0072] The control unit 160 may generate a control signal CON and output the control signal CON to the row decoding circuit 120 and the ramp signal generator 130. In addition, the control unit 160 may generate a reference clock CLK and output the reference clock CLK to the ADC block 140. In addition, the control unit 160 may generate an output control signal OCON, a reference clock CLK, and a sensing enable signal SEN and transmit the output control signal OCON, the reference clock CLK, and the sensing enable signal SEN to the data output circuit 150.

[0073] The control unit 160 can generate control signals. The control signals can convert the signals received from the pixels of the pixel array 110 into digital signals using the CDS method, and control the ramp signal generator 130 and the ADC block 140.

[0074] As described above, the analog-to-digital conversion circuit proposed in the present disclosure can be used in an ACiM system or a CMOS image sensor. In particular, the analog-to-digital conversion circuit can be a dynamic comparator-based single-slope analog-to-digital conversion circuit, which is developed from the static comparator-based single-slope analog-to-digital conversion circuit used in traditional image sensors and operates according to a clock. Therefore, the power consumption of the analog-to-digital conversion circuit can be reduced, the operation speed can be increased, and the implementation area can be made smaller.

[0075] In addition, as Figure 7 shown, the analog-to-digital conversion circuit proposed herein can be used in an ACiM system, and compared with the successive approximation register (SAR) analog-to-digital conversion circuit used in traditional ACiM systems, it has a smaller implementation area and can significantly increase the operation speed.

[0076] In addition, the analog-to-digital conversion circuit proposed herein can solve the problem of mismatch in the operation range between the output of the ACiM system and the input of the comparator, and maximize the input range of the analog-to-digital conversion circuit.

[0077] Although Figure 7 and Figure 8 show examples of applying the analog-to-digital conversion circuit proposed herein to an ACiM system or a CMOS image sensor, the application of the analog-to-digital conversion circuit proposed herein is not limited thereto, and it can be used in all necessary electronic devices in the same or similar manner.

[0078] The implementation method of the analog-to-digital converter proposed herein can be used to minimize the power consumption and area of the analog-to-digital converters in products that should operate multiple analog-to-digital converters simultaneously.

Claims

1. An analog-to-digital conversion device, comprising: a comparator having a first input terminal, a second input terminal and an output terminal, and comparing an input signal input to the first input terminal with a reference voltage input to the second input terminal, and outputting a comparison result value to the output terminal, the reference voltage decreasing by a preset value from a previous value in response to input of each clock signal; A counter outputting a digital count value, wherein the digital count value increases by 1 each time the clock signal is input; a register, latching and storing the digital count value based on the comparison result value, and generating a digital value corresponding to the input signal based on the latched digital count value; a first blocking capacitor, one end of which is connected to the first input terminal, and the first blocking capacitor transmits the input signal to the first input terminal; as well as The control circuit generates the clock signal.

2. The analog-to-digital conversion device according to claim 1, further comprising: A first switch connected between the first blocking capacitor and the first input terminal and providing a power supply voltage VDD to the first input terminal; as well as The second switch is connected to the second input terminal and provides the power supply voltage to the second input terminal.

3. The analog-to-digital conversion device according to claim 2, wherein: The control circuit further generates a switch control signal to control the first switch and the second switch.

4. The analog-to-digital conversion device according to claim 3, wherein: The control circuit further generates a switch control signal that turns on the first switch and the second switch to perform an auto-zero operation.

5. The analog-to-digital conversion device according to claim 4, wherein: The control circuit further generates a switch control signal to turn off the first switch and the second switch, and generates an offset detection control signal that controls application of a preset reference value as the input signal.

6. The analog-to-digital conversion device according to claim 5, wherein: The control circuit includes a reference value generator connected to the other end of the first blocking capacitor and providing the preset reference value in response to the offset detection control signal.

7. The analog-to-digital conversion device according to claim 5, wherein: The register stores a first digital count value obtained by latching a digital count value corresponding to the preset reference value.

8. The analog-to-digital conversion device according to claim 7, wherein: The control circuit generates a conversion control signal, the conversion control signal controls the application of the analog signal to be converted as the input signal, and The register further generates the digital value by subtracting the first digital count value from a second digital count value obtained by latching a digital count value corresponding to the analog signal.

9. The analog-to-digital conversion device according to claim 1, further comprising: A reference voltage generator generates the reference voltage.

10. The analog-to-digital conversion device according to claim 9, further comprising: A second blocking capacitor is connected between the second input terminal and the reference voltage generator and transmits the reference voltage to the second input terminal.

11. The analog-to-digital conversion device according to claim 1, wherein: The comparator further outputs a first value as the comparison result value when the reference voltage is greater than the input signal, and outputs a second value different from the first value as the comparison result value when the reference voltage is less than the input signal.

12. The analog-to-digital conversion device according to claim 11, wherein: The register further latches the digital count value at a point in time when the comparison result value changes from the first value to the second value.

13. The analog-to-digital conversion device according to claim 11, wherein: The control circuit outputs the clock signal when the comparison result value output by the comparator is the first value.

14. An analog-to-digital conversion device, comprising: a reference voltage generator that generates a reference voltage that decreases by a preset value from a previous value in response to input of each clock signal; A counter outputting a digital count value, wherein the digital count value increases by 1 each time the clock signal is input; A control circuit generates the clock signal; as well as Multiple analog-to-digital conversion circuits, Wherein, each of the plurality of analog-to-digital conversion circuits comprises: A comparator having a first input terminal, a second input terminal and an output terminal, and comparing an input signal input to the first input terminal with a reference voltage input to the second input terminal, and outputting a comparison result value to the output terminal; a register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value; and A first blocking capacitor, one end of the first blocking capacitor is connected to the first input terminal, and the first blocking capacitor transmits the input signal to the first input terminal.

15. The analog-to-digital conversion device according to claim 14, wherein: Each of the plurality of analog-to-digital conversion circuits further comprises: a first switch connected between the first blocking capacitor and the first input terminal and providing a power supply voltage VDD to the first input terminal; and a second switch connected to the second input terminal and providing the power supply voltage to the second input terminal, and The control circuit generates a switch control signal for controlling all the first switches and the second switches of the plurality of analog-to-digital conversion circuits.

16. The analog-to-digital conversion device according to claim 15, wherein: The control circuit further: generating a switch control signal for turning on all the first switches and the second switches of the plurality of analog-to-digital conversion circuits so as to perform an auto-zero operation of the plurality of analog-to-digital conversion circuits; generating the switch control signal for disconnecting the first switch and the second switch after a predetermined time, and generating an offset detection control signal for controlling application of a preset reference value to the first input terminals of the plurality of analog-to-digital conversion circuits; and A conversion control signal is generated, and after all the plurality of analog-to-digital conversion circuits acquire the first digital count value of the preset reference value, the conversion control signal controls the first input signal to be converted to be applied to the first input terminal.

17. The analog-to-digital conversion device according to claim 16, wherein: A register of each of the plurality of analog-to-digital conversion circuits: storing the first digital count value, the first digital count value being obtained by latching a digital count value corresponding to the preset reference value; and The digital value is generated by subtracting the first digital count value from a second digital count value acquired by latching a digital count value corresponding to the first input signal.

18. The analog-to-digital conversion device according to claim 16, wherein: The comparator of each of the multiple analog-to-digital conversion circuits outputs a first value as the comparison result value when the reference voltage is greater than the first input signal, and outputs a second value different from the first value as the comparison result value when the reference voltage is less than the first input signal.

19. The analog-to-digital conversion device according to claim 18, wherein: The register of each of the plurality of analog-to-digital conversion circuits latches the digital count value at a point in time when the comparison result value changes from the first value to the second value.

20. A complementary metal oxide semiconductor image sensor, namely a CMOS image sensor, comprising: a pixel array including a plurality of pixels formed at contact points in a plurality of rows and a plurality of columns; A row decoding circuit selects a row of output pixel signals from the pixel array; a reference voltage generator that generates a reference voltage that decreases by a preset value from a previous value in response to input of each clock signal; A counter outputting a digital count value, wherein the digital count value increases by 1 each time the clock signal is input; A control circuit generates the clock signal; as well as a plurality of analog-to-digital conversion circuits disposed in each of the plurality of columns and generating a digital value of a pixel signal of each column using the reference voltage, Wherein, each of the plurality of analog-to-digital conversion circuits comprises: A comparator having a first input terminal, a second input terminal and an output terminal, and comparing an input signal input to the first input terminal with a reference voltage input to the second input terminal, and outputting a comparison result value to the output terminal; a register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value; and A first blocking capacitor, one end of the first blocking capacitor is connected to the first input terminal, and the first blocking capacitor transmits the input signal to the first input terminal.

21. An analog in-memory computing system, namely an ACiM system, comprising: A memory array storing weight information of contact points of a plurality of rows and a plurality of columns; a plurality of digital-to-analog converters, disposed at an input end of each of the plurality of rows, and converting a digital input signal of each of the plurality of rows into an analog input signal; a reference voltage generator that generates a reference voltage that decreases by a preset value from a previous value in response to input of each clock signal; A counter outputting a digital count value, wherein the digital count value increases by 1 each time the clock signal is input; A control circuit generates the clock signal; as well as a plurality of analog-to-digital conversion circuits, arranged in each of the plurality of columns, and converting an analog output signal of each of the plurality of columns into a digital output signal, the analog output signal of each of the plurality of columns being generated by physically multiplying an analog input signal of each of the plurality of rows and corresponding weight information and physically adding the multiplication results of all rows of each of the plurality of columns, Wherein, each of the plurality of analog-to-digital conversion circuits comprises: A comparator having a first input terminal, a second input terminal and an output terminal, and comparing an input signal input to the first input terminal with a reference voltage input to the second input terminal, and outputting a comparison result value to the output terminal; a register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value; and A first blocking capacitor, one end of the first blocking capacitor is connected to the first input terminal, and the first blocking capacitor transmits the input signal to the first input terminal.

Images