Digital expansion circuit and method applied to high-precision digital-to-analog converter

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a digit expansion circuit and method applied to a high-precision digital-to-analog converter. Comprising a resistance voltage division module which generates output voltage VOUTMSB represented by high M-bit input data D [L + M-1: L] through an operational amplifier I and resistance string voltage division; the low-bit injection current generation module is used for generating binary weight current sources represented by low L-bit input data D [L-1: 0] according to the current flowing through the resistor string, and summarizing the current sources to generate output current IOUTLSB; and the output-stage operational amplifier module is used for combining the output current IOUTLSB and the output voltage VOUTMSB so as to generate the output voltage VOUT represented by all M + L-bit input data. The problem that the digits of an existing resistance voltage division type digital-to-analog converter are difficult to expand is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a bit extension circuit and method for a high-precision digital-to-analog converter. Background Art

[0002] As an interface between the analog and digital worlds, a Digital to Analog Converter (DAC) plays an irreplaceable role in fields such as communication, detection, and industrial control. In the field of low-speed, low-cost digital-to-analog converters that focus on high precision, resistor-divider digital-to-analog converters have been widely used.

[0003] Traditional resistor-divider digital-to-analog converters use a resistor string for voltage division, and the input digital signal controls the selection of the output voltage, and then an operational amplifier provides amplification and driving capabilities to generate a stable voltage output. However, for an N-bit digital-to-analog converter, 2 N resistors are required for voltage division, and the area of the resistor array increases exponentially with the precision, which limits the number of bits of traditional resistor-divider digital-to-analog converters to less than 10 bits and is difficult to expand. Although the R-2R digital-to-analog converter only requires 2×N resistors, the mismatch of high-order resistors will have a great impact on the precision, and calibrating the resistors will cause a large amount of additional area and power consumption overhead. Summary of the Invention

[0004] The purpose of the present invention is to provide a bit extension circuit and method for a high-precision digital-to-analog converter. By introducing a current related to the resistance value of the resistor string and constructing a resistor-current hybrid digital-to-analog converter, the present invention can expand the number of bits of the digital-to-analog converter to more than 16 bits and ensure relatively good linearity to solve the problem that the number of bits of existing resistor-divider digital-to-analog converters is difficult to expand.

[0005] To solve the above technical problems, the present invention provides a bit extension circuit for a high-precision digital-to-analog converter, including: A resistor voltage division module that generates an output voltage represented by high M-bit input data D[L+M-1:L] through operational amplifier 1 and resistor string voltage division V OUT_MSB ; A low-order injection current generation module that generates a binary-weighted current source represented by low L-bit input data D[L-1:0] according to the current flowing through the resistor string, and sums up the current sources to generate an output current I OUT_LSB ; An output-stage operational amplifier module that, by combining the output current I OUT_LSB and the output voltage V OUT_MSBare combined to generate the output voltage represented by all M + L bits of input data V OUT .

[0006] Preferably, the resistor voltage dividing module includes: a resistor string, a high - order control switch, an operational amplifier 1, a first PMOS transistor, and a second PMOS transistor; one end of the resistor string is grounded, and the other end is connected to the non - inverting input terminal of the operational amplifier 1, the gate terminal and the drain terminal of the second PMOS transistor; the inverting input terminal of the operational amplifier 1 is connected to a reference voltage V REF , and the output terminal is connected to the gate terminal of the first PMOS transistor; the source terminal of the first PMOS transistor is connected to the power supply voltage, and the drain terminal is connected to the source terminal of the second PMOS transistor; between every two adjacent series - connected resistors in the resistor string, they are respectively connected to the input terminal of a high - order control switch, and the output terminals of several high - order control switches are commonly connected to generate an output voltage V OUT_MSB , and the control terminals of several high - order control switches are used to input high - order M - bit input data D[L + M - 1:L].

[0007] Preferably, the resistor string is composed of 2 M +1 series - connected resistors, and the total resistance value of the resistor string is 2 M × R； wherein the total resistance value of the 2 M -1 series - connected resistors in the middle of the resistor string is R , and the resistance values of the resistors at the head and tail ends of the resistor string are respectively R OFS and R- R OFS .

[0008] Preferably, the low - order injection current generation module includes: a third PMOS transistor, a fourth PMOS transistor, and a low - order control switch; the source terminals of several third PMOS transistors are commonly connected to the power supply voltage, the gate terminals of several third PMOS transistors and the output terminal of the operational amplifier 1 are commonly connected, the drain terminal of the third PMOS transistor is connected to the source terminal of the fourth PMOS transistor, the gate terminals of several fourth PMOS transistors and the non - inverting input terminal of the operational amplifier 1 are commonly connected, the drain terminals of several fourth PMOS transistors are respectively connected to the input terminal of a low - order control switch, and the output terminals of several low - order control switches are commonly connected to generate an output current I OUT_LSB , and the control terminals of several low - order control switches are used to input low - order L - bit data D[L - 1:0].

[0009] Preferably, the output - stage operational amplifier module includes: an operational amplifier 2, a feedback resistor, and an injection resistor; the non - inverting input terminal of the operational amplifier 2 is connected to the output voltage V OUT_MSB, the output terminal is connected to one end of the feedback resistor, and the other ends of the feedback resistors are commonly connected to the inverting input terminal and one end of the injection resistor. The other end of the injection resistor is grounded, and the output current I OUT_LSB is injected onto the injection resistor.

[0010] Preferably, the feedback resistor and the injection resistor have the same resistance value.

[0011] Preferably, the current flowing through the resistor string I R= V REF / (2 M ×R) is generated, and there is I R = 2 × I L-1 = 2 2 × I L-2 = 2 3 × I L-3 … = 2 L × I 0; The output current I OUT_LSB = (1 - D[L - 1]) × I L-1 + (1 - D[L - 2]) × I L-2 + … + (1 - D[0]) × I 0; The output voltage V OUT_MSB =V REF / (2 M × R ) × ( CODE MSB × R + R OFS ); where CODE MSB is the code value represented by the high M-bit input data D[L + M - 1:L].

[0012] Preferably, the output voltage V OUT = 2 × ( V OUT_MSB - R × I OUT_LSB ), by designing V REF × R OFS / (2M × R )=( I L-1 +…+ I 0) R , that is R OFS = R (2 -1 +2 -2 +…+2 -L ) when V OUT =2×( V REF × CODE / 2 M+L ) such that V OUT represents the output voltage represented by all M+L-bit input data; where CODE is the magnitude of the code value represented by all M+L-bit input data.

[0013] The present invention also provides a method for expanding the number of bits applied to a high-precision digital-to-analog converter, which executes a circuit for expanding the number of bits applied to a high-precision digital-to-analog converter as described above, and includes the following steps: Step 1: Generate the output voltage represented by the high M-bit input data D[L+M-1:L] by means of resistor string voltage division V OUT_MSB ; Step 2: Generate a series of binary-weighted current sources based on the current flowing through the resistor string and connect them to the low-order control switches; Step 3: Sum up the total current represented by the low L-bit input data D[L-1:0] to generate an output current I OUT_LSB ; Step 4: Through the output stage operational amplifier module, combine the output current I OUT_LSB of the low L bits and the output voltage V OUT_MSB of the high M bits, and use operational amplifier amplification to obtain the output voltage V OUT =2×( V REF × CODE / 2 M+L ).

[0014] Preferably, for the binary-weighted current sources in step 2, through thermometer decoding, the current sources of some data bits can be converted into current sources with the same magnitude, and the linearity of the digital-to-analog converter can be further improved through matching current sources.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The resistor voltage division module of the present invention is used to generate an output voltage represented by high M-bit input data D[L+M-1:L]; the low-bit injection current generation module generates a series of binary-weighted current sources represented by low L-bit data D[L-1:0] according to the current flowing through the resistor string I R The output stage operational amplifier combines the current of the low L bits I OUT_LSB and the voltage of the high bits V OUT_MSB By injecting the total current flowing out of the low bits I OUT_LSB into the resistor 2R, the output V OUT adds the voltage of the low bits to the voltage of the high bits V OUT_MSB to finally obtain the output voltage represented by all M+L-bit data bits. The present invention can effectively relieve the pressure brought by the exponentially increasing resistor string area caused by bit expansion. By dividing the input data bits into two segments, the high segment and the low segment, the matching is realized in the low segment by using the binary current source method, and the proportional relationship between the low segment and the high segment is ensured. Finally, on the output operational amplifier, the output V OUT_LSB is the superposition value of the voltages represented by the two segments, realizing bit expansion. V OUT BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. is a functional block diagram of a bit expansion circuit applied to a high-precision digital-to-analog converter provided by the present invention.

[0017] Figure 2 FIG. is a circuit diagram of the resistor voltage division module and the low-bit injection current generation module provided by the present invention.

[0018] Figure 3 FIG. is a circuit diagram of the output stage operational amplifier module provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0020] As Figure 1 shown, the embodiment of the present invention specifically provides a bit expansion circuit applied to a high-precision digital-to-analog converter, including: ​The resistor voltage division module generates the output voltage represented by the high M-bit input data D[L+M-1:L] through the operational amplifier OP1 and resistor string voltage division. V OUT_MSB ; The low-bit injection current generation module generates the binary-weighted current sources represented by the low L-bit input data D[L-1:0] based on the current flowing through the resistor string I R and sums up the current sources to generate the output current. I OUT_LSB ; The output stage operational amplifier module combines the output current I OUT_LSB and the output voltage V OUT_MSB by injecting the total current flowing out from the low bits I OUT_LSB onto the injection resistor 2R, so that the output V OUT adds the voltage of the low bits V OUT_MSB to the voltage of the high bits V OUT_LSB to generate the output voltage represented by all M+L-bit input data. V OUT .

[0021] The bit expansion circuit of the present invention can effectively relieve the pressure brought by the exponentially increasing resistor string area caused by bit expansion. By dividing the input data bits into two segments, the high segment and the low segment, binary current sources are used in the low segment to achieve matching and ensure the proportional relationship between the low segment and the high segment. Finally, on the output operational amplifier, the output V OUT is the superposition value of the voltages represented by the two segments, realizing bit expansion.

[0022] As Figure 2 shown, the resistor voltage division module includes: a resistor string, a high-bit control switch, operational amplifier OP1, first PMOS transistor P1, and second PMOS transistor P2; one end of the resistor string is grounded, and the other end is connected to the non-inverting input terminal of operational amplifier OP1, the gate terminal and the drain terminal of second PMOS transistor P2; the inverting input terminal of operational amplifier OP1 is connected to the reference voltage V REF , and the output terminal is connected to the gate terminal of first PMOS transistor P1; the source terminal of the first PMOS transistor is connected to the power supply voltage, and the drain terminal is connected to the source terminal of the second PMOS transistor; between every two adjacent series resistors in the resistor string, they are respectively connected to the input terminal of a high-bit control switch, and the output terminals of several high-bit control switches are commonly connected to generate the output voltage V OUT_MSB, the control terminals of several high - order control switches are used to input high - order M - bit input data D[L + M - 1:L].

[0023] The resistance string is 2 M +1 resistors are connected in series to form a resistor array, and the total resistance value of the resistance string is 2 M × R； where the total resistance value of the 2 M -1 resistors connected in series at the middle end of the resistance string is R , and the resistance values of the resistors at the head and tail ends of the resistance string are respectively R OFS and R-R OFS . And the output voltage is controlled by the input M - bit data D[L + M - 1:L] to be gated V OUT_MSB , and the voltage at the uppermost end of the resistance string is clamped to V REF through the operational amplifier OP1. Therefore, there is an output voltage V OUT_MSB =V REF / (2 M × R )×( CODE MSB × R + R OFS ); where CODE MSB is the value represented by the high - order M - bit input data D[L + M - 1:L]. The number of bits of M is usually between 6 and 10 to avoid excessive area overhead caused by too many resistors in the resistor voltage - dividing module.

[0024] As Figure 2 shown, the low - order injection current generation module includes: the third PMOS transistor P3, the fourth PMOS transistor P4, and low - order control switches; a current source array is formed by the third PMOS transistor P3 and the fourth PMOS transistor P4. The source terminals of several third PMOS transistors P3 are commonly connected to the power supply voltage. The gate terminals of several third PMOS transistors P3 and the output terminal of the operational amplifier OP1 are commonly connected. The drain terminal of the third PMOS transistor P3 is connected to the source terminal of the fourth PMOS transistor P4. The gate terminals of several fourth PMOS transistors P4 and the non - inverting input terminal of the operational amplifier OP1 are commonly connected. The drain terminals of several fourth PMOS transistors P4 are respectively connected to the input terminal of a low - order control switch. The output terminals of several low - order control switches are commonly connected to generate an output current I OUT_LSB , and the control terminals of several low - order control switches are used to input low - order L - bit data D[L - 1:0].

[0025] AsFigure 3 As shown, the output stage operational amplifier module includes: operational amplifier OP2, a feedback resistor, and an injection resistor. The feedback resistor and the injection resistor have the same resistance value, both being 2R. The non-inverting input terminal of the operational amplifier OP2 is connected to the output voltage V OUT_MSB , and the output terminal is connected to one end of the feedback resistor. The other end of the feedback resistor is commonly connected to the inverting input terminal and one end of the injection resistor. The other end of the injection resistor is grounded, and the output current I OUT_LSB is injected onto the injection resistor.

[0026] The low L-bit binary current generated by the low-bit injection current generation module is based on the current flowing through the resistor string in the resistor voltage division module I R generated, and there is I R= V REF / (2 M ×R)=2× I L-1 =2 2 × I L-2 =2 3 × I L-3 …=2 L × I 0; The low-bit injection current generation module generates the current represented by the low L-bit data D[L-1:0] I L-1 , I L-2 … I 0. When the data bit D[L-1:0] is 0, the current flows into I OUT_LSB , otherwise no current flows out. Therefore I OUT_LSB =(1-D[L-1])× I L-1 +(1-D[L-2])× I L-2 +…+(1-D[0])× I 0.

[0027] The output stage operational amplifier module, while achieving 2-fold voltage amplification of V OUT_MSB , injects the total current of I OUT_LSB onto the injection resistor 2R, so that V OUT the output simultaneously includes the voltage outputs represented by the high M bits and the low L bits.

[0028] Specifically, due to the clamping effect of operational amplifier OP2, the feedback voltage of the output-stage operational amplifier module is equal to V OUT_MSB , so there is: I a =( V OUT - V OUT_MSB ) / 2R, I b = V OUT_MSB / 2R = I a + I OUT_LSB , so there is: V OUT = 2×( V OUT_MSB - R× I OUT_LSB ).

[0029] Furthermore, since V OUT_MSB = V REF ×(( CODE MSB × R + R OFS ) / (2 M × R ) = V REF × CODE MSB / 2 M + V REF × R OFS / (2 M × R ); I OUT_LSB =(1 - D[L - 1])× I L-1 +(1 - D[L - 2])× I L-2 +…+(1 - D[0])× I 0 =(( I L-1 + I L-2 +…+ I 0)- CODE LSB × I 0 =(( IL-1 + I L-2 +…+ I 0)- CODE LSB × V REF / (2 M+L × R ) Substitute CODE =2 L × CODE MSB + CODE LSB This CODE is the code value size represented by all M + L - bit input data. We can get: V OUT =2× V REF × CODE MSB / 2 M + V REF × CODE MSB / 2 M+L + V REF × R OFS / (2 M × R )-( I L-1 +…+ I 0) R =2× V REF × CODE / 2 M+L + V REF × R OFS / (2 M × R )-( I L-1 +…+ I 0) R By designing V REF × R OFS / (2 M × R )=( I L-1 +…+ I 0) R That is R ​​OFS = R (2 -1 +2 -2 +…+2 -L ) when V OUT= 2 × ( V REF × CODE / 2 M+L ). At this time, the output voltage V OUT can represent the voltage weights of all M + L bits, so that the bit width of the DAC is extended to M + L bits.

[0030] The embodiment of the present invention also specifically provides a method for extending the number of bits applied to a high-precision digital-to-analog converter, including the following steps: Step 1: Generate the output voltage represented by the high M-bit input data D[L + M - 1:L] by means of resistor string voltage division V OUT_MSB ; Step 2: Based on the current flowing through the resistor string, generate a series of binary-weight current sources and connect them to the low-bit control switches; Step 3: Sum up the total current represented by the low L-bit input data D[L - 1:0] to generate an output current I OUT_LSB ; Step 4: Through the output stage operational amplifier module, combine the output current of the low L bits I OUT_LSB and the output voltage of the high M bits V OUT_MSB to obtain an output voltage V OUT = 2 × ( V REF × CODE / 2 M+L ).

[0031] As a preferred embodiment of the present invention, the binary-weight current sources in the step 2 can, through the way of thermometer decoding, convert the current sources of some data bits into current sources with the same magnitude, and further improve the linearity of the digital-to-analog converter through the matching current sources.

[0032] As a preferred embodiment of the present invention, the linearity of the digital-to-analog converter can be further improved by optimizing the layout of the resistor array and the current source array in the step 1 and the step 2.

[0033] As a preferred embodiment of the present invention, in the step 4, it can be through R OFSCalibrating the current source of the low-injection current generation module can further improve the linearity of the digital-to-analog converter.

[0034] In summary, based on the traditional low-resolution resistive digital-to-analog converter, the present invention expands its bit number to more than 14 to 16 bits by adding a small circuit overhead, meets the usage requirements of most current high-precision digital-to-analog converters, and ensures relatively good linearity.

[0035] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A bit extension circuit applied to a high-precision digital-to-analog converter, characterized in that, Including: The resistor voltage division module generates the output voltage represented by the high M-bit input data D[L+M-1:L] through the first operational amplifier and resistor string voltage division V OUT_MSB ; The low-injection current generation module generates binary-weight current sources represented by low L-bit input data D[L-1:0] according to the current flowing through the resistor string, and sums up the current sources to generate an output current I OUT_LSB ; Output stage operational amplifier module, by combining the output current I OUT_LSB and the output voltage V OUT_MSB That is, by injecting the output current I OUT_LSB flowing out from the low L bits into the injection resistor, so that the output voltage V OUT is superimposed on the output voltage V OUT_MSB of the high M bits V OUT_LSB of the low L bits to generate the output voltage V OUT .

2. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 1, characterized in that The resistor voltage division module includes: a resistor string, a high-bit control switch, an operational amplifier 1, a first PMOS transistor, and a second PMOS transistor; one end of the resistor string is grounded, and the other end is connected to the non-inverting input terminal of the operational amplifier 1, the gate terminal and the drain terminal of the second PMOS transistor; the inverting input terminal of the operational amplifier 1 is connected to a reference voltage V REF , and the output terminal is connected to the gate terminal of the first PMOS transistor; the source terminal of the first PMOS transistor is connected to the power supply voltage, and the drain terminal is connected to the source terminal of the second PMOS transistor; between every two adjacent series resistors in the resistor string, they are respectively connected to the input terminal of a high-bit control switch, and the output terminals of several high-bit control switches are commonly connected to generate an output voltage V OUT_MSB , and the control terminals of several high-bit control switches are used to input high M-bit input data D[L+M-1:L].

3. The bit extension circuit for a high-precision digital-to-analog converter according to claim 2, characterized in that, The resistor string is 2 M +1 resistors are connected in series, and the total resistance value of the resistor string is 2 M × R； Among them, the total resistance value of the 2 M -1 resistors connected in series at the middle end of the resistor string is R , and the resistance values of the resistors at the head and tail ends of the resistor string are respectively R OFS and R-R OFS .

4. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 1, wherein The low-injection current generation module includes: a third PMOS transistor, a fourth PMOS transistor, and a low-level control switch; the source terminals of a plurality of the third PMOS transistors are commonly connected to a power supply voltage, the gate terminals of the plurality of the third PMOS transistors and the output terminal of the first operational amplifier are commonly connected, the drain terminal of the third PMOS transistor is connected to the source terminal of the fourth PMOS transistor, the gate terminals of the plurality of the fourth PMOS transistors and the non-inverting input terminal of the first operational amplifier are commonly connected, the drain terminals of the plurality of the fourth PMOS transistors are respectively connected to the input terminal of a low-level control switch, and the output terminals of the plurality of low-level control switches are commonly connected to generate an output current I OUT_LSB , and the control terminals of the plurality of low-level control switches are used to input low L-bit data D[L-1:0].

5. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 1, wherein The output stage operational amplifier module includes: operational amplifier two, a feedback resistor, and an injection resistor; the non-inverting input terminal of the operational amplifier two is connected to the output voltage V OUT_MSB , the output terminal is connected to one end of the feedback resistor, the other end of the feedback resistor is commonly connected to the inverting input terminal and one end of the injection resistor, the other end of the injection resistor is grounded, and the output current I OUT_LSB is injected onto the injection resistor.

6. The bit extension circuit for a high-precision digital-to-analog converter according to claim 5, characterized in that, The resistance values of the feedback resistor and the injection resistor are the same.

7. The bit extension circuit for a high-precision digital-to-analog converter according to claim 3, characterized in that, The current flowing through the resistor string I R= V REF / (2 M ×R), and there is I R =2× I L-1 =2 2 × I L-2 =2 3 × I L-3 …=2 L × I 0; The output current I OUT_LSB =(1 - D[L - 1]) × I L-1 +(1 - D[L - 2]) × I L-2 +…+(1 - D[0]) × I 0; The output voltage V OUT_MSB =V REF / (2 M × R )×( CODE MSB × R + R OFS ); where CODE MSB is the code value represented by the high M-bit input data D[L+M-1:L].

8. The bit expansion circuit applied to a high-precision digital-to-analog converter according to claim 7, characterized in that, The output voltage V OUT = 2 × ( V OUT_MSB - R × I OUT_LSB ), by designing V REF × R OFS / (2 M × R ) = ( I L-1 + … + I 0) R , that is R OFS = R (2 -1 + 2 -2 + … + 2 -L ) when V OUT = 2 × ( V REF × CODE / 2 M+L ), such that V OUT represents the output voltage represented by all M + L - bit input data; where CODE is the magnitude of the code value represented by all M + L - bit input data.

9. A method for expanding the number of bits applied to a high-precision digital-to-analog converter, which executes a circuit for expanding the number of bits applied to a high-precision digital-to-analog converter according to any one of claims 1 to 8, characterized in that, Including the following steps: Step 1: Generate the output voltage represented by the high M-bit input data D[L+M-1:L] by means of resistor string voltage division V OUT_MSB ; Step 2: Based on the current flowing through the resistor string, generate a series of binary-weighted current sources and connect them to the low-bit control switches; Step 3: Aggregate the total current represented by the low L-bit input data D[L-1:0] to generate an output current I OUT_LSB ; Step 4: Through the output stage operational amplifier module, combine the output current of the lower L bits I OUT_LSB and the output voltage of the higher M bits V OUT_MSB and use an operational amplifier to amplify to obtain the output voltage V OUT = 2 × ( V REF × CODE / 2 M+L ).

10. A method for bit expansion applied to a high-precision digital-to-analog converter according to claim 9, characterized in that, The binary-weighted current sources in Step 2 can, through thermometer decoding, convert the current sources of some data bits into current sources with the same magnitude, and further improve the linearity of the digital-to-analog converter through the matching current sources.

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