A bit extension circuit and method applied to a high-precision digital-to-analog converter

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a bit expansion circuit and method applied to a high-precision digital-to-analog converter. It includes: a resistor voltage division module that generates an output voltage represented by high M-bit input data D[L+M-1:L] through an operational amplifier 1 and resistor string voltage division V <subgt;OUT_MSB< / subgt>; a low-bit injection current generation module that generates a binary-weighted current source represented by low L-bit input data D[L-1:0] based on the current flowing through the resistor string, and sums up the current sources to generate an output current I <subgt;OUT_LSB< / subgt>; an output-stage operational amplifier module that generates an output voltage represented by all M+L-bit input data by combining the output current I <subgt;OUT_LSB< / subgt> and the output voltage V <subgt;OUT_MSB< / subgt> V

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a bit expansion circuit and method applied to a high-precision digital-to-analog converter. Background Art

[0002] As an interface between the analog and digital worlds, a digital-to-analog converter (DAC) plays an irreplaceable role in fields such as communication, detection, and industrial control. In the field of low-speed, low-cost digital-to-analog converters that focus on high precision, the resistor-divider type digital-to-analog converter has been widely used.

[0003] A traditional resistor-divider type digital-to-analog converter uses a resistor string for voltage division, and the input digital signal controls the selection of the output voltage, and then an operational amplifier provides amplification and driving capabilities to generate a stable voltage output. However, for an N-bit digital-to-analog converter, 2 N resistors are required for voltage division, and the area of the resistor array increases exponentially with the precision, which limits the number of bits of the traditional resistor-divider type digital-to-analog converter to less than 10 bits and is difficult to expand. Although the R-2R type digital-to-analog converter only requires 2×N resistors, the high-order resistor mismatch will have a great impact on the precision, and calibrating the resistors will cause a large amount of additional area and power consumption overhead. Summary of the Invention

[0004] The purpose of the present invention is to provide a bit expansion circuit and method applied to a high-precision digital-to-analog converter. By introducing a current related to the resistance value of the resistor string and constructing a resistor-current hybrid digital-to-analog converter, the number of bits of the digital-to-analog converter can be expanded to more than 16 bits and relatively good linearity can be ensured, so as to solve the problem that the number of bits of the existing resistor-divider type digital-to-analog converter is difficult to expand.

[0005] To solve the above technical problems, the present invention provides a bit expansion circuit applied to a high-precision digital-to-analog converter, including:

[0006] A resistor voltage division module that generates an output voltage represented by high M-bit input data D[L+M-1:L] through an operational amplifier one and a resistor string voltage division V OUT_MSB ;

[0007] A low-order injection current generation module that generates a binary-weighted current source represented by low L-bit input data D[L-1:0] according to the current flowing through the resistor string, and sums up the current sources to generate an output current I OUT_LSB ;

[0008] An output stage operational amplifier module that, by using the output current IOUT_LSB and the output voltage V OUT_MSB are combined to generate the output voltage represented by all M + L bits of input data V OUT .

[0009] Preferably, the resistive voltage division module includes: a resistor string, a high - order control switch, an operational amplifier 1, a first PMOS transistor, and a second PMOS transistor; one end of the resistor string is grounded, and the other end is connected to the non - inverting input terminal of the operational amplifier 1, the gate terminal and the drain terminal of the second PMOS transistor; the inverting input terminal of the operational amplifier 1 is connected to a reference voltage V REF , and the output terminal is connected to the gate terminal of the first PMOS transistor; the source terminal of the first PMOS transistor is connected to the power supply voltage, and the drain terminal is connected to the source terminal of the second PMOS transistor; between every two adjacent series - connected resistors in the resistor string, they are respectively connected to the input terminal of a high - order control switch, and the output terminals of several high - order control switches are commonly connected to generate an output voltage V OUT_MSB , and the control terminals of several high - order control switches are used to input high - order M - bit input data D[L + M - 1:L].

[0010] Preferably, the resistor string is composed of 2 M +1 series - connected resistors, and the total resistance value of the resistor string is 2 M × R； Among them, the total resistance value of 2 M -1 resistors connected in series at the middle end of the resistor string is R , and the resistance values of the resistors at the head and tail ends of the resistor string are respectively R OFS and R- R OFS .

[0011] Preferably, the low - order injection current generation module includes: a third PMOS transistor, a fourth PMOS transistor, and a low - order control switch; the source terminals of several third PMOS transistors are commonly connected to the power supply voltage, the gate terminals of several third PMOS transistors and the output terminal of the operational amplifier 1 are commonly connected, the drain terminal of the third PMOS transistor is connected to the source terminal of the fourth PMOS transistor, the gate terminals of several fourth PMOS transistors and the non - inverting input terminal of the operational amplifier 1 are commonly connected, the drain terminals of several fourth PMOS transistors are respectively connected to the input terminal of a low - order control switch, and the output terminals of several low - order control switches are commonly connected to generate an output current I OUT_LSB , and the control terminals of several low - order control switches are used to input low - order L - bit data D[L - 1:0].

[0012] Preferably, the output stage operational amplifier module includes: operational amplifier two, a feedback resistor, and an injection resistor; the non-inverting input terminal of the operational amplifier two is connected to the output voltage V OUT_MSB , the output terminal is connected to one end of the feedback resistor, the other end of the feedback resistor is commonly connected to the inverting input terminal and one end of the injection resistor, the other end of the injection resistor is grounded, and the output current I OUT_LSB is injected onto the injection resistor.

[0013] Preferably, the feedback resistor and the injection resistor have the same resistance value.

[0014] Preferably, the current flowing through the resistor string I R= V REF / (2 M ×R) is generated, and there is I R =2× I L-1 =2 2 × I L-2 =2 3 × I L-3 …=2 L × I 0;

[0015] The output current I OUT_LSB =(1 - D[L - 1])× I L-1 +(1 - D[L - 2])× I L-2 +…+(1 - D[0])× I 0;

[0016] The output voltage V OUT_MSB =V REF / (2 M × R )×( CODE MSB × R + R OFS ); where CODE MSB is the code value represented by the high M-bit input data D[L + M - 1:L].

[0017] Preferably, the output voltage V OUT =2×( V OUT_MSB-R× I OUT_LSB )), by designing V REF × R OFS / (2 M × R ) = ( I L-1 +…+ I 0) R , that is R OFS = R (2 -1 +2 -2 +…+2 -L )), when V OUT = 2 × ( V REF × CODE / 2 M+L ), making V OUT represent the output voltage represented by all M + L - bit input data; where CODE is the code value size represented by all M + L - bit input data.

[0018] The present invention also provides a method for expanding the number of bits applied to a high - precision digital - to - analog converter, implementing a circuit for expanding the number of bits applied to a high - precision digital - to - analog converter as described above, including the following steps:

[0019] Step 1: Generate the output voltage represented by the high M - bit input data D[L + M - 1:L] by means of resistor string voltage division V OUT_MSB ;

[0020] Step 2: Generate a series of binary - weighted current sources based on the current flowing through the resistor string and connect them to the low - order control switches;

[0021] Step 3: Sum up the total current represented by the low L - bit input data D[L - 1:0] to generate an output current I OUT_LSB ;

[0022] Step 4: Combine the output current I OUT_LSB of the low L - bits and the output voltage V OUT_MSB of the high M - bits through the output - stage operational amplifier module, and use the operational amplifier to amplify to obtain the output voltage V OUT = 2 × ( V REF × CODE / 2 M+L ).

[0023] Preferably, for the binary weighted current source in step 2, through thermometer decoding, the current sources of some data bits can be converted into current sources with the same magnitude, and the linearity of the digital-to-analog converter can be further improved through the matching current sources.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The resistor voltage division module of the present invention is used to generate the output voltage represented by the high M-bit input data D[L+M-1:L]; the low-order injection current generation module generates a series of binary weighted current sources represented by the low L-bit data D[L-1:0] according to the current flowing through the resistor string I R The output stage operational amplifier combines the current of the low L bits I OUT_LSB and the voltage of the high bits V OUT_MSB By injecting the total current flowing out of the low bits I OUT_LSB into the resistor 2R, the output V OUT adds the voltage of the low bits V OUT_MSB on the voltage of the high bits V OUT_LSB to finally obtain the output voltage represented by all M+L data bits. The present invention can effectively relieve the pressure caused by the exponentially increasing resistor string area due to the bit expansion. By dividing the input data bits into two segments, the high segment and the low segment, the matching is realized in the low segment by using the binary current source method, and the proportional relationship between the low segment and the high segment is ensured. Finally, on the output operational amplifier, the output V OUT is the superposition value of the voltages represented by the two segments, realizing the bit expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is the functional block diagram of the bit expansion circuit applied to the high-precision digital-to-analog converter provided by the present invention.

[0027] Figure 2 is the circuit diagram of the resistor voltage division module and the low-order injection current generation module provided by the present invention.

[0028] Figure 3 is the circuit diagram of the output stage operational amplifier module provided by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0030] As Figure 1 shown, the embodiment of the present invention specifically provides a bit extension circuit applied to a high-precision digital-to-analog converter, including:

[0031] A resistor voltage division module that generates an output voltage represented by the high M-bit input data D[L+M-1:L] through an operational amplifier OP1 and resistor string voltage division V OUT_MSB ;

[0032] A low-bit injection current generation module that generates a binary-weighted current source represented by the low L-bit input data D[L-1:0] according to the current flowing through the resistor string I R and sums up the current sources to generate an output current I OUT_LSB ;

[0033] An output stage operational amplifier module that combines the output current I OUT_LSB and the output voltage V OUT_MSB by injecting the total current flowing out of the low bit I OUT_LSB into the injection resistor 2R, so that the output V OUT adds the voltage of the low bit V OUT_MSB to the voltage of the high bit V OUT_LSB to generate an output voltage represented by all M+L-bit input data V OUT .

[0034] The bit extension circuit of the present invention can effectively relieve the pressure caused by the exponentially increasing resistor string area due to bit extension. By dividing the input data bits into two segments, a high segment and a low segment, binary current sources are used in the low segment to achieve matching, and the proportional relationship between the low segment and the high segment is ensured. Finally, on the output operational amplifier, the output V OUT is the superposition value of the voltages represented by the two segments, realizing bit extension.

[0035] As Figure 2As shown, the resistor voltage division module includes: a resistor string, a high - level control switch, an operational amplifier OP1, a first PMOS transistor P1, and a second PMOS transistor P2; one end of the resistor string is grounded, and the other end is connected to the non - inverting input terminal of the operational amplifier OP1, the gate terminal and the drain terminal of the second PMOS transistor P2; the inverting input terminal of the operational amplifier OP1 is connected to a reference voltage V REF , and the output terminal is connected to the gate terminal of the first PMOS transistor P1; the source terminal of the first PMOS transistor is connected to the power supply voltage, and the drain terminal is connected to the source terminal of the second PMOS transistor P2; between every two adjacent series - connected resistors in the resistor string, they are respectively connected to the input terminal of a high - level control switch, and the output terminals of several high - level control switches are commonly connected to generate an output voltage V OUT_MSB , and the control terminals of several high - level control switches are used to input high M - bit input data D[L + M - 1:L].

[0036] The resistor string is formed by connecting 2 M +1 resistors in series to form a resistor array. The total resistance value of the resistor string is 2 M × R； Among them, the total resistance value of the 2 M -1 resistors connected in series at the middle end of the resistor string is R , and the resistance values of the resistors at the head and tail ends of the resistor string are respectively R OFS and R-R OFS . And the output voltage is selected and gated by inputting M - bit data D[L + M - 1:L] V OUT_MSB , and the voltage at the uppermost end of the resistor string is clamped to V REF by the operational amplifier OP1. Therefore, there is an output voltage V OUT_MSB =V REF / (2 M × R )×( CODE MSB × R + R OFS ); where CODE MSB is the value of the code represented by the high M - bit input data D[L + M - 1:L]. The number of bits of M is usually between 6 and 10 to avoid excessive area overhead caused by too many resistors in the resistor voltage division module.

[0037] Such as Figure 2As shown in the figure, the low-bit injection current generation module includes: a third PMOS transistor P3, a fourth PMOS transistor P4, and a low-bit control switch; a current source array is formed by the third PMOS transistor P3 and the fourth PMOS transistor P4. The source terminals of several third PMOS transistors P3 are commonly connected to the power supply voltage. The gate terminals of several third PMOS transistors P3 and the output terminal of the first operational amplifier OP1 are commonly connected. The drain terminal of the third PMOS transistor P3 is connected to the source terminal of the fourth PMOS transistor P4. The gate terminals of several fourth PMOS transistors P4 and the non-inverting input terminal of the first operational amplifier OP1 are commonly connected. The drain terminals of several fourth PMOS transistors P4 are respectively connected to the input terminal of a low-bit control switch. The output terminals of several low-bit control switches are commonly connected to generate an output current I OUT_LSB , and the control terminals of several low-bit control switches are used to input the low L-bit data D[L-1:0].

[0038] As Figure 3 shown in the figure, the output stage operational amplifier module includes: a second operational amplifier OP2, a feedback resistor, and an injection resistor. The feedback resistor and the injection resistor have the same resistance value, and the resistance value is 2R; the non-inverting input terminal of the second operational amplifier OP2 is connected to the output voltage V OUT_MSB , the output terminal is connected to one end of the feedback resistor, the other end of the feedback resistor is commonly connected to the inverting input terminal and one end of the injection resistor, the other end of the injection resistor is grounded, and the output current I OUT_LSB is injected onto the injection resistor.

[0039] The low L-bit binary current generated by the low-bit injection current generation module is based on the current flowing through the resistor string in the resistor voltage division module I R generated, and there is I R= V REF / (2 M ×R)=2× I L-1 =2 2 × I L-2 =2 3 × I L-3 …=2 L × I 0; the low-bit injection current generation module generates the current represented by the low L-bit data D[L-1:0] I L-1 、 I L-2 、… I 0. When the data bit D[L-1:0] is 0, the current flows inI OUT_LSB , conversely, no current flows out. Therefore I OUT_LSB =(1 - D[L - 1])× I L-1 +(1 - D[L - 2])× I L-2 +…+(1 - D[0])× I 0.

[0040] The output - stage operational - amplifier module, while achieving a 2 - fold voltage amplification of V OUT_MSB , injects the total current of I OUT_LSB into the injection resistor 2R, such that V OUT the output simultaneously includes the voltage outputs represented by the high M - bits and the low L - bits.

[0041] Specifically, due to the clamping effect of operational amplifier OP2, the feedback voltage of the output - stage operational - amplifier module is equal to V OUT_MSB , so there is: I a =( V OUT - V OUT_MSB ) / 2R, I b = V OUT_MSB / 2R = I a + I OUT_LSB , so there is: V OUT =2×( V OUT_MSB - R× I OUT_LSB ).

[0042] Furthermore, since V OUT_MSB = V REF ×( CODE MSB × R + R OFS ) / (2 M × R ) = V REF × CODE MSB / 2 M + V REF ×R OFS / (2 M × R );

[0043] I OUT_LSB =(1 - D[L - 1])× I L-1 +(1 - D[L - 2])× I L-2 +…+(1 - D[0])× I 0

[0044] =( I L-1 + I L-2 +…+ I 0)- CODE LSB × I 0

[0045] =( I L-1 + I L-2 +…+ I 0)- CODE LSB × V REF / (2 M+L × R )

[0046] Substitute CODE =2 L × CODE MSB + CODE LSB , which CODE is the code value size represented by all M + L - bit input data, we can get:

[0047] V OUT =2× V REF × CODE MSB / 2 M + V REF × CODE MSB / 2 M+L + V REF × R OFS / (2 M × R )-( I L-1 +…+I 0) R

[0048] =2× V REF × CODE / 2 M+L + V REF × R OFS / (2 M × R )-( I L-1 +…+ I 0) R

[0049] By designing V REF × R OFS / (2 M × R )=( I L-1 +…+ I 0) R That is R OFS = R (2 -1 +2 -2 +…+2 -L ) when V OUT= 2×( V REF × CODE / 2 M+L ) At this time, the output voltage V OUT can represent the voltage weights of all M + L bits, so that the bit width of the DAC is extended to M + L bits.

[0050] This embodiment of the present invention also specifically provides a method for expanding the number of bits applied to a high-precision digital-to-analog converter, including the following steps:

[0051] Step 1: Generate the output voltage represented by the high M-bit input data D[L + M - 1:L] by means of resistor string voltage division V OUT_MSB ;

[0052] Step 2: Generate a series of binary-weighted current sources based on the current flowing through the resistor string and connect them to the low-order control switches;

[0053] Step 3: Sum up the total current represented by the low L-bit input data D[L - 1:0] to generate an output current I OUT_LSB ; ​​

[0054] Step 4: Through the output-stage operational amplifier module, output the current of the lower L bits I OUT_LSB and the output voltage of the higher M bits V OUT_MSB are combined, and an operational amplifier is used for amplification to obtain the output voltage V OUT = 2 × ( V REF × CODE / 2 M+L ).

[0055] As a preferred embodiment of the present invention, the binary-weighted current source in the above step 2 can, through the thermometer decoding method, convert the current sources of some data bits into current sources with the same magnitude, and further improve the linearity of the digital-to-analog converter through the matching current sources.

[0056] As a preferred embodiment of the present invention, the linearity of the digital-to-analog converter can be further improved by optimizing the layout of the resistor array and the current source array in the above steps 1 and 2.

[0057] As a preferred embodiment of the present invention, in the above step 4, the linearity of the digital-to-analog converter can be further improved by calibrating the current sources of R OFS or the low-bit injection current generation module.

[0058] In summary, based on the traditional low-resolution resistor digital-to-analog converter, the present invention expands its bit number to more than 14 - 16 bits by adding a relatively small circuit overhead, meets the usage requirements of most current high-precision digital-to-analog converters, and ensures relatively good linearity.

[0059] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure fall within the protection scope of the claims.

Claims

1. A bit expansion circuit applied to a high-precision digital-to-analog converter, characterized in that, Including: The resistor voltage division module generates the output voltage represented by the high M-bit input data D[L+M-1:L] through the first operational amplifier and resistor string voltage division V OUT_MSB ; The low-injection current generation module generates binary-weight current sources represented by the low L-bit input data D[L-1:0] according to the current flowing through the resistor string, and sums up the current sources to generate an output current I OUT_LSB ; Output stage operational amplifier module, by combining the output current I OUT_LSB and the output voltage V OUT_MSB That is, by designing feedback resistors and injection resistors with a resistance value of 2R, the output current I OUT_LSB flowing out from the low L bits is injected onto the injection resistor, so that the output voltage V OUT is superimposed on the output voltage V OUT_MSB of the high M bits V OUT_LSB of the low L bits, to generate the output voltage V OUT represented by all M + L bit input data; The resistor string is 2 M +1 resistors are connected in series, and the total resistance of the resistor string is 2 M × R； where the total resistance of the 2 M -1 resistors connected in series at the middle end of the resistor string is R , and the resistance values of the resistors at the head and tail ends of the resistor string are respectively R OFS and R-R OFS ; The current flowing through the resistor string I R= V REF / (2 M ×R), and there is I R =2× I L-1 =2 2 × I L-2 =2 3 × I L-3 …=2 L × I 0; The output current I OUT_LSB =(1 - D[L - 1]) × I L-1 +(1 - D[L - 2]) × I L-2 +…+(1 - D[0]) × I 0; The output voltage V OUT_MSB =V REF / (2 M × R )×( CODE MSB × R + R OFS ); where CODE MSB is the code value represented by the high M-bit input data D[L+M-1:L]; The output voltage V OUT = 2 × ( V OUT_MSB - R × I OUT_LSB ), by designing V REF × R OFS / (2 M × R ) = ( I L-1 + … + I 0) R , that is R OFS = R (2 -1 + 2 -2 + … + 2 -L ) when V OUT = 2 × ( V REF × CODE / 2 M+L ), such that V OUT represents the output voltage represented by all M + L - bit input data; where CODE is the magnitude of the code value represented by all M + L - bit input data.

2. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 1, wherein The resistor voltage division module includes: a resistor string, a high-bit control switch, an operational amplifier 1, a first PMOS transistor, and a second PMOS transistor; one end of the resistor string is grounded, and the other end is connected to the non-inverting input terminal of the operational amplifier 1, the gate terminal and the drain terminal of the second PMOS transistor; the inverting input terminal of the operational amplifier 1 is connected to a reference voltage V REF , and the output terminal is connected to the gate terminal of the first PMOS transistor; the source terminal of the first PMOS transistor is connected to a power supply voltage, and the drain terminal is connected to the source terminal of the second PMOS transistor; between every two adjacent series resistors in the resistor string, they are respectively connected to the input terminal of a high-bit control switch, and the output terminals of several high-bit control switches are commonly connected to generate an output voltage V OUT_MSB , and the control terminals of several high-bit control switches are used to input high M-bit input data D[L+M-1:L].

3. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 1, characterized in that, The low-injection current generation module includes: a third PMOS transistor, a fourth PMOS transistor, and a low-level control switch; the source terminals of a plurality of the third PMOS transistors are commonly connected to a power supply voltage, the gate terminals of a plurality of the third PMOS transistors and the output terminal of the first operational amplifier are commonly connected, the drain terminal of the third PMOS transistor is connected to the source terminal of the fourth PMOS transistor, the gate terminals of a plurality of the fourth PMOS transistors and the non-inverting input terminal of the first operational amplifier are commonly connected, the drain terminals of a plurality of the fourth PMOS transistors are respectively connected to the input terminal of a low-level control switch, and the output terminals of a plurality of low-level control switches are commonly connected to generate an output current. I OUT_LSB , and the control terminals of a plurality of low-level control switches are used to input low L-bit data D[L-1:0].

4. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 1, wherein The output stage operational amplifier module includes: operational amplifier two, a feedback resistor, and an injection resistor; the non-inverting input terminal of the operational amplifier two is connected to the output voltage V OUT_MSB , the output terminal is connected to one end of the feedback resistor, the other end of the feedback resistor is commonly connected to the inverting input terminal and one end of the injection resistor, the other end of the injection resistor is grounded, and the output current I OUT_LSB is injected onto the injection resistor.

5. The bit extension circuit applied to the high-precision digital-to-analog converter according to claim 4, characterized in that, The values of the feedback resistor and the injection resistor are the same.

6. A method for expanding the number of bits applied to a high-precision digital-to-analog converter, which executes a circuit for expanding the number of bits applied to a high-precision digital-to-analog converter according to any one of claims 1 to 5, characterized in that, Including the following steps: Step 1: Generate the output voltage represented by the high M-bit input data D[L+M-1:L] by means of voltage division with a resistor string V OUT_MSB ; Step 2: Based on the current flowing through the resistor string, generate a series of binary-weighted current sources and connect them to the low-order control switches; Step 3: Aggregate the total current represented by the low L-bit input data D[L-1:0] to generate an output current I OUT_LSB ; Step 4: Through the output stage operational amplifier module, combine the output current of the lower L bits I OUT_LSB and the output voltage of the higher M bits V OUT_MSB and use an operational amplifier to amplify to obtain the output voltage V OUT = 2 × ( V REF × CODE / 2 M+L ).

7. A bit expansion method applied to a high-precision digital-to-analog converter according to claim 6, characterized in that The binary-weighted current sources in Step 2 can, through thermometer decoding, convert the current sources of some data bits into current sources with the same magnitude, and further improve the linearity of the digital-to-analog converter through the matching current sources.

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