Electronic substrate

Abstract

The invention provides an electronic substrate capable of reducing the workload required for setting the ID of a memory. An electronic substrate includes a support substrate, a memory and a processor connected to the support substrate by solder, and two or more memory elements storing an ID of the memory. Each of the two or more memory elements includes a conductive first pad disposed on the support substrate, and a conductive second pad disposed on the support substrate with a gap therebetween. At least one of the two or more memory elements has a connection layer that contains solder and electrically connects the first pad and the second pad.

Description

Technical Field

[0001] The present invention relates to an electronic substrate. Background Art

[0002] When a user wants to purchase a PC (Personal Computer), the user accesses the website of a company that sells PCs and can order a PC on the website. When the user orders a PC, the user can specify the specifications of the CPU (Central Processing Unit) and memory etc. mounted on the PC.

[0003] In an existing normal manufacturing process, a factory manufactures motherboards according to each combination of various types of CPUs and memories by using SMT (Surface Mount Technology). The manufactured motherboards are stored in the factory. Patent Document 1 discloses a motherboard manufactured by using SMT.

[0004] After the user orders a PC, the factory confirms the inventory of motherboards according to the order content in the factory. If there is no motherboard mounted with the CPU and memory specified by the user in storage, the factory manufactures a motherboard mounted with the CPU and memory.

[0005] As described above, in an existing normal manufacturing process, a factory needs to store a large number of motherboards in order to cope with each combination of various types of CPUs and memories. Therefore, costs are incurred for storing the motherboards. In addition, when a motherboard mounted with the CPU and memory specified by the user is not stored and it is necessary to manufacture the motherboard, the factory may not be able to promptly start manufacturing the motherboard.

[0006] On the other hand, in order to reduce the inventory of motherboards in the factory, the following manufacturing process is used. The factory manufactures a motherboard that does not have a CPU mounted but has a memory mounted, and stores the motherboard. In the process of manufacturing the motherboard, a production line (SMT line) of SMT is used. After the user orders a PC, the factory selects a motherboard mounted with the memory specified by the user and mounts the CPU specified by the user on the motherboard. In the process of mounting the CPU on the motherboard, a production line different from the SMT line is used.

[0007] In the above manufacturing process, compared with the normal manufacturing process, the inventory of motherboards is reduced. In addition, since the factory can mount the CPU on the motherboard by a production line different from the SMT line, it does not affect the manufacturing of motherboards on the SMT line.

[0008] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2023-134353.

[0009] In order to further reduce the inventory of motherboards in the factory, a manufacturing process of mounting a CPU and a memory on a motherboard after a user orders a PC was studied. Hereinafter, this manufacturing process will be described. The factory manufactures motherboards without a mounted CPU and memory through an SMT line and stores the motherboards. After the user orders a PC, the factory mounts the CPU and memory specified by the user on the motherboard through a production line different from the SMT line.

[0010] The CPU uses firmware corresponding to the specifications of the memory mounted on the motherboard. The CPU selects the firmware according to the ID of the memory set in the motherboard. In the above manufacturing process, according to the type of memory mounted on the motherboard, the operator in the factory needs to set the ID manually. Summary of the Invention

[0011] An object of the present invention is to provide an electronic substrate capable of reducing the workload required for setting the ID of a memory.

[0012] One aspect of the present invention is an electronic substrate including: a support substrate; a memory and a processor soldered to the support substrate; and two or more storage elements storing the ID of the memory. Each of the two or more storage elements includes: a conductive first pad disposed on the support substrate; and a conductive second pad disposed on the support substrate with a gap therebetween. At least one of the two or more storage elements has a connection layer including solder that electrically connects the first pad and the second pad.

[0013] In one aspect of the present invention, it may also be configured that the electronic substrate includes: a first insulating layer disposed on the first pad other than a first region where a part of the first pad and the connection layer overlap; and a second insulating layer disposed on the second pad other than a second region where a part of the second pad and the connection layer overlap.

[0014] In one aspect of the present invention, it may also be configured that the first insulating layer and the second insulating layer are not disposed in the gap.

[0015] In one aspect of the present invention, it may also be configured that the width of the gap is 0.15 mm or more and 0.175 mm or less.

[0016] According to the above aspect of the present invention, the electronic substrate can reduce the workload required for setting the ID of the memory. Brief Description of the Drawings

[0017] Figure 1 It is a diagram showing an example of the hardware structure of an electronic device according to an embodiment.

[0018] Figure 2 This is a diagram showing a structural example of an ID storage unit included in an electronic device according to an embodiment.

[0019] Figure 3 This is a diagram showing a structural example of a storage element included in an electronic device according to an embodiment.

[0020] Figure 4 This is a diagram showing an example of a manufacturing process of a storage element and a main memory included in an electronic device according to an embodiment.

[0021] Figure 5 This is a diagram showing an example of a manufacturing process of a storage element and a main memory included in an electronic device according to an embodiment.

[0022] Figure 6 This is a diagram showing an example of a manufacturing process of a storage element and a main memory included in an electronic device according to an embodiment.

[0023] Figure 7 This is a diagram showing an example of a manufacturing process of a storage element and a main memory included in an electronic device according to an embodiment.

[0024] Figure 8 This is a diagram showing an example of a manufacturing process of a storage element and a main memory included in an electronic device according to an embodiment.

[0025] Description of Reference Numerals

[0026] 10... Electronic device; 11... CPU; 12... Main memory; 13... Video subsystem; 14... Display unit; 15... ID storage unit; 16... Support substrate; 17... Electronic substrate; 21... Chipset; 22... BIOS memory; 23... Storage medium; 24... Audio system; 25... WLAN card; 26... USB connector; 31... Embedded controller; 32... Input unit; 33... Power supply circuit; 34... Battery; 120, 1506... Connection layer; 121... Substrate; 150, 151, 152, 153, 154... Storage element; 1500... First pad; 1501... Second pad; 1502... First connection pad; 1503... Second connection pad; 1504... First insulating layer; 1505... Second insulating layer. Detailed Embodiments

[0027] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0028] Refer to Figure 1 to describe a hardware structural example of the electronic device 10 according to an embodiment. Figure 1 This is a block diagram showing an example of the hardware structure of the electronic device 10.

[0029] The electronic device 10 includes: a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, an ID storage unit 15, a chipset 21, a BIOS memory 22, a storage medium 23, an audio system 24, a WLAN card 25, a USB connector 26, an embedded controller 31, an input unit 32, a power supply circuit 33, and a battery 34.

[0030] The CPU 11 performs various arithmetic processes through program control and controls the entire electronic device 10. For example, the CPU 11 executes processes based on programs of an OS (Operating System) and a BIOS (Basic Input Output System). The CPU 11 is an example of a processor.

[0031] The main memory 12 is a writable memory that is used as a read-in area for the execution program of the CPU 11 or as a work area for writing the processing data of the execution program. The main memory 12 is constituted by, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. The execution program includes various driver programs, various service / utilities, application programs, etc. for performing hardware operations on the OS and peripheral devices.

[0032] The video subsystem 13 is a subsystem for implementing functions related to image display and includes a video controller. The video controller processes rendering commands from the CPU 11, writes the processed rendering information into a video memory, and reads out the rendering information from the video memory and outputs it as rendering data (display data) to the display unit 14.

[0033] The display unit 14 is, for example, a liquid crystal display or an organic EL display, and displays a display screen based on the rendering data (display data) output from the video subsystem 13.

[0034] The ID storage unit 15 stores an ID for identifying the main memory 12. Hereinafter, the ID of the main memory 12 is referred to as a memory ID.

[0035] The chipset 21 includes controllers such as USB (Universal Serial Bus), serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count) bus, and is connected to multiple devices. For example, as the multiple devices, it includes the BIOS memory 22, storage medium 23, audio system 24, WLAN card 25, USB connector 26, and embedded controller 31 described later.

[0036] The BIOS memory 22 is composed of an electrically rewritable non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) or flash ROM, for example. The BIOS memory 22 stores system firmware for controlling the BIOS, embedded controller 31, etc. The BIOS memory 22 is an example of a sub-memory.

[0037] The storage medium 23 includes HDD (Hard Disk Drive), SSD (Solid State Drive), etc. For example, the storage medium 23 stores the OS, various drivers, various services / utilities, application programs, and various data.

[0038] The audio system 24 is connected to a microphone and a speaker (not shown) and performs recording, playback, and output of sound data. In addition, the microphone and the speaker are built into the electronic device 10 as an example.

[0039] The WLAN (Wireless Local Area Network) card 25 is connected to a network via a wireless LAN and performs data communication. For example, when the WLAN card 25 receives data from the network, it generates an event trigger indicating that the data has been received. The USB connector 26 is a connector for connecting peripheral device classes using USB.

[0040] The input unit 32 collectively represents the input devices of the electronic device 10. The input unit 32 includes a keyboard, a mouse, etc. The input unit 32 outputs the input information input by the user's operation to the embedded controller 31.

[0041] The power supply circuit 33 includes, for example, a DC / DC converter, a charge and discharge unit, an AC / DC adapter, etc. For example, the power supply circuit 33 converts the DC voltage supplied from an external power supply such as an AC adapter (not shown) or the battery 34 into multiple voltages required for the operation of the electronic device 10. In addition, based on the control from the embedded controller 31, the power supply circuit 33 supplies power to each part of the electronic device 10.

[0042] The battery 34 is, for example, a secondary battery such as a lithium-ion battery. When power is supplied to the electronic device 10 from an external power supply, the battery 34 is charged via the power supply circuit 33. When power is not supplied to the electronic device 10 from an external power supply, the battery 34 outputs the stored power as the operating power of the electronic device 10 via the power supply circuit 33.

[0043] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices and sensors, etc.) regardless of the system state of the electronic device 10. The embedded controller 31 includes a CPU, a ROM, a RAM, A / D input terminals of multiple channels, D / A output terminals, a timer, and digital input / output terminals (not shown). The input unit 32 and the power supply circuit 33, etc. are connected to the digital input / output terminals of the embedded controller 31, and the embedded controller 31 controls their operations. In addition, the embedded controller 31 controls changes in the clock frequency of the CPU 11 via the chipset 21.

[0044] The electronic device 10 can also be a portable device such as a clamshell personal computer, a tablet terminal, or a smart phone, etc., and a display device can be integrally installed in the housing of the electronic device 10. Alternatively, like a desktop personal computer, the device main body and the display device can be separated. The electronic device according to the present embodiment can be applied to all devices equipped with a CPU.

[0045] Refer to Figure 2 , and a structural example of the ID storage unit 15 will be described. Figure 2 is a block diagram showing a structural example of the ID storage unit 15.

[0046] The ID storage unit 15 includes two or more storage elements. In the Figure 2 example shown, the ID storage unit 15 includes a storage element 150, a storage element 151, a storage element 152, a storage element 153, and a storage element 154. Figure 2 Five storage elements are shown, but the number of storage elements is not limited to five. The number of storage elements included in the ID storage unit 15 is, for example, two or more and five or less.

[0047] For example, the memory ID is five - bit data. The memory ID includes bit ID0, bit ID1, bit ID2, bit ID3, and bit ID4. Storage elements 150 to 154 store bit ID0 to ID4 respectively. Storage elements 150 to 154 are electrically connected to the CPU 11.

[0048] The respective states of storage elements 150 to 154 are set to an open state (high - resistance state) or a closed state (low - resistance state). One of these two states corresponds to the value of each bit.

[0049] Refer to Figure 3 , and a structural example of the storage elements included in the ID storage unit 15 will be described. Figure 3 are a top view and a cross - sectional view showing a structural example of the storage element 150. The structures of storage elements 151 to 154 are the same as that of the storage element 150, so the description of the structures of storage elements 151 to 154 is omitted.

[0050] Figure 3 The upper side of Figure 3 is a top view of the storage element 150.

[0051] The lower side of Figure 1 is a cross - sectional view of the storage element 150 in the line A1 - A1. Figure 3 The CPU 11 and the main memory 12 shown, etc., are also arranged on the support substrate 16, but are omitted in

[0052] The storage element 150 includes a first pad 1500, a second pad 1501, a first connection pad 1502, a second connection pad 1503, a first insulating layer 1504, a second insulating layer 1505, and a connection layer 1506.

[0053] The first pad 1500 and the second pad 1501 are arranged on the surface of the support substrate 16. The first pad 1500 and the second pad 1501 are formed of a conductive material. The first pad 1500 and the second pad 1501 are arranged with a gap G1 therebetween. One of the first pad 1500 and the second pad 1501 is electrically connected to the CPU 11 via Figure 3 wiring (not shown) in Figure 3 . The other of the first pad 1500 and the second pad 1501 is electrically connected to a ground terminal provided on the support substrate 16 via

[0054] The first connection pad 1502 is disposed on the surface of the first pad 1500. The first connection pad 1502 electrically connects the first pad 1500 and the connection layer 1506. The second connection pad 1503 is disposed on the surface of the second pad 1501. The second connection pad 1503 electrically connects the second pad 1501 and the connection layer 1506. The first connection pad 1502 and the second connection pad 1503 are formed of solder.

[0055] The first insulating layer 1504 covers a part of the surface of the first pad 1500 and the surface of the support substrate 16. The second insulating layer 1505 covers a part of the surface of the second pad 1501 and the surface of the support substrate 16. The first insulating layer 1504 and the second insulating layer 1505 are formed of an insulating material. The first insulating layer 1504 and the second insulating layer 1505 protect the surfaces of the first pad 1500, the second pad 1501, and the support substrate 16.

[0056] The first pad 1500 overlaps with the first connection pad 1502 in a first region on the surface of the first pad 1500, and overlaps with a part of the connection layer 1506 in the first region. The first insulating layer 1504 is not disposed in the first region but is disposed on the surface of the first pad 1500 outside the first region. The second pad 1501 overlaps with the second connection pad 1503 in a second region on the surface of the second pad 1501, and overlaps with a part of the connection layer 1506 in the second region. The second insulating layer 1505 is not disposed in the second region but is disposed on the surface of the second pad 1501 outside the second region.

[0057] In Figure 3 the example shown, the first insulating layer 1504 and the second insulating layer 1505 are shown as different insulating layers from each other, but the first insulating layer 1504 and the second insulating layer 1505 may also be the same insulating layer connected in a region not shown in Figure 3 .

[0058] The connection layer 1506 is disposed on the surface of the first connection pad 1502 and the surface of the second connection pad 1503. The connection layer 1506 is formed of solder. When observing the connection layer 1506 in a direction perpendicular to the surface of the support substrate 16, the shape of the connection layer 1506 is, for example, circular. The connection layer 1506 electrically connects the first connection pad 1502 and the second connection pad 1503.

[0059] When the state of the storage element 150 is set to the off state, the connection layer 1506 is disposed. When the state of the storage element 150 is set to the on state, the connection layer 1506 is not disposed. At least one of the storage elements 150 to 154 has the connection layer 1506.

[0060] Solder is not easily formed on the insulating layer. In order to ensure the electrical connection between the connection layer 1506 and the first connection pad 1502, and to ensure the electrical connection between the connection layer 1506 and the second connection pad 1503, no insulating layer is provided in the gap G1 between the first pad 1500 and the second pad 1501.

[0061] The width W1 of the gap G1 is, for example, 6 mil (0.15 mm) or more and 7 mil (0.175 mm) or less. 1 mil is 0.0254 mm. The width W1 is the distance between the first pad 1500 and the second pad 1501 in a direction parallel to the surface of the support substrate 16. The diameter of the connection layer 1506 in a direction parallel to the surface of the support substrate 16 is, for example, 15 mil (0.39 mm).

[0062] In a normal manufacturing process, a resistance element is provided instead of the connection layer 1506. In the case where a resistance element is provided, an insulating layer is provided in the gap G1 between the first pad 1500 and the second pad 1501. In this case, the width W1 of the gap G1 is, for example, 8 mil (0.20 mm). In the embodiment of the present invention, the connection layer 1506 is provided instead of the resistance element, so that the width W1 of the gap G1 can be reduced compared with the case where a resistance element is provided.

[0063] Refer to Figures 4 to 8 , and a method for manufacturing the storage element 150 will be described. Figures 4 to 8 is a cross-sectional view showing an example of the manufacturing process of the storage element 150 and the main memory 12. The storage elements 151 to 154 are formed simultaneously with the formation of the storage element 150. Since the manufacturing methods of the storage elements 151 to 154 are the same as the manufacturing method of the storage element 150, the description of the manufacturing methods of the storage elements 151 to 154 is omitted.

[0064] First, as Figure 4 shown, a support substrate 16 is prepared.

[0065] Next, as Figure 5 shown, the first pad 1500 and the second pad 1501 are formed on the surface of the support substrate 16. The first pad 1500 and the second pad 1501 are separated from each other with a gap G1 therebetween. Further, the first insulating layer 1504 is formed on the surface of the first pad 1500 except for the first region A1 of the first pad 1500 and on the surface of the support substrate 16. In addition, the second insulating layer 1505 is formed on the surface of the second pad 1501 except for the second region A2 of the second pad 1501 and on the surface of the support substrate 16.

[0066] Next, as Figure 6 shown, the first connection pad 1502 is formed on Figure 5on the first region A1 shown, and the second connection pad 1503 is formed on Figure 5 the second region A2 shown.

[0067] The factory implements Figures 4 to 6 the process shown by using the SMT line. The factory stores the mother board with Figure 6 the structure shown.

[0068] After the user specifies the specifications of the specific CPU 11 and the main memory 12, the factory implements Figure 7 and Figure 8 the process shown by using a production line different from the SMT line.

[0069] As Figure 7 shown, the connection layer 1506 is formed on the surface of the first connection pad 1502 and on the surface of the second connection pad 1503. In addition, the connection layer 120 is formed on the surface of the support substrate 16. The connection layer 120 is formed of solder. The connection layer 1506 and the connection layer 120 are formed simultaneously by using jet solder printing. At this time, a connection layer identical to the connection layer 120 is formed on the surface of the support substrate 16 on which the CPU 11 is formed. The connection layer 120 is connected to the wiring on the support substrate 16.

[0070] Next, as Figure 8 shown, the substrate 121 of the main memory 12 is arranged on the connection layer 120. The substrate 121 is connected to the support substrate 16 through the connection layer 120. That is, the substrate 121 is electrically connected to the wiring on the support substrate 16 via the connection layer 120. Similarly, the substrate of the CPU 11 is arranged on the connection layer formed on the support substrate 16. The substrate of the CPU 11 is connected to the support substrate 16 through this connection layer. That is, the substrate of the CPU 11 is electrically connected to the wiring on the support substrate 16 via this connection layer.

[0071] Implement Figures 4 to 8 the process shown to manufacture Figure 8 the electronic substrate 17 shown.

[0072] As described above, the electronic substrate 17 includes: a support substrate 16, a main memory 12 and a CPU 11 connected to the support substrate 16 by solder, and two or more storage elements 150 to 154 that store memory IDs. Each of the two or more storage elements 150 to 154 includes a conductive first pad 1500 and a conductive second pad 1501. The first pad 1500 is disposed on the support substrate 16. The second pad 1501 is disposed on the support substrate 16 with a gap G1 therebetween from the first pad 1500. At least one of the two or more storage elements 150 to 154 has a connection layer 1506 that includes solder and electrically connects the first pad 1500 and the second pad 1501.

[0073] By using jet solder printing, the connection layer 1506 is formed simultaneously with the connection layers of the main memory 12 and the CPU 11. The user does not need to manually set the memory ID, so the workload required for setting the memory ID can be reduced. In addition, there is no need to add new equipment in the factory to form the connection layer 1506.

[0074] The electronic substrate 17 includes a first insulating layer 1504 and a second insulating layer 1505. The first insulating layer 1504 is disposed on the first pad 1500 outside a first region A1 where the first pad 1500 and a part of the connection layer 1506 overlap. The second insulating layer 1505 is disposed on the second pad 1501 outside a second region A2 where the second pad 1501 and a part of the connection layer 1506 overlap.

[0075] The first insulating layer 1504 and the second insulating layer 1505 are not disposed in the gap G1. Therefore, the width W1 of the gap G1 can be reduced.

[0076] The width W1 of the gap G1 is 6 mil (0.15 mm) or more and 7 mil (0.175 mm) or less. If the width W1 is less than 6 mil, the risk of electrical short circuit between the first pad 1500 and the second pad 1501 increases. If the width W1 is greater than 7 mil, it is difficult to form the connection layer 1506 that connects the first pad 1500 and the second pad 1501. By setting the range of the width W1 as described above, short circuit between the first pad 1500 and the second pad 1501 can be avoided, and the connection layer 1506 can be easily formed.

[0077] As described above, the embodiments of the present invention have been described in detail with reference to the drawings, but the specific structure is not limited to the above embodiments, and also includes design changes and the like within the scope not departing from the gist of the present invention.

Claims

1. An electronic substrate, comprising: a support substrate; a memory and a processor, connected to the support substrate by solder; and two or more storage elements that store the ID of the memory, each of the two or more storage elements comprising: a conductive first pad disposed on the support substrate; and a conductive second pad disposed on the support substrate with a gap therebetween from the first pad, at least one of the two or more storage elements having a connection layer that includes solder and electrically connects the first pad and the second pad.

2. The electronic substrate according to claim 1, wherein the electronic substrate comprises: a first insulating layer disposed on the first pad outside a first region, the first region being a region where a part of the first pad and the connection layer overlap; and a second insulating layer disposed on the second pad outside a second region, the second region being a region where a part of the second pad and the connection layer overlap.

3. The electronic substrate according to claim 2, wherein the first insulating layer and the second insulating layer are not disposed in the gap.

4. The electronic substrate according to claim 1, wherein the width of the gap is 0.15 mm or more and 0.175 mm or less.

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