Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, the array substrate comprises a substrate, a first electrode layer, a gate insulation layer, a semiconductor layer and a second electrode layer, and the first electrode layer is arranged on the substrate; the gate insulating layer is arranged on the first electrode layer, and a first groove is formed in the upper surface of the gate insulating layer; the semiconductor layer is arranged in the first groove, the semiconductor layer comprises a bottom channel part and a side channel part, the bottom channel part covers the bottom wall of the first groove, the side channel part covers the side wall of the first groove, and the side channel part is arranged on the periphery of the bottom channel part; and the second electrode layer comprises two second electrodes which are arranged at an interval, the second electrodes are arranged on the upper surface of the gate insulating layer, and the bottoms of the second electrodes are in lap joint with one part of the upper surface of the side channel part. According to the invention, the influence of the thickness of the semiconductor layer on the on-state current of the TFT device can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and more particularly to an array substrate and a display panel. Background Art

[0002] In a conventional array substrate, in a thin film transistor (TFT) device with a bottom gate structure, a gate, a semiconductor layer, and source and drain layers are stacked. Among them, the on-state characteristics of the TFT device are related to the thickness of the semiconductor layer within the TFT device. Under certain conditions, the thicker the semiconductor layer, the higher the resistance value of the semiconductor layer, resulting in a decrease in the on-state current of the TFT device when the TFT device is turned on.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0004] The purpose of the present application is to provide an array substrate and a display panel to reduce the influence of the thickness of the semiconductor layer on the on-state current of the TFT device.

[0005] To solve the above problems, the technical solution of the present application is as follows:

[0006] The present application provides an array substrate, including:

[0007] A substrate;

[0008] A first electrode layer disposed on the substrate;

[0009] A gate insulating layer disposed on the first electrode layer, and a first groove is provided on the upper surface of the gate insulating layer;

[0010] A semiconductor layer disposed in the first groove, the semiconductor layer includes a bottom channel portion and a side channel portion, the bottom channel portion covers the bottom wall of the first groove, the side channel portion covers the side wall of the first groove, and the side channel portion is disposed on the periphery of the bottom channel portion; and

[0011] A second electrode layer, including two second electrodes disposed at intervals, the second electrodes are disposed on the upper surface of the gate insulating layer, and the bottom of the second electrodes overlaps a part of the upper surface of the side channel portion.

[0012] In an embodiment of the present application, the upper surface of the side channel portion is flush with the upper surface of the gate insulating layer.

[0013] In an embodiment of the present application, the side channel portion and the bottom channel portion enclose a second groove, and the orthographic projection of the second groove on the substrate does not overlap with the orthographic projection of the second electrode on the substrate;

[0014] The orthographic projection of the first groove on the substrate overlaps with a part of the orthographic projection of the second electrode on the substrate.

[0015] In an embodiment of the present application, the array substrate further includes a protective layer, and the protective layer covers the gate insulating layer, the second electrode layer, and the semiconductor layer;

[0016] Wherein, a part of the second electrode and a part of the protective layer are disposed on the upper surface of the side channel portion, and another part of the protective layer is disposed on a surface of the side channel portion away from the side wall of the first groove.

[0017] In an embodiment of the present application, the side channel portion includes:

[0018] A first front channel portion disposed on the side wall of the first groove, the upper surface of the first front channel portion is flush with the gate insulating layer and is in lap joint with the bottom of the second electrode; and

[0019] A first back channel portion disposed on a surface of the first front channel portion away from the side wall of the first groove;

[0020] Wherein, the protective layer covers the first back channel portion, and the orthographic projection of the first back channel portion on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.

[0021] In an embodiment of the present application, the array substrate further includes two pads, which are spaced apart and disposed on the substrate;

[0022] Wherein, the first electrode layer covers the pads, a first part of the first electrode layer located between the two pads corresponds to the bottom channel portion, and a second part of the first electrode layer covering the side surfaces of the pads corresponds to the side channel portion;

[0023] The first part and the second part enclose a third groove, and a part of the gate insulating layer covering the third groove forms the first groove.

[0024] In an embodiment of the present application, the gate insulating layer includes:

[0025] A first insulating portion disposed between the first part and the bottom channel portion;

[0026] A second insulating portion disposed between the second part and the side channel portion, the second insulating portion is connected to the first insulating portion, and the second insulating portion and the first insulating portion enclose the first groove; and

[0027] A third insulating portion is disposed between a third portion of the first electrode layer covering the upper surface of the spacer and the second electrode. The third insulating portion is connected to the second insulating portion, and the upper surface of the third insulating portion is flush with the upper surface of the side channel portion.

[0028] In an embodiment of the present application, the first electrode layer includes:

[0029] Two first gate portions, which are spaced apart and disposed on the substrate; and

[0030] A second gate portion, which is disposed between the two first gate portions and connects the two first gate portions. The thickness of the second gate portion is less than the thickness of the first gate portion;

[0031] Wherein, a third groove is formed between the upper surface of the second gate portion and the side surfaces of the two first gate portions, and a portion of the gate insulating layer covering the inner wall of the third groove forms the first groove.

[0032] In an embodiment of the present application, the gate insulating layer includes:

[0033] A first insulating portion, which is disposed between the second gate portion and the bottom channel portion;

[0034] A second insulating portion, which is disposed between the first gate portion and the side channel portion. The second insulating portion is connected to the first insulating portion, and the second insulating portion and the first insulating portion enclose the first groove; and

[0035] A third insulating portion, which is disposed between the first gate portion and the second electrode. The third insulating portion is connected to the second insulating portion, and the upper surface of the third insulating portion is flush with the upper surface of the side channel portion.

[0036] The present application provides a display panel. The display panel includes an array substrate, and the array substrate includes: a substrate; a first electrode layer, which is disposed on the substrate; a gate insulating layer, which is disposed on the first electrode layer, and a first groove is provided on the upper surface of the gate insulating layer; a semiconductor layer, which is disposed in the first groove. The semiconductor layer includes a bottom channel portion and a side channel portion. The bottom channel portion covers the bottom wall of the first groove, the side channel portion covers the side wall of the first groove, and the side channel portion is disposed on the periphery of the bottom channel portion; a second electrode layer, which includes two second electrodes arranged at intervals. The second electrode is disposed on the upper surface of the gate insulating layer, and the bottom of the second electrode is lapped with a part of the upper surface of the side channel portion.

[0037] In the present application, the semiconductor layer includes a side channel portion disposed on the sidewall of the first groove and a bottom channel portion disposed on the bottom wall of the first groove. Among them, the portion of the side channel portion directly overlapping with the second electrode is the front channel of the side channel portion, and the portion of the side channel portion not directly overlapping with the second electrode is the back channel of the side channel portion. The side of the bottom channel portion close to the bottom wall of the first groove is the front channel of the bottom channel portion, and the side of the bottom channel portion away from the bottom wall of the first groove is the back channel of the bottom channel portion. The front channel of the side channel portion and the front channel of the bottom channel portion form the front channel of the semiconductor layer, and the back channel of the side channel portion and the back channel of the bottom channel portion form the back channel of the semiconductor layer. At this time, the front channel of the semiconductor layer is directly overlapped with the second electrode, and the front channel of the semiconductor layer is located between the first electrode layer and the back channel of the semiconductor layer. The back channel of the semiconductor layer is not directly overlapped with the second electrode, and the back channel of the semiconductor layer is located on the side of the front channel of the semiconductor layer away from the first electrode layer. When a threshold voltage is applied to the first electrode layer, a conductive channel is formed in the front channel of the semiconductor layer, and the two second electrodes are conducted through the conductive channel. Compared with the design in the TFT device with a traditional bottom gate structure, where the gate, semiconductor layer, source, and drain are stacked, and the back channel of the semiconductor layer is located between the front channel of the semiconductor layer and the gate, in the TFT device with the bottom gate structure of the present application, the source and drain are directly overlapped with the front channel of the semiconductor layer, and the back channel of the semiconductor layer is located on the side of the front channel of the semiconductor layer away from the gate. The TFT device with the bottom gate structure of the present application can form a conductive channel across the resistance of the back channel when conducting. The TFT device of the present application improves the on-state current compared with the TFT device with a traditional bottom gate structure and reduces the influence of the thickness of the semiconductor layer on the on-state current of the TFT device. Description of the Drawings

[0038] Figure 1 is a schematic diagram of an embodiment of the array substrate of the present application;

[0039] Figure 2 is a schematic diagram of another embodiment of the array substrate of the present application;

[0040] Figure 3 is a schematic diagram of a traditional array substrate. Detailed Embodiments

[0041] The meanings of the terms used in this specification and the claims correspond to those commonly understood by those of ordinary skill in the art to which the present application belongs. The terms used in this specification and the claims are only for the purpose of facilitating the description and understanding of the present application, and are not intended to limit the present application to the narrow interpretation of the specific terms used in the specification and the claims.

[0042] The present application proposes a display panel, which can be an LCD, an OLED, or an MLED. The display panel includes an array substrate 100.

[0043] Referring to Figures 1 to 2 , the present application provides an array substrate 100, comprising:

[0044] a substrate 10;

[0045] a first electrode layer 20 disposed on the substrate 10;

[0046] a gate insulating layer 30 disposed on the first electrode layer 20, and a first groove is provided on the upper surface of the gate insulating layer 30;

[0047] a semiconductor layer 40 disposed in the first groove, the semiconductor layer 40 includes a bottom channel portion 42 and a side channel portion 41, the bottom channel portion 42 covers the bottom wall of the first groove, the side channel portion 41 covers the side wall of the first groove, and the side channel portion 41 is disposed around the bottom channel portion 42; and

[0048] a second electrode layer, including two second electrodes 50 disposed at intervals, the second electrodes 50 are disposed on the upper surface of the gate insulating layer 30, and the bottom of the second electrodes 50 overlaps with a part of the upper surface of the side channel portion 41.

[0049] In the present application, the semiconductor layer 40 includes a side channel portion 41 provided on the side wall of the first groove and a bottom channel portion 42 provided on the bottom wall of the first groove. Among them, the portion of the side channel portion 41 directly overlapping with the second electrode 50 is the front channel of the side channel portion 41, and the portion of the side channel portion 41 not directly overlapping with the second electrode 50 is the back channel of the side channel portion 41. The side of the bottom channel portion 42 close to the bottom wall of the first groove is the front channel of the bottom channel portion 42, and the side of the bottom channel portion 42 away from the bottom wall of the first groove is the back channel of the bottom channel portion 42. The front channel of the side channel portion 41 and the front channel of the bottom channel portion 42 form the front channel of the semiconductor layer 40, and the back channel of the side channel portion 41 and the back channel of the bottom channel portion 42 form the back channel of the semiconductor layer 40. At this time, the front channel of the semiconductor layer 40 directly overlaps with the second electrode 50, and the front channel of the semiconductor layer 40 is located between the first electrode layer 20 and the back channel of the semiconductor layer 40. The back channel of the semiconductor layer 40 does not directly overlap with the second electrode 50, and the back channel of the semiconductor layer 40 is located on the side of the front channel of the semiconductor layer 40 away from the first electrode layer 20. When a threshold voltage is applied to the first electrode layer 20, a conductive channel is formed in the front channel of the semiconductor layer 40, and the two second electrodes 50 are conducted through the conductive channel. Compared with Figure 3In the TFT device with the conventional bottom-gate structure shown, the gate, semiconductor layer 40, and source and drain are stacked, and the design where the back channel of the semiconductor layer 40 is located between the front channel of the semiconductor layer 40 and the gate. In the TFT device with the bottom-gate structure of the present application, the source and drain are directly overlapped with the front channel of the semiconductor layer 40, and the back channel of the semiconductor layer 40 is located on the side of the front channel of the semiconductor layer 40 away from the gate. When the TFT device with the bottom-gate structure of the present application is turned on, a conductive channel can be formed across the resistance of the back channel. The TFT device of the present application, compared with the TFT device with the conventional bottom-gate structure as shown in Figure 3 has an increased on-state current and reduces the influence of the thickness of the semiconductor layer 40 on the on-state current of the TFT device.

[0050] The first electrode layer 20 is the gate, one of the two second electrodes 50 is the source, and the other of the two second electrodes 50 is the drain.

[0051] Referring to Figure 3 , in the TFT device with the conventional bottom-gate structure, the gate, gate insulating layer 30, semiconductor layer 40, source, and drain are stacked, and the back channel of the semiconductor layer is located between the gate and the front channel of the semiconductor layer. When a threshold voltage is applied to the gate, due to the existence of a certain thickness of the back channel, the resistance generated by the thickness of the back channel cannot be overcome, resulting in a relatively large resistance of the conductive channel and a decrease in the on-state current in the TFT device.

[0052] Referring to Figure 1 and Figure 2 , in the TFT device with the bottom-gate structure of the present application, the source and drain are directly overlapped only with a part of the semiconductor layer 40. At this time, the part of the semiconductor layer 40 directly overlapped with the source and drain is the front channel, and the part of the semiconductor layer 40 not in contact with the source and drain is the back channel. At this time, the front channel is located between the gate and the back channel. When a threshold voltage is applied to the gate, since the back channel is located on the side of the front channel away from the gate, the resistance generated by the thickness of the back channel can be overcome, and the resistance of the conductive channel is relatively small, resulting in an increase in the on-state current in the TFT device.

[0053] In the present application, when the substrate 10 is a flexible substrate 10, the material of the substrate 10 is polyimide. When the substrate 10 is a rigid substrate 10, the material of the substrate 10 is glass.

[0054] In the present application, the thickness of the side channel portion 41 is the distance from one surface of the side channel portion 41 away from the side wall of the first groove to one surface of the side channel portion 41 close to the side wall of the first groove. The thickness of the bottom channel portion 42 is the distance from one surface of the bottom channel portion 42 away from the bottom wall of the first groove to one surface of the bottom channel portion 42 close to the bottom wall of the first groove. The upper surface of the side channel portion 41 is one surface of the side channel portion 41 away from the substrate 10. A part of the second electrode 50 is disposed on the upper surface of the gate insulating layer 30, and another part of the second electrode 50 is disposed on a part of the upper surface of the side channel portion 41. The portion of the semiconductor layer 40 directly overlapping with the second electrode 50 is the front channel of the semiconductor layer 40, and the portion of the semiconductor layer 40 not directly overlapping with the second electrode 50 is the back channel of the semiconductor layer 40.

[0055] Since the back channel of the semiconductor layer 40 does not directly overlap with the second electrode 50, the off-state current of the TFT device is reduced, the ratio of the on-state current to the off-state current is increased, and thus the control ability of the first electrode layer 20 as a gate is improved.

[0056] The orthographic projection of the semiconductor layer 40 on the substrate 10 is within the orthographic projection of the first electrode layer 20 on the substrate 10, improving the control ability of the gate over the channel.

[0057] In the present application, the front channel of the side channel portion 41 is overlapped between the second electrode 50 and the first electrode layer 20, and the back channel of the side channel portion 41 is not overlapped between the second electrode 50 and the first electrode layer 20.

[0058] Refer to Figure 1 and Figure 2 In an embodiment of the present application, the upper surface of the side channel portion 41 is flush with the upper surface of the gate insulating layer 30.

[0059] When the upper surface of the side channel portion 41 is flush with the upper surface of the gate insulating layer 30, the bottom of the second electrode 50 abuts against the gate insulating layer 30 and overlaps with a part of the upper surface of the side channel portion 41, improving the flatness of the upper surface of the second electrode 50, and thus improving the flatness of the film layer above the second electrode 50.

[0060] In a cross-section of the array substrate 100 perpendicular to the substrate 10, the shape of the first groove is one of a trapezoid, a rectangle, a semi-circle, and a semi-ellipse. When the shape of the first groove is a trapezoid, the lower bottom side of the trapezoid is the bottom wall of the first groove, and the waist of the trapezoid is the side wall of the first groove.

[0061] In an embodiment of the present application, the side channel portion 41 and the bottom channel portion 42 enclose a second groove, and the orthographic projection of the second groove on the substrate 10 does not overlap with the orthographic projection of the second electrode 50 on the substrate 10;

[0062] The orthographic projection of the first groove on the substrate 10 partially overlaps with the orthographic projection of the second electrode 50 on the substrate 10.

[0063] One surface of the side channel portion 41 away from the gate insulating layer 30 serves as the side wall of the second groove, and one surface of the bottom channel portion 42 away from the gate insulating layer 30 serves as the bottom wall of the second groove. The orthographic projection of the second groove on the substrate 10 is within the range of the orthographic projection of the first groove on the substrate 10.

[0064] The semiconductor layer 40 is disposed in the first groove. The upper surface of the side channel portion 41 is flush with the upper surface of the gate insulating layer 30. A part of the second electrode 50 is disposed on the upper surface of the gate insulating layer 30, and another part of the second electrode 50 is disposed on the upper surface of the side channel portion 41. At this time, a part of the orthographic projection of the second electrode 50 on the substrate 10 does not overlap with the orthographic projection of the first groove on the substrate 10, and another part of the orthographic projection of the second electrode 50 on the substrate 10 overlaps with the orthographic projection of the first groove on the substrate 10.

[0065] The second electrode 50 only overlaps with a part of the upper surface of the side channel portion 41, and another part of the upper surface of the side channel portion 41 does not overlap with the second electrode 50. Among them, the other part of the upper surface of the side channel portion 41 that does not overlap with the second electrode 50 is located on the side away from the upper surface of the gate insulating layer 30 of the part of the upper surface of the side channel portion 41 that overlaps with the second electrode 50. At this time, the orthographic projection of the second groove on the substrate 10 does not overlap with the orthographic projection of the second electrode 50 on the substrate 10.

[0066] Refer to Figure 1 and Figure 2 , in an embodiment of the present application, the array substrate 100 further includes a protective layer 70, and the protective layer 70 covers the gate insulating layer 30, the second electrode layer, and the semiconductor layer 40;

[0067] Among them, a part of the second electrode 50 and a part of the protective layer 70 are disposed on the upper surface of the side channel portion 41, and another part of the protective layer 70 is disposed on one surface of the side channel portion 41 facing away from the side wall of the first groove.

[0068] The material of the protective layer 70 is one of silicon nitride, silicon oxide, and silicon dioxide, and is used to block the intrusion of external water and oxygen into the array substrate 100.

[0069] The bottom of the second electrode 50 overlaps with the front channel of the side channel portion 41, and the protective layer 70 covers the back channel of the side channel portion 41. The protective layer 70 is used to prevent water and oxygen from invading the semiconductor layer 40 through the back channel of the side channel portion 41, and improve the stability of the thin film transistor structure.

[0070] The thickness of the protective layer 70 ranges from 0.05 μm to 1 μm, and the value of the thickness of the protective layer 70 is one of the values 0.05 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, 1 μm.

[0071] Referring Figure 1 and Figure 2 , in an embodiment of the present application, the side channel portion 41 includes:

[0072] A first front channel portion 411, disposed on the side wall of the first groove, the upper surface of the first front channel portion 411 is flush with the gate insulating layer 30, and is overlapped with the bottom of the second electrode 50; and

[0073] A first back channel portion 412, disposed on a surface of the first front channel portion 411 away from the side wall of the first groove;

[0074] Wherein, the protective layer 70 covers the first back channel portion 412, and the orthographic projection of the first back channel portion 412 on the substrate 10 does not overlap with the orthographic projection of the second electrode 50 on the substrate 10.

[0075] The side channel portion 41 includes a first front channel portion 411 and a first back channel portion 412. The first front channel portion 411 and the second back channel portion 422 are sequentially stacked on the side wall of the first groove. The upper surface of the first front channel portion 411 is flush with the gate insulating layer 30, and the side channel portion 41 is located between the bottom wall of the first groove and the upper surface of the gate insulating layer 30.

[0076] The first back channel portion 412 does not overlap with the second electrode 50, and the orthographic projection of the first back channel portion 412 on the substrate 10 does not overlap with the orthographic projection of the second electrode 50 on the substrate 10.

[0077] The bottom channel portion 42 includes:

[0078] A second front channel portion 421, disposed on the bottom wall of the first groove, wherein the first front channel portion 411 is located on the periphery of the second front channel portion 421, and the first front channel portion 411 is connected to the second front channel portion 421;

[0079] A second back channel portion 422, disposed on the second front channel portion 421, wherein the first back channel portion 412 is located on the periphery of the second back channel portion 422, and the first back channel portion 412 is connected to the second back channel portion 422;

[0080] Among them, the first front channel portion 411 and the second front channel portion 421 form the front channel of the semiconductor layer 40, and the first back channel portion 412 and the second back channel portion 422 form the back channel of the semiconductor layer 40.

[0081] In a cross-section perpendicular to the direction of the substrate 10, the first electrode layer 20, the gate insulating layer 30, and the front channel of the semiconductor layer 40 are sequentially stacked. The back channel of the semiconductor layer 40 is located on the side of the front channel of the semiconductor layer 40 away from the first electrode layer 20. At this time, when the TFT device of the present application is turned on, the front channels of the semiconductor layer 40 that are in direct contact with the two second electrodes 50 respectively form a conductive channel, and the two second electrodes 50 are turned on through the conductive channel, which can bypass the back channel of the semiconductor layer 40, reduce the resistance influence caused by the thickness of the back channel of the semiconductor layer 40, and improve the on-state current of the TFT device.

[0082] In an embodiment, the materials of the first front channel portion 411, the first back channel portion 412, the second front channel portion 421, and the second back channel portion 422 are the same, and the first front channel portion 411, the first back channel portion 412, the second front channel portion 421, and the second back channel portion 422 are integrally formed. In this embodiment, the material of the semiconductor layer 40 is amorphous silicon (a-Si).

[0083] In another embodiment, the materials of the first front channel portion 411 and the second front channel portion 421 are the same, and the first front channel portion 411 and the second front channel portion 421 are integrally formed. The materials of the first back channel portion 412 and the second back channel portion 422 are the same, and the first back channel portion 412 and the second back channel portion 422 are integrally formed. In this embodiment, the materials of the first front channel portion 411 and the first back channel portion 412 are different. Among them, the electron mobility of the first front channel portion 411 is greater than that of the first back channel portion 412. Further, the hole mobility of the first back channel portion 412 is greater than that of the first front channel portion 411. In this embodiment, the electron mobility of the front channel of the semiconductor layer 40 is greater than that of the back channel of the semiconductor layer 40. Preferably, the hole mobility of the back channel of the semiconductor layer 40 is greater than that of the front channel of the semiconductor layer 40.

[0084] In this embodiment, the thickness of the semiconductor layer 40 is in the range of 60 nm to 160 nm, where the value of the thickness of the semiconductor layer 40 is one of the values of 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, and 160 nm.

[0085] In a cross-section perpendicular to the direction of the substrate 10, the length of a part of the second electrode 50 extending above the first groove is 20 nm to 50 nm. Among them, a part of the second electrode 50 extending above the first groove overlaps with the first pre-channel portion 411 in the semiconductor layer 40. Therefore, in this embodiment, the length of a part of the second electrode 50 extending above the first groove is equal to the thickness of the first pre-channel portion 411.

[0086] The thickness of the first pre-channel portion 411 is in the range of 20 nm to 50 nm. Among them, the value of the thickness of the first pre-channel portion 411 is one of the values of 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm.

[0087] Correspondingly, the thickness of the first back-channel portion 412 is in the range of 10 nm to 140 nm. The thickness of the first back-channel portion 412 is one of the values of 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm.

[0088] Correspondingly, the ratio of the thickness of the first pre-channel portion 411 to the thickness of the semiconductor layer 40 is in the range of 0.125 to 0.833, and the ratio of the thickness of the first back-channel portion 412 to the thickness of the semiconductor layer 40 is in the range of 0.167 to 0.875. The ratio of the thickness of the first pre-channel portion 411 to the thickness of the first back-channel portion 412 is in the range of 0.143 to 5.

[0089] In this embodiment, the thickness of the side-channel portion 41 is equal to the thickness of the bottom-channel portion 42, and the thickness of the first pre-channel portion 411 is equal to the thickness of the second pre-channel portion 421, and the thickness of the first back-channel portion 412 is equal to the thickness of the second back-channel portion 422. Among them, the equal thickness mentioned above means that the thicknesses of the two are basically equal. Due to the limited precision of the process, it is impossible to make the thicknesses of the two absolutely equal. Therefore, in this embodiment, the ratio of the thickness of the side-channel portion 41 to the thickness of the bottom-channel portion 42 is in the range of 0.95 to 1.05.

[0090] Refer to Figure 1 and Figure 2 , in an embodiment of the present application, the array substrate 100 further includes two spacer blocks 60, which are spaced apart and arranged on the substrate 10;

[0091] Among them, the first electrode layer 20 covers the spacer 60. The first part of the first electrode layer 20 located between the two spacers 60 corresponds to the bottom channel part 42, and the second part of the first electrode layer 20 covering the side of the spacer 60 corresponds to the side channel part 41.

[0092] The first part and the second part enclose a third groove, and the part of the gate insulating layer 30 covering the third groove forms the first groove.

[0093] Since the semiconductor layer 40 is disposed in the first groove, when the first electrode layer 20 is disposed on the substrate 10, the distance from the first electrode layer 20 to the side channel part 41 is greater than the distance from the first electrode layer 20 to the bottom channel part 42, resulting in a carrier mobility of the side channel part 41 being less than that of the bottom channel part 42. When the semiconductor layer 40 is turned on, the on-state current of the conductive channel becomes smaller.

[0094] In this embodiment, two spacers 60 are disposed on the substrate 10. The material of the spacer 60 is a metal material or a non-metal material. The spacer 60 is used to raise the part of the first electrode layer 20 located below the second electrode 50, so that the shortest distance from the side channel part 41 to the first electrode layer 20 is equal to the shortest distance from the bottom channel part 42 to the first electrode layer 20. The above equal distance is basically equal, where the ratio of the shortest distance from the side channel part 41 to the first electrode layer 20 to the shortest distance from the bottom channel part 42 to the first electrode layer 20 is in the range of 0.95 to 1.05.

[0095] When the material of the spacer 60 is metal, the first manufacturing method of the array substrate 100 includes the following steps:

[0096] Step 101: Form two spaced metal spacers 60 on the substrate 10;

[0097] Step 102: Form a first electrode layer 20 on the substrate 10. Among them, the first electrode layer 20 covers the two spacers 60, and the second part of the first electrode layer 20 covering the two spacers 60 and the first part of the first electrode layer 20 covering the substrate 10 enclose a third groove;

[0098] Step 103: Form a gate insulating layer 30 on the first electrode layer 20. Among them, the part of the gate insulating layer 30 covering the third groove forms the first groove;

[0099] Step 104: Form a semiconductor layer 40 on the inner wall of the first groove. Among them, the semiconductor layer 40 includes a side channel part 41 and a bottom channel part 42. The bottom channel part 42 is disposed on the bottom wall of the first groove, and the side channel part 41 is disposed on the side wall of the first groove;

[0100] Step 105: Form two second electrodes 50 which are arranged at intervals on the upper surface of the gate insulating layer 30. Among them, a part of the upper surface of the side channel portion 41 is directly lapped with the second electrode 50, and another part of the upper surface of the side channel portion 41 is not in contact with the second electrode 50. The part of the side channel portion 41 that is directly lapped with the second electrode 50 is the first front channel portion 411, and the part of the side channel portion 41 that is not in contact with the second electrode 50 is the first back channel portion 412;

[0101] Step 106: Form a protective layer 70 on the substrate 10, wherein the protective layer 70 covers the gate insulating layer 30, the second electrode 50 and the semiconductor layer 40.

[0102] The material of the semiconductor layer 40 is a photosensitive material, and the first electrode layer 20 is a metal material and the first electrode layer 20 is opaque. When the light emitted by the backlight structure of the display panel enters the array substrate 100 from below the substrate 10 without setting the cushion block, the light will be blocked by the first electrode layer 20. However, when the ambient light or the reflected light enters the array substrate 100 from the side, the first electrode layer 20 cannot block it, resulting in the light irradiating on the side channel portion 41 of the semiconductor layer 40. Since the material of the semiconductor layer 40 is a photosensitive material, after the semiconductor layer 40 is irradiated by light, a photocurrent will be generated in the semiconductor layer 40, causing an increase in the leakage current of the TFT.

[0103] In the present application, due to the provision of the cushion block 60, the cushion block 60 raises the second part of the first electrode layer 20 and blocks the side channel portion 41 of the semiconductor layer 40, and the first part of the first electrode layer 20 blocks the bottom channel portion 42 of the semiconductor layer 40, increasing the light-shielding area of the semiconductor layer 40, reducing the leakage current of the semiconductor layer 40, and improving the photosensitive characteristics of the TFT device.

[0104] Refer to Figure 1 and Figure 2 , in an embodiment of the present application, the gate insulating layer 30 includes:

[0105] A first insulating portion 31, arranged between the first part and the bottom channel portion 42;

[0106] A second insulating portion 32, arranged between the second part and the side channel portion 41. The second insulating portion 32 is connected to the first insulating portion 31, and the second insulating portion 32 and the first insulating portion 31 enclose the first groove; and

[0107] The third insulating portion 33 is disposed between the third part of the first electrode layer 20 covering the upper surface of the spacer 60 and the second electrode 50. The third insulating portion 33 is connected to the second insulating portion 32, and the upper surface of the third insulating portion 33 is flush with the upper surface of the side channel portion 41.

[0108] The thickness of the gate insulating layer 30 is in the range of 400 nm to 500 nm. Among them, the value of the thickness of the gate insulating layer 30 is one of the values of 400 nm, 410 nm, 420 nm, 430 nm, 440 nm, 450 nm, 460 nm, 470 nm, 480 nm, 490 nm, 500 nm.

[0109] The first insulating portion 31 is located between the first part of the first electrode layer 20 and the bottom channel portion 42. The first part of the first electrode layer 20 is used to control the opening or closing of the conductive channel of the second front channel portion 421.

[0110] The second insulating portion 32 is located between the second part of the first electrode layer 20 and the side channel portion 41. The second part of the second electrode layer is used to control the opening or closing of the conductive channel of the first front channel portion 411.

[0111] The third insulating portion 33 is located between the spacer 60 and the second electrode 50, and is used to set and raise the second electrode 50.

[0112] Among them, the upper surface of the gate insulating layer 30 mentioned above is the upper surface of the third insulating portion 33.

[0113] In this embodiment, the angle between the second insulating portion 32 and the plane of the substrate 10 is in the range of 35° to 90°. Among them, the value of the angle between the second insulating portion 32 and the plane of the substrate 10 is one of the values of 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°.

[0114] In the cross-section of the array substrate 100 perpendicular to the substrate 10, the shape of the third groove is one of a trapezoid, a rectangle, a semi-circle, and a semi-ellipse. When the shape of the third groove is a trapezoid, the bottom of the trapezoid is the first part of the first electrode layer 20, and the waist of the trapezoid is the second part of the first electrode layer 20.

[0115] Refer to Figure 1 and Figure 2 , in an embodiment of the present application, the first electrode layer 20 includes:

[0116] Two first gate portions 21, which are spaced apart from each other on the substrate 10; and

[0117] The second gate part 22 is disposed between the two first gate parts 21 and connects the two first gate parts 21, and the thickness of the second gate part 22 is less than the thickness of the first gate part 21;

[0118] Wherein, the upper surface of the second gate part 22 and the side surfaces of the two first gate parts 21 form a third groove, and the part of the gate insulating layer 30 covering the inner wall of the third groove forms the first groove.

[0119] In another embodiment, the second gate part 22 and the two first gate parts 21 can be directly formed on the substrate 10 through a halftone mask, or the two first gate parts 21 can be fabricated first, and then the second gate part 22 connecting the two first gate parts 21 is fabricated.

[0120] The materials of the two first gate parts 21 and the second gate part 22 are metal materials.

[0121] The thickness of the first gate part 21 is greater than the thickness of the second gate part 22. Wherein, the absolute value of the difference between the thickness of the first gate part 21 and the thickness of the second gate part 22 is in the range of 0.1 μm to 1 μm. Wherein, the absolute value of the difference between the thickness of the first gate part 21 and the thickness of the second gate part 22 takes a value of one of 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm.

[0122] The first gate part 21 is used to block the light incident on the side channel part 41 from the side, and the second gate part 22 is used to block the light incident on the bottom channel part 42 from below the substrate 10. The design of the first gate part 21 and the second gate part 22 increases the light-shielding area of the semiconductor layer 40, reduces the leakage current of the semiconductor layer 40, and improves the photosensitive characteristics of the TFT device.

[0123] In the present application, the second manufacturing method of the array substrate 100 includes the following steps:

[0124] Step 201: Form a first electrode layer 20 on the substrate 10, and pattern the first electrode layer 20 through a halftone mask to form two first gate parts 21 and a second gate part 22 connecting the two first gate parts 21. Wherein, the thickness of the first gate part 21 is greater than the thickness of the second gate part 22, and the two first gate parts 21 and the second gate part 22 form a third groove;

[0125] Step 202: Form a gate insulating layer 30 on the first electrode layer 20. Wherein, the part of the gate insulating layer 30 covering the third groove forms the first groove;

[0126] Step 203: A semiconductor layer 40 is formed on the inner wall of the first groove. The semiconductor layer 40 includes a side channel portion 41 and a bottom channel portion 42. The bottom channel portion 42 is disposed on the bottom wall of the first groove, and the side channel portion 41 is disposed on the side wall of the first groove.

[0127] Step 204: Two second electrodes 50 are formed at intervals on the upper surface of the gate insulating layer 30. A part of the upper surface of the side channel portion 41 is directly overlapped with the second electrode 50, and another part of the upper surface of the side channel portion 41 is not in contact with the second electrode 50. The part of the side channel portion 41 directly overlapped with the second electrode 50 is the first front channel portion 411, and the part of the side channel portion 41 not in contact with the second electrode 50 is the first back channel portion 412.

[0128] Step 205: A protective layer 70 is formed on the substrate 10. The protective layer 70 covers the gate insulating layer 30, the second electrode 50, and the semiconductor layer 40.

[0129] Fabricating the array substrate 100 by the second method can reduce one photomask, lower the production cost, and improve the production efficiency.

[0130] In this application, a third method for fabricating the array substrate 100 includes the following steps:

[0131] Step 301: A first electrode layer 20 is formed on the substrate 10, and the first electrode layer 20 is patterned to form two first gate portions 21 disposed at intervals.

[0132] Step 302: A second gate portion 22 is formed on the substrate 10. The second gate portion 22 is located between the two first gate portions 21 and connects the two first gate portions 21. The thickness of the second gate portion 22 is less than that of the first gate portion 21, and the second gate portion 22 and the first gate portion 21 form a third groove.

[0133] Step 303: A gate insulating layer 30 is formed on the first electrode layer 20. The part of the gate insulating layer 30 covering the third groove forms a first groove.

[0134] Step 304: A semiconductor layer 40 is formed on the inner wall of the first groove. The semiconductor layer 40 includes a side channel portion 41 and a bottom channel portion 42. The bottom channel portion 42 is disposed on the bottom wall of the first groove, and the side channel portion 41 is disposed on the side wall of the first groove.

[0135] Step 305: Form two second electrodes 50 which are arranged at intervals on the upper surface of the gate insulating layer 30. A part of the upper surface of the side channel portion 41 is directly overlapped with the second electrode 50, and another part of the upper surface of the side channel portion 41 is not in contact with the second electrode 50. The part of the side channel portion 41 directly overlapped with the second electrode 50 is the first front channel portion 411, and the part of the side channel portion 41 not in contact with the second electrode 50 is the first back channel portion 412;

[0136] Step 306: Form a protective layer 70 on the substrate 10, wherein the protective layer 70 covers the gate insulating layer 30, the second electrode 50, and the semiconductor layer 40.

[0137] Referring to Figure 1 and Figure 2 , in an embodiment of the present application, the gate insulating layer 30 includes:

[0138] A first insulating portion 31 is disposed between the second gate portion 22 and the bottom channel portion 42;

[0139] A second insulating portion 32 is disposed between the first gate portion 21 and the side channel portion 41. The second insulating portion 32 is connected to the first insulating portion 31, and the second insulating portion 32 and the first insulating portion 31 enclose the first groove; and

[0140] A third insulating portion 33 is disposed between the first gate portion 21 and the second electrode 50. The third insulating portion 33 is connected to the second insulating portion 32, and the upper surface of the third insulating portion 33 is flush with the upper surface of the side channel portion 41.

[0141] The first insulating portion 31 is located between the second gate portion 22 and the bottom channel portion 42, and the second gate portion 22 is used to control the opening or closing of the conductive channel of the second front channel portion 421.

[0142] The second insulating portion 32 is located between the first gate portion 21 and the side channel portion 41, and the first gate portion 21 is used to control the opening or closing of the conductive channel of the first front channel portion 411.

[0143] The third insulating portion 33 is located between the spacer 60 and the second electrode 50 and is used to set and raise the second electrode 50.

[0144] Wherein, the upper surface of the gate insulating layer 30 mentioned above is the upper surface of the third insulating portion 33.

[0145] The specific embodiments of the present application have been described in detail above. The above-described embodiments disclosed in the present application are only the preferred embodiments of the present application. For those of ordinary skill in the art, many variations and improvements can be made without departing from the concept of the present application. These variations and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. An array substrate, characterized in that, Comprising: A substrate; A first electrode layer disposed on the substrate; A gate insulating layer disposed on the first electrode layer, and a first groove is provided on the upper surface of the gate insulating layer; A semiconductor layer disposed in the first groove, the semiconductor layer includes a bottom channel portion and a side channel portion, the bottom channel portion covers the bottom wall of the first groove, the side channel portion covers the side wall of the first groove, and the side channel portion is disposed on the periphery of the bottom channel portion; And A second electrode layer including two second electrodes disposed at intervals, the second electrodes are disposed on the upper surface of the gate insulating layer, and the bottom of the second electrodes overlaps with a part of the upper surface of the side channel portion.

2. The array substrate according to claim 1, wherein The upper surface of the side channel portion is flush with the upper surface of the gate insulating layer.

3. The array substrate according to claim 2, wherein The side channel portion and the bottom channel portion enclose a second groove, and the orthographic projection of the second groove on the substrate does not overlap with the orthographic projection of the second electrode on the substrate; The orthographic projection of the first groove on the substrate partially overlaps with the orthographic projection of the second electrode on the substrate.

4. The array substrate according to claim 3, wherein The array substrate further includes a protective layer, and the protective layer covers the gate insulating layer, the second electrode layer and the semiconductor layer; Wherein, a part of the second electrode and a part of the protective layer are disposed on the upper surface of the side channel portion, and another part of the protective layer is disposed on a surface of the side channel portion facing away from the side wall of the first groove.

5. The array substrate according to claim 4, wherein The side channel portion includes: A first front channel portion disposed on the side wall of the first groove, the upper surface of the first front channel portion is flush with the gate insulating layer and overlaps with the bottom of the second electrode; and A first back channel portion disposed on a surface of the first front channel portion away from the side wall of the first groove; Wherein, the protective layer covers the first back channel portion, and the orthographic projection of the first back channel portion on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.

6. The array substrate according to claim 1, wherein The array substrate further includes two pads disposed at intervals on the substrate; Wherein, the first electrode layer covers the pads, a first part of the first electrode layer between the two pads corresponds to the bottom channel portion, and a second part of the first electrode layer covering the side surfaces of the pads corresponds to the side channel portion; The first part and the second part enclose a third groove, and a part of the gate insulating layer covering the third groove forms the first groove.

7. The array substrate according to claim 6, wherein The gate insulating layer includes: A first insulating portion disposed between the first part and the bottom channel portion; A second insulating portion disposed between the second part and the side channel portion, the second insulating portion is connected to the first insulating portion, and the second insulating portion and the first insulating portion enclose the first groove; and A third insulating portion disposed between a third part of the first electrode layer covering the upper surface of the pad and the second electrode, the third insulating portion is connected to the second insulating portion, and the upper surface of the third insulating portion is flush with the upper surface of the side channel portion.

8. The array substrate according to claim 1, characterized in that, The first electrode layer includes: Two first gate portions, and the two first gate portions are disposed at intervals on the substrate; and The second gate part is disposed between the two first gate parts and connects the two first gate parts, and the thickness of the second gate part is smaller than that of the first gate part; Wherein, a third groove is formed between the upper surface of the second gate part and the side surfaces of the two first gate parts, and a part of the gate insulating layer covering the inner wall of the third groove forms the first groove.

9. The array substrate according to claim 8, wherein The gate insulating layer includes: A first insulating part disposed between the second gate part and the bottom channel part; A second insulating part disposed between the first gate part and the side channel part, the second insulating part is connected to the first insulating part, and the second insulating part and the first insulating part enclose to form the first groove; and A third insulating part disposed between the first gate part and the second electrode, the third insulating part is connected to the second insulating part, and the upper surface of the third insulating part is flush with the upper surface of the side channel part.

10. A display panel, characterized in that, An array substrate includes any one of claims 1-9.

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