Preparation method of semiconductor power device

Abstract

The invention discloses a preparation method of a semiconductor power device, and belongs to the technical field of semiconductors. Comprising the steps that an epitaxial layer and a barrier layer are sequentially arranged on a substrate layer, a groove is formed through photoetching, and a heavily-doped polycrystalline silicon layer is deposited in the groove through thermal oxidation; performing wet etching on the side wall of the groove, and performing thermal oxidation to form a gate oxide layer; the method comprises the following steps of: depositing a heavily doped polycrystalline silicon layer in a groove; performing ion implantation on the epitaxial layer in sequence; an insulating medium layer is formed above the grid polycrystalline silicon and the first isolation layer, a plurality of contact holes are etched inwards, and the distance between each contact hole and the corresponding groove is linearly increased; injecting ions into the bottom of the contact hole, and filling a metal filling layer; arranging a back drain metal layer on the back of the substrate layer; and mirroring and repeating. The manufacturing method has the beneficial effects that the basic unit cells are mirrored and repeated, so that the distance between the grooves and the contact holes is linearly increased, the heating uniformity of the device is improved, the heat dissipation capability is improved, and the safe working area of the device is widened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor power device. Background Art

[0002] Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a commonly used switching power device, which has the significant advantage of high switching frequency and plays a key role in many circuit applications. In the normal working state, due to the device impedance existing in itself, the power MOSFET will generate a certain power consumption. And with the continuous reduction of the process technology, the cell density is continuously increasing and the switching frequency is further improved, its application in the circuit is becoming more and more extensive.

[0003] In the prior art, due to the power consumption problem of the power MOSFET itself, especially as the switching frequency increases, the proportion of the switching loss in the total loss is continuously increasing. At the same time, due to process and frequency changes, it is easy to cause overcurrent or overvoltage phenomena in the device circuit, resulting in a sharp rise in the chip junction temperature, and ultimately leading to device failure. In addition, in terms of the safe operation of the device, its Safe Operating Area (SOA) has limitations, and it is difficult to ensure stable operation within the maximum junction temperature limit in a wider voltage-current range, which seriously affects the performance and reliability of the power MOSFET. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a semiconductor power device to solve the above technical problems;

[0005] A method for manufacturing a semiconductor power device includes:

[0006] Step S1: After sequentially disposing an epitaxial layer and a barrier layer on a substrate layer, a trench is formed by photolithography, and a basic structure is obtained by thermally oxidizing and depositing a heavily doped polysilicon layer inside the trench;

[0007] Step S2: After wet etching the sidewall of the trench, a gate oxide layer is formed by thermal oxidation;

[0008] Step S3: A gate polysilicon is formed by depositing and heavily doping the polysilicon layer inside the trench;

[0009] Step S4: Ion implantation is sequentially performed on the epitaxial layer to form a P-body region and an N+ source region;

[0010] Step S5: Form an insulating dielectric layer above the gate polysilicon and the first isolation layer, and etch multiple contact holes inwardly through photolithography. The distance between a single contact hole and the corresponding trench increases linearly.

[0011] Step S6: Inject ions at the bottom of the contact holes to form a contact hole injection layer, and form a front source metal layer after filling a metal filling layer.

[0012] Step S7: Set a back drain metal layer on the back of the substrate layer to obtain a basic unit cell.

[0013] Step S8: Mirror and repeat the basic unit cell to form a semiconductor power device.

[0014] Preferably, step S1 includes

[0015] Step S11: Set the epitaxial layer above the substrate layer.

[0016] Step S12: Set the barrier layer above the epitaxial layer.

[0017] Step S13: Form the trenches on the epitaxial layer and the barrier layer through photolithography.

[0018] Step S14: Form a first isolation layer through thermal oxidation inside the trenches and on the barrier layer.

[0019] Step S15: Form source polysilicon by depositing and heavily doping the polysilicon layer inside the trenches.

[0020] Step S16: Form a second isolation layer through thermal oxidation on the source polysilicon to obtain the basic structure.

[0021] Preferably, step S4 includes

[0022] Step S41: Inject P-type doping elements through ion implantation on the epitaxial layer to form the P-body region.

[0023] Step S42: Inject N-type doping elements through ion implantation on the upper part of the P-body region to form the N+ source region.

[0024] Preferably, step S5 includes

[0025] Step S51: Form an insulating dielectric layer by depositing a layer of borophosphosilicate glass above the gate polysilicon and the first isolation layer.

[0026] In step S52, after removing the insulating dielectric layer and the first isolation layer by dry etching, through the N+ source region, contact holes are formed in the P- body region, and the distance between a single contact hole and the corresponding trench increases linearly in a first direction.

[0027] Preferably, step S6 includes

[0028] Step S61, setting a P- well region at the bottom of the contact hole by ion- implanting the P- type doping element, and the P- well region is heavily doped with P- type;

[0029] Step S62, activating the P- type doping element by well- pushing to form the contact hole implantation layer;

[0030] Step S63, after filling the metal filling layer in the contact hole, depositing a first metal layer on the metal filling layer and the insulating dielectric layer by metal sputtering process, and then forming the front- side source metal layer by photolithography.

[0031] Preferably, step S7 includes

[0032] Thinning the back side of the substrate layer to a set thickness by a back- side thinning process, and then evaporating a second metal layer on the back side to form the back- side drain metal layer.

[0033] Preferably, the gate polysilicon in step S3 is flush with the first isolation layer in step S5 in the horizontal direction.

[0034] Preferably, the material of the contact hole implantation layer in step S6 is titanium or titanium nitride.

[0035] Preferably, the material of the first metal layer in step S63 is aluminum or copper.

[0036] Preferably, the material of the second metal layer is titanium or nickel or silver.

[0037] The beneficial effects of the present invention are: by mirroring and repeating the basic unit cell, a layout with a linearly increasing distance between the trench and the contact hole is constructed, improving the heat generation uniformity of the device, enhancing the heat dissipation capacity, and broadening the safe operating area of the power device. Description of the Drawings

[0038] Figure 1 is a step diagram of the preparation method of the semiconductor power device of the present invention;

[0039] Figure 2 is a schematic diagram of step S1 of the present invention;

[0040] Figure 3 is a schematic diagram of step S4 of the present invention;

[0041] Figure 4 It is a schematic diagram of step S5 of the present invention;

[0042] Figure 5 It is a schematic diagram of step S6 of the present invention;

[0043] Figure 6 It is a schematic diagram of the structure of the present invention after sequentially disposing an epitaxial layer and a barrier layer on a substrate layer;

[0044] Figure 7 It is a schematic diagram of the structure of the trench of the present invention;

[0045] Figure 8 It is a schematic diagram of the structure of the first isolation layer of the present invention;

[0046] Figure 9 It is a schematic diagram of the structure of the source polysilicon of the present invention;

[0047] Figure 10 It is a schematic diagram of the structure in which the source polysilicon of the present invention is filled in the trench;

[0048] Figure 11 It is a schematic diagram of the structure of the second isolation layer of the present invention;

[0049] Figure 12 It is a schematic diagram of the structure of the gate oxide layer of the present invention;

[0050] Figure 13 It is a schematic diagram of the structure of the gate polysilicon of the present invention;

[0051] Figure 14 It is a schematic diagram of the gate polysilicon and the first isolation layer being flush in the horizontal direction in the present invention;

[0052] Figure 15 It is a schematic diagram of the structure of the P - body region of the present invention;

[0053] Figure 16 It is a schematic diagram of the structure of the N+ source region of the present invention;

[0054] Figure 17 It is a schematic diagram of the structure of the insulating dielectric layer of the present invention;

[0055] Figure 18 It is a schematic diagram of the structure of the contact hole of the present invention;

[0056] Figure 19 It is a schematic diagram that the distance between a single contact hole and the corresponding trench increases linearly in a first direction in the present invention;

[0057] Figure 20 It is a schematic diagram of the structure of the contact hole injection layer of the present invention;

[0058] Figure 21It is a schematic structural diagram of the front source metal layer of the present invention;

[0059] Figure 22 It is a schematic structural diagram of the back drain metal layer of the present invention;

[0060] Figure 23 It is a schematic diagram of mirroring the basic unit cell of the present invention;

[0061] Figure 24 It is a schematic diagram of mirroring and symmetry of the basic unit cell of the present invention;

[0062] Figure 25 It is a schematic diagram showing that the threshold voltage, transconductance, and drain current of the present invention are wavy.

[0063] In the drawings: 1, substrate layer; 2, epitaxial layer; 3, barrier layer; 4, trench; 5, first isolation layer; 6, source polysilicon; 7, second isolation layer; 8, gate oxide layer; 9, gate polysilicon; 10, P-body region; 11, N+ source region; 12, insulating dielectric layer; 13, contact hole; 14, contact hole implantation layer; 15, metal filling layer; 16, front source metal layer; 17, back drain metal layer. Detailed implementation manners

[0064] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0065] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0066] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but it is not a limitation of the present invention.

[0067] A preparation method of a semiconductor power device, as Figure 1 、 Figures 6 to 22 shown, includes,

[0068] Step S1, after sequentially disposing an epitaxial layer 2 and a barrier layer 3 on a substrate layer 1, a trench 4 is formed by photolithography, and a basic structure is obtained by thermal oxidation and deposition of a heavily doped polysilicon layer inside the trench 4;

[0069] Step S2, after wet etching the sidewalls of the trench 4, a gate oxide layer 8 is formed by thermal oxidation;

[0070] Step S3: Deposit a heavily doped polysilicon layer inside the trench 4 to form the gate polysilicon 9;

[0071] Step S4: Perform ion implantation on the epitaxial layer 2 in sequence to form the P-body region 10 and the N+ source region 11;

[0072] Step S5: Form an insulating dielectric layer 12 above the gate polysilicon 9 and the first isolation layer 5, and etch multiple contact holes 13 inward through photolithography. The distance between a single contact hole 13 and the corresponding trench 4 increases linearly;

[0073] Step S6: Inject ions at the bottom of the contact hole 13 to form the contact hole injection layer 14, and form the front source metal layer 16 after filling the metal filling layer 15;

[0074] Step S7: Set the back drain metal layer 17 on the back of the substrate layer 1 to obtain the basic unit cell;

[0075] Step S8: Mirror and repeat the basic unit cell to form the semiconductor power device.

[0076] Specifically, the present invention provides a method for manufacturing a semiconductor power device. By performing mirroring and repeating operations on the basic unit cell, a layout with a linearly increasing distance between the trench 4 and the contact hole 13 is constructed, gradually reducing the influence of contact hole injection on body region injection, improving the device heating uniformity, enhancing the heat dissipation capacity, and broadening the safe operating area of the power device.

[0077] In a preferred embodiment, referring to Figure 2 、 Figures 6 to 11 , step S1 includes

[0078] Step S11: Set the epitaxial layer 2 above the substrate layer 1;

[0079] Step S12: Set the barrier layer 3 above the epitaxial layer 2;

[0080] Step S13: Form the trench 4 on the epitaxial layer 2 and the barrier layer 3 through photolithography;

[0081] Step S14: Form the first isolation layer 5 inside the trench 4 and on the barrier layer 3 through thermal oxidation;

[0082] Step S15: Deposit a heavily doped polysilicon layer inside the trench 4 to form the source polysilicon 6;

[0083] Step S16: Form the second isolation layer 7 on the source polysilicon 6 through thermal oxidation to obtain the basic structure.

[0084] Specifically, a substrate layer 1 and an epitaxial layer 2 are provided. The epitaxial layer 2 is disposed on the substrate layer 1. A silicon dioxide hard mask layer is deposited on the epitaxial layer 2 as a barrier layer 3 for trench etching, as Figure 6 shown.

[0085] Through photolithography (such as coating, exposure, and development) on the barrier layer 3, the position of the oxide mask plate area where the corresponding trench 4 needs to be etched is determined. Etching is performed on the epitaxial layer 2 and the barrier layer 3 to form the trench 4, as Figure 7 shown. By determining the position of the oxide mask plate area where the trench 4 needs to be etched through photolithography (such as coating, exposure, and development) on the barrier layer 3, the trench 4 can be accurately formed at the required position, improving the manufacturing precision of the structure and ensuring the consistency and repeatability of the device structure.

[0086] A first isolation layer 5 is thermally oxidized inside the trench 4. To prevent the bottom of the trench 4 from being easily broken down by the electric field, the first isolation layer 5 has a relatively thick thickness, as Figure 8 shown, thereby improving the reliability of the device under high voltage and avoiding device failure caused by electric field breakdown.

[0087] A heavily doped polysilicon layer is deposited inside the trench 4, and the polysilicon is etched by means of chemical mechanical polishing and dry etching back to form the source polysilicon 6, as Figure 9 、 Figure 10 shown. Heavy doping can improve the conductivity of the source, ensuring that the source can efficiently inject or collect carriers, providing a good path for current transmission, helping to reduce the resistance of the source, and improving the conductivity of the device;

[0088] An isolation oxide layer (second isolation layer 7) is thermally oxidized above the source polysilicon 6, as Figure 11 shown. The second isolation layer 7 is made of the same material as the first isolation layer 5, providing effective isolation protection for different regions, avoiding mutual interference between different conductive regions, reducing leakage, and improving the electrical performance and stability of the device.

[0089] Referring to Figure 12 , by wet etching the sidewall of the trench 4 of the first isolation layer 5, and since the second isolation layer 7 is made of the same material as the first isolation layer 5, part of the second isolation layer 7 is etched. Then, a high-quality gate oxide layer 8 is grown by thermal oxidation, which can improve the control effect of the gate on the channel, enable the electric field of the gate to more effectively modulate the carriers in the channel, and further optimize the switching characteristics and performance of the device.

[0090] A heavily doped polysilicon layer is deposited, and the polysilicon is etched by means of chemical mechanical polishing and dry etching back to the surface of the first isolation layer 5 to form the gate polysilicon 9, as Figure 13 、 Figure 14 shown.

[0091] The gate polysilicon 9 in step S3 is flush with the first isolation layer 5 in step S5 in the horizontal direction, which can optimize the gate's control ability over the channel.

[0092] When they are at the same level, the gate electric field distribution is more uniform, which can more effectively modulate the carrier concentration in the channel, enabling the device to have a faster response speed and lower switching loss during the switching process.

[0093] The flush structure helps reduce the electric field concentration phenomenon caused by the structural height difference, avoids the breakdown problem caused by excessive local electric field, improves the stability of the device when operating at high voltage and high current, and further improves the reliability and lifespan of the device.

[0094] The flush structure provides a flat surface for subsequent process steps, facilitating operations such as the deposition of insulating dielectric layers, photolithography, and ion implantation on this surface, reducing process errors and difficulties caused by surface unevenness, and improving the process repeatability and yield.

[0095] The flat structure enables the device to occupy less space on the plane, which is beneficial for improving the integration of semiconductor chips. More devices can be integrated on the same chip area, reducing costs and improving chip performance.

[0096] In a preferred embodiment, referring to Figure 3 、 Figure 15 、 Figure 16 , step S4 includes,

[0097] Step S41: P-type doping elements are implanted into the epitaxial layer 2 through ion implantation to form a P-body region 10;

[0098] Step S42: N-type doping elements are implanted into the upper part of the P-body region 10 through ion implantation to form an N+ source region 11.

[0099] Specifically, P-type doping elements (such as boron B) are ion-implanted on the surface of the epitaxial layer 2, and then the body imp (body region impurity) is pushed to the required junction depth (the junction depth must be above the bottom of the gate polysilicon 9) through the thermal push trap method to form the P-body region 10, as Figure 15 shown.

[0100] By ion-implanting N-type heavily doped elements (such as arsenic As), as Figure 16 shown, and then the SNimp (source N-type impurity) is pushed to the required junction depth through the thermal push trap method to form the N+ source region 11.

[0101] The P-body region 10 and the N+ source region 11 are formed by a specific ion implantation and thermal push trap process, which can precisely control the doping concentration and the junction depth, making the electrical performance of the device more stable. For example, the reasonable formation of the P-body region 10 and the N+ source region 11 helps to optimize the on and off characteristics of the device, reduce the leakage current, improve the switching speed and efficiency of the device, and reduce the power loss.

[0102] The layout of the trench 4 and the contact hole 13 with a linearly increasing distance and the corresponding manufacturing process can effectively improve the heat dissipation uniformity of the device. Because the power consumption distribution of the cells at different positions is more uniform during operation, reducing the local overheating situation, thus improving the heat dissipation capacity. The better heat dissipation effect enables the device to work stably at higher voltages and currents, broadens the safe operating area of the power device, and improves the reliability and application range of the device.

[0103] Lithography technology uses the chemical reaction of photoresist under light to define patterns, and can precisely form structures such as the trench 4 and the contact hole 13 on the semiconductor substrate.

[0104] Ion implantation technology can precisely control the type, dose and implantation depth of doping elements to meet the doping requirements of different regions.

[0105] The thermal oxidation process can grow high-quality oxide layers on the semiconductor surface, such as the gate oxide layer 8, the isolation layer, etc. These oxide layers have good insulation performance and stability.

[0106] The deposition process is used to form structures such as polysilicon layers and metal layers. After long-term development and application in semiconductor manufacturing, it has a mature equipment and process parameter control system. Their combination and connection have been optimized, and can realize an efficient manufacturing process on the premise of ensuring the device performance, reflecting good process compatibility.

[0107] In a preferred embodiment, referring to Figure 4 、 Figures 17 to 19 ,step S5 includes,

[0108] Step S51, an insulating dielectric layer 12 is formed by depositing a layer of borophosphosilicate glass above the gate polysilicon 9 and the first isolation layer 5;

[0109] Step S52, after removing the insulating dielectric layer 12 and the first isolation layer 5 by dry etching, passing through the N+ source region 11, a contact hole 13 is formed in the P-body region 10, and the distance between a single contact hole 13 and the corresponding trench 4 increases linearly in the first direction.

[0110] Specifically, a layer of BPSG (borophosphosilicate glass) is deposited as a device isolation layer to form the insulating dielectric layer 12, as Figure 12 shown;

[0111] Through the photolithography process, the CT (contact hole 13) area to be etched is defined using a Contact mask. The contact hole 13 sequentially passes through the insulating dielectric layer 12, the first isolation layer 5, and is connected to the P-body region 10 through the N+ source electrode. The distance from the contact hole 13 to the trench 4 increases linearly (d1 < d2 < d3 < dn) as Figure 19 shown. The surface insulating dielectric layer 12 and the first isolation layer 5 are removed by dry etching. After removing the photoresist, silicon is removed by dry etching process. Its depth must penetrate the N+ heavily doped source layer (N+ source region 11) and enter the P-body region 10 to form the contact hole 13, as Figure 18 shown.

[0112] Depositing borophosphosilicate glass (BPSG) to form the insulating dielectric layer 12 usually uses techniques such as chemical vapor deposition (CVD).

[0113] Under high temperature and gas atmosphere, gaseous source substances such as boron, phosphorus, and silicon undergo chemical reactions, decompose and deposit on the substrate surface to form a BPSG thin film.

[0114] BPSG has good insulation performance and filling characteristics, can effectively isolate different conductive layers and structures, prevent problems such as leakage and short circuit. At the same time, its chemical stability and thermal stability also help to ensure the reliability of the device under different working environments.

[0115] In a preferred embodiment, referring to Figure 5 、 Figures 20 to 22 , step S6 includes,

[0116] Step S61, a P-well region is set at the bottom of the contact hole 13 by ion implantation of P-type doping elements. The P-well region is P-type heavily doped. High-concentration P-type CT imp is implanted in the contact hole 13 to prevent the latching effect, so as to form a good ohmic contact;

[0117] Step S62, the P-type doping elements are activated by pushing the well to form the contact hole injection layer 14;

[0118] Step S63, after filling the metal filling layer 15 in the contact hole 13, a first metal layer is deposited on the metal filling layer 15 and the insulating dielectric layer 12 by metal sputtering process, and then the front source electrode metal layer 16 is formed by photolithography;

[0119] The material of the contact hole injection layer 14 in step S6 is titanium or titanium nitride;

[0120] The material of the first metal layer in step S63 is aluminum or copper.

[0121] Specifically, P-type doping elements are implanted by ion implantation, and then the implanted elements are activated by high-temperature well pushing to form the contact hole injection layer 14, as Figure 20As shown, a metal barrier layer (Ti / TiN) is deposited, and high temperature is used to form a good ohmic contact on the surface of the contact hole 13.

[0122] Then, a layer of tungsten is redeposited. The surface metal tungsten of the BPSG is removed through a etch-back process to form a metal filling layer 15. Then, a metal layer (Al / Cu) is deposited by a metal sputtering process, and then a front source metal layer 16 is formed through a photolithography process, as Figure 21 shown.

[0123] A P-well region is set at the bottom of the contact hole 13 and a high-concentration P-type CT imp is implanted to form a contact hole implantation layer 14, which can effectively prevent the latch-up effect, ensure a good ohmic contact, enable the current to be efficiently and stably transmitted between the contact hole 13 and the P-body region 10, reduce the contact resistance, lower the power loss, and improve the electrical performance and efficiency of the device.

[0124] The latch-up effect is usually caused by a parasitic PNPN structure forming a positive feedback loop under certain conditions, resulting in out-of-control current. Implanting a high-concentration P-type CT imp in the contact hole 13 to form a P-well region changes the local doping structure and electric field distribution, destroys the conditions that may form the latch-up effect, thereby effectively preventing the occurrence of the latch-up phenomenon and ensuring the normal operation of the device.

[0125] The heavy doping of the P-well region increases the carrier concentration in the contact area and reduces the contact resistance. Titanium or titanium nitride, as the material of the contact hole implantation layer 14, has a work function that matches the semiconductor material, can promote the effective injection and transmission of electrons at the contact interface, thereby achieving a good ohmic contact and improving the current transmission efficiency.

[0126] The material of the contact hole implantation layer 14 is titanium or titanium nitride. These materials have good electrical conductivity and compatibility with the semiconductor, can guide the current to be more evenly distributed and transmitted in the contact hole 13, reduce the current crowding phenomenon, further reduce the resistance, and improve the overall performance of the device.

[0127] In a preferred embodiment, step S7 includes,

[0128] The back surface of the substrate layer 1 is thinned to a set thickness through a back thinning process, and then a second metal layer is evaporated on the back surface to form a back drain metal layer 17;

[0129] The material of the second metal layer is titanium or nickel or silver.

[0130] Specifically, the back thinning process can be chemical mechanical polishing. Place the back side of the wafer substrate layer 1 on the polishing pad while applying a polishing liquid. The polishing liquid contains a chemical etchant (such as an alkaline or acidic solution) and nano-sized abrasive grains. The chemical etchant reacts with the substrate surface, dissolving or oxidizing the surface atomic layer, while the abrasive grains mechanically remove the reaction products through the relative movement between the polishing pad and the substrate.

[0131] It can also be mechanical grinding. Use the grinding disk of the grinding machine and the grinding slurry to bring the back side of the wafer substrate layer 1 into contact with the rotating grinding disk. The grinding disk is usually made of a material with a higher hardness (such as diamond, etc.). By applying a certain pressure and controlling the rotation speed of the grinding disk, the back side of the substrate layer 1 is ground. During the grinding process, the abrasive grains (such as alumina, silica, etc.) in the grinding slurry will produce a microscopic cutting effect on the substrate surface, gradually removing the excess material. The grinding process is usually divided into two stages: rough grinding and fine grinding. In the rough grinding stage, larger particle-sized abrasive grains and higher pressure are used to remove a thicker layer of material at a faster speed; in the fine grinding stage, smaller particle-sized abrasive grains and lower pressure are used to obtain a smoother surface. During the grinding process, a thickness measuring instrument (such as an optical interferometer) is used to monitor the thickness of the substrate in real time, and the grinding parameters are adjusted according to the measurement results to achieve an accurate thinning effect.

[0132] Thin the back side of the wafer to the required thickness, and then evaporate a metal layer (Ti / Ni / Ag) on the back side to form the device back drain metal layer 17, as Figure 22 shown.

[0133] For some low-voltage, low-power semiconductor power devices, the thinning thickness of the back substrate layer 1 can be around 10 μm - 50 μm. The thinned substrate can meet the basic requirements of reducing the series resistance and improving heat dissipation, while maintaining a certain mechanical strength.

[0134] For medium-high voltage, high-power semiconductor power devices, especially those that need to work at high current and high voltage, in order to further reduce the series resistance and improve the heat dissipation efficiency, the thinning thickness of the substrate layer 1 reaches 5 μm - 20 μm.

[0135] The back evaporation can be physical vapor deposition. Place the wafer in a vacuum chamber, and the vacuum degree in the chamber generally needs to reach a high vacuum state (for example, about 10 -6 Pa) to avoid the collision of metal atoms with other gas molecules during the transmission process, which may affect the coating quality.

[0136] Metals such as titanium, nickel or silver are used as evaporation sources, and usually resistance heating or electron beam heating is adopted to heat the metal source material to the evaporation temperature. Resistance heating generates heat by passing an electric current through a high-resistance material to heat the metal source to the evaporation point; electron beam heating uses a focused electron beam to bombard the metal source to locally heat it up and evaporate it.

[0137] The evaporated metal atoms will freely diffuse in the chamber. When they encounter the back surface of the wafer substrate layer 1, they will deposit on its surface to form a metal film. By controlling parameters such as the power of the evaporation source, the evaporation time, and the position of the wafer, the thickness and uniformity of the metal layer can be controlled.

[0138] By reducing the thickness of the substrate layer 1 through the back thinning process, the transmission path of the current in the substrate layer can be shortened, thereby reducing the resistance of the substrate layer.

[0139] A back drain metal layer 17 of titanium, nickel or silver is deposited on the back surface. These metals have good electrical conductivity, can further reduce the contact resistance of the drain, reduce power loss, improve the electrical efficiency of the device, enable the device to transmit current more effectively during operation, and enhance the overall performance.

[0140] The thinner substrate layer 1 helps the heat transfer from the inside of the device to the back heat dissipation structure. At the same time, the metal layer (Ti / Ni / Ag) also has a certain thermal conductivity, which can enhance the heat dissipation effect, prevent the device from being affected by overheating and causing performance degradation or failure, and improve the reliability and stability of the device.

[0141] In semiconductor manufacturing, the reduction of chip size is an important development trend. The back thinning process reduces the thickness of the substrate layer 1, which reduces the volume of the entire device without affecting the device function, is conducive to the miniaturization of the chip, improves the integration of the chip, meets the requirements of modern electronic devices for miniaturization and light weight, and can reduce production costs.

[0142] Refer to Figure 23 、 Figure 24 By mirroring and repeating the basic unit cell of the device, changing the distance from the contact hole 13 to the trench 4, calculating Figure 25 the changing trends of Vth, Gfs, and Ids in

[0143] During device operation, as the distance between the trench 4 and the contact hole 13 increases linearly, the power consumption distribution of cells at different positions changes. The cells near the contact hole 13 closer to the trench 4 turn on and generate heat first, while the cells farther away have a relatively smaller influence from the contact hole injection and turn on relatively later. They can act as a heat dissipation field plate to absorb and disperse heat, thus making the heat distribution more uniform inside the device and improving the heat dissipation effect.

[0144] The reduction of the influence of contact hole injection on the body region injection and the formed concentration gradient change the internal electric field distribution and carrier movement in the device. Near the trench 4, the influence of contact hole injection on the body region is greater, and the doping concentration and electrical characteristics change significantly;

[0145] As the distance increases, the influence gradually weakens, forming a gradient change in the electrical properties of different regions, which in turn causes the threshold voltage, transconductance, and drain current to change in a wavy shape, optimizing the overall electrical performance of the device.

[0146] Based on the basic unit cell for design, the complex device structure is decomposed into multiple identical units, which is convenient for precise control and optimization of the structure and performance of each unit.

[0147] By adjusting the distance relationship between the trench 4 and the contact hole 13 in the cell, the performance of the entire device can be regulated, reflecting the advantages of modular design and improving the design efficiency and flexibility.

[0148] Refer to Figure 25 , through the mirroring and repetition of the basic unit cell in the active region of the device, a layout with different widths of the distance between the trench 4 and the contact hole 13 is formed. This basic cell layout makes the width of the distance between the trench 4 and the contact hole 13 increase linearly (d1 < d2 < d3 < dn), gradually reducing the influence of contact hole injection on the body region injection, thereby forming a concentration gradient after contact hole injection. The device forms a working mode in which the threshold voltage, transconductance, and drain current change in a wavy shape, reducing the temperature coefficient of the device threshold voltage, decreasing the zero temperature coefficient point ZTCP (Zero Temperature Coefficient Point) of the current, realizing the process of sequential step-by-step turning on of the cell region when the device is conducting, and the region with delayed turning on can be used as a heat dissipation field plate for the region with priority turning on, improving the heat generation uniformity of the device, enhancing the heat dissipation ability of the device, and broadening the safe operating area of the power device.

[0149] The preparation method of the present invention can be compatible with the general power device manufacturing process and can be applied to power devices such as planar, trench-type, and shield-gate MOSFETs.

[0150] The above are only the preferred embodiments of the present invention, and thus do not limit the implementation and protection scope of the present invention. For those skilled in the art, it should be realized that all the equivalent replacements and obvious changes made by using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor power device, characterized in that: include, Step S1, after sequentially disposing an epitaxial layer and a barrier layer on a substrate layer, a groove is formed by photolithography, and a base structure is obtained by thermally oxidizing the inside of the groove and depositing a heavily doped polysilicon layer; Step S2, wet etching the sidewalls of the trench and then thermally oxidizing to form a gate oxide layer; Step S3, forming gate polysilicon by depositing the heavily doped polysilicon layer inside the trench; Step S4, ion implantation is performed on the epitaxial layer in sequence to form a P-body region and an N+ source region; Step S5, forming an insulating dielectric layer above the gate polysilicon and the first isolation layer, and etching a plurality of contact holes inwardly by photolithography, wherein the distance between a single contact hole and the corresponding trench increases linearly; Step S6, injecting ions into the bottom of the contact hole to form a contact hole injection layer, and filling the metal filling layer to form a front source metal layer; Step S7, providing a back drain metal layer on the back side of the substrate layer to obtain a basic unit cell; Step S8, mirroring and repeating the basic unit cell to form a semiconductor power device.

2. The method for preparing a semiconductor power device according to claim 1, characterized in that: Step S1 comprises, Step S11, disposing the epitaxial layer above the substrate layer; Step S12, disposing the barrier layer above the epitaxial layer; Step S13, forming the grooves on the epitaxial layer and the barrier layer by photolithography; Step S14, forming a first isolation layer inside the trench and on the barrier layer by thermal oxidation; Step S15, forming source polysilicon inside the trench by depositing the heavily doped polysilicon layer; Step S16, forming a second isolation layer on the source polysilicon by thermal oxidation to obtain the basic structure.

3. The method for preparing a semiconductor power device according to claim 1, characterized in that: Step S4 comprises, Step S41, forming the P-body region by ion implanting a P-type doping element on the epitaxial layer; Step S42, forming the N+ source region by ion implanting N-type doping elements on the upper portion of the P-body region.

4. The method for preparing a semiconductor power device according to claim 1, characterized in that: Step S5 comprises, Step S51, forming an insulating dielectric layer by depositing a layer of borophosphosilicate glass on the gate polysilicon and the first isolation layer; Step S52, after removing the insulating dielectric layer and the first isolation layer by dry etching, the contact hole is formed in the P-body region through the N+ source region, and the distance between a single contact hole and the corresponding trench increases linearly along the first direction.

5. The method for preparing a semiconductor power device according to claim 3, characterized in that: Step S6 comprises, Step S61, setting a P-well region at the bottom of the contact hole by ion implantation of the P-type doping element, wherein the P-well region is heavily doped with P-type; Step S62, activating the P-type doping element by well-driving to form the contact hole injection layer; Step S63, after the contact hole is filled with the metal filling layer, a first metal layer is deposited on the metal filling layer and the insulating dielectric layer by a metal sputtering process, and then the front source metal layer is formed by photolithography.

6. The method for preparing a semiconductor power device according to claim 1, characterized in that: Step S7 comprises, The back side of the substrate layer is thinned to a set thickness through a back side thinning process, and then a second metal layer is evaporated on the back side to form the back side drain metal layer.

7. The method for preparing a semiconductor power device according to claim 1, characterized in that: The gate polysilicon in step S3 is flush with the first isolation layer in step S5 in a horizontal direction.

8. The method for preparing a semiconductor power device according to claim 1, characterized in that: The material of the contact hole injection layer in step S6 is titanium or titanium nitride.

9. The method for preparing a semiconductor power device according to claim 5, characterized in that: In step S63 , the material of the first metal layer is aluminum or copper.

10. The method for preparing a semiconductor power device according to claim 6, characterized in that: The material of the second metal layer is titanium, nickel or silver.

Images