Light detection device and electronic apparatus

Abstract

The reduction of crosstalk is achieved. The light detection device includes: a first semiconductor layer having first and second surfaces positioned opposite to each other, and including a photoelectric conversion portion for photoelectrically converting light entering from the second surface side; a second semiconductor layer including a transistor and disposed on a first surface side of the first semiconductor layer; a third semiconductor layer that includes a transistor, is provided on a side opposite to the first semiconductor layer side of the second semiconductor layer, and overlaps the second semiconductor layer; and a shield disposed between the second semiconductor layer and the third semiconductor layer.

Description

Technical Field

[0001] The present technology (the technology according to the present disclosure) relates to an optical detection device and an electronic device, and particularly to a technology effective when applied to an optical detection device having a multi-stage stacked semiconductor layer and an electronic device including the optical detection device. Background Art

[0002] A stacked optical detection device is an optical detection device such as a solid-state imaging device and a distance measurement device that includes a plurality of semiconductor layers stacked in multiple levels and provided as layers respectively. The stacked optical detection device can transmit signals at high speed. Patent Document 1 discloses a solid-state imaging device having a two-layer structure formed by stacking two semiconductor layers. In addition, Patent Document 1 also discloses a technology for providing a light shielding member that prevents light emitted from an active element from entering a photoelectric conversion unit during the operation of the active element.

[0003] In addition, Patent Document 2 discloses a solid-state imaging device having a three-layer structure including three semiconductor layers in an upper level, a middle level, and a lower level. The semiconductor layer in the upper level includes a photoelectric conversion unit. The semiconductor layers in the middle level and the lower level respectively include transistors constituting a pixel circuit (read circuit) for outputting a pixel signal corresponding to the signal charge photoelectrically converted by the photoelectric conversion unit, a logic circuit for processing the pixel signal output from the pixel circuit, and the like. Citation List Patent Documents

[0004] Patent Document 1: JP 2012-64709 A Patent Document 2: JP 2021-7176 A Summary of the Invention Technical Problem

[0005] As described above, an optical detection device having a three-layer structure includes transistors constituting a logic circuit in each semiconductor layer in the middle level and the lower level. In this case, noise generated by a transistor included in one of the semiconductor layers in the lower level and the middle level during operation may propagate to a transistor included in the other semiconductor layer and cause crosstalk, thereby affecting the operation of the transistor in the other semiconductor layer.

[0006] The present technology has been developed in view of the above circumstances, and provides an optical detection device and an electronic device capable of reducing crosstalk. Solution to the Problem

[0007] (1) The light detection device according to one aspect of the present technology includes: a first semiconductor layer having a first surface and a second surface located at opposite positions, and including a photoelectric conversion portion for photoelectrically converting light entering from the second surface side; a second semiconductor layer including a transistor and provided on the first surface side of the first semiconductor layer; a third semiconductor layer including a transistor and provided on the side opposite to the first semiconductor layer side of the second semiconductor layer and overlapping the second semiconductor layer; and a shield provided between the second semiconductor layer and the third semiconductor layer.

[0008] (2) The electronic device according to another aspect of the present technology includes: the above-described light detection device; an optical lens that forms an image of image light received from a subject on the imaging surface of the light detection device; and a signal processing circuit that performs signal processing on the signal output from the light detection device. Description of the Drawings

[0009] Figure 1 is a chip layout diagram showing a structural example of a solid-state imaging device according to the first embodiment of the present technology. Figure 2 is a block diagram showing a structural example of a solid-state imaging device according to the first embodiment of the present technology. Figure 3 is an equivalent circuit diagram showing a structural example of a sensor pixel and a pixel circuit of a solid-state imaging device according to the first embodiment of the present technology. Figure 4 is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a solid-state imaging device according to the first embodiment of the present technology. Figure 5A is a view showing Figure 4 the enlarged part in Figure 5B is a view showing Figure 4 the enlarged part in Figure 6A is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a shielding solid film mounted on a solid-state imaging device according to the first embodiment of the present invention. Figure 6B is a view schematically showing Figure 6A the planar pattern of the shielding solid film in Figure 7 is a view showing an example of a circuit block of a solid-state imaging device according to the first embodiment of the present technology. Figure 8A is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a modification of the first embodiment. Figure 8BIt is a plan view schematically showing a planar pattern of a modification of the first embodiment. Figure 9 It is a vertical sectional view schematically showing a vertical sectional structure of a solid-state imaging device according to a second embodiment of the present technology. Figure 10 It shows Figure 9 a magnified portion of Figure 11A It is a vertical sectional view schematically showing a vertical sectional structure of a shielding structure mounted on a solid-state imaging device according to a second embodiment of the present technology. Figure 11B It schematically shows Figure 11A a planar pattern of the shielding structure in Figure 12A It is a vertical sectional view schematically showing a vertical sectional structure of a shielding structure mounted on a solid-state imaging device according to a third embodiment of the present technology. Figure 12B It schematically shows Figure 11A a planar pattern of the shielding structure in Figure 13 It is a plan view schematically showing a planar pattern of a modification of the third embodiment. Figure 14A It is a vertical sectional view schematically showing a vertical sectional structure of a shielding structure mounted on a solid-state imaging device according to a fourth embodiment of the present technology. Figure 14B It schematically shows Figure 14A a planar pattern of the shielding structure in Figure 15 It is a plan view schematically showing a planar pattern of a modification of the fourth embodiment. Figure 16A It is a vertical sectional view schematically showing a vertical sectional structure of a shielding structure mounted on a solid-state imaging device according to a fifth embodiment of the present technology. Figure 16B It schematically shows Figure 16A a planar pattern of the shielding structure in Figure 17 It is a plan view schematically showing a planar pattern of a modification of the fifth embodiment. Figure 18A It is a vertical sectional view schematically showing a vertical sectional structure of a shielding structure mounted on a solid-state imaging device according to a sixth embodiment of the present technology. Figure 18B It schematically shows Figure 18A a planar pattern of the shielding structure in Figure 19AIt is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the seventh embodiment of the present technology. Figure 19B It is schematically shown Figure 19A A plan view of the planar pattern of the shielding structure in Figure 20 It is a plan view schematically showing the planar pattern of a modified example of the seventh embodiment. Figure 21A It is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the eighth embodiment of the present technology. Figure 21B It is schematically shown Figure 21A A plan view of the planar pattern of the shielding structure in Figure 22 It is a plan view schematically showing the planar pattern of a modified example of the eighth embodiment. Figure 23A It is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the ninth embodiment of the present technology. Figure 23B It is schematically shown Figure 23A A plan view of the planar pattern of the shielding structure in Figure 24 It is a plan view schematically showing the planar pattern of a modified example of the ninth embodiment. Figure 25 It is a diagram showing a schematic configuration of an electronic device according to the tenth embodiment of the present technology. Figure 26 It is a block diagram showing a schematic configuration example of a vehicle control system. Figure 27 It is a diagram for assisting in explaining an example of the installation positions of an external information detection unit and an imaging unit. Figure 28 It is a diagram showing a schematic configuration example of an endoscopic surgical system. Figure 29 It is a block diagram showing a schematic functional configuration example of a camera head and an imaging machine control unit (CCU). Detailed Description of the Embodiment

[0010] Hereinafter, embodiments according to the present technology will be described in detail with reference to the drawings. Note that the same or similar parts included in the drawings referred to in the following description will be given the same or similar reference numerals. However, it should be noted that the drawings are only schematic diagrams, and these schematic diagrams may include relationships between thickness and planar dimensions, ratios of layer thicknesses, and other conditions different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description.

[0011] In addition, of course, the dimensional relationships and ratios included in certain drawings may be different from those in other drawings. Moreover, the beneficial effects provided are not limited to those effects illustrated only by way of example in this specification, and other beneficial effects may also be provided.

[0012] In addition, the following embodiments are merely examples of devices and methods for implementing the technical concept of the present technology, and do not require the adoption of the specific configurations described below. Therefore, the technical concept of the present technology can be modified in various ways within the technical scope defined by the claims.

[0013] In addition, the direction definitions (such as the up-down direction) included in the following description are provided only for the convenience of explanation, and thus do not limit the technical concept of the present technology. For example, needless to say, the up-down direction of the target is switched to the left-right direction to observe the target rotated by 90 degrees, or the up-down direction of the target is vertically inverted to observe the target rotated by 180 degrees.

[0014] In addition, among the three directions perpendicular to each other in space, in the following embodiments, it is assumed that the first direction and the second direction perpendicular to each other in the same plane are the X direction and the Y direction respectively, and the third direction perpendicular to the first direction and the second direction respectively is the Z direction. In addition, the thickness direction of each of the following semiconductor layers corresponds to the Z direction in the description of the following embodiments. In addition, in the description of the following embodiments, the Z direction corresponds to "one direction" of the present technology. In addition, in the following embodiments, the thickness of each semiconductor layer corresponds to the distance between the first surface portion and the second surface portion located at opposite positions in the Z direction, and the thickness direction of each semiconductor layer corresponds to the thickness direction of the corresponding semiconductor layer. In addition, in the following embodiments, the plan view refers to the view of the semiconductor layer observed along the Z direction (one direction). The sectional view refers to the sectional view obtained by intercepting along the Z direction (one direction) and observing along the direction perpendicular to the section (Z direction).

[0015] [First Embodiment] Here, an example in which the present technology is applied to a light detection device, which is a solid-state imaging device constituting a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor, will be described in the first embodiment. In addition, in the first embodiment herein, a shielding solid film, which is a shielding body for shielding electromagnetic fields, will be described. The shielding solid film corresponds to a specific example of the "shielding body" according to the present technology.

[0016] 《Overall Structure of the Solid-State Imaging Device》 First, the overall structure of the solid-state imaging device 1A will be introduced. AsFigure 1 As shown, the solid-state imaging device 1A according to the first embodiment of the present technology mainly includes a semiconductor chip 2, which has a square two-dimensional planar shape in a plan view. Specifically, since the solid-state imaging device 1A is mounted on the semiconductor chip 2, the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As Figure 25 shown, the solid-state imaging device 1A (101) introduces the image light (incident light 106) received from the subject via the optical lens 102, converts the amount of light of the incident light 106 that forms an image on the imaging surface into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal.

[0017] As Figure 1 shown, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes, in a two-dimensional plane including the X direction and the Y direction perpendicular to each other: a sensor pixel array portion 2A, which has a square shape and is provided at the central portion; and a peripheral portion 2B, which is provided outside the sensor pixel array portion 2A and surrounds the sensor pixel array portion 2A. The semiconductor chip 2 is formed by dicing a semiconductor wafer including the first to third semiconductor layers 20, 50, and 80 described below and dividing it for each chip formation area during the manufacturing process. Therefore, the solid-state imaging device 1A described below has a substantially similar structure even in the wafer state before the semiconductor wafer is diced into smaller pieces. In other words, the present technology is applicable to the semiconductor chip state and the semiconductor wafer state.

[0018] For example, the sensor pixel array portion 2A is a light receiving surface that receives the light collected by the optical lens (optical system) 102 shown in Figure 25 As shown. In addition, in a two-dimensional plane including the X direction and the Y direction, a plurality of sensor pixels 3 are arranged in a matrix shape in the sensor pixel array portion 2A. In other words, in the two-dimensional plane, the sensor pixels 3 are repeatedly arranged in each of the X direction and the Y direction perpendicular to each other.

[0019] As Figure 1 shown, a plurality of bonding pads 14 are disposed in the peripheral portion 2B. For example, the plurality of bonding pads 14 are arranged along each of the four sides of the two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 serves as an input / output terminal to electrically connect the semiconductor chip 2 to an external device.

[0020] <Logic circuit> The semiconductor chip 2 includes Figure 2 the logic circuit 13 shown in Figure 2As shown, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc. The logic circuit 13 includes a CMOS (complementary MOS) circuit, which, for example, has an n-channel conductivity type MOSFET (metal oxide semiconductor field effect transistor) and a p-channel conductivity type MOSFET as field effect transistors.

[0021] The vertical drive circuit 4 includes, for example, a shift register. The vertical drive circuit 4 sequentially selects a desired pixel drive line 10 and supplies a pulse for driving the sensor pixel 3 to the selected pixel drive line 10 to drive each sensor 3 in each row. Specifically, the vertical drive circuit 4 selectively scans each sensor pixel 3 of the sensor pixel array section 2A row by row in the vertical direction, and supplies a pixel signal to the column signal processing circuit 5 through the vertical signal line 11. Each pixel signal is received from the sensor pixel 3 and is a signal corresponding to the signal charge generated by the photoelectric conversion section (photoelectric conversion element) of the corresponding sensor pixel 3 based on the light reception amount.

[0022] For example, the column signal processing circuits 5 are arranged in a one-to-one correspondence with the columns of the sensor pixels 3, and perform signal processing such as noise cancellation on the signals output from the sensor pixels 3 in one row for each pixel column. For example, each column signal processing circuit 5 performs signal processing such as CDS (correlated double sampling) and AD (analog-to-digital) conversion to eliminate fixed pattern noise peculiar to pixels.

[0023] The horizontal drive circuit 6 includes, for example, a shift register. The horizontal drive circuit 6 sequentially selects each column signal processing circuit 5 by sequentially outputting horizontal scan pulses to each column signal processing circuit 5, and causes each column signal processing circuit 5 to output the processed pixel signal to the horizontal signal line 12.

[0024] The output circuit 7 performs signal processing on the pixel signals sequentially supplied from each column signal processing circuit 5 through the horizontal signal line 12 and outputs the processed pixel signals. For example, the signal processing may include buffering, black level adjustment, column difference correction, and various digital signal processings, etc.

[0025] The control circuit 8 generates a clock signal and a control signal serving as operation references for the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. according to the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal, and outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0026] <Circuit configuration of sensor pixel> As Figure 3As shown, each of the plurality of sensor pixels 3 includes a photoelectric conversion region 21 and a pixel circuit (read circuit) 15. The photoelectric conversion region 21 includes a photoelectric conversion section 24, a transfer transistor TR serving as a pixel transistor, and a floating diffusion region FD serving as a charge holding section. The pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 21.

[0027] The first embodiment proposed herein by way of example has a circuit configuration in which one pixel circuit 15 is assigned to one sensor pixel 3. However, it is not required to adopt such a configuration of the first embodiment. For example, the following circuit configuration can be adopted: a plurality of sensor pixels 3 share one pixel circuit 15. Specifically, the following circuit configuration can be adopted: one sensor pixel group (photoelectric conversion group) shares one pixel circuit 15, and the sensor pixel group is a unit composed of 4 pixels arranged in a 2×2 layout, with 2 pixels 3 arranged in each of the X direction and the Y direction in the 2×2 layout. In addition, the following circuit configuration can be adopted: one sensor pixel group (photoelectric conversion group) shares one pixel circuit 15, and the sensor pixel group is a unit composed of two sensor pixels 3. In addition, the following circuit configuration can be adopted: one sensor pixel group (photoelectric conversion group) shares one pixel circuit 15, and the sensor pixel group is a unit composed of four or more sensor pixels 3.

[0028] Figure 3 The photoelectric conversion section 24 shown includes, for example, a pn junction type photodiode (PD), and generates signal charges corresponding to the received light amount. The photoelectric conversion section 24 is configured such that the cathode side is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground).

[0029] Figure 3 The transfer transistor TR shown transfers the signal charges photoelectrically converted by the photoelectric conversion section 24 to the floating diffusion region FD. The source region of the transfer transistor RT is electrically connected to the cathode side of the photoelectric conversion section 24, and the drain region of the transfer transistor TR is electrically connected to the floating diffusion region FD. In addition, the gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line in the pixel drive line 10 (see Figure 2 ).

[0030] Figure 3 The floating diffusion region FD shown temporarily holds (accumulates) the signal charges transferred from the photoelectric conversion region 24 through the transfer transistor TR.

[0031] For each sensor pixel 3, the photoelectric conversion region 21 including the photoelectric conversion section 24, the transfer transistor TR, and the floating diffusion region FD is mounted in the first semiconductor layer 20 shown in FIG. 5.

[0032] Figure 3 The pixel circuit 15 shown reads the signal charge held in the floating diffusion region FD and outputs a pixel signal corresponding to the read signal charge. For example, the pixel circuit 15 includes (but is not limited to) an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. For example, as field effect transistors, each of the above pixel transistors (AMP, SEL, RST) and the transfer transistor TR includes a MOSFET having a gate insulating film including a silicon oxide (SiO2) film, a gate electrode, and a pair of main electrode regions serving as a source region and a drain region. Alternatively, each transistor may be a MISFET (metal insulator semiconductor field effect transistor) including a silicon nitride (Si3N4) film as the gate insulating film or a stacked film formed by stacking a silicon nitride film and a silicon oxide film, etc.

[0033] As Figure 3 shown, the amplification transistor AMP is configured such that the source region is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. In addition, the gate electrode of the amplification transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.

[0034] As Figure 3 shown, the selection transistor SEL is configured such that the source region is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. In addition, the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line in the pixel drive line 10 Figure 2 shown.

[0035] As Figure 3 shown, the reset transistor RST is configured such that the source region is electrically connected to the floating diffusion region FD and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. In addition, the gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line in the pixel drive line 10 Figure 2 shown.

[0036] When Figure 3 the transfer transistor TRG shown enters the on state, the transfer transistor TR transfers the signal charge generated by the photoelectric conversion unit 24 to the floating diffusion region FD.

[0037] When Figure 3When the shown reset transistor RST enters the conducting state, the reset transistor resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal received from the pixel circuit 15.

[0038] Figure 3 The shown amplification transistor AMP generates a signal as a pixel signal, and this signal indicates a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal that indicates a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 24. When the selection transistor SEL enters the conducting state, the amplification transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to this potential to the column signal processing circuit 5 through the vertical signal line 11 (VSL).

[0039] This article refers to Figure 3 For the description, during the operation of the solid-state imaging device 1A according to the first embodiment of this article, the signal charge generated by the photoelectric conversion unit 24 of the sensor pixel 3 is held (accumulated) in the floating diffusion region FD through the transfer transistor TR of the sensor pixel 3. Thereafter, the pixel circuit 15 reads the signal charge held in the floating diffusion region FD and applies it to the gate electrode of the amplification transistor AMP of the pixel circuit 15. The horizontal line selection control signal is supplied from the vertical shift register to the gate electrode of the selection transistor SEL of the pixel circuit 15. Thereafter, the selection transistor SEL conducts in response to the selection control signal set to the high (H) level and causes a current corresponding to the potential amplified by the amplification transistor AMP of the floating diffusion region FD to flow in the vertical signal line 11. In addition, the reset transistor RST conducts in response to the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 and set to the high (H) level, and resets the signal charge accumulated in the floating diffusion region FD.

[0040] <Different pixel circuits> In addition, the selection transistor SEL can also be omitted as needed. In a configuration that does not include the selection transistor SEL, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

[0041] In addition, a switching transistor can also be provided between the reset transistor RST and the floating diffusion region FD and the gate electrode of the amplification transistor AMP. This switching transistor controls the charge holding of the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplification transistor AMP.

[0042] In addition, a switching transistor is used to switch the conversion efficiency. Generally, the pixel signal is low during imaging in the dark. If the FD capacitance C (floating diffusion capacitance C) of the charge holding section (floating diffusion region FD) is high during charge-voltage conversion based on Q = CV, the voltage V will decrease when converted to a voltage by the amplifying transistor AMP. At the same time, the pixel signal is high in the bright area. Therefore, unless the FD capacitance C of the charge holding section is high, it is difficult for the charge of the photoelectric conversion section 24 (photodiode PD) to be received by the charge holding section. In addition, the FD capacitance C of the charge holding section needs to be high to avoid excessive increase in the voltage V (i.e., decrease the voltage V) when converted to a voltage by the amplifying transistor AMP. Considering these situations, when the switching transistor is turned on, the gate capacitance increases the capacitance of the switching transistor. Therefore, the overall FD capacitance C increases. At the same time, when the switching transistor is turned off, the overall FD capacitance C decreases. As can be seen from the above, the FD capacitance C is variable, so the conversion efficiency can be switched according to the on / off switching of the switching transistor.

[0043] Specific Structure of the Solid-State Imaging Device Next, reference will be made to Figure 4 、 5A and 5B to illustrate the specific structure of the solid-state imaging device 1A.

[0044] <Stacked Structure of the Solid-State Imaging Device> As Figure 4 、 5A and 5B show, the solid-state imaging device 1A (semiconductor chip 2) has a stacked structure, which includes a light collection layer 90, a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 40, a second semiconductor layer 50, a third wiring layer 60, a fourth wiring layer 70, and a third semiconductor layer 80 stacked in sequence. Note here that the first semiconductor layer 20, the second semiconductor layer 50, and the third semiconductor layer 80 respectively correspond to a specific example of the "first semiconductor layer", "second semiconductor layer", and "third semiconductor layer" of the present technology. In addition, the third wiring layer 60 and the fourth wiring layer 70 respectively correspond to a specific example of the "first wiring layer" and "second wiring layer" of the present technology.

[0045] The first semiconductor layer 20 corresponding to the "first semiconductor layer" of the present technology has a first surface S1 and a second surface S2 located at positions opposite to each other along the thickness direction (Z direction) of the first semiconductor layer 20 (see Figure 5A ). In addition, the first semiconductor layer 20 includes a photoelectric conversion region 21 described below (see Figure 5A ). The light collection layer 90 is provided on the second surface S2 side of the first semiconductor layer 20. Additionally, for example, the light collection layer 90 has (but is not limited to) a stacked structure in which a color filter 91 and an on-chip lens 92 are stacked in sequence from the second surface S2 side of the first semiconductor layer 20. The first wiring layer 30 is provided on the first surface S1 side of the first semiconductor layer 20 and overlaps with the first surface S1 of the first semiconductor layer 20. The second wiring layer 40 is provided on the side of the first wiring layer 30 opposite to the first semiconductor layer 20 side and overlaps with the surface of the first wiring layer 30 located on the first semiconductor layer 20 side.

[0046] The second semiconductor layer 50 corresponding to the "second semiconductor layer" of the present technology has a third surface S3 and a fourth surface S4 located at positions opposite to each other along the thickness direction (Z direction) of the second semiconductor layer 50 (see Figure 5B ). Additionally, the second semiconductor layer 50 is provided on the side of the second wiring layer 40 opposite to the first wiring layer 30 side and overlaps with the surface of the second wiring layer 40 located on the side opposite to the first wiring layer 30 side. The third wiring layer 60 corresponding to the "first wiring layer" of the present technology is provided on the side of the second semiconductor layer 50 opposite to the second wiring layer 40 side and overlaps with the fourth surface S4 of the second semiconductor layer 50. The fourth wiring layer 70 corresponding to the "second wiring layer" of the present technology is provided on the side of the third wiring layer 60 opposite to the second semiconductor layer 50 side and overlaps with the surface of the third wiring layer 60 located on the side opposite to the second semiconductor layer 50 side.

[0047] The third semiconductor layer 80 corresponding to the "third semiconductor layer" of the present technology has a fifth surface S5 and a sixth surface S6 located at positions opposite to each other along the thickness direction of the third semiconductor layer 80. Additionally, the third semiconductor layer 80 is provided on the side of the fourth wiring layer 70 opposite to the third wiring layer 60 side and overlaps with the surface of the fourth wiring layer 70 located on the side opposite to the third wiring layer 60 side.

[0048] Here, note that the first surface S1 of the first semiconductor layer 20 is also referred to as the element formation surface or the main surface, and the second surface S2 of the first semiconductor layer 20 is also referred to as the light incident surface or the back surface. In addition, the third surface S3 of the second semiconductor layer 50 is also referred to as the element formation surface or the main surface, and the fourth surface S4 of the second semiconductor layer 50 is also referred to as the back surface. In addition, the fifth surface S5 of the third semiconductor layer 80 is also referred to as the element formation surface or the main surface, and the surface on the opposite side of the fifth surface S5 is also referred to as the back surface.

[0049] In addition, the first semiconductor layer 20 and the second semiconductor layer 50 are joined by the first wiring layer 30 and the second wiring layer 40 in an F2F (face-to-face) manner, that is, such that the corresponding element formation surfaces face each other. In addition, the second semiconductor layer 50 and the third semiconductor layer 80 are joined by the third wiring layer 60 and the fourth wiring layer 70 in a B2F (back-to-face) manner, that is, such that the back surface and the element formation surface face each other.

[0050] <First semiconductor layer> The first semiconductor layer 20 includes a semiconductor substrate. For example, the first semiconductor layer 20 includes a p-type single-crystalline silicon substrate corresponding to the first conductivity type. The photoelectric conversion region 21 is formed in a region included in the first semiconductor layer 20 and overlapping with the sensor pixel array unit 2A in a plan view, and is provided for each sensor pixel 3. Although not shown in the figure, the photoelectric conversion region 21 is divided by divided regions formed in the first semiconductor layer 20. Note that the number of sensor pixels 3 is not limited to Figure 4 the number shown.

[0051] Although not shown in the figure, the photoelectric conversion region 21 includes a p-type well region and an n-type semiconductor region (photoelectric conversion portion). For example, the n-type semiconductor region is a region corresponding to the second conductivity type and is embedded within the above-mentioned well region. Figure 3 The photoelectric conversion element PD shown is formed in the photoelectric conversion region 21 including the well region and the photoelectric conversion portion of the first semiconductor layer 20. In addition, the photoelectric conversion region 21 also includes, for example, but is not limited to, a charge holding portion (charge accumulation portion) including an n-type semiconductor region and a transfer transistor TR.

[0052] <First wiring layer> The first wiring layer 30 includes an insulating film 31, wirings 32, bonding pads (bonding metal pads) 33, and contact electrodes (vertical interconnections (vias)). As shown in the figure, the wirings 32 and the bonding pads 33 are stacked with the insulating film 31 therebetween. The bonding pads 33 face the surface of the first wiring layer 30 on the side opposite to the first semiconductor layer 20 side. The bonding pads 33 are provided in the uppermost layer of the first wiring layer 30 on the side opposite to the first semiconductor layer 20 side and are electrically connected to the lower-layer wirings 32 through the contact electrodes. Each of the wirings 32 and the bonding pads 33 can be made of, for example, but is not limited to, copper and is formed by a damascene method.

[0053] <Second wiring layer> The second wiring layer 40 includes an insulating film 41, wirings 42, bonding pads (bonding metal pads) 43, and contact electrodes (vertical interconnection portions). As shown in the figure, the wirings 42 and the bonding pads 43 are stacked with the insulating film 41 therebetween. The bonding pads 43 face the surface of the second wiring layer 40 on the side opposite to the second semiconductor layer 50 side. The bonding pads 43 are provided in the uppermost layer of the second wiring layer 40 on the side opposite to the second semiconductor layer 50, and are electrically connected to the underlying wirings 42 through the contact electrodes. Further, the bonding pads 43 are bonded to the corresponding bonding pads 33 in the first wiring layer 30. Each of the wirings 42 and the bonding pads 43 may be made of, for example but not limited to, copper, and is formed by a damascene method.

[0054] <Second semiconductor layer> The second semiconductor layer 50 includes, but is not limited to, for example, a p-type single crystal silicon substrate as described below. A plurality of transistors T1 are provided in the second semiconductor layer 50. For example, the transistor T1 is a pixel transistor that constitutes Figure 3 the pixel circuit (read circuit) 15 shown, and a transistor that constitutes Figure 2 the logic circuit 13 shown.

[0055] <Third wiring layer> As Figure 5B shown, the third wiring layer 60 includes an insulating film 61, wirings 62, and bonding pads (bonding metal pads) 63. As shown in the figure, the wirings 62 and the bonding pads 63 are stacked with the insulating film 61 therebetween. The bonding pads 63 face the surface of the third wiring layer 60 on the side opposite to the second semiconductor layer 50 side. Each of the wirings 62 and the bonding pads 63 may be made of, for example but not limited to, copper, and is formed by a damascene method.

[0056] According to the first embodiment proposed herein, each bonding pad 63 corresponds to a specific example of the "first bonding pad" of the present technology, and the third wiring layer 60 corresponds to a specific example of the "first wiring layer" of the present technology.

[0057] <Fourth wiring layer> As Figure 5BAs shown, the fourth wiring layer 70 includes an insulating film 71, wirings 72 and 72a, bonding pads (bonding metal pads) 73, and contact electrodes. As shown in the figure, the wirings 72 and the bonding pads 73 are stacked with the insulating film 71 therebetween. The bonding pads 73 face the surface of the fourth wiring layer 70 on the side opposite to the side of the third semiconductor layer 80. The bonding pads 73 are provided in the uppermost layer of the fourth wiring layer 70 on the side of the second semiconductor layer 50, and are electrically connected to the wirings 72a in the lower layer through the contact electrodes. Each of the wirings 72 and the bonding pads 73 can be made of, for example but not limited to, copper, and is formed by a damascene method. Meanwhile, different from the wiring 72 in the lower layer of the above-mentioned wiring 72a, the wiring 72a includes, for example, an aluminum film.

[0058] <Third semiconductor layer> The third semiconductor layer 80 includes, for example, a p-type single-crystalline silicon substrate. A plurality of transistors T2 are provided in the third semiconductor layer 80. The transistors T2 are, for example, the transistors constituting Figure 2 the logic circuit 13 shown.

[0059] <Through-contact electrode> As Figure 5B shown, the wiring 42 in the second wiring layer 40 and the bonding pad 63 in the third wiring layer 60 are electrically connected to each other through the through-contact electrodes 51 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction). Although not shown in the figure, each through-contact electrode 51 penetrates a through-hole in the second semiconductor layer 50 and is electrically insulated from the second semiconductor layer 50 within the through-hole by the insulating film therebetween. The through-contact electrodes 51 that penetrate the second semiconductor layer 50 are preferably made of a material having a linear thermal expansion coefficient close to that of the second semiconductor layer 50. Since the second semiconductor layer 50 in this embodiment includes single-crystalline silicon, the through-contact electrodes 51 are made of polycrystalline silicon into which impurities for reducing resistance are introduced.

[0060] <Shielding solid film> As Figure 5B shown, a shielding solid film 66 serving as a shield is provided on the side of the fourth surface S4 of the second semiconductor layer 50. In other words, the solid-state imaging device 1A according to the first embodiment herein includes the shielding solid film 66 serving as a shield between the second semiconductor layer 50 and the third semiconductor layer 80. The shielding solid film 66 is fixed on the fourth surface S4 of the second semiconductor layer 50 with the fixed charge film 65 therebetween. In addition, the shielding solid film 66 reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0061] For example, the fixed charge film 65 includes a dielectric film that generates negative fixed charges. For example, the dielectric film can be made of hafnium oxide (HfO2) having a high dielectric constant. The fixed charge film 65 arranged in this way can induce holes (h + ) at the surface portion of the second semiconductor layer 50 on the side of the fourth surface S4, and achieve sufficient pinning at this interface portion. Alternatively, the dielectric film can be made of other materials, such as zirconium oxide (ZrO2) and tantalum oxide (Ta2O5).

[0062] The shielding solid film 66 is electrically connected to the wiring to which a potential is applied. In addition, the potential of the shielding solid film 66 is fixed to the potential applied to this wiring. For example, this potential is the power supply potential provided by the power supply generation circuit. For example, this power supply potential is the first reference potential of 0V, the second reference potential as a positive potential higher than the above-mentioned first reference potential, or the third reference potential as a negative potential lower than the above-mentioned first reference potential, etc. According to this embodiment, for example, the first reference potential of 0V is provided to the shielding solid film 66. During the operation of the solid-state imaging device 1A, the potential applied to the shielding solid film 66 is maintained.

[0063] The shielding solid film 66 is preferably made of a material suitable for shielding electromagnetic fields (such as band noise and hot carrier light). For example, the shielding solid film 66 can be made of high melting point metals such as tantalum (Ta), titanium (Ti), and tungsten (W) (for example), or their nitrides, or made of metals such as copper (Cu) and aluminum (Al).

[0064] As Figure 5B shown, in the plan view, the shielding solid film 66 is arranged on the side of the fourth surface S4 of the second semiconductor layer 50 so as to cover the sensor pixel array portion 2A and the peripheral portion 2B, and has a two-dimensionally extended plate shape. In addition, as Figure 6A and 6B shown, the shielding solid film 66 has an opening 66a, and the through contact electrode 51 passes through the opening. Specifically, each through contact electrode 51 penetrates the through hole in the second semiconductor layer 50 and the opening 66a in the shielding solid film 66, and realizes the electrical connection between the wiring 42 formed in the second wiring layer 40 on the side of the third surface S3 of the second semiconductor layer 50 and the bonding pad 63 formed in the third wiring layer 60 on the side of the fourth surface S4 of the second semiconductor layer 50.

[0065] The opening 66a can be formed by patterning the shielding solid film 66 using known lithography techniques or known dry etching techniques. In addition, the shielding solid film 66 can be selectively arranged by patterning in a manner aligned with the area to be shielded. Therefore, although in this embodiment, asFigure 5B As shown, the shielding solid film 66 is disposed on the fourth surface S4 side of the second semiconductor layer 50 so as to cover the sensor pixel array portion 2A and the peripheral portion 2B. However, the shielding solid film 66 may be selectively disposed on the area that needs to be shielded, such as the peripheral portion 2B.

[0066] 《Main Beneficial Effects of the Embodiment》 Next, the main beneficial effects of the above first embodiment will be described. The transistor T1 that constitutes the pixel circuit 15 and the logic circuit 13 is disposed in the second semiconductor layer 50. At the same time, the transistor T2 that constitutes the logic circuit 13 is disposed in the third semiconductor layer 80. At the same time, according to this embodiment, the shielding solid film 66 is disposed between the third semiconductor layer 80 of the lower layer and the second semiconductor layer 50 of the intermediate layer. In this case, the shielding solid film 66 is disposed between the transistor T2 in the third semiconductor layer 80 of the lower layer and the transistor T1 in the second semiconductor layer 50 of the intermediate layer. Therefore, through the shielding solid film 66, the propagation of the band noise generated during the operation of the transistor T2 to the transistor T1 can be blocked. Conversely, through the shielding solid film 66, the propagation of the band noise generated during the operation of the transistor T1 to the transistor T2 can also be blocked. Therefore, this structure can reduce the band noise generated during the operation of the transistor T2 in the third semiconductor layer 80 of the lower layer or the transistor T1 in the second semiconductor layer 50 of the intermediate layer and propagated from the transistor that generates the band noise to other transistors, thereby reducing the crosstalk that affects the operation of other crystals. In addition, the pixel transistors included in the pixel circuit 15 are disposed in the second semiconductor layer 50, and this semiconductor layer is different from the first semiconductor layer 20 in which the photoelectric conversion portion 24, the transfer transistor TR, and the charge holding portion (FD) are disposed. Therefore, the layout freedom of the pixel transistors (AMP, SEL, RST) included in the pixel circuit 15 can be improved, and compared with the case where the photoelectric conversion portion 24, the transfer transistor TR, the charge holding portion (FD), and the pixel transistors are disposed in the same semiconductor layer, the integration degree and the noise immunity can be further enhanced.

[0067] Figure 7 is a diagram showing an example of a circuit block. For example, the solid-state imaging device 1A according to the first embodiment herein includes Figure 7 the circuit block shown. In Figure 7 the circuit block, the circuit block 18a includes a logic operation circuit, the circuit block 18b includes a load MOS transistor circuit, the circuit block 18c includes a comparator circuit, and the circuit block 18d includes a counter circuit. In addition, the circuit block 18e includes a scanner circuit, the circuit block 18f includes a D / C converter, and the circuit block 18G includes a mobile processor interface circuit.

[0068] Each of these circuit blocks includes a transistor T1 in the second semiconductor layer 50 and a transistor T2 in the third semiconductor layer 80. In addition, among these circuit blocks, each of the circuit blocks 18a, 18b, 18c, 18f, and 18G operates at high speed and is therefore likely to become a noise source. Therefore, if a structure is adopted in which the shielding solid film 66 is selectively arranged so as to overlap with the circuit blocks that are likely to become noise sources in the plan view, crosstalk between the third semiconductor layer 80 in the lower layer and the second semiconductor layer 50 in the intermediate layer can be reduced. In this case, the shielding solid film 66 selectively overlaps with the circuit blocks that need to be shielded in the plan view.

[0069] As described above, Figure 2 The logic circuit 13 shown includes a CMOS circuit. This CMOS circuit needs to take measures to prevent latch up. However, hot carrier light is emitted during the operation of the transistor. This hot carrier light may be one of the factors causing latch up. At the same time, the shielding solid film 66 between the transistor T2 in the third semiconductor layer 80 in the lower layer and the transistor T1 in the second semiconductor layer 50 in the intermediate layer can block the hot carrier light emitted from the transistors T2 and T1. Therefore, latch up caused by hot carrier light can be reduced.

[0070] Note that the shielding solid film 66 can also be directly provided on the fourth surface S4 of the second semiconductor layer 50. In this case, a reference potential is usually provided to the second semiconductor layer 50. Therefore, the potential of the shielding solid film 66 is also fixed to the reference potential of the second semiconductor layer 50. In addition, Figure 3 All pixel transistors included in the pixel circuit 15 in In addition, the pixel transistors included in the pixel circuit 15, Figure 3 shown and not shown, can be appropriately divided into groups arranged in the first semiconductor layer 20 and groups arranged in the second semiconductor layer 50. In addition, signal processing circuits, drive circuits, storage circuits, etc. can also be arranged in an arbitrary manner in at least any one of the first semiconductor layer 20, the second semiconductor layer 50, and the third semiconductor layer 80.

[0071] 《Modification of the First Embodiment》 According to the above first embodiment, a gap is generated between the shielding solid film 66 and the through contact electrode 51 according to the separation between the shielding solid film 66 and the through contact electrode 51. Therefore, electromagnetic fields (such as band noise and hot carrier light) may pass through these gaps. To solve this problem, as Figure 8A and 8BAs shown, at least one of the bonding pads 63 and 73 may be formed to have a planar dimension sufficient to overlap the entire opening 66a of the shielding solid film 66 in a plan view, so as to prevent the electromagnetic field from passing through. In Figure 8A and 8B , the bonding pads 63 and 73 are respectively formed to have a planar dimension sufficient to overlap the entire opening 66a of the shielding solid film 66 in a plan view.

[0072] [Second Embodiment] In the second embodiment herein, a shielding structure will be described, which includes a first bonding pad and a second bonding pad and serves as a shield for blocking the electromagnetic field. Figure 9 is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of the solid-state imaging device 1B according to the second embodiment of the present technology. Figure 10 is showing Figure 9 an enlarged part of Figure 11A is showing Figure 9 a simplified vertical cross-sectional structure of the shielding structure shown in Figure 11B is showing Figure 9 a simplified planar pattern of the shielding structure shown in As Figure 9 and 10 shown, the configuration of the solid-state imaging device 1B according to the second embodiment herein is substantially similar to the configuration of the solid-state imaging device 1A of the above-described first embodiment, but is different in the following configurations.

[0073] Specifically, as Figure 9 and 10 shown, the solid-state imaging device 1B according to the second embodiment herein includes a shielding structure 55B instead of Figure 5B the shielding solid film 66 according to the above-described first embodiment shown in

[0074] As Figure 9 and 10 shown, the solid-state imaging device 1B according to the second embodiment herein includes a shielding structure 55B as a shield between the second semiconductor layer 50 and the third semiconductor layer 80.

[0075] As Figure 11A and 11BAs shown, the shielding structure 55B includes: a bonding pad 63 disposed between the second semiconductor layer 50 and the third semiconductor layer 80 and linearly extending in the X direction (first direction) in a plan view; and a bonding pad 73 located on the third semiconductor layer 80 side of the bonding pad 63 and joined to the bonding pad 63, and linearly extending in the X direction (first direction) in a plan view.

[0076] As Figure 11A and 11B shown, the shielding structure 55B has a bonding pad 63 and a bonding pad 73; in a plan view, the bonding pad 63 and the bonding pad 73 are repeatedly arranged at positions offset from each other in the Y direction (second direction) intersecting the X direction. In addition, in a plan view, portions of the bonding pad 63 and portions of the bonding pad 73 in each adjacent pair overlap each other and are joined to each other. Thus, the shielding structure 55B constitutes a shielding plate that combines the bonding pad 63 and the bonding pad 73 and extends two-dimensionally in a plan view. Similar to the above-described shielding solid film 66, the shielding structure 55B in the second embodiment herein is electrically connected to a wiring to which a potential is applied, and the potential of the shielding structure 55B is fixed to the potential applied to the wiring. In addition, the shielding structure 55B also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0077] The shielding structure 55B of the second embodiment herein constitutes a shielding plate that combines the bonding pad 63 and the bonding pad 73 and extends two-dimensionally in a plan view. The shielding structure 55B configured as above can reduce the noise generated during the operation of the transistor T2 in the third semiconductor layer 80 of the lower layer or the transistor T1 in the second semiconductor layer 50 of the intermediate layer and propagated from the transistor generating the band noise to other transistors, and thus can reduce the crosstalk affecting the operation of other transistors.

[0078] Therefore, the solid-state imaging device 1B including the above-described shielding structure 55B according to the second embodiment can also provide advantageous effects similar to those of the solid-state imaging device 1A of the first embodiment above.

[0079] [Third Embodiment] A shielding structure will be described in the third embodiment herein. The shielding structure includes a first bonding pad, a second bonding pad, and a conductor penetrating the second semiconductor layer, and serves as a shield for blocking an electromagnetic field.

[0080] Figure 12A is a vertical cross-sectional view showing a simplified vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the third embodiment of the present technology.

[0081] Figure 12B is a view showing Figure 12AA plan view of a simplified planar pattern of the shielding structure in

[0082] The solid-state imaging device 1C according to the third embodiment includes a shielding structure 55C in place of Figure 9 the shielding structure 55B of the second embodiment shown above. Other configurations are substantially similar to the corresponding configurations of the first embodiment above.

[0083] Although not shown in the figure, similar to the second embodiment above, as can be understood with reference to Figure 10 the solid-state imaging device 1C according to the third embodiment herein includes a shielding structure 55C as a shielding body located between the second semiconductor layer 50 and the third semiconductor layer 80, in place of the shielding structure 55B. The shielding structure 55C of the third embodiment herein corresponds to a specific example of the "shielding body" according to the present technology.

[0084] As Figure 12A and 12B shown, the shielding structure 55C includes a bonding pad 63 and a bonding pad 73; the bonding pad 63 is located between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10 ) and linearly extends in the X direction (first direction) in the plan view, while the bonding pad 73 is located on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63, and linearly extends in the X direction (first direction) in the plan view. In addition, different from the shielding structure 55B of the second embodiment above, the shielding structure 55C further includes a conductor 52, each conductor 52 penetrates in the thickness direction (Z direction) of the second semiconductor layer 50, overlaps with the bonding pad 63 in the plan view, and linearly extends in the X direction. The conductor 52 arranged as such can be formed by the same steps as the steps of forming the through contact electrode 51. The above conductor 52 corresponds to a specific example of the "conductor" of the present technology.

[0085] As Figure 12A and 12B shown, the shielding structure 55C has the bonding pads 63 and the bonding pads 73 repeatedly arranged at positions offset from each other in the Y direction (second direction) intersecting the X direction in the plan view. In addition, in the plan view, the portions of the bonding pad 63 and the bonding pad 73 in each adjacent pair overlap and are bonded to each other. Therefore, the shielding structure 55C also constitutes a shielding plate that combines the bonding pad 63 and the bonding pad 73 and extends two-dimensionally in the plan view. Similar to the above shielding solid film 66, the shielding structure 55C in the third embodiment herein is electrically connected to the wiring to which a potential is applied, and the potential of the shielding structure 55C is fixed to the potential applied to the wiring. In addition, the shielding structure 55C also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0086] The conductor 52 is electrically connected to the corresponding bonding pad 63 through a contact electrode. Additionally, among the multiple bonding pads 63 arranged repeatedly along the Y direction, the conductor 52 is arranged at (but not limited to) the position overlapping the bonding pad 63 arranged in the most primary stage in the plan view and the position overlapping the bonding pad 63 arranged in the final stage in the plan view.

[0087] The shielding structure 55C according to the third embodiment herein constitutes a shielding plate that combines the bonding pad 63 and the bonding pad 73 and extends two-dimensionally in the plan view. Therefore, the shielding structure 55C can reduce the noise generated during the operation of the transistor T2 in the third semiconductor layer 80 of the lower layer or the transistor T1 in the second semiconductor layer 50 of the intermediate layer and propagated from the transistor generating the band noise to other transistors, and thus can reduce the crosstalk affecting the operation of other transistors.

[0088] Furthermore, the shielding structure 55C of this embodiment includes the conductor 52 penetrating the second semiconductor layer 50. Therefore, compared with the shielding structure 55B of the second embodiment above, the shielding efficiency is improved.

[0089] Therefore, the solid-state imaging device 1C according to this embodiment can further reduce crosstalk.

[0090] <<Modification of the Third Embodiment>> In the third embodiment, it has been described that the shielding structure 55C includes the conductors 52 extending along the X direction respectively. However, the present technology is not limited to the configuration equipped with the conductors 52 extending along the X direction.

[0091] For example, as Figure 13 shown, such a configuration can be used as a shield including the conductors 53 instead of the conductors 52 extending along the X direction. Similar to the conductors 52, these conductors 53 penetrate the second semiconductor layer 50 in the thickness direction (Z direction), overlap the bonding pad 63 in the plan view, and are arranged as a plurality of conductors scattered pointwise along the X direction. In this case, each conductor 53 can have a circular or square planar shape. Additionally, the shielding efficiency in the planar direction can be further improved by arranging the conductors 53 in a staggered shape instead of a straight line. The conductors 53 configured as such can be formed by the same steps as the steps for forming the through contact electrode 51. The above-mentioned conductors 53 correspond to a specific example of the "conductor" of the present technology.

[0092] [Fourth Embodiment] Figure 14A is a vertical sectional view showing a simplified vertical sectional structure of a shielding structure mounted on a solid-state imaging device according to the fourth embodiment of the present technology. Figure 14B is a view showing Figure 14APlan view of a simplified planar pattern of the shielding structure shown.

[0093] The solid-state imaging device 1D according to the fourth embodiment of the present text includes a shielding structure 55D in place of Figure 11A and 11B the shielding structure 55B shown according to the second embodiment above. Other configurations are substantially similar to the corresponding configurations in the first embodiment above.

[0094] Similar to the second embodiment above, as can be understood with reference to Figure 10 the solid-state imaging device 1D according to the fourth embodiment of the present text includes a shielding structure 55D located between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B. The shielding structure 55D in the fourth embodiment of the present text corresponds to a specific example of the "shielding body" of the present technology.

[0095] As Figure 14A and 14B shown, the shielding structure 55D includes a bonding pad 63 and a bonding pad 73; the bonding pad 63 is located between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10 ) and linearly extends in the X direction (first direction) in the plan view, while the bonding pad 73 is located on the third semiconductor layer 80 side of the bonding pad 63 and is joined to the bonding pad 63, and linearly extends in the X direction (first direction) in the plan view. In addition, different from the shielding structure 55B of the second embodiment above, the shielding structure 55D further includes a conductor 53, the conductor 53 penetrates the second semiconductor layer 50 in the thickness direction (Z direction), overlaps with the bonding pad 63 in the plan view, and is arranged as a plurality of conductors scattered pointwise in the X direction.

[0096] The shielding structure 55D has the bonding pad 63 and the bonding pad 73 arranged at positions offset from each other in the Y direction (second direction) intersecting the X direction in the plan view. In addition, in the plan view, the portions of the bonding pad 63 and the bonding pad 73 in each adjacent pair overlap each other and are joined to each other. Therefore, the shielding structure 55D also constitutes a shielding plate that combines the bonding pad 63 and the bonding pad 73 and extends two-dimensionally in the plan view. Similar to the shielding solid film 66 above, the shielding structure 55D in the fourth embodiment of the present text is electrically connected to the wiring to which the potential is applied, and the potential of the shielding structure 55D is fixed to the potential applied to the wiring. In addition, the shielding structure 55D also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0097] The conductor 53 is electrically connected to the bonding pad 63 through the contact electrode. In addition, for each of the plurality of bonding pads 63 arranged repeatedly in the Y direction, the conductor 53 is arranged as (but not limited to) a plurality of conductors scattered pointwise in the X direction.

[0098] The solid-state imaging device 1D according to the fourth embodiment of the present disclosure also provides advantageous effects similar to those of the solid-state imaging device 1C of the third embodiment described above.

[0099] <<Modification of the Fourth Embodiment>> In the fourth embodiment, it has been described that the conductor 53 is arranged as a plurality of conductors scattered in the X direction to form the conductor included in the shielding structure. However, the present technology is not limited to the configuration in which the conductor 53 is a plurality of conductors scattered in the X direction.

[0100] For example, as Figure 15 shown, the conductor 52 linearly extending in the X direction can be combined with the conductor 53 arranged as a plurality of conductors scattered pointwise in the X direction. Such a configuration can also provide advantageous effects similar to those of the first embodiment described above. In this case, the conductor 52 corresponds to a specific example of the "first conductor" in the present technology, and the conductor 53 corresponds to a specific example of the "second conductor" in the present technology.

[0101] [Fifth Embodiment] Figure 16A FIG. is a vertical sectional view showing a simplified configuration example of a shielding structure mounted on a solid-state imaging device according to the fifth embodiment of the present technology. Figure 16B FIG. is showing Figure 16A a plan view of a simplified planar pattern of the shielding structure shown.

[0102] The solid-state imaging device 1E according to the fifth embodiment of the present disclosure includes a shielding structure 55E instead of Figure 10 the shielding structure 55B shown according to the second embodiment described above. Other configurations are substantially similar to the corresponding configurations of the first embodiment.

[0103] Although not shown in the figure, similar to the second embodiment described above, as can be understood with reference to Figure 10 the solid-state imaging device 1E according to the fifth embodiment of the present disclosure includes a shielding structure 55E as a shielding body between the second semiconductor layer 50 and the third semiconductor layer 80, instead of the shielding structure 55B. The shielding structure 55E corresponds to a specific example of the "shielding body" in the present technology.

[0104] As Figure 16A and 16BAs shown, the shielding structure 55E includes a conductor 52 that penetrates the second semiconductor layer 50 in the thickness direction (Z direction) and linearly extends in the X direction in the plan view, a bonding pad 63 provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10 ) and linearly extending in the X direction (first direction) in the plan view, and a bonding pad 73 located on the third semiconductor layer 80 side of the bonding pad 63, joined to the bonding pad 63, and linearly extending in the X direction (first direction) in the plan view.

[0105] The shielding structure 55E has the conductor 52, the bonding pad 63, and the bonding pad 73 repeatedly arranged at positions offset from each other in the Y direction intersecting the X direction in the plan view. Further, in the plan view, portions of the bonding pad 63 and the bonding pad 73 in each adjacent pair overlap each other and are joined to each other. Further, in the plan view, there is an overlap between the bonding pad 63 and the bonding pad 73 in each adjacent pair with respect to the overlapping portions of the bonding pad 63 and 73. Therefore, the shielding structure 55E constitutes a shielding plate that combines the conductor 52, the bonding pad 63, and the bonding pad 73 and two-dimensionally expands in the plan view. The conductor 52 is separated from each of the bonding pads 63 and 73. Similar to the shielding solid film 66 described above, the shielding structure 55E in the fifth embodiment of the present invention is electrically connected to a wiring to which a potential is applied, and the potential of the shielding structure 55E is fixed to the potential applied to the wiring. Further, the shielding structure 55E also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0106] The solid-state imaging device 1E according to the fifth embodiment of the present invention also provides advantageous effects similar to those of the solid-state imaging device 1C of the third embodiment described above.

[0107] [Modification Example of the Fifth Embodiment] In the fifth embodiment, it has been described that the shielding structure 55E includes the conductor 52 extending in the X direction. However, the present technology is not limited to a configuration equipped with the conductor 52 extending in the X direction. For example, as Figure 17 shown, a configuration can be adopted as the shielding structure that includes the conductor 53 arranged as a plurality of conductors discretely dispersed in the X direction, instead of the conductor 52 extending in the X direction.

[0108] [Sixth Embodiment] In the sixth embodiment of the present invention, a shielding structure including first and second bonding pads and wiring as a shielding body for blocking an electromagnetic field will be described. Figure 18A is a vertical cross-sectional view showing a simplified vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the sixth embodiment of the present technology. Figure 18B is a plan view showing Figure 18A a simplified plan pattern of the shielding structure shown.

[0109] The solid-state imaging device 1F according to the sixth embodiment herein includes a shielding structure 55F in place of Figure 10 the shielding structure 55B according to the second embodiment shown above. Other configurations are substantially similar to the corresponding configurations in the first embodiment above. Similar to the second embodiment above, as can be understood with reference to Figure 10 the solid-state imaging device 1F according to the sixth embodiment herein includes a shielding structure 55F located between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B. The shielding structure 55F corresponds to a specific example of the "shielding body" of the present technology.

[0110] As Figure 18A and 18B shown, the shielding structure 55F includes a bonding pad 63 disposed between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10 ) and linearly extending in the X direction (first direction) in the plan view, and a bonding pad 73 located on the third semiconductor layer 80 side of the bonding pad 63 and bonded to the bonding pad 63 and linearly extending in the X direction in the plan view. In addition, the shielding structure 55F further includes a wiring 72a disposed on the third semiconductor layer 80 side of the bonding pad 73 and linearly extending in the X direction in the plan view. The thus-formed wiring 72a is disposed in the fourth wiring layer 70 and is located on the third semiconductor layer 80 side with respect to the bonding pad 73.

[0111] The shielding structure 55F has bonding pads 63, 73 and wiring 72a repeatedly arranged at positions offset from each other in the Y direction (second direction) intersecting the X direction in the plan view. In addition, in the plan view, the bonding pad 63 and the bonding pad 73 in each adjacent pair overlap and are bonded to each other. In addition, in the plan view, the wiring 72a partially overlaps the bonding pads 63 and 73 between the bonding pads 63 and 73. Therefore, the shielding structure 55F constitutes a shielding plate that combines the bonding pads 63 and 73 and the wiring 72a and extends two-dimensionally in the plan view. Similar to the shielding solid film 66 above, the shielding structure 55F in the sixth embodiment herein is electrically connected to the wiring to which a potential is applied, and the potential of the shielding structure 55F is fixed to the potential applied to the wiring. In addition, the shielding structure 55F also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0112] The solid-state imaging device 1F according to the sixth embodiment herein also provides advantageous effects similar to those of the solid-state imaging device 1B of the second embodiment above.

[0113] [Seventh Embodiment] Figure 19A FIG. is a vertical cross-sectional view showing a simplified vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the seventh embodiment of the present technology. Figure 19B It shows Figure 19A A plan view of a simplified planar pattern of the shielding structure shown. The solid-state imaging device 1G according to the seventh embodiment of the present document includes a shielding structure 55G in place of Figure 10 the shielding structure 55B shown according to the second embodiment above. Other configurations are substantially similar to the corresponding configurations in the first embodiment above.

[0114] Similar to the second embodiment above, as can be understood with reference to Figure 10 the solid-state imaging device 1G according to the seventh embodiment of the present document includes a shielding structure 55G located between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B. The shielding structure 55G in the seventh embodiment of the present document corresponds to a specific example of the "shielding body" of the present technology.

[0115] As Figure 19A and 19B shown, the shielding structure 55G has a configuration in which a conductor 52 is incorporated into the shielding structure 55F of the sixth embodiment above. Each conductor 52 is electrically connected to a bonding pad 63 through a contact electrode. In addition, among the plurality of bonding pads 63 arranged repeatedly in the Y direction, the conductor 52 is provided at (but not limited to) a position overlapping the bonding pad 63 arranged in the outermost stage in a plan view and a position overlapping the bonding pad 63 arranged in the innermost stage in a plan view. In addition, the bonding pad 73 is electrically connected to the wiring 72a in the lower layer through a contact electrode. Similar to the shielding solid film 66 above, the shielding structure 55G in the seventh embodiment of the present document is electrically connected to the wiring to which a potential is applied, and the potential of the shielding structure 55G is fixed to the potential applied to the wiring. In addition, the shielding structure 55G configured as above also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0116] The solid-state imaging device 1G according to the seventh embodiment of the present document also provides advantageous effects similar to those of the solid-state imaging device 1C of the third embodiment above.

[0117] <Variations of the Seventh Embodiment> In the seventh embodiment, it has been described that the shielding structure 55G includes a conductor 52 extending in the X direction. However, the present technology is not limited to a configuration equipped with a conductor 52 extending in the X direction.

[0118] For example, as Figure 20As shown, the following configuration can be adopted. This configuration includes a conductor 53, which is similar to the conductor 52. The conductor 53 is configured to penetrate the second semiconductor layer 50 in the thickness direction (Z direction), overlap with the bonding pad 63 in the plan view, and is arranged as a plurality of conductors that are dot-like and dispersed in the X direction, instead of the conductor 52 that extends in the X direction. In this case, each conductor 53 can have a circular or square planar shape. In addition, by arranging the conductors 53 in a staggered shape instead of in a straight line, the shielding efficiency of this configuration in the planar direction can be further improved.

[0119] [Eighth Embodiment] Figure 21A FIG. is a vertical cross-sectional view showing a simplified vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the eighth embodiment of the present technology. Figure 21B FIG. shows Figure 21A a plan view of a simplified planar pattern of the shielding structure shown.

[0120] The solid-state imaging device 1H according to the eighth embodiment herein includes a shielding structure 55H, instead of Figure 10 the shielding structure 55B shown according to the second embodiment above. Other configurations are substantially similar to the corresponding configurations of the first embodiment above.

[0121] Similar to the second embodiment above, as can be understood with reference to Figure 10 the solid-state imaging device 55H according to the eighth embodiment herein includes a shielding structure 55H located between the second semiconductor layer 50 and the third semiconductor layer 80, instead of the shielding structure 55B. The shielding structure 55H in the eighth embodiment herein corresponds to a specific example of the "shielding body" of the present technology.

[0122] As Figure 21A and 21B shown, the shielding structure 55H basically has a configuration that is substantially similar to the configuration of the shielding structure 55G of the seventh embodiment above. The difference between the shielding structure 1H and the shielding structure 1G is that a conductor 52 is provided for each bonding pad 63. Similar to the shielding solid film 66 above, the shielding structure 55H in the eighth embodiment herein is electrically connected to the wiring to which a potential is applied, and the potential of the shielding structure 55H is fixed to the potential applied to the wiring. In addition, the shielding structure 55H configured as above also reduces the electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0123] The solid-state imaging device 1H according to the eighth embodiment herein also provides advantageous effects similar to those of the solid-state imaging device 1D of the fourth embodiment above.

[0124] [Modification of the Eighth Embodiment] In the eighth embodiment, it has been described that the shielding structure 55H includes the conductor 52 extending in the X direction. However, the present technology is not limited to the configuration equipped with the conductor 52 extending in the X direction.

[0125] For example, as Figure 22 shown, a configuration can be adopted which includes the conductor 53. Similar to the conductor 52, the conductor 53 is configured to penetrate the second semiconductor layer 50 in the thickness direction (Z direction), overlap with the bonding pad 63 in the plan view, and is arranged as a plurality of conductors dispersed pointwise in the X direction to replace the conductor 52 extending in the X direction. In this case, each conductor 53 can have a circular or square planar shape. In addition, the conductors 53 can be arranged in a staggered shape instead of linearly as in this modification example.

[0126] [Ninth Embodiment] Figure 23A FIG. is a vertical cross-sectional view showing a simplified vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to the ninth embodiment of the present technology. Figure 23B FIG. is showing Figure 23A a plan view of a simplified planar pattern of the shielding structure shown.

[0127] The solid-state imaging device 1I according to the ninth embodiment herein includes a shielding structure 55I to replace Figure 10 the shielding structure 55B according to the second embodiment shown above. Other configurations are substantially similar to the corresponding configurations in the first embodiment above.

[0128] Similar to the second embodiment above, as can be understood with reference to Figure 10 the solid-state imaging device 1I according to the ninth embodiment herein includes a shielding structure 55I located between the second semiconductor layer 50 and the third semiconductor layer 80 to replace the shielding structure 55B. The shielding structure 55I in the ninth embodiment herein corresponds to a specific example of the "shielding body" of the present technology.

[0129] As Figure 23A and 23B shown, the shielding structure 55I includes the conductor 52 penetrating the second semiconductor layer 50 in the thickness direction, provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10)A bonding pad 63 linearly extending in the X direction in a plan view, a bonding pad 73 located on the third semiconductor layer 80 side of the bonding pad 63, bonded to the bonding pad 63, and linearly extending in the X direction in the plan view, and a wiring 72a disposed on the third semiconductor layer 80 side with respect to the bonding pad 73 and linearly extending in the X direction in the plan view. Further, the shielding structure 55I includes a conductor 52, the bonding pad 63, the bonding pad 73, and the wiring 72a, which are repeatedly arranged at positions offset from each other in the Y direction intersecting the X direction in the plan view.

[0130] Portions of the bonding pad 63 and the bonding pad 73 in each adjacent pair overlap and are bonded to each other in the plan view. In the plan view, between the adjacent bonding pads 63 and 73, the wiring 72a overlaps with portions of the bonding pads 63 and 73. Further, in the plan view, between the adjacent bonding pads 63 and 73, each conductor 52 overlaps with portions of the bonding pads 63 and 73. In addition, the wiring 72a and the conductor 52 are alternately arranged in the Y direction in the plan view. The shielding structure 55I configured as such also constitutes a shielding plate that combines the conductor 52, the bonding pad 63, and the bonding pad 73 and extends two-dimensionally in the plan view. Further, similar to the above-described shielding solid film 66, the shielding structure 55I in the ninth embodiment of the present invention is electrically connected to a wiring to which a potential is applied, and the potential of the shielding structure 55I is fixed to the potential applied to the wiring. In addition, the shielding structure 55I configured as above also reduces an electromagnetic field propagated from one of the second semiconductor layer 50 and the third semiconductor layer 80 to the other.

[0131] Each of the conductor 52 and the wiring 72a is separated from each of the bonding pads 63 and 73 and is not electrically connected to the bonding pads 63 and 73 via a contact electrode.

[0132] The solid-state imaging device 1I according to the ninth embodiment of the present invention also provides advantageous effects similar to those of the solid-state imaging device 1D of the fourth embodiment described above.

[0133] <<Modification Example of the Ninth Embodiment>> In the ninth embodiment, it has been described that the shielding structure 55I includes a conductor 52 extending in the X direction. However, the present technology is not limited to a configuration equipped with a conductor 52 extending in the X direction.

[0134] For example, as Figure 24As shown, the following configuration can be adopted. This configuration includes a conductor 53, which is similar to the conductor 52. The conductor 53 is configured to penetrate the second semiconductor layer 50 in the thickness direction (Z direction), overlap with the bonding pad 63 in a plan view, and is arranged as a plurality of conductors that are dot-like and dispersed in the X direction, instead of the conductor 52 that extends in the X direction. In this case, each conductor 53 can have a circular or square planar shape. In addition, the conductors 53 can be arranged in a staggered shape instead of linearly as in this modification example.

[0135] [Tenth Embodiment] <1. Application Example on an Electronic Device> Next, the Figure 25 electronic device 100 according to the tenth embodiment of the present technology shown will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. For example, the electronic device 100 is, but not limited to, an electronic device such as a camera. In addition, the electronic device 100 includes the above-mentioned solid-state imaging device 1A as the solid-state imaging device 101.

[0136] The optical lens (optical system) 102 forms an image of the image light (incident light 106) received from the subject on the imaging surface of the solid-state imaging device 101. Therefore, signal charges are accumulated in the solid-state imaging device 101 for a fixed period. The shutter device 103 controls the light-receiving period and the light-shielding period of the solid-state imaging device 101. The drive circuit 104 provides drive signals for controlling the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The signal transfer of the solid-state imaging device 101 is performed according to the drive signals (timing signals) provided by the drive circuit 104. The signal processing circuit 105 performs various types of signal processing on the signals (pixel signals) output from the solid-state imaging device 101. The video signal obtained through signal processing is stored in a storage medium such as a memory or output to a monitor.

[0137] The electronic device 100 configured as above reduces crosstalk by using the solid-state imaging device 101. Therefore, the reliability of the electronic device 100 can be improved.

[0138] In addition, the electronic device 100 is not limited to a camera and can also be other types of electronic devices. For example, the electronic device 100 can also be an imaging device such as a camera module for a mobile phone or other mobile devices.

[0139] Furthermore, as the solid-state imaging device 101, the electronic device 100 can include the light detection device 1 according to the first embodiment or its modification example, or a combination of at least two of the first embodiment and its modification examples.

[0140] <2. Application Examples on Moving Bodies>

[0141] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of moving body selected from automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, and the like.

[0142] Figure 26 It is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0143] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 26 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0144] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for devices such as a driving force generation device (e.g., an internal combustion engine, a drive motor, etc.) for generating vehicle driving force, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating vehicle braking force.

[0145] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for devices such as a keyless entry system, a smart key system, an electric window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, or a fog light. In this case, radio waves or signals from various switches sent from a portable device serving as a key substitute can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle door lock device, the electric window device, or the vehicle lights.

[0146] The vehicle external information detection unit 12030 detects external information about a vehicle including the vehicle control system 12000. For example, the vehicle external information detection unit 12030 is connected to the imaging unit 12031. The vehicle external information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle external information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, or characters on the road surface, or processing for detecting their distances.

[0147] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the received light amount. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measurement distance information. Additionally, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light or the like.

[0148] The vehicle interior information detection unit 12040 detects internal information about the vehicle. For example, the vehicle interior information detection unit 12040 is connected to the driver state detection unit 12041 for detecting the driver's state. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or the driver's attention concentration level, or can determine whether the driver is dozing off.

[0149] The microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device based on the information about the interior and exterior of the vehicle obtained by the vehicle external information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), including vehicle collision avoidance or shock absorption, following driving based on the vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0150] In addition, based on the environmental information about the vehicle obtained by the vehicle external information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform coordinated control for autonomous driving by controlling the driving force generation device, the steering mechanism, or the braking device, etc., so that the vehicle can automatically drive without relying on the driver's operation, etc.

[0151] In addition, the microcomputer 12051 can output a control command to the vehicle body system control unit 12030 based on the external information of the vehicle acquired by the vehicle external information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control for preventing glare by controlling the vehicle headlamp to change from high beam to low beam according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle external information detection unit 12030, for example.

[0152] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of notifying information visually or auditorily to vehicle occupants or the outside of the vehicle. In Figure 22 the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. The display unit 12062 can include, for example, at least one of an in-vehicle display and a head-up display.

[0153] Figure 27 is a diagram showing an example of the installation position of the imaging unit 12031. In Figure 27 the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0154] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the rearview mirror, the rear bumper, the rear door, and the upper part of the windshield inside the vehicle, for example. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or the rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal lamp, a traffic sign, or a lane, etc.

[0155] Note that Figure 27 shows an example of the imaging range of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0156] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0157] For example, the microcomputer 12051 may determine the distance and the temporal change of the distance (relative speed with respect to the vehicle 12100) of each three-dimensional object within the imaging ranges 12111 to 12114 based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as a preceding vehicle, which particularly exists on the traveling path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, the microcomputer 12051 can preset a following distance to be maintained in front of the preceding vehicle, and execute automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, coordinated control for autonomous driving can be executed so that the vehicle can automatically travel without relying on the operations of the driver or the like.

[0158] For example, the microcomputer 12051 may classify the three-dimensional object data of the three-dimensional objects into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to be visually recognized by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk for indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and executes forced deceleration or avoidance steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0159] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, through the following processes: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the object contour. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to superimpose and display a square contour line for emphasis on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 to display an icon or the like for indicating the pedestrian at a desired position.

[0160] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the above-described plurality of electronic control units and the imaging unit 12031 proposed in the above configuration. Specifically, each shielding body (shielding solid film and shielding structure) according to the first to ninth embodiments described above can be applied to the above-described plurality of electronic control units and the imaging unit 12031. By applying the technology according to the present disclosure to the electronic control units and the imaging unit 12031, crosstalk can be reduced. Therefore, the reliability of the electronic control units and the imaging unit 12031 can be improved.

[0161] <3. Application Example on Endoscopic Surgery System> The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0162] Figure 28 is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to the present disclosure (this technology) can be applied.

[0163] In Figure 28 it shows a state in which a surgical operator (doctor) 11131 is performing surgery on a patient 11132 on a hospital bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100 thereon, and a cart 11200 on which various endoscopic surgery devices are mounted.

[0164] The endoscope 11100 includes an endoscope tube 11101 and a camera 11102 connected to the proximal end of the endoscope tube 11101. An area of the endoscope tube 11101 having a predetermined length starting from its distal end is inserted into the body cavity of the patient 11132. In the illustrated example, the endoscope 11100 is shown as including a rigid endoscope including a rigid endoscope tube 11101. However, the endoscope 11100 can also be a flexible endoscope including a flexible endoscope tube 11101.

[0165] The endoscope tube 11101 has an opening at its distal end, and an objective lens is fitted in the opening. A light source device 11203 is connected to the endoscope 11100 such that light generated by the light source device 11203 is introduced into the distal end of the endoscope tube 11101 through an optical fiber extending inside the endoscope tube 11101 and is irradiated through the objective lens toward an observation target in the body cavity of the patient 11132. It should be noted that the endoscope 11100 can be a forward-viewing endoscope, or can be an oblique-viewing endoscope or a side-viewing endoscope.

[0166] An optical system and an image pickup element are provided inside the camera 11102 such that reflected light (observation light) from the observation target is converged on the image pickup element through the optical system. The observation light is subjected to photoelectric conversion by the image pickup element to generate an electric signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as raw data.

[0167] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and overall controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives the image signal from the camera 11102 and performs various image processing such as development processing (demosaicing processing) on the image signal to display an image based on the image signal.

[0168] Under the control of the CCU 11201, the display device 11202 displays an image thereon based on the image signal on which the CCU 11201 has performed image processing.

[0169] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and provides irradiation light to the endoscope 11100 when imaging the surgical area.

[0170] The input device 11204 is an input interface of the endoscopic surgery system 11000. A user can input various types of information or instructions into the endoscopic surgery system 11000 through the input device 11204. For example, the user can input an instruction for changing the image pickup conditions (type of irradiation light, magnification factor, focal length, etc.) of the endoscope 11100.

[0171] The treatment tool control device 11205 controls the driving of the energy device 11112 for cauterizing tissue, cutting tissue, sealing blood vessels, etc. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the visual field of the endoscope 11100 and ensuring the working space for the surgery. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device - that can print various information related to the surgery in various forms such as text, images, and charts.

[0172] It should be noted that, for example, the light source device 11203 that provides illumination light to the endoscope 11100 when imaging the surgical area may include a white light source, which, for example, includes an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. Additionally, in this case, if the laser beams from the RGB laser light sources are irradiated to the observation target in a time-division manner and the driving of the image capture element of the camera 11102 is controlled in synchronization with the emission timing, images corresponding to RGB can be captured in a time-division manner. According to this method, a color image can be obtained even without setting a color filter for the image capture element.

[0173] Furthermore, the light source device 11203 can be controlled such that the intensity of the output light changes every predetermined period of time. By controlling the driving of the image capture element of the camera 11102 in synchronization with the changing timing of the light intensity to obtain images in a time-division manner and synthesize the images, a high-dynamic-range image without underexposure occlusion shadows and overexposure highlights can be generated.

[0174] In addition, the light source device 11203 may be configured to provide light having a predetermined wavelength region prepared for specific light observation. In specific light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue, light having a narrower band than the illumination light (i.e., white light) during normal observation is irradiated, and imaging (narrow-band imaging) is performed for a predetermined tissue such as blood vessels in the surface portion of the mucosal layer having high contrast. Alternatively, in specific light observation, fluorescence observation for obtaining an image based on fluorescence generated by irradiation with excitation light may be performed. In fluorescence observation, observation of fluorescence from body tissue (autofluorescence observation) may be performed by irradiating body tissue, or a fluorescence image may be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 may be configured to provide narrow-band light and / or excitation light suitable for the specific light observation described above.

[0175] Figure 29 is a diagram showing Figure 28 a functional configuration example of the illustrated camera 11102 and CCU 11201.

[0176] The camera 11102 includes a lens unit 11401, an image capturing unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 to communicate with each other.

[0177] The lens unit 11401 is an optical system provided at a position connected to the lens barrel 11101. Observation light obtained from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses, which include a zoom lens and a focusing lens.

[0178] The number of image capture elements included in the image capture unit 11402 may be one (single-board type) or more (multi-board type). In the case where the image capture unit 11402 is configured as a multi-board type, for example, image signals corresponding to R, G, and B are generated by the image capture elements, and a color image can be obtained by synthesizing these image signals. The image capture unit 11402 may also be configured to have a pair of image capture elements for obtaining a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If 3D display is performed, the surgical operator 11131 can more accurately perceive the depth of the body tissue at the surgical site. It should be noted that in the case where the image capture unit 11402 is configured as a multi-board type, a plurality of systems of lens units 11401 can be provided in a manner corresponding to the respective image capture elements.

[0179] In addition, the image capture unit 11402 may not necessarily be provided in the camera 11102. For example, the image capture unit 11402 may be provided immediately after the objective lens inside the lens barrel 11101.

[0180] The drive unit 11403 includes an actuator, and under the control of the camera control unit 11405, the drive unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance. Therefore, the magnification and focus of the image captured by the image capture unit 11402 can be appropriately adjusted.

[0181] The communication unit 11404 includes a communication device for transmitting / receiving various information to / from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the image capture unit 11402 as raw data to the CCU 11201 through the transmission cable 11400.

[0182] In addition, the communication unit 11404 receives a control signal for controlling the drive of the camera 11102 from the CCU 11201 and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, and the image capture conditions are, for example, information for specifying the frame rate of the captured image, information for specifying the exposure value at the time of image capture, and / or information for specifying the magnification and focus of the captured image.

[0183] It should be noted that image capture conditions such as the frame rate, exposure value, magnification, and focus can be appropriately specified by the user or automatically set by the control unit 11413 of the CCU 11201 based on the obtained image signal. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are combined in the endoscope 11100.

[0184] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0185] The communication unit 11411 includes communication means for transmitting / receiving various types of information to / from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 through the transmission cable 11400.

[0186] In addition, the communication unit 11411 transmits the control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0187] The image processing unit 11412 performs various image processes on the image signal transmitted from the camera 11102 in the form of raw data.

[0188] The control unit 11413 performs various types of control related to the image capturing of the surgical area, etc. performed by the endoscope 11100 and the display of the captured images obtained through the image capturing of the surgical area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102.

[0189] In addition, the control unit 11413 controls the display device 11202 to display the captured image for depicting the surgical area, etc. based on the image signal on which the image processing unit 11412 has performed image processing. At this time, the control unit 11413 can identify various objects in the captured image by using various image recognition techniques. For example, the control unit 11413 can identify surgical tools such as forceps, specific living body parts, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edges of the objects included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can display various surgical assistance information in a manner superimposed on the image of the surgical area by using the recognition result. By displaying the surgical assistance information in a superimposed manner and presenting it to the surgical operator 11131, the burden on the surgical operator 11131 can be reduced, or the surgeon 11131 can perform the surgery more reliably.

[0190] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 to each other is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable for both electrical communication and optical communication.

[0191] Here, in the illustrated example, although communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 can be performed by wireless communication.

[0192] An example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the CCU 11201 and the image capturing unit 11402 of the camera 11102 in the above configuration. Specifically, each of the shielding bodies (shielding solid films and shielding structures) according to the first to ninth embodiments described above can be applied to the CCU 11201 and the image capturing unit 10402. By applying the technology according to the present disclosure to the CCU 11201 and the image capturing unit 10402, the reliability of the CCU 11201 and the image capturing unit 10402 can be improved.

[0193] Although the endoscopic surgical system has been described herein by way of example, the technology according to the present disclosure can be applied to other systems, such as a microsurgical system.

[0194] [Other Embodiments] Although the present technology has been described above based on the first to ninth embodiments, it should not be considered that the statements and drawings forming a part of the present disclosure impose limitations on the present technology. Those skilled in the art will be clear about various alternative embodiments, examples, and operation techniques according to the present disclosure.

[0195] In addition, the present technology can be generally applied to optical detection devices, such as distance measurement sensors (also referred to as ToF (Time of Flight) sensors) and solid-state imaging devices constituting the above image sensors. A distance measurement sensor is a sensor that emits irradiation light toward an object, detects the reflected light (i.e., the irradiation light reflected from the surface of the object and returned), and calculates the distance to the object based on the time of flight from the emission of the irradiation light to the reception of the reflected light. The structures of the above first conductor and second conductor can both be used as the structure of the distance measurement sensor. In addition, the present technology can be applied to semiconductor devices other than optical detection devices.

[0196] Please note that the present technology can also adopt the following configuration. (1) An optical detection device, comprising: A first semiconductor layer having a first surface and a second surface located at opposite positions, and including a photoelectric conversion portion for photoelectrically converting light entering from the second surface side; A second semiconductor layer including a transistor and disposed on the first surface side of the first semiconductor layer; A third semiconductor layer including a transistor and disposed on a side opposite to the first semiconductor layer side of the second semiconductor layer and overlapping the second semiconductor layer; and A shielding body is disposed between the second semiconductor layer and the third semiconductor layer. (2) The optical detection device according to (1) above, wherein the shielding body blocks an electromagnetic field propagating from one of the second semiconductor layer and the third semiconductor layer to the other. (3) The optical detection device according to (1) or (2) above, wherein in a plan view, the shielding body selectively overlaps with a circuit block including transistors of at least one of the second semiconductor layer and the third semiconductor layer. (4) The optical detection device according to any one of (1) to (3) above, wherein the shielding body is a shielding solid film having a plate-like shape and extending two-dimensionally. (5) The optical detection device according to any one of (1) to (4) above, wherein the shielding solid film is fixed on a surface of the second semiconductor layer on the third semiconductor layer side with a fixed charge film interposed therebetween. (6) The optical detection device according to any one of (1) to (5) above, wherein the shielding solid film is electrically connected to a wiring to which a potential is applied. (7) The optical detection device according to any one of (1) to (6) above, further comprising: A through contact electrode that penetrates the second semiconductor layer in a thickness direction and penetrates an opening in the shielding solid film; A first bonding pad disposed between the second semiconductor layer and the third semiconductor layer; and A second bonding pad disposed on the third semiconductor layer side of the first bonding pad and bonded to the first bonding pad, wherein at least one of the first bonding pad and the second bonding pad has a planar dimension sufficient to overlap the entire opening in a plan view. (8) The optical detection device according to (4) above, further comprising: A first wiring layer disposed on the third semiconductor layer side of the second semiconductor layer and including the shielding solid film and the first bonding pad; and A second wiring layer located on the second semiconductor layer side of the third semiconductor layer and bonded to the first wiring layer and including the second bonding pad. (9) The optical detection device according to (1) above, wherein the shielding body is a shielding structure, and the shielding structure includes: A first bonding pad disposed between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view; and A second bonding pad, which is located on the third semiconductor layer side of the first metal pad and is bonded to the first bonding pad, and extends in the first direction in a plan view, and The shielding structure is configured such that a set of the first bonding pad and the second bonding pad located at positions relatively offset from each other in a second direction intersecting the first direction are repeatedly arranged. (10) The optical detection device according to (9) above, wherein the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps with the first metal pad in a plan view, and extends in the first direction. (11) The optical detection device according to (9) above, wherein the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps with the first metal pad in a plan view, and is arranged as a plurality of conductors dispersed in the first direction. (12) The optical detection device according to (9) above, wherein the shielding structure further includes: A first conductor that penetrates the second semiconductor layer in a thickness direction, overlaps with the first bonding pad in a plan view, and extends in the first direction; and A second conductor that penetrates the second semiconductor layer in the thickness direction, overlaps with the first bonding pad in a plan view, and is arranged as a plurality of conductors dispersed in the first direction. (13) The optical detection device according to (1) above, wherein the shield is a shielding structure, and the shielding structure includes: A conductor that penetrates the second semiconductor layer in a thickness direction; A first bonding pad that is provided between the second semiconductor layer and the third semiconductor layer and extends in a first direction in a plan view; and A second bonding pad, which is located on the third semiconductor layer side of the first metal pad and is bonded to the first bonding pad, and extends in the first direction in a plan view, and The shielding structure is configured such that a set of the conductor, the first bonding pad, and the second bonding pad located at positions relatively offset from each other in a second direction intersecting the first direction in a plan view are repeatedly arranged. (14) The optical detection device according to (13) above, wherein the conductor forms a strip shape extending in the first direction in a plan view. (15) The optical detection device according to (13) above, wherein the conductor is arranged as a plurality of conductors dispersed in the first direction in a plan view. (16) The optical detection device according to (1) above, wherein the shielding body is a shielding structure, and the shielding structure includes: A first bonding pad, which is disposed between the second semiconductor layer and the third semiconductor layer and extends in a first direction in a plan view; A second bonding pad, which is located on the third semiconductor layer side of the first metal pad and is bonded to the first bonding pad, and extends in the first direction in a plan view; and A wiring, which is disposed on the third semiconductor layer side with respect to the second bonding pad and extends in the first direction in a plan view, and The shielding structure is configured such that a set of the first bonding pad, the second bonding pad, and the wiring, which are located at positions offset from each other in a second direction intersecting the first direction in a plan view, are repeatedly arranged. (17) The optical detection device according to (16) above, wherein the shielding structure further includes a conductor, the conductor penetrates the second semiconductor layer in a thickness direction, overlaps with the first metal pad in a plan view, and extends in the first direction in a plan view. (18) The optical detection device according to (16) above, wherein the shielding structure further includes a conductor, the conductor penetrates the second semiconductor layer in a thickness direction, overlaps with the first metal pad in a plan view, and is arranged as a plurality of conductors dispersed in the first direction in a plan view. (19) The optical detection device according to (1) above, wherein the shielding body is a shielding structure, and the shielding structure includes: A conductor, which penetrates the second semiconductor layer in a thickness direction; A first bonding pad, which is disposed between the second semiconductor layer and the third semiconductor layer and extends in a first direction in a plan view; A second bonding pad, which is located on the third semiconductor layer side of the first metal pad and is bonded to the first bonding pad, and extends in the first direction in a plan view; and A wiring, which is disposed on the third semiconductor layer side with respect to the second bonding pad and extends in the first direction in a plan view, and The shielding structure is configured such that a set of the conductor, the first bonding pad, the second bonding pad, and the wiring, which are located at positions offset from each other in a second direction intersecting the first direction in a plan view, are repeatedly arranged. (20) The optical detection device according to (19) above, wherein the conductor forms a strip shape extending in the first direction in a plan view. (21) The optical detection device according to (19) above, wherein the conductors are arranged as a plurality of conductors dispersed in the first direction in a plan view. (22) An electronic device, comprising: The optical detection device according to any one of (1) to (21); An optical lens that forms an image of image light received from a subject on an imaging surface of the optical detection device; and A signal processing circuit that performs signal processing on a signal output from the optical detection device.

[0197] The scope of the present technology is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide advantageous effects corresponding to the purpose of the present technology. In addition, the scope of the present technology is not limited to the combination of inventive features defined in the claims, and may be defined by any desired combination of specific features included in all the disclosed features. List of reference numerals

[0198] 1A to 1I: Solid-state imaging device 2: Semiconductor chip 2A: Sensor pixel array section 2B: Peripheral section 3: Sensor pixel 4: Vertical drive circuit 5: Column signal processing circuit 6: Horizontal drive circuit 7: Output circuit 8: Control circuit 10: Pixel drive line 11: Vertical signal line 12: Horizontal signal line 13: Logic circuit 14: Pad 15: Pixel circuit 20: First semiconductor layer 21: Photoelectric conversion region 30: First wiring layer 32: Wiring 40: Second wiring layer 41: Insulating film 42: Wiring 50: Second semiconductor layer 51: Through contact electrode 52, 53: Conductors 55B to 55I: Shielding structure 60: Third wiring layer 62: Wiring 63: Bonding pad 70: Fourth wiring layer 72, 72a: Wiring 73: Bonding pad 80: Third semiconductor layer 90: Light collection layer 91: Color filter 92: On-chip lens 100: Electronic device 101: Solid-state imaging device 102: Optical system (optical lens) 103: Shutter device 104: Driving circuit 105: Signal processing circuit.

Claims

1. A light detection device, comprising: A first semiconductor layer having a first surface and a second surface located at opposite positions, and including a photoelectric conversion portion for photoelectrically converting light incident from the second surface side; A second semiconductor layer including a transistor and disposed on the first surface side of the first semiconductor layer; A third semiconductor layer including a transistor and disposed on a side opposite to the first semiconductor layer side of the second semiconductor layer and overlapping the second semiconductor layer; And A shield disposed between the second semiconductor layer and the third semiconductor layer.

2. The optical detection device according to claim 1, wherein, The shield blocks an electromagnetic field propagating from one of the second semiconductor layer and the third semiconductor layer to the other.

3. The optical detection device according to claim 1, wherein, In a plan view, the shield selectively overlaps a circuit block including the transistor of at least one of the second semiconductor layer and the third semiconductor layer.

4. The optical detection device according to claim 1, wherein, The shield is a shield solid film having a plate-like shape and two-dimensionally extending.

5. The optical detection device according to claim 4, wherein, The shield solid film is fixed on a surface of the second semiconductor layer on the third semiconductor layer side via a fixed charge film.

6. The optical detection device according to claim 4, wherein The shield solid film is electrically connected to a wiring to which a potential is applied.

7. The light detection device according to claim 4, further comprising: A through contact electrode penetrating the second semiconductor layer in a thickness direction and penetrating an opening in the shield solid film; A first bonding pad disposed between the second semiconductor layer and the third semiconductor layer; And A second bonding pad disposed on the third semiconductor layer side of the first bonding pad and bonded to the first bonding pad, wherein At least one of the first bonding pad and the second bonding pad has a planar dimension sufficient to overlap the entire opening in a plan view.

8. The light detection device according to claim 4, further comprising: A first wiring layer disposed on the third semiconductor layer side of the second semiconductor layer and including the shield solid film and the first bonding pad; And A second wiring layer located on the second semiconductor layer side of the third semiconductor layer and bonded to the first wiring layer and including the second metal pad.

9. The optical detection device according to claim 1, wherein, The shield is a shield structure, the shield structure including: A first bonding pad disposed between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view; and A second bonding pad located on the third semiconductor layer side of the first metal pad and bonded to the first bonding pad and extending in the first direction in a plan view, and The shield structure is configured such that a set of the first bonding pad and the second bonding pad located at positions relatively offset from each other in a second direction intersecting the first direction are repeatedly arranged.

10. The optical detection device according to claim 9, wherein, The shield structure further includes a conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first metal pad in a plan view, and extending in the first direction.

11. The optical detection device according to claim 9, wherein, The shielding structure further includes a conductor that penetrates the second semiconductor layer in the thickness direction, overlaps with the first metal pad in a plan view, and is arranged as a plurality of conductors dispersed in the first direction.

12. The optical detection device according to claim 9, wherein, The shielding structure further includes: a first conductor that penetrates the second semiconductor layer in the thickness direction, overlaps with the first bonding pad in a plan view, and extends in the first direction; and a second conductor that penetrates the second semiconductor layer in the thickness direction, overlaps with the first bonding pad in a plan view, and is arranged as a plurality of conductors dispersed in the first direction.

13. The optical detection device according to claim 1, wherein, The shield is a shielding structure, and the shielding structure includes: a conductor that penetrates the second semiconductor layer in the thickness direction; a first bonding pad that is provided between the second semiconductor layer and the third semiconductor layer and extends in a first direction in a plan view; and a second bonding pad that is located on the third semiconductor layer side of the first metal pad and is joined to the first bonding pad and extends in the first direction in a plan view, and the shielding structure is configured such that a set of the conductor, the first bonding pad, and the second bonding pad located at positions relatively offset from each other in a second direction intersecting the first direction in a plan view are repeatedly arranged.

14. The optical detection device according to claim 13, wherein, The conductor forms a strip shape extending in the first direction in a plan view.

15. The optical detection device according to claim 13, wherein, The conductor is arranged as a plurality of conductors dispersed in the first direction in a plan view.

16. The optical detection device according to claim 1, wherein, The shield is a shielding structure, and the shielding structure includes: a first bonding pad that is provided between the second semiconductor layer and the third semiconductor layer and extends in a first direction in a plan view; a second bonding pad that is located on the third semiconductor layer side of the first metal pad and is joined to the first bonding pad and extends in the first direction in a plan view; and a wiring that is provided on the third semiconductor layer side with respect to the second bonding pad and extends in the first direction in a plan view, and the shielding structure is configured such that a set of the first bonding pad, the second bonding pad, and the wiring located at positions relatively offset from each other in a second direction intersecting the first direction in a plan view are repeatedly arranged.

17. The optical detection device according to claim 16, wherein, The shielding structure further includes a conductor that penetrates the second semiconductor layer in the thickness direction, overlaps with the first metal pad in a plan view, and extends in the first direction in a plan view.

18. The optical detection device according to claim 16, wherein, The shielding structure further includes a conductor that penetrates the second semiconductor layer in the thickness direction, overlaps with the first metal pad in a plan view, and is arranged as a plurality of conductors dispersed in the first direction in a plan view.

19. The optical detection device according to claim 1, wherein, The shield is a shielding structure, and the shielding structure includes: a conductor that penetrates the second semiconductor layer in the thickness direction; a first bonding pad that is provided between the second semiconductor layer and the third semiconductor layer and extends in a first direction in a plan view; A second bonding pad, which is located on the third semiconductor layer side of the first metal pad and is bonded to the first bonding pad, and extends in the first direction in a plan view; and A wiring, which is disposed on the third semiconductor layer side with respect to the second bonding pad, and extends in the first direction in a plan view, and The shielding structure is configured such that a set of the conductors, the first bonding pad, the second bonding pad, and the wiring, which are located at positions offset from each other in a second direction intersecting the first direction in a plan view, are repeatedly arranged.

20. The optical detection device according to claim 19, wherein, The conductors form a strip shape extending in the first direction in a plan view.

21. The optical detection device according to claim 19, wherein, The conductors are arranged as a plurality of conductors dispersed in the first direction in a plan view.

22. An electronic device, comprising: A light detection device; An optical lens, which forms an image of image light received from a subject on an imaging surface of the light detection device; And A signal processing circuit, which performs signal processing on a signal output from the light detection device, wherein, The light detection device includes: A first semiconductor layer, which has a first surface and a second surface located at opposite positions, and includes a photoelectric conversion portion for photoelectrically converting light entering from the second surface side; A second semiconductor layer, which includes a transistor, and is disposed on the first surface side of the first semiconductor layer; A third semiconductor layer, which includes a transistor, and is disposed on the side opposite to the first semiconductor layer side of the second semiconductor layer and overlaps the second semiconductor layer; and A shield, which is disposed between the second semiconductor layer and the third semiconductor layer.

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