Test method convenient for monitoring and testing interlayer withstand voltage

Abstract

A PCB test method convenient for monitoring and testing interlayer withstand voltage comprises n PCBs, two ends of the n PCBs are provided with positioning holes, so that the n PCBs are stacked through the positioning holes and form an L1 layer, an L2 layer, an L3 layer, an Ln-2 layer, an Ln-1 layer and an Ln layer in sequence from top to bottom, and the L1 layer, the L2 layer, the L3 layer, the Ln-2 layer, the Ln-1 layer and the Ln layer are stacked through the positioning holes. N test holes are formed in the n stacked PCBs (Printed Circuit Board); the numbers of the n test holes are n, n-1, n-2, n-3, n-4, 2 and 1; wherein the test hole with the number n in the L1 layer is communicated with the test hole with the number n in the Ln layer, the test hole with the number n-1 in the L1 layer is communicated with the test hole with the number n-1 in the Ln-1 layer, and the test hole with the number 2 in the L1 layer is communicated with the test hole with the number 2 in the L2 layer.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuits, and specifically to a test method for facilitating the monitoring and testing of the interlayer withstand voltage. Background Art

[0002] In view of the monitoring and testing of the interlayer withstand voltage of the finished PCB in the PCB factory after processing, the previous method of finding points within the board for measurement has low efficiency, requires manual measurement, and takes a long time, and cannot measure in batches and quickly. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a test method that can solve the problems of low efficiency of finding points within the board for the interlayer withstand voltage test of the PCB, requiring manual measurement and taking a long time, and being unable to measure in batches and quickly.

[0004] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0005] A PCB test method for facilitating the monitoring and testing of the interlayer withstand voltage, including n PCB boards. Positioning holes are provided at both ends of the n PCB boards, so that the n PCB boards are stacked through the positioning holes and form layers L1, L2, L3,..., Ln-2, Ln-1, Ln from top to bottom in sequence;

[0006] n test holes are provided on the stacked n PCB boards; the numbers of the n test holes are n, n-1, n-2, n-3, n-4,..., 2, 1;

[0007] Among them, the test hole numbered n in layer L1 is communicated with the test hole numbered n in layer Ln, the test hole numbered n-1 in layer L1 is communicated with the test hole numbered n-1 in layer Ln-1,..., and the test hole numbered 2 in layer L1 is communicated with the test hole numbered 2 in layer L2.

[0008] In one embodiment, copper foils are provided on each layer of the inner layers of the stacked n PCB boards.

[0009] In one embodiment, the size of the copper foil is 6*10 mm.

[0010] In one embodiment, the aperture of the test hole is 0.8 mm.

[0011] In one embodiment, the aperture of the positioning hole is 3.2 mm.

[0012] In one embodiment, the connection between the two test holes is communicated through a 16-mil trace.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] The present invention can solve the problems that the efficiency of finding points and measuring inside the PCB interlayer withstand voltage test board is low, manual measurement is required, the time consumption is long, and batch and rapid measurement cannot be carried out. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic structural diagram of Embodiment 1 of the present invention;

[0016] Figure 2 For the present invention Figure 1 multi-layer structural schematic diagram.

[0017] In the figure: 1. PCB board, 2. positioning hole, 3. test hole. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Embodiment 1

[0020] As Figure 1-2 shown, this embodiment includes n PCB boards 1; in this embodiment, n is 6, that is, 6 PCB boards;

[0021] Positioning holes 2 are provided at both ends of the n PCB boards 1, so that the n PCB boards 1 are stacked through the positioning holes 2 and form L1, L2, L3,..., Ln-2, Ln-1, Ln layers from top to bottom; in this embodiment, positioning holes 2 are provided at both ends of the 6 PCB boards; so that the 6 PCB boards 1 are stacked through the positioning holes 2 and form L1, L2, L3, L4, L5, L6 layers from top to bottom;

[0022] n test holes 3 are provided on the stacked n PCB boards 1; the numbers of the n test holes 3 are n, n-1, n-2, n-3, n-4,..., 2, 1; in this embodiment, 6 test holes 3 are provided on the stacked 6 PCB boards 1; the numbers of the 6 test holes 3 are 6, 5, 4, 3, 2, 1;

[0023] Among them, the test hole 3 numbered n in the L1 layer is communicated with the test hole 3 numbered n in the Ln layer, the test hole 3 numbered n-1 in the L1 layer is communicated with the test hole 3 numbered n-1 in the Ln-1 layer,..., the test hole 3 numbered 2 in the L1 layer is communicated with the test hole 3 numbered 2 in the L2 layer;

[0024] That is, in this embodiment, the test hole 3 numbered (2) in the L1 layer is connected to the test hole 3 numbered (2) in the L2 layer, the test hole 3 numbered (3) in the L1 layer is connected to the test hole 3 numbered (2) in the L3 layer, the test hole 3 numbered (4) in the L1 layer is connected to the test hole 3 numbered (4) in the L4 layer, the test hole 3 numbered (5) in the L1 layer is connected to the test hole 3 numbered (5) in the L5 layer, and the test hole 3 numbered (6) in the L1 layer is connected to the test hole 3 numbered (6) in the L6 layer;

[0025] Measurement method: Select the test points between adjacent two layers, and the numbers correspond to the test points of which layer; Measure the test points of L1-L2, L2-L3, L3-L4, L4-L5, and L5-L6 in sequence; After measuring two by two as described above, if the medium is broken down by voltage, resulting in board burning and a conducting path, it is determined that the withstand voltage fails; On the contrary, if there is no abnormality under the specified voltage, the withstand voltage test is passed and it is judged as qualified;

[0026] In this embodiment, each layer of the inner layer of the stacked n PCB boards 1 is provided with a copper foil; The size of the copper foil is 6*10mm.

[0027] In this embodiment, the aperture of the test hole 3 is 0.8mm, the aperture of the positioning hole is 3.2mm, and the connection between the two test holes 3 is connected through a 16mil trace.

[0028] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; Although the technical solutions of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A PCB testing method for monitoring and testing interlayer withstand voltage, characterized in that: It comprises n PCB boards (1), both ends of the n PCB boards (1) are provided with positioning holes (2), so that the n PCB boards (1) are stacked through the positioning holes (2) and form L1, L2, L3, Ln-2, ​​Ln-1, Ln layers in sequence from top to bottom; The n stacked PCB boards (1) are provided with n test holes (3); the n test holes (3) are numbered n, n-1, n-2, n-3, n-4, ..., 2, 1; Among them, the test hole (3) numbered n in the L1 layer is connected with the test hole (3) numbered n in the Ln layer, the test hole (3) numbered n-1 in the L1 layer is connected with the test hole (3) numbered n-1 in the Ln-1 layer, and so on. The test hole (3) numbered 2 in the L1 layer is connected with the test hole (3) numbered 2 in the L2 layer.

2. The PCB testing method for monitoring and testing the interlayer withstand voltage according to claim 1 is characterized in that: Each inner layer of the n stacked PCB boards (1) is provided with a copper sheet.

3. The PCB testing method for monitoring and testing interlayer withstand voltage according to claim 1, characterized in that: The copper sheet has a size of 6*10 mm.

4. The PCB testing method for monitoring and testing the interlayer withstand voltage according to claim 1, characterized in that: The diameter of the test hole (3) is 0.8 mm.

5. The PCB testing method for monitoring and testing the interlayer withstand voltage according to claim 4 is characterized in that: The diameter of the positioning hole is 3.2 mm.

6. The PCB testing method for monitoring and testing interlayer withstand voltage according to claim 1, characterized in that: The two test holes (3) are connected via a 16 mil wiring.

Images