Multi-channel driving circuit and laser radar

Abstract

A multichannel drive circuit and a laser radar belong to the technical field of electronic circuits, and are characterized in that a first control signal is accessed through a first drive circuit, and the first control signal is converted into a first drive signal; the first switch tube is connected with a first power supply voltage and outputs the first power supply voltage to the light source according to the first driving signal so as to lighten the light source; the semiconductor device performs reverse cut-off on the first power supply voltage, accesses a second power supply voltage, and outputs the second power supply voltage to the light source so as to lighten the light source; wherein the first power supply voltage is greater than the second power supply voltage; therefore, the accuracy and reliability of distance measurement are improved while the dynamic distance measurement range of the vehicle-mounted laser radar is expanded.

Description

Technical Field

[0001] This application belongs to the technical field of electronic circuits, and particularly relates to a multi-channel drive circuit and a lidar. Background Art

[0002] With the development of lidar technology, the demand for laser distance measurement in vehicle-mounted main radars or intelligent networked applications is increasing. Some lidars hope to reduce the transmitted optical power for close-range strong reflection surfaces to solve the problem of inaccurate ranging timing, while some lidars hope to increase the transmitted optical power for long-range low reflection surfaces to enhance the ranging ability; especially vehicle-mounted lidars not only need to measure farther but also need to measure closer, reduce blind spots, and increase the ranging field of view, which means that during the ranging process of vehicle-mounted lidars, the output optical power needs to be dynamically changed. Related technical solutions often adjust the transmitted optical power by changing the capacitor charging time, or achieve encoded light emission of strong and weak light by changing the laser discharge pulse width during constant voltage power supply.

[0003] In the first above-mentioned technical solution, because the capacitor charging time is changed, the controllability is unstable, which is mainly manifested in the unstable charging voltage of each channel or the inconsistent transmitted power of each channel, thus affecting the correction effect; while in the second above-mentioned technical solution, changing the discharge pulse width of the laser drive during constant voltage power supply will result in a small difference in the strong and weak light emission powers, which is not conducive to increasing the dynamic ranging range of vehicle-mounted lidars and cannot meet the actual use requirements.

[0004] Therefore, there is an urgent need to provide a multi-channel drive circuit to improve the ranging accuracy while increasing the dynamic ranging range of vehicle-mounted lidars. Summary of the Invention

[0005] The purpose of this application is to provide a multi-channel drive circuit and a lidar, aiming to solve the problem that related lidars cannot improve the ranging accuracy while increasing the dynamic ranging range of vehicle-mounted lidars.

[0006] An embodiment of this application provides a multi-channel drive circuit, including:

[0007] A first drive circuit configured to receive a first control signal and convert the first control signal into a first drive signal;

[0008] A first switching transistor connected to the first drive circuit, configured to receive a first supply voltage and output the first supply voltage to the light source according to the first drive signal to turn on the light source;

[0009] A semiconductor device connected to the first switching transistor, configured to perform reverse cut-off on the first supply voltage and receive a second supply voltage, and output the second supply voltage to the light source to turn on the light source;

[0010] Wherein, the first supply voltage is greater than the second supply voltage.

[0011] In one embodiment, the semiconductor device is a first diode.

[0012] In one embodiment, the semiconductor device is a second switching transistor; the multi-channel driving circuit further includes:

[0013] A second driving circuit, configured to receive a second control signal and convert the second control signal into a second driving signal;

[0014] The second switching transistor, connected to the second driving circuit and the first switching transistor, is configured to reversely cut off the first supply voltage through a body diode, access the second supply voltage, and output the second supply voltage to the light source according to the second driving signal to turn on the light source.

[0015] In one embodiment, the first driving circuit includes a first high-side driving circuit, a first unidirectional conduction circuit, and a first energy storage circuit;

[0016] The first unidirectional conduction circuit is configured to unidirectionally transmit a third supply voltage to the first high-side driving circuit and the first energy storage circuit;

[0017] The first energy storage circuit, connected to the first unidirectional conduction circuit, is configured to charge according to the third supply voltage to generate a charging voltage when the first high-side driving circuit stops outputting the first driving signal, and boost the third supply voltage according to the charging voltage to output a bootstrap voltage when the first high-side driving circuit outputs the first driving signal;

[0018] The first high-side driving circuit, connected to the first unidirectional conduction circuit and the first energy storage circuit, is specifically configured to convert the first control signal into the first driving signal according to the bootstrap voltage.

[0019] In one embodiment, the first high-side driving circuit includes a third high-side driver and a third resistor;

[0020] The power terminal of the third high-side driver is connected to the fourth power supply, and the ground terminal of the third high-side driver is connected to the power ground; the high-side drive input terminal of the third high-side driver serves as the first control signal input terminal of the first drive circuit to receive the first control signal; the high-side drive enable terminal of the third high-side driver is connected to the first end of the third resistor, and the second end of the third resistor and the high-side drive disable terminal of the third high-side driver together serve as the first drive signal output terminal of the first drive circuit and are connected to the first switching transistor to output the first drive signal; the high-side switch source connection terminal of the third high-side driver serves as the signal ground of the first drive circuit and is connected to the first energy storage circuit and the first switching transistor; when the first drive signal is at a high level, this signal ground is the first supply voltage; when the first drive signal is at a low level, this signal ground is the second supply voltage; the bootstrap capacitor terminal of the third high-side driver serves as the bootstrap voltage input terminal of the first high-side drive circuit and is connected to the first unidirectional conduction circuit and the first energy storage circuit to input the bootstrap voltage.

[0021] In one embodiment, the second drive circuit includes the first low-side driver, a sixth field-effect transistor, and a second resistor;

[0022] The power terminal of the first low-side driver is connected to the fourth power supply; the ground terminal of the first low-side driver and the source electrode of the sixth field-effect transistor are commonly connected to the power ground; the logic level terminal of the first low-side driver serves as the second control signal input terminal of the second drive circuit to receive the second control signal; the pull-up gate drive terminal of the first low-side driver is connected to the pull-down gate drive terminal of the first low-side driver and the gate electrode of the sixth field-effect transistor, and the drain electrode of the sixth field-effect transistor and the first end of the second resistor together serve as the second drive signal output terminal of the second drive circuit and are connected to the second switching transistor to output the second drive signal; the second end of the second resistor is connected to the third power supply

[0023] In one embodiment, the second drive circuit includes the first low-side driver, and the first low-side driver is a first high-voltage low-side driver;

[0024] The power terminal of the first high-voltage low-side driver is connected to the third power supply; the logic level terminal of the first high-voltage low-side driver serves as the second control signal input terminal of the second drive circuit to receive the second control signal; the gate drive terminal of the first high-voltage low-side driver serves as the second drive signal output terminal of the second drive circuit and is connected to the second switching transistor to output the second drive signal; the ground terminal of the first high-voltage low-side driver is commonly connected to the power ground.

[0025] In one embodiment, the multi-channel driving circuit further includes:

[0026] A third driving circuit configured to receive a third control signal and convert the third control signal into a third driving signal;

[0027] A third switching transistor, connected to the first switching transistor and the third driving circuit, and connected between the second switching transistor and the light source, configured to output the second supply voltage to the light source according to the third driving signal to turn on the light source;

[0028] Wherein, at the same moment, at most one of the first switching transistor and the second switching transistor is turned on; and the conduction time of the second switching transistor and the conduction time of the third switching transistor overlap; the first supply voltage is greater than the second supply voltage, and the body diodes of the second switching transistor and the third switching transistor are connected in opposite directions.

[0029] In one embodiment, the third driving circuit includes a second high-side driver or a second low-side driver.

[0030] In one embodiment, the third driving circuit includes the second low-side driver, a second unidirectional conduction circuit, and a second energy storage circuit;

[0031] The second unidirectional conduction circuit is configured to unidirectionally transmit a third supply voltage to the second low-side driver and the second energy storage circuit;

[0032] The second energy storage circuit is connected to the third switching transistor, the second low-side driver, and the second unidirectional conduction circuit, and is configured to charge according to the third supply voltage to generate a charging voltage when the second low-side driver stops outputting the third driving signal, and to bootstrap the supply voltage according to the charging voltage to output a bootstrapping voltage when the second low-side driver outputs the third driving signal;

[0033] The second low-side driver is connected to the second unidirectional conduction circuit, and is specifically configured to convert the third control signal into the third driving signal according to the bootstrapping voltage.

[0034] In one embodiment, the multi-channel driving circuit further includes:

[0035] A fourth driving circuit configured to receive a fourth control signal and convert the fourth control signal into a fourth driving signal;

[0036] The fourth switching transistor is connected to the third switching transistor, the first switching transistor, and the fourth driving circuit, and is configured to provide a charging path for the bootstrap capacitor in the third driving circuit and / or the bootstrap capacitor in the first driving circuit according to the fourth driving signal;

[0037] Wherein, when the fourth switching transistor is turned on, both the first switching transistor and the third switching transistor are turned off.

[0038] In one embodiment, the fourth driving circuit includes a microprocessor or an FPGA.

[0039] In one embodiment, the first driving circuit includes a third high-side driver or a third low-side driver.

[0040] In one embodiment, the first driving circuit includes the third low-side driver, a third unidirectional conduction circuit, and a third energy storage circuit;

[0041] The third unidirectional conduction circuit is configured to unidirectionally transmit a third supply voltage to the third low-side driver and the third energy storage circuit;

[0042] The third energy storage circuit is connected to the third unidirectional conduction circuit and is configured to charge according to the third supply voltage to generate a charging voltage when the third low-side driver stops outputting the first driving signal, and to bootstrap the supply voltage according to the charging voltage to output a bootstrap voltage when the third low-side driver outputs the first driving signal;

[0043] The third low-side driver is connected to the third unidirectional conduction circuit and the third energy storage circuit, and is specifically configured to convert the first control signal into the first driving signal according to the bootstrap voltage.

[0044] In one embodiment, the multi-channel driving circuit further includes:

[0045] A first capacitor assembly is connected to the first switching transistor and is configured to charge according to the first supply voltage and output charge to the light source when the first switching transistor is turned on;

[0046] A second capacitor assembly is connected to the semiconductor device and is configured to charge according to the second supply voltage and output charge to the light source when the semiconductor device is turned on.

[0047] An embodiment of the present application further provides a lidar, and the lidar includes the above multi-channel driving circuit.

[0048] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: In the case of long-distance ranging of the vehicle-mounted lidar, the first switching tube outputs the first power supply voltage to the light source according to the first driving signal to turn on the light source. At this time, the semiconductor device reversely cuts off the first power supply voltage, so the first power supply voltage will not flow back to the power supply providing the second power supply voltage and long-distance ranging is achieved; in the case of short-distance ranging of the vehicle-mounted lidar, the first switching tube stops outputting the first power supply voltage according to the stop of the first driving signal, and the semiconductor device outputs the second power supply voltage to the light source to turn on the light source. Since the first power supply voltage is disconnected, the first power supply voltage will not flow back to the power supply providing the second power supply voltage and short-distance ranging of the vehicle-mounted lidar is achieved; thus, while improving the dynamic ranging range of the vehicle-mounted lidar, the accuracy and reliability of ranging are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical invention in the embodiments of the present application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 A schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0051] Figure 2 Another schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0052] Figure 3 Another schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0053] Figure 4 Another schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0054] Figure 5 Another schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0055] Figure 6 Another schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0056] Figure 7 Another schematic structural diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0057] Figure 8 A partial example circuit schematic diagram of a multi-channel drive circuit provided by an embodiment of the present application;

[0058] Figure 9 Another partial schematic circuit diagram of the multi-channel drive circuit provided by an embodiment of the present application;

[0059] Figure 10 Another partial schematic circuit diagram of the multi-channel drive circuit provided by an embodiment of the present application;

[0060] Figure 11 Another partial schematic circuit diagram of the multi-channel drive circuit provided by an embodiment of the present application;

[0061] Figure 12 Another partial schematic circuit diagram of the multi-channel drive circuit provided by an embodiment of the present application. Detailed implementation manners

[0062] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0063] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0064] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0065] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0066] Figure 1 A structural schematic diagram of the multi-channel drive circuit provided by a preferred embodiment of the present application is shown. For the convenience of description, only the parts related to this embodiment are shown and are described in detail as follows:

[0067] The above multi-channel drive circuit includes a first drive circuit 11, a first switching transistor 12, and a semiconductor device 13.

[0068] The first drive circuit 11 is configured to receive a first control signal PWM1 and convert the first control signal PWM1 into a first drive signal.

[0069] The first switching transistor 12 is connected to the first drive circuit 11, configured to receive a first supply voltage VIN1, and output the first supply voltage VIN1 to the light source 90 according to the first drive signal to turn on the light source 90.

[0070] The semiconductor device 13 is connected to the first switching transistor 12, configured to perform reverse cut-off on the first supply voltage VIN1, and receive a second supply voltage VIN2, and output the second supply voltage VIN2 to the light source 90 to turn on the light source 90.

[0071] Wherein, the first supply voltage VIN1 is greater than the second supply voltage VIN2.

[0072] The first switching transistor 12 can be an NMOS or a PMOS.

[0073] The second supply voltage VIN2 provides a low-voltage power supply to ensure that the light source 90 emits weak light; the first supply voltage VIN1 provides a high-voltage power supply to ensure that the light source 90 emits strong light.

[0074] When the first supply voltage VIN1 is input, since the semiconductor device 13 performs reverse cut-off on the first supply voltage VIN1, there is no situation of the first power supply reverse charging or current backflow burning out the second power supply when outputting the first supply voltage VIN1; when the second supply voltage VIN2 is input, the working voltage of the anode of the body diode inside the first switching transistor 12 is low voltage and the cathode is high voltage, so there is also no situation of the second power supply reverse charging or current backflow burning out the first power supply when outputting the second supply voltage VIN2, thus ensuring the safety of the circuit.

[0075] The multi-channel drive circuit improves the dynamic ranging range of the vehicle-mounted lidar, and also improves the ranging accuracy and reliability.

[0076] As an example but not a limitation, the semiconductor device 13 can be a first diode.

[0077] Using the first diode as the semiconductor device 13, the circuit structure is simple and reliable, and the cost is low.

[0078] As an example but not a limitation, as Figure 2 shown, the semiconductor device 13 is a second switching transistor 131; the multi-channel drive circuit further includes a second drive circuit 14 and a second switching transistor 131.

[0079] The second driving circuit 14 is configured to receive the second control signal PWM2 and convert the second control signal PWM2 into a second driving signal.

[0080] The second switching transistor 131 is connected to the second driving circuit 14 and the first switching transistor 12, and is configured to reversely cut off the first supply voltage VIN1 through the body diode, receive the second supply voltage VIN2, and output the second supply voltage VIN2 to the light source 90 according to the second driving signal to turn on the light source 90.

[0081] Using the second switching transistor 131 as the semiconductor device 13, the output of the second supply voltage VIN2 can be controlled by receiving the second control signal PWM2, improving the control accuracy of the multi-channel driving circuit.

[0082] By way of example and not limitation, as Figure 3 shown, the first driving circuit includes a first high-side driving circuit 114, a first unidirectional conduction circuit 115, and a first energy storage circuit 116.

[0083] The first unidirectional conduction circuit 115 is configured to unidirectionally transmit the third supply voltage to the first high-side driving circuit 114 and the first energy storage circuit 116.

[0084] The first energy storage circuit 116 is connected to the first unidirectional conduction circuit 115, and is configured to charge according to the third supply voltage to generate a charging voltage when the first high-side driving circuit 114 stops outputting the first driving signal, and to bootstrap the third supply voltage according to the charging voltage to output a bootstrap voltage when the first high-side driving circuit 114 outputs the first driving signal.

[0085] The first high-side driving circuit 114 is connected to the first unidirectional conduction circuit 115 and the first energy storage circuit 116, and is specifically configured to convert the first control signal into a first driving signal according to the bootstrap voltage.

[0086] The driving ability of the first high-side driving circuit 114 is improved by outputting the bootstrap voltage through the first energy storage circuit 116.

[0087] When switching from the second supply voltage VIN2 to the first supply voltage VIN1, the voltage at the connection node of the first switching transistor, the second switching transistor and the light source can be directly changed from the second supply voltage VIN2 to the first supply voltage VIN1, without directly changing from the power ground to the first supply voltage VIN1, reducing the voltage jump amplitude, reducing crosstalk, improving the stability of the radar, and avoiding unnecessary light emission of the light source.

[0088] By way of example and not limitation, the second driving circuit 14 includes a first high-side driver or a first low-side driver.

[0089] When the second driving circuit 14 includes a first high-side driver, the circuit is simple and reliable.

[0090] By way of example and not limitation, the first low-side driver may be a high-voltage low-side driver. The driving pulse width of the high-voltage low-side driver can be as low as 1 ns, which can ensure that the driving pulse width is within 2 - 5 ns. At the same time, it can quickly turn on and off the NMOS transistor. In addition, its size is small, which is beneficial to the miniaturization of the second driving circuit 14. The first low-side driver may also be a common low-side driver. In this case, the second driving circuit 14 may further include a pull-up resistor to enhance the driving ability of the low-side driver and ensure the normal operation of the circuit.

[0091] By way of example and not limitation, as Figure 4 shown, the multi-channel driving circuit further includes a third driving circuit 15 and a third switching transistor 16.

[0092] The third driving circuit 15 is configured to receive a third control signal PWM3 and convert the third control signal PWM3 into a third driving signal.

[0093] The third switching transistor 16 is connected to the first switching transistor 12 and the third driving circuit 15, and is connected between the second switching transistor 131 and the light source 90. It is configured to output the second supply voltage VIN2 to the light source 90 according to the third driving signal to turn on the light source 90.

[0094] Wherein, at the same moment, at most one of the first switching transistor 12 and the second switching transistor 131 is conducting; and there is an overlap between the conduction time of the second switching transistor 131 and the conduction time of the third switching transistor 16; the first supply voltage VIN1 is greater than the second supply voltage VIN2, and the body diodes of the second switching transistor 131 and the third switching transistor 16 are connected in opposite directions.

[0095] The third switching transistor 16 may be an NMOS or a PMOS.

[0096] Since the body diodes of the second switching transistor 131 and the third switching transistor 16 are connected in opposite directions, the voltage at the node connecting the first switching transistor 12 and the light source 90 is pulled down by the third switching transistor 16, thereby increasing the difference between this voltage and the first supply voltage VIN1, making the boost capacitor in the first driving circuit charge fully, and further ensuring the normal conduction of the first switching transistor 12.

[0097] By way of example and not limitation, the third driving circuit 15 includes a second high-side driver or a second low-side driver 151.

[0098] When the third driving circuit 15 includes a second high-side driver, the circuit is simple and reliable.

[0099] By way of example and not limitation, asFigure 5 As shown, the third driving circuit 15 includes a second low-side driver 151, a second unidirectional conduction circuit 152, and a second energy storage circuit 153.

[0100] The second unidirectional conduction circuit 152 is configured to unidirectionally transmit the third supply voltage to the second low-side driver 151 and the second energy storage circuit 153 to supply power to the second low-side driver 151 and charge the second energy storage circuit 153.

[0101] The second energy storage circuit 153 is connected to the third switching transistor 16, the second low-side driver 151, and the second unidirectional conduction circuit 152. It is configured to charge according to the third supply voltage to generate a charging voltage when the second low-side driver 151 stops outputting the third driving signal, and to bootstrap the supply voltage according to the charging voltage to output a bootstrapping voltage when the second low-side driver 151 outputs the third driving signal.

[0102] The second low-side driver 151 is connected to the second unidirectional conduction circuit 152 and is specifically configured to convert the third control signal PWM3 into a third driving signal according to the bootstrapping voltage.

[0103] It can be understood that the voltage of the third supply voltage is higher than the voltage value of the second supply voltage VIN2 and the difference between the two is greater than or equal to the conduction threshold voltage value of the third switching transistor 16 to ensure the normal conduction of the third switching transistor 16; the voltage of the third supply voltage is also lower than the maximum limit operating voltage value of the third switching transistor 16 to ensure that the third switching transistor 16 will not be damaged.

[0104] Therefore, the high-side driving of the light source 90 is realized by the low-side driving circuit, that is, when the light source 90 works with the common cathode grounded, the turn-off speed is increased and the circuit volume is reduced.

[0105] As an example rather than a limitation, as Figure 6 shown, the multi-channel driving circuit further includes a fourth driving circuit 17 and a fourth switching transistor 18.

[0106] The fourth driving circuit 17 is configured to access the fourth control signal PWM4 and convert the fourth control signal PWM4 into a fourth driving signal.

[0107] The fourth switching transistor 18 is connected to the third switching transistor 16, the first switching transistor 12, and the fourth driving circuit 17 and is configured to provide a charging circuit for the bootstrap capacitor in the third driving circuit 15 and / or the bootstrap capacitor in the first driving circuit 11 according to the fourth driving signal.

[0108] Wherein, when the fourth switching transistor 18 is turned on, both the first switching transistor 12 and the third switching transistor 16 are turned off.

[0109] It is connected to the power ground through the fourth switching transistor 18, thereby providing a charging loop for the bootstrap capacitors in the third driving circuit 15 and the first driving circuit 11, and improving the driving capabilities of the first driving circuit 11 and the third driving circuit 15.

[0110] As an example but not limitation, the fourth driving circuit 17 includes a microprocessor or an FPGA.

[0111] This circuit is simple and reliable.

[0112] As an example but not limitation, the first driving circuit 11 includes a third high-side driver or a third low-side driver U4.

[0113] When the first driving circuit 11 includes a third high-side driver, the circuit is simple and reliable.

[0114] As an example but not limitation, as Figure 7 shown, the first driving circuit 11 includes a third low-side driver 111, a third unidirectional conduction circuit 112, and a third energy storage circuit 113.

[0115] The third unidirectional conduction circuit 112 is configured to unidirectionally transmit the third supply voltage to the third low-side driver 111 and the third energy storage circuit 113 to supply power to the third low-side driver 111 and charge the third energy storage circuit 113.

[0116] The third energy storage circuit 113 is connected to the third unidirectional conduction circuit 112 and is configured to charge according to the third supply voltage to generate a charging voltage when the third low-side driver 111 stops outputting the first driving signal, and to bootstrap the supply voltage according to the charging voltage to output a bootstrap voltage when the third low-side driver 111 outputs the first driving signal.

[0117] The third low-side driver 111 is connected to the third unidirectional conduction circuit 112 and the third energy storage circuit 113, and is specifically configured to convert the first control signal PWM1 into a first driving signal according to the bootstrap voltage.

[0118] Therefore, the high-side driving of the light source is realized by a low-side driving circuit, that is, when the light source works with a common cathode grounded, the turn-off speed is increased and the circuit volume is reduced.

[0119] As an example but not limitation, as Figure 8 shown, the multi-channel driving circuit further includes a first capacitor assembly 70 and a second capacitor assembly 80.

[0120] The first capacitor assembly 70 is connected to the first switching transistor and is configured to charge according to the first supply voltage and output charges to the light source when the first switching transistor is turned on.

[0121] The second capacitor component 80 is connected to the semiconductor device, configured to be charged according to the second supply voltage, and output charges to the light source when the semiconductor device is turned on.

[0122] The transient driving capability is enhanced by the first capacitor component 70 and the second capacitor component 80.

[0123] Figure 9 FIG. shows a partial example circuit structure of the multi-channel driving circuit provided by the embodiment of the present application. For the sake of convenience of description, only the part related to the embodiment of the present application is shown and is described in detail as follows:

[0124] The first driving circuit 11 includes a third high-side driver U1 and a first capacitor C1.

[0125] The power supply terminal VDD of the third high-side driver U1 is connected to the fourth power supply VBB, and the ground terminal VSS of the third high-side driver U1 is connected to the power ground; the high-side driving input terminal HI of the third high-side driver U1 serves as the first control signal input terminal of the first driving circuit 11 to access the first control signal PWM1; the high-side driving enable terminal HOH and the high-side driving disable terminal HOL of the third high-side driver U1 together serve as the first driving signal output terminal of the first driving circuit 11 and are connected to the first switching transistor 12 to output the first driving signal; the high-side switch source connection terminal HS of the third high-side driver U1 and the first end of the first capacitor C1 together serve as the signal ground of the first driving circuit 11; when the first driving signal is at a high level, the signal ground is the first supply voltage VIN1; when the first driving signal is at a low level, the signal ground is the power ground; the second end of the first capacitor C1 is connected to the bootstrap capacitor terminal HB of the third high-side driver U1.

[0126] Using the third high-side driver U1 to implement the first driving circuit 11 realizes the high-side driving of the first switching transistor 12, and the circuit is simple and reliable.

[0127] The first switching transistor 12 is a first NMOS transistor N1.

[0128] The gate of the first NMOS transistor N1 serves as the first driving signal input terminal of the first switching transistor 12 and is connected to the first driving circuit 11 to access the first driving signal; the drain of the first NMOS transistor N1 serves as the first supply voltage VIN1 input terminal of the first switching transistor 12 to access the first supply voltage VIN1; the source of the first NMOS transistor N1 serves as the first supply voltage VIN1 output terminal of the first switching transistor 12 and is connected to the light source 90, the first driving circuit 11, the third switching transistor 16, and the fourth switching transistor 18 to output the first supply voltage VIN1.

[0129] The second switching transistor 131 is a second NMOS transistor N2.

[0130] The gate of the second NMOS transistor N2 serves as the second drive signal input terminal of the second switching transistor 131 and is connected to the second drive circuit 14 to receive the second drive signal; the source of the second NMOS transistor N2 serves as the second power supply voltage VIN2 input terminal of the second switching transistor 131 to receive the second power supply voltage VIN2; the drain of the second NMOS transistor N2 serves as the second power supply voltage VIN2 output terminal of the second switching transistor 131 and is connected to the third switching transistor 16 to output the second power supply voltage VIN2.

[0131] The second drive circuit 14 includes a first low-side driver U2, a fifth field-effect transistor N5, and a first resistor R1.

[0132] The power supply terminal VDD of the first low-side driver U2 is connected to the fourth power supply VBB; the ground terminal GND of the first low-side driver U2, the negative logic level terminal IN- of the first low-side driver U2, and the source of the fifth field-effect transistor N5 are commonly connected to the power ground; the positive logic level terminal IN+ of the first low-side driver U2 serves as the second control signal input terminal of the second drive circuit 14 to receive the second control signal PWM2; the pull-up gate drive terminal OUTH of the first low-side driver U2 is connected to the pull-down gate drive terminal OUTL of the first low-side driver U2 and the gate of the fifth field-effect transistor N5. The drain of the fifth field-effect transistor N5 and the first end of the first resistor R1 together serve as the second drive signal output terminal of the second drive circuit 14 and are connected to the second switching transistor 131 to output the second drive signal; the second end of the first resistor R1 is connected to the third power supply VAA.

[0133] The second drive signal is pulled up through the first resistor R1, enabling the low-side driver to achieve high-side drive, improving the heat dissipation speed, well realizing narrow pulse width control, also increasing the turn-off speed, and reducing the circuit volume.

[0134] The third switching transistor 16 is a third NMOS transistor N3.

[0135] The gate of the third NMOS transistor N3 serves as the third drive signal input terminal of the third switching transistor 16 and is connected to the third drive circuit 15 to receive the third drive signal; the drain of the third NMOS transistor N3 serves as the second power supply voltage VIN2 input terminal of the third switching transistor 16 and is connected to the second switching transistor 131 to receive the second power supply voltage VIN2; the source of the third NMOS transistor N3 serves as the second power supply voltage VIN2 output terminal of the third switching transistor 16 and is connected to the light source 90, the first drive circuit 11, the first switching transistor 12, and the fourth switching transistor 18 to output the second power supply voltage VIN2.

[0136] The third drive circuit 15 includes a second high-side driver U3 and a second capacitor C2.

[0137] The power supply terminal VDD of the second high-side driver U3 is connected to the fourth power supply VBB, and the ground terminal VSS of the second high-side driver U3 is connected to the power ground; the high-side drive input terminal HI of the second high-side driver U3 serves as the third control signal input terminal of the third drive circuit 15 to access the third control signal PWM3; the high-side drive enable terminal HOH and the high-side drive disable terminal HOL of the second high-side driver U3 together serve as the third drive signal output terminal of the third drive circuit 15 and are connected to the third switching transistor 16 to output the third drive signal; the high-side switch source connection terminal HS of the second high-side driver U3 and the first terminal of the second capacitor C2 together serve as the signal ground of the third drive circuit 15; when the third drive signal and the first drive signal are at a high level, this signal ground is the second supply voltage VIN2; when the third drive signal or the first drive signal is at a low level, this signal ground is the power ground; the second terminal of the second capacitor C2 is connected to the bootstrap capacitor terminal HB of the second high-side driver U3.

[0138] The third drive circuit 15 is implemented using the second high-side driver U3, realizing the high-side drive of the third switching transistor 16, and the circuit is simple and reliable.

[0139] The fourth switching transistor 18 is a fourth NMOS transistor N4. Among them, the gate of the fourth NMOS transistor N4 serves as the fourth drive signal input terminal of the fourth switching transistor 18 and is connected to the fourth drive circuit 17 to access the fourth drive signal; the drain of the fourth NMOS transistor N4 is connected to the first drive circuit 11, the first switching transistor 12, the third switching transistor 16, and the light source 90, and the source of the fourth NMOS transistor N4 is connected to the power ground.

[0140] The first capacitor assembly 70 includes a third capacitor C3. The third capacitor C3 is used for energy storage when the first switching transistor 12 is turned off and, when the first switching transistor 12 is turned on, provides charge to the light source together with the first supply voltage VIN1 to enhance the transient drive capability.

[0141] The second capacitor assembly 80 includes a fourth capacitor C4. The fourth capacitor C4 is used for energy storage when the second switching transistor 131 is turned off and, when the second switching transistor 131 is turned on, provides charge to the light source together with the second supply voltage VIN2 to enhance the transient drive capability.

[0142] The following further describes with reference to the working principle Figure 9 as shown:

[0143] In the case of long-distance ranging of an in-vehicle lidar, the high-side drive input terminal HI of the third high-side driver U1 is connected to the first control signal PWM1. The third high-side driver U1 converts the first control signal PWM1 into a first drive signal and outputs it to the gate of the first NMOS transistor N1 from the high-side drive enable terminal HOH and the high-side drive disable terminal HOL of the third high-side driver U1. The first NMOS transistor N1 conducts, and outputs the first supply voltage VIN1 from the source of the first NMOS transistor N1 to the light source 90 to turn on the light source 90. At the same time, the second control signal PWM2 and the third control signal PWM3 are stopped from being connected. The first low-side driver U2 stops converting the second control signal PWM2 into a second drive signal, and the second NMOS transistor N2 is cut off; and the second high-side driver U3 stops converting the third control signal PWM3 into a third drive signal, the third NMOS transistor N3 is cut off, and stops outputting the second supply voltage VIN2 from the drain of the third NMOS transistor N3. Since the first supply voltage VIN1 is greater than the second supply voltage VIN2 and the body diodes of the second switching transistor 131 and the third switching transistor 16 are connected in opposite directions, the body diode of the second switching transistor 131 or the body diode of the third switching transistor 16 reversely blocks the first supply voltage VIN1. Therefore, the first supply voltage VIN1 will not backflow to the second power supply that provides the second supply voltage VIN2, and long-distance ranging is achieved.

[0144] In the case of short-range ranging of the vehicle-mounted lidar, the access to the first control signal PWM1 is stopped. The third high-side driver U1 stops converting the first control signal PWM1 into the first drive signal. The first NMOS transistor N1 disconnects the output of the first supply voltage VIN1 according to the stop of the first drive signal. And the positive logic level terminal IN+ of the first low-side driver U2 accesses the second control signal PWM2. The first low-side driver U2 converts the second control signal PWM2 into the second PWM signal and outputs it to the gate of the fifth field-effect transistor N5 from the pull-up gate drive terminal OUTH and the pull-down gate drive terminal OUTL of the first low-side driver U2. The fifth field-effect transistor N5 converts the second PWM signal into the second drive signal and outputs it from the drain of the fifth field-effect transistor N5 to the gate of the second NMOS transistor N2. The second NMOS transistor N2 outputs the second supply voltage VIN2 from the drain of the second NMOS transistor N2 to the drain of the third NMOS transistor N3 according to the second drive signal. The high-side drive input terminal HI of the second high-side driver U3 accesses the third control signal PWM3. The second high-side driver U3 converts the third control signal PWM3 into the third drive signal and outputs it from the high-side drive enable terminal HOH and the high-side drive disable terminal HOL of the second high-side driver U3 to the gate of the third NMOS transistor N3. The third NMOS transistor N3 outputs the second supply voltage VIN2 from the source of the third NMOS transistor N3 to the light source 90 according to the third drive signal to turn on the light source 90. Since the first supply voltage VIN1 is disconnected, the first supply voltage VIN1 will not backflow to the power supply providing the second supply voltage VIN2, and short-range ranging of the vehicle-mounted lidar is achieved.

[0145] It should be noted that when the fourth NMOS transistor N4 is turned on, both the first NMOS transistor N1 and the third NMOS transistor N3 are turned off. At this time, the first capacitor C1 and the second capacitor C2 are charged. When the first NMOS transistor N1 is turned on, the first capacitor C1 bootstraps the first supply voltage VIN1 according to the charged first charging voltage to supply power to the third high-side driver U1, so as to boost the first control signal PWM1 and output the first drive signal to achieve high-side drive of the first NMOS transistor N1. Similarly, when the third NMOS transistor N3 is turned on, the second capacitor C2 bootstraps the second supply voltage VIN2 according to the charged second charging voltage to supply power to the second high-side driver U3, so as to boost the third control signal PWM3 and output the third drive signal to achieve high-side drive of the third NMOS transistor N3.

[0146] Figure 10 Another partial example circuit structure of the multi-channel drive circuit provided by the embodiment of the present application is shown. For the convenience of description, only the part related to the embodiment of the present application is shown and is described in detail as follows:

[0147] The first driving circuit 11 includes a third low-side driver U4, a first diode D1, and a fifth capacitor C5.

[0148] The positive electrode of the first diode D1 is connected to the third power supply, and the negative electrode of the first diode D1 is connected to the power supply terminal VDD of the third low-side driver U4 and the first end of the fifth capacitor C5.

[0149] The ground terminal GND of the third low-side driver U4, the negative logic level terminal IN- of the third low-side driver U4, and the second end of the fifth capacitor C5 together serve as the signal ground of the first driving circuit 11; when the first driving signal is at a high level, this signal ground is the first supply voltage VIN1; when the first driving signal is at a low level, this signal ground is the power ground.

[0150] The positive logic level terminal IN+ of the third low-side driver U4 serves as the first control signal input terminal of the first driving circuit 11 to access the first control signal PWM1.

[0151] The pull-up gate driving terminal OUTH of the third low-side driver U4 and the pull-down gate driving terminal OUTL of the second low-side driver 151 together serve as the first driving signal output terminal of the first driving circuit 11, and are connected to the first switching transistor 12 to output the first driving signal.

[0152] A bootstrap voltage is generated through the fifth capacitor C5 to supply power to the third low-side driver U4, raise the first driving signal, so that a high-side drive is achieved with a low-side driver. The common cathode of the light source 90 can be grounded, improving the heat dissipation speed and reliability, and also improving the turn-off speed and reducing the circuit volume. At the same time, while increasing the gate-source voltage of the first NMOS transistor, the bootstrap voltage can also reduce the on-resistance of the first NMOS transistor, thereby reducing the heat dissipation loss.

[0153] The first switching transistor 12 is a first NMOS transistor N1.

[0154] The gate of the first NMOS transistor N1 serves as the first driving signal input terminal of the first switching transistor 12 and is connected to the first driving circuit 11 to access the first driving signal; the drain of the first NMOS transistor N1 serves as the first supply voltage VIN1 input terminal of the first switching transistor 12 to access the first supply voltage VIN1; the source of the first NMOS transistor N1 serves as the first supply voltage VIN1 output terminal of the first switching transistor 12 and is connected to the light source 90, the first driving circuit 11, and the second switching transistor 131 to output the first supply voltage VIN1.

[0155] The second switching transistor 131 is a second NMOS transistor N2.

[0156] The gate of the second NMOS transistor N2 serves as the second drive signal input terminal of the second switching transistor 131 and is connected to the second drive circuit 14 to receive the second drive signal; the source of the second NMOS transistor N2 serves as the second power supply voltage VIN2 input terminal of the second switching transistor 131 to receive the second power supply voltage VIN2; the drain of the second NMOS transistor N2 serves as the second power supply voltage VIN2 output terminal of the second switching transistor 131 and is connected to the light source 90, the second drive circuit 14, and the first switching transistor 12 to output the second power supply voltage VIN2.

[0157] The second drive circuit 14 includes a first low-side driver U5, a sixth field-effect transistor N6, and a second resistor R2.

[0158] The power supply terminal VDD of the first low-side driver U5 is connected to the fourth power supply VBB; the ground terminal GND of the first low-side driver U5 and the source of the sixth field-effect transistor N6 are commonly connected to the power supply ground; the logic level terminal IN of the first low-side driver U5 serves as the second control signal input terminal of the second drive circuit 14 to receive the second control signal PWM2; the pull-up gate drive terminal OUTH of the first low-side driver U5 is connected to the pull-down gate drive terminal OUTL of the first low-side driver U5 and the gate of the sixth field-effect transistor N6, and the drain of the sixth field-effect transistor N6 and the first end of the second resistor R2 together serve as the second drive signal output terminal of the second drive circuit 14 and are connected to the second switching transistor 131 to output the second drive signal; the second end of the second resistor R2 is connected to the third power supply VAA. Among them, the logic level terminal IN of the first low-side driver U5 includes the positive logic level terminal IN+ and the negative logic level terminal IN- of the first low-side driver U5; or the logic level terminal IN of the first low-side driver U5 only includes the positive logic level terminal IN+ of the first low-side driver U5.

[0159] The first capacitor component 70 includes a third capacitor C3. The third capacitor C3 is used for energy storage when the first switching transistor 12 is turned off and, when the first switching transistor 12 is turned on, provides charge together with the first power supply voltage VIN1 for the light source to enhance the transient drive capability.

[0160] The second capacitor component 80 includes a fourth capacitor C4. The fourth capacitor C4 is used for energy storage when the second switching transistor 131 is turned off and, when the second switching transistor 131 is turned on, provides charge together with the second power supply voltage VIN2 for the light source to enhance the transient drive capability.

[0161] The following further explains in combination with the working principle Figure 10 as shown:

[0162] In the case of long-distance ranging of the vehicle-mounted lidar, the positive logic level terminal IN+ of the third low-side driver U4 is connected to the first control signal PWM1. The third low-side driver U4 converts the first control signal PWM1 into a first driving signal and outputs it to the gate of the first NMOS transistor N1 from the pull-up gate driving terminal OUTH of the third low-side driver U4 and the pull-down gate driving terminal OUTL of the third low-side driver U4. The first NMOS transistor N1 conducts, and outputs the first power supply voltage VIN1 from the source of the first NMOS transistor N1 to the light source 90 to turn on the light source 90. At the same time, the second control signal PWM2 is stopped from being connected, and the first low-side driver U5 stops converting the second control signal PWM2 into a second driving signal; the second NMOS transistor N2 is cut off, and stops outputting the second power supply voltage VIN2 from the drain of the second NMOS transistor N2. Since the first power supply voltage VIN1 is greater than the second power supply voltage VIN2, the body diode of the second NMOS transistor N2 reversely cuts off the first power supply voltage VIN1. Therefore, the first power supply voltage VIN1 will not backflow to the power supply providing the second power supply voltage VIN2, and long-distance ranging is achieved.

[0163] In the case of short-distance ranging of the vehicle-mounted lidar, the first control signal PWM1 is stopped from being connected, so that the third low-side driver U4 stops converting the first control signal PWM1 into a first driving signal, and the first NMOS transistor N1 disconnects the output of the first power supply voltage VIN1 according to the stop of the first driving signal; the positive logic level terminal IN+ of the first low-side driver U5 is connected to the second control signal PWM2. The first low-side driver U5 converts the second control signal PWM2 into a second driving signal and outputs the first control signal PWM1 to the gate of the sixth field-effect transistor N6 from the pull-up gate driving terminal OUTH of the first low-side driver U5 and the pull-down gate driving terminal OUTL of the first low-side driver U5. The sixth field-effect transistor N6 converts the first control signal PWM1 into a first PWM signal and outputs it to the second NMOS transistor N2 from the drain of the sixth field-effect transistor N6; the second NMOS transistor N2 outputs the second power supply voltage VIN2 to the light source 90 according to the first PWM signal to turn on the light source 90. Since the first power supply voltage VIN1 is disconnected, the first power supply voltage VIN1 will not backflow to the power supply providing the second power supply voltage VIN2, and short-distance ranging of the vehicle-mounted lidar is achieved.

[0164] Figure 11 Another partial example circuit structure of the multi-channel driving circuit provided by the embodiment of the present application is shown. For the convenience of description, only the part related to the embodiment of the present application is shown, and the details are as follows:

[0165] The first high-side driving circuit 114 includes a third high-side driver U6 and a third resistor R3.

[0166] The power supply terminal of the third high-side driver U6 is connected to the fourth power supply VBB, and the ground terminal VSS of the third high-side driver U6 is connected to the power supply ground; the high-side drive input terminal HI of the third high-side driver U6 serves as the first control signal input terminal of the first high-side drive circuit 114 to access the first control signal; the high-side drive enable terminal HOH of the third high-side driver U6 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 and the high-side drive disable terminal HOL of the third high-side driver U6 jointly serve as the first drive signal output terminal of the first high-side drive circuit 114 and are connected to the first switching transistor 12 to output the first drive signal; the high-side switch source connection terminal HS of the third high-side driver U6 serves as the signal ground of the first high-side drive circuit 114 and is connected to the first energy storage circuit 116 and the first switching transistor 12; when the first drive signal is at a high level, this signal ground is the first supply voltage; when the first drive signal is at a low level, this signal ground is the second supply voltage (it should be noted that when both the first drive signal and the second drive circuit are at low levels, the signal ground is the difference between the second supply voltage and the body diode voltage drop of the second switching transistor); the bootstrap capacitor terminal HB of the third high-side driver U6 serves as the bootstrap voltage input terminal of the first high-side drive circuit 114 and is connected to the first unidirectional conduction circuit 115 and the first energy storage circuit 116 to input the bootstrap voltage.

[0167] In addition, the high-side drive disable terminal HOL of the third high-side driver U6 can also be connected to a current-limiting resistor.

[0168] After current limiting by the resistor, the current jump slope becomes smaller and the crosstalk becomes smaller.

[0169] The first unidirectional conduction circuit 115 includes a second diode D2.

[0170] The positive electrode of the second diode D2 serves as the third supply voltage input terminal of the first unidirectional conduction circuit 115 to access the third supply voltage; the negative electrode of the second diode D2 serves as the third supply voltage output terminal of the first unidirectional conduction circuit 115 and is connected to the first high-side drive circuit 114 and the first energy storage circuit 116 to output the third supply voltage.

[0171] The first energy storage circuit 116 includes a sixth capacitor C6.

[0172] The first end of the sixth capacitor C6 serves as the third supply voltage input terminal of the first energy storage circuit 116 and the bootstrap voltage output terminal of the first energy storage circuit 116 to access the third supply voltage and output the bootstrap voltage; the second end of the sixth capacitor C6 serves as the signal ground of the first energy storage circuit 116 and is connected to the first high-side drive circuit 114, the light source 90, the first switching transistor 12, and the second switching transistor 131; when the first drive signal is at a high level, this signal ground is the first supply voltage; when the first drive signal is at a low level, this signal ground is the power supply ground.

[0173] The first switching transistor 12 is the first NMOS transistor N1.

[0174] The gate of the first NMOS transistor N1 serves as the first drive signal input terminal of the first switching transistor 12 and is connected to the first drive circuit 11 to receive the first drive signal; the drain of the first NMOS transistor N1 serves as the first power supply voltage VIN1 input terminal of the first switching transistor 12 to receive the first power supply voltage VIN1; the source of the first NMOS transistor N1 serves as the first power supply voltage VIN1 output terminal of the first switching transistor 12 and is connected to the light source 90, the first drive circuit 11, and the second switching transistor 131 to output the first power supply voltage VIN1.

[0175] The second switching transistor 131 is the second NMOS transistor N2.

[0176] The gate of the second NMOS transistor N2 serves as the second drive signal input terminal of the second switching transistor 131 and is connected to the second drive circuit 14 to receive the second drive signal; the source of the second NMOS transistor N2 serves as the second power supply voltage VIN2 input terminal of the second switching transistor 131 to receive the second power supply voltage VIN2; the drain of the second NMOS transistor N2 serves as the second power supply voltage VIN2 output terminal of the second switching transistor 131 and is connected to the light source 90, the second drive circuit 14, and the first switching transistor 12 to output the second power supply voltage VIN2.

[0177] The second drive circuit 14 includes a first high-voltage low-side driver U7.

[0178] The power supply terminal of the first high-voltage low-side driver U7 is connected to the third power supply VAA; the logic level terminal IN of the first high-voltage low-side driver U7 serves as the second control signal input terminal of the second drive circuit 14 to receive the second control signal PWM2; the gate drive terminal OUT of the first high-voltage low-side driver U7 serves as the second drive signal output terminal of the second drive circuit 14 and is connected to the second switching transistor 131 to output the second drive signal; the ground terminal GND of the first high-voltage low-side driver U7 is commonly connected to the power supply ground. Among them, the logic level terminal IN of the first high-voltage low-side driver U7 includes the positive logic level terminal IN+ and the negative logic level terminal IN- of the first high-voltage low-side driver U7, or the logic level terminal IN of the first high-voltage low-side driver U7 only includes the positive logic level terminal IN+ of the first high-voltage low-side driver U7.

[0179] The first capacitor component 70 includes a third capacitor C3. The third capacitor C3 is used for energy storage when the first switching transistor 12 is turned off and, when the first switching transistor 12 is turned on, provides charge together with the first power supply voltage VIN1 for the light source 90 to enhance the transient drive capability.

[0180] The second capacitor component 80 includes a fourth capacitor C4. The fourth capacitor C4 is used for energy storage when the second switching transistor 131 is turned off, and when the second switching transistor 131 is turned on, it provides charge to the light source 90 together with the second supply voltage VIN2 to enhance the transient driving ability.

[0181] The following further describes with reference to the working principle Figure 11 the shown as follows:

[0182] In the case of long-distance ranging of the vehicle-mounted lidar, the high-side drive input terminal HI of the third high-side driver U6 is connected to the first control signal PWM1. The third high-side driver U6 converts the first control signal PWM1 into a first drive signal and outputs it to the gate of the first NMOS transistor N1 from the high-side drive enable terminal HOH and the high-side drive disable terminal HOL of the third high-side driver U6. The first NMOS transistor N1 is turned on, and the first supply voltage VIN1 is output from the source of the first NMOS transistor N1 to the light source 90 to light up the light source 90. At the same time, the second control signal PWM2 and the third control signal PWM3 are stopped from being connected. The first high-voltage low-side driver U7 stops converting the second control signal PWM2 into a second drive signal, the second NMOS transistor N2 is turned off, and since the first supply voltage VIN1 is greater than the second supply voltage VIN2, the body diode of the second switching transistor 131 reversely cuts off the first supply voltage VIN1. Therefore, the first supply voltage VIN1 will not backflow to the second power supply that provides the second supply voltage VIN2, and long-distance ranging is achieved.

[0183] In the case of short-distance ranging of the vehicle-mounted lidar, the first control signal PWM1 is stopped from being connected, so that the third high-side driver U6 stops converting the first control signal PWM1 into a first drive signal, and the first NMOS transistor N1 disconnects the output of the first supply voltage VIN1 according to the stop of the first drive signal; the positive logic level terminal IN+ of the first high-voltage low-side driver U7 is connected to the second control signal PWM2. The first high-voltage low-side driver U7 converts the second control signal PWM2 into a second drive signal and outputs the second drive signal to the gate of the second NMOS transistor N2 from the gate drive terminal OUT of the first high-voltage low-side driver U7; the second NMOS transistor N2 outputs the second supply voltage VIN2 to the light source 90 according to the second drive signal to light up the light source 90. Since the first supply voltage VIN1 is disconnected, the first supply voltage VIN1 will not backflow to the power supply that provides the second supply voltage VIN2, and short-distance ranging of the vehicle-mounted lidar is achieved.

[0184] Figure 12 Fig. shows another partial example circuit structure of the multi-channel drive circuit provided by the embodiment of the present application. For the convenience of description, only the part related to the embodiment of the present application is shown and is described in detail as follows:

[0185] The first driving circuit 11 includes a third high-side driver U8 and a seventh capacitor C7.

[0186] The power supply terminal VDD of the third high-side driver U8 is connected to the fourth power supply VBB, and the ground terminal VSS of the third high-side driver U8 is connected to the power ground; the high-side driving input terminal HI of the third high-side driver U8 serves as the first control signal input terminal of the first driving circuit 11 to receive the first control signal PWM1; the high-side driving enable terminal HOH and the high-side driving disable terminal HOL of the third high-side driver U8 jointly serve as the first driving signal output terminal of the first driving circuit 11 and are connected to the first switching transistor 12 to output the first driving signal; the high-side switch source connection terminal HS of the third high-side driver U8 and the first terminal of the seventh capacitor C7 jointly serve as the signal ground of the first driving circuit 11; when the first driving signal is at a high level, this signal ground is the first supply voltage VIN1; when the first driving signal is at a low level, this signal ground is the power ground; the second terminal of the seventh capacitor C7 is connected to the bootstrap capacitor terminal HB of the third high-side driver U8.

[0187] The first switching transistor 12 is a first NMOS transistor N1.

[0188] The gate of the first NMOS transistor N1 serves as the first driving signal input terminal of the first switching transistor 12 and is connected to the first driving circuit 11 to receive the first driving signal; the drain of the first NMOS transistor N1 serves as the first supply voltage VIN1 input terminal of the first switching transistor 12 to receive the first supply voltage VIN1; the source of the first NMOS transistor N1 serves as the first supply voltage VIN1 output terminal of the first switching transistor 12 and is connected to the light source 90, the first driving circuit 11, the third switching transistor 16, and the fourth switching transistor 18 to output the first supply voltage VIN1.

[0189] The second switching transistor 131 is a second NMOS transistor N2.

[0190] The gate of the second NMOS transistor N2 serves as the second driving signal input terminal of the second switching transistor 131 and is connected to the second driving circuit 14 to receive the second driving signal; the source of the second NMOS transistor N2 serves as the second supply voltage VIN2 input terminal of the second switching transistor 131 to receive the second supply voltage VIN2; the drain of the second NMOS transistor N2 serves as the second supply voltage VIN2 output terminal of the second switching transistor 131 and is connected to the third switching transistor 16 to output the second supply voltage VIN2.

[0191] The second driving circuit 14 includes a second high-voltage low-side driver U9.

[0192] The power supply terminal of the second high-voltage low-side driver U9 is connected to the third power supply VAA; the positive logic level terminal IN+ of the second high-voltage low-side driver U9 serves as the second control signal input terminal of the second driving circuit 14 to access the second control signal PWM2; the gate driving terminal OUT of the second high-voltage low-side driver U9 serves as the second driving signal output terminal of the second driving circuit 14 and is connected to the second switching transistor 131 to output the second driving signal; the ground terminal GND of the second high-voltage low-side driver U9 and the negative logic level terminal IN- of the second high-voltage low-side driver U9 are commonly connected to the power ground.

[0193] The third switching transistor 16 is a third NMOS transistor N3.

[0194] The gate of the third NMOS transistor N3 serves as the third driving signal input terminal of the third switching transistor 16 and is connected to the third driving circuit 15 to access the third driving signal; the drain of the third NMOS transistor N3 serves as the second power supply voltage VIN2 input terminal of the third switching transistor 16 and is connected to the first switching transistor 12 to access the second power supply voltage VIN2; the source of the third NMOS transistor N3 serves as the second power supply voltage VIN2 output terminal of the third switching transistor 16 and is connected to the light source 90, the first driving circuit 11, the first switching transistor 12, and the fourth switching transistor 18 to output the second power supply voltage VIN2.

[0195] The third driving circuit 15 includes a second high-side driver U10 and an eighth capacitor C8.

[0196] The power supply terminal VDD of the second high-side driver U10 is connected to the fourth power supply VBB, and the ground terminal VSS of the second high-side driver U10 is connected to the power ground; the high-side driving input terminal HI of the second high-side driver U10 serves as the third control signal input terminal of the third driving circuit 15 to access the third control signal PWM3; the high-side driving enable terminal HOH and the high-side driving disable terminal HOL of the second high-side driver U10 jointly serve as the third driving signal output terminal of the third driving circuit 15 and are connected to the third switching transistor 16 to output the third driving signal; the high-side switch source connection terminal HS of the second high-side driver U10 and the first end of the eighth capacitor C8 jointly serve as the signal ground of the third driving circuit 15; when the third driving signal and the first driving signal are high-level, this signal ground is the second power supply voltage VIN2; when the third driving signal or the first driving signal is low-level, this signal ground is the power ground; the second end of the eighth capacitor C8 is connected to the bootstrap capacitor terminal HB of the second high-side driver U10.

[0197] The fourth switching transistor 18 is a fourth NMOS transistor N4. Among them, the gate of the fourth NMOS transistor N4 serves as the fourth drive signal input terminal of the fourth switching transistor 18 and is connected to the fourth drive circuit 17 to access the fourth drive signal; the drain of the fourth NMOS transistor N4 is connected to the first drive circuit 11, the first switching transistor 12, the third switching transistor 16, and the light source 90, and the source of the fourth NMOS transistor N4 is connected to the power ground.

[0198] The first capacitor component 70 includes a third capacitor C3. The third capacitor C3 is used for energy storage when the first switching transistor 12 is turned off and, when the first switching transistor 12 is turned on, provides charge to the light source together with the first supply voltage VIN1 to enhance the transient drive capability.

[0199] The second capacitor component 80 includes a fourth capacitor C4. The fourth capacitor C4 is used for energy storage when the second switching transistor 131 is turned off and, when the second switching transistor 131 is turned on, provides charge to the light source together with the second supply voltage VIN2 to enhance the transient drive capability.

[0200] The following further describes with reference to the working principle Figure 12 as shown:

[0201] In the case of long-distance ranging of the vehicle-mounted lidar, the high-side drive input terminal HI of the third high-side driver U8 accesses the first control signal PWM1. The third high-side driver U8 converts the first control signal PWM1 into a first drive signal and outputs it to the gate of the first NMOS transistor N1 from the high-side drive turn-on terminal HOH and the high-side drive turn-off terminal HOL of the third high-side driver U8. The first NMOS transistor N1 is turned on, and the first supply voltage VIN1 is output from the source of the first NMOS transistor N1 to the light source 90 to turn on the light source 90. At the same time, the second control signal PWM2 and the third control signal PWM3 are stopped from being accessed. The second high-voltage low-side driver U9 stops converting the second control signal PWM2 into a second drive signal, and the second NMOS transistor N2 is turned off; and the second high-side driver U10 stops converting the third control signal PWM3 into a third drive signal, the third NMOS transistor N3 is turned off, and the second supply voltage VIN2 is stopped from being output from the drain of the third NMOS transistor N3. Since the first supply voltage VIN1 is greater than the second supply voltage VIN2 and the body diodes of the second switching transistor 131 and the third switching transistor 16 are connected in opposite directions, the body diode of the second switching transistor 131 or the body diode of the third switching transistor 16 reversely blocks the first supply voltage VIN1. Therefore, the first supply voltage VIN1 will not backflow to the second power supply that provides the second supply voltage VIN2, and long-distance ranging is achieved.

[0202] In the case of short-range ranging of the vehicle-mounted lidar, the access to the first control signal PWM1 is stopped. The third high-side driver U8 stops converting the first control signal PWM1 into the first drive signal. The first NMOS transistor N1 disconnects the output of the first supply voltage VIN1 according to the stop of the first drive signal. And the positive logic level terminal IN+ of the second high-voltage low-side driver U9 accesses the second control signal PWM2. The second high-voltage low-side driver U9 converts the second control signal PWM2 into the second PWM signal and outputs it from the gate drive terminal OUT of the second high-voltage low-side driver U9 to the gate of the second NMOS transistor N2. The second NMOS transistor N2 outputs the second supply voltage VIN2 from the drain of the second NMOS transistor N2 to the drain of the third NMOS transistor N3 according to the second drive signal. The high-side drive input terminal HI of the second high-side driver U10 accesses the third control signal PWM3. The second high-side driver U10 converts the third control signal PWM3 into the third drive signal and outputs it from the high-side drive enable terminal HOH and the high-side drive disable terminal HOL of the second high-side driver U10 to the gate of the third NMOS transistor N3. The third NMOS transistor N3 outputs the second supply voltage VIN2 from the source of the third NMOS transistor N3 to the light source 90 according to the third drive signal to turn on the light source 90. Since the first supply voltage VIN1 is disconnected, the first supply voltage VIN1 will not backflow to the power supply providing the second supply voltage VIN2, and short-range ranging of the vehicle-mounted lidar is achieved.

[0203] The embodiment of the present application also provides a lidar, and the lidar includes the multi-channel drive circuit described above.

[0204] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0205] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A multi-channel driving circuit, characterized in that, Comprising: A first driving circuit configured to receive a first control signal and convert the first control signal into a first driving signal; A first switching transistor connected to the first driving circuit, configured to receive a first supply voltage and output the first supply voltage to a light source according to the first driving signal to turn on the light source; A semiconductor device connected to the first switching transistor, configured to perform reverse cut-off on the first supply voltage and receive a second supply voltage, and output the second supply voltage to the light source to turn on the light source; Wherein, the first supply voltage is greater than the second supply voltage.

2. The multi-channel driving circuit according to claim 1, wherein The semiconductor device is a first diode.

3. The multi-channel driving circuit according to claim 1, wherein The semiconductor device is a second switching transistor; the multi-channel driving circuit further comprises: A second driving circuit configured to receive a second control signal and convert the second control signal into a second driving signal; The second switching transistor, connected to the second driving circuit and the first switching transistor, configured to perform reverse cut-off on the first supply voltage through a body diode, receive the second supply voltage, and output the second supply voltage to the light source according to the second driving signal to turn on the light source.

4. The multi-channel driving circuit according to claim 3, wherein The first driving circuit includes a first high-side driving circuit, a first unidirectional conduction circuit, and a first energy storage circuit; The first unidirectional conduction circuit is configured to unidirectionally transmit a third supply voltage to the first high-side driving circuit and the first energy storage circuit; The first energy storage circuit, connected to the first unidirectional conduction circuit, is configured to charge according to the third supply voltage to generate a charging voltage when the first high-side driving circuit stops outputting the first driving signal, and bootstrap the third supply voltage according to the charging voltage to output a bootstrap voltage when the first high-side driving circuit outputs the first driving signal; The first high-side driving circuit, connected to the first unidirectional conduction circuit and the first energy storage circuit, is specifically configured to convert the first control signal into the first driving signal according to the bootstrap voltage.

5. The multi-channel driving circuit according to claim 4, characterized in that, The first high-side driving circuit includes a third high-side driver and a third resistor; The power terminal of the third high-side driver is connected to a fourth power supply, and the ground terminal of the third high-side driver is connected to the power ground; the high-side driving input terminal of the third high-side driver serves as the first control signal input terminal of the first high-side driving circuit to receive the first control signal; the high-side driving enabling terminal of the third high-side driver is connected to the first end of the third resistor, and the second end of the third resistor and the high-side driving disabling terminal of the third high-side driver jointly serve as the first driving signal output terminal of the first high-side driving circuit, connected to the first switching transistor to output the first driving signal; the high-side switch source terminal connection of the third high-side driver serves as the signal ground of the first high-side driving circuit, connected to the first energy storage circuit and the first switching transistor; when the first driving signal is at a high level, this signal ground is the first supply voltage; when the first driving signal is at a low level, this signal ground is the second supply voltage; The bootstrap capacitor terminal of the third high-side driver serves as the bootstrap voltage input terminal of the first high-side driving circuit, and is connected to the first unidirectional conduction circuit and the first energy storage circuit to input the bootstrap voltage.

6. The multi-channel driving circuit according to claim 3, wherein The second driving circuit includes a first high-side driver or a first low-side driver.

7. The multi-channel driving circuit according to claim 6, wherein The second driving circuit includes the first low-side driver, a sixth field-effect transistor, and a second resistor; The power supply terminal of the first low-side driver is connected to a fourth power supply; the grounding terminal of the first low-side driver and the source electrode of the sixth field-effect transistor are commonly connected to the power ground; the logic level terminal of the first low-side driver serves as the second control signal input terminal of the second driving circuit to access the second control signal; the pull-up gate driving terminal of the first low-side driver is connected to the pull-down gate driving terminal of the first low-side driver and the gate electrode of the sixth field-effect transistor, and the drain electrode of the sixth field-effect transistor and the first end of the second resistor jointly serve as the second driving signal output terminal of the second driving circuit and are connected to the second switching tube to output the second driving signal; the second end of the second resistor is connected to a third power supply.

8. The multi-channel driving circuit according to claim 6, wherein The second driving circuit includes the first low-side driver, and the first low-side driver is a first high-voltage low-side driver; The power supply terminal of the first high-voltage low-side driver is connected to a third power supply; the logic level terminal of the first high-voltage low-side driver serves as the second control signal input terminal of the second driving circuit to access the second control signal; the gate driving terminal of the first high-voltage low-side driver serves as the second driving signal output terminal of the second driving circuit and is connected to the second switching tube to output the second driving signal; the grounding terminal of the first high-voltage low-side driver is connected to the power ground.

9. The multi-channel driving circuit according to claim 3, wherein The multi-channel driving circuit further includes: A third driving circuit configured to access a third control signal and convert the third control signal into a third driving signal; A third switching tube connected to the first switching tube and the third driving circuit and connected between the second switching tube and the light source, configured to output the second supply voltage to the light source according to the third driving signal to turn on the light source; Wherein, at the same moment, at most one of the first switching tube and the second switching tube is turned on; and the conduction time of the second switching tube and the conduction time of the third switching tube overlap; the first supply voltage is greater than the second supply voltage, and the body diodes of the second switching tube and the third switching tube are connected in opposite directions.

10. The multi-channel driving circuit according to claim 9, wherein The third driving circuit includes a second high-side driver or a second low-side driver.

11. The multi-channel driving circuit according to claim 10, characterized in that, The third driving circuit includes the second low-side driver, a second unidirectional conduction circuit, and a second energy storage circuit; The second unidirectional conduction circuit is configured to unidirectionally transmit a third supply voltage to the second low-side driver and the second energy storage circuit; The second energy storage circuit is connected to the third switching transistor, the second low-side driver, and the second unidirectional conduction circuit, and is configured to charge according to the third supply voltage to generate a charging voltage when the second low-side driver stops outputting the third driving signal, and to boost the supply voltage according to the charging voltage to output a boosted voltage when the second low-side driver outputs the third driving signal; The second low-side driver is connected to the second unidirectional conduction circuit, and is specifically configured to convert the third control signal into the third driving signal according to the boosted voltage.

12. The multi-channel drive circuit according to claim 9, characterized in that, The multi-channel driving circuit further includes: A fourth driving circuit configured to receive a fourth control signal and convert the fourth control signal into a fourth driving signal; A fourth switching transistor is connected to the third switching transistor, the first switching transistor, and the fourth driving circuit, and is configured to provide a charging path for the boost capacitor in the third driving circuit and / or the boost capacitor in the first driving circuit according to the fourth driving signal; Wherein, when the fourth switching transistor is turned on, the first switching transistor and the third switching transistor are both turned off.

13. The multi-channel drive circuit according to claim 12, characterized in that, The fourth driving circuit includes a microprocessor or an FPGA.

14. The multi-channel driving circuit according to claim 1, wherein The first driving circuit includes a third low-side driver.

15. The multi-channel driving circuit according to claim 14, characterized in that, The first driving circuit includes the third low-side driver, a third unidirectional conduction circuit, and a third energy storage circuit; The third unidirectional conduction circuit is configured to unidirectionally transmit the third supply voltage to the third low-side driver and the third energy storage circuit; The third energy storage circuit is connected to the third unidirectional conduction circuit, and is configured to charge according to the third supply voltage to generate a charging voltage when the third low-side driver stops outputting the first driving signal, and to boost the supply voltage according to the charging voltage to output a boosted voltage when the third low-side driver outputs the first driving signal; The third low-side driver is connected to the third unidirectional conduction circuit and the third energy storage circuit, and is specifically configured to convert the first control signal into the first driving signal according to the boosted voltage.

16. The multi-channel driving circuit according to any one of claims 1 to 15, characterized in that, It further includes: A first capacitor assembly is connected to the first switching transistor, and is configured to charge according to the first supply voltage and output charge to the light source when the first switching transistor is turned on; A second capacitor assembly is connected to the semiconductor device, and is configured to charge according to the second supply voltage and output charge to the light source when the semiconductor device is turned on.

17. A lidar, characterized in that, The lidar includes the multi-channel driving circuit according to any one of claims 1 to 16.

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