A clock and data driving circuit

Abstract

The present invention provides a clock and data drive circuit, comprising a loop formed by a comparator, a clock drive circuit, and a data drive circuit. The comparator stabilizes the loop operating voltage based on a reference voltage; the clock drive circuit is used to convert a clock input signal into a clock output signal and transmit it; the data drive circuit includes a drive enable signal transmission tube, a second switch, and a data drive unit, which is used to start under the control of the drive enable signal, convert the data input signal into a data output signal, and transmit it; a pre-power tube that can be turned on after the clock drive circuit is started, and is used to increase the gate voltage of the second switch to the loop operating voltage; and a delay module that can delay the differential data input signal until the second switch is turned on before it is transmitted to the data drive unit. By using the pre-power tube and the delay module, this solution improves circuit switching speed and reduces voltage drop at the switching moment.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a clock and data driving circuit. Background Art

[0002] Clock signals are crucial in digital systems. They provide a precise time reference for data transmission, synchronize the operation of various components, and ensure the correct timing of data transmission and reception.

[0003] Various existing transmission interfaces require clock and data driver circuits to generate and transmit clock and data signals. For example, the MIPI (Mobile Industry Processor Interface) interface, an open standard and specification for mobile application processors, is currently the mainstream high-speed image transmission method. During data transmission, clock and data driver circuits are required to convert the input differential signal into corresponding signals for transmission. However, timing requirements require the clock driver circuit to be activated before the data driver circuit. When activating the data driver circuit, the switching unit cannot be activated instantaneously, which may increase the voltage of the clock driver circuit, thereby affecting the stability of the clock driver circuit.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a clock and data driving circuit to increase the circuit switching speed, reduce the voltage drop at the switching moment, and also reduce the voltage stabilizing capacitor and the device area.

[0006] In order to solve the above problems, a clock and data driving circuit is provided below, including a comparator, a clock driving circuit and a data driving circuit;

[0007] The comparator, the clock driving circuit and the data driving circuit form a loop circuit, which is used to stabilize the loop operating voltage according to the reference voltage;

[0008] The clock driving circuit is used to convert the differential clock input signal into a differential clock output signal and send it;

[0009] The data driving circuit includes a driving enable signal transmission tube, a second switch and a data driving unit coupled in sequence, and the data driving circuit is used to start under the control of the driving enable signal, convert the differential data input signal into a differential data output signal and send it;

[0010] The data driving circuit further includes a pre-on power tube, which is turned on after the clock driving circuit is started, and is used to increase the gate voltage of the second switch to the loop operating voltage;

[0011] The data driving circuit further includes a delay module, which can delay the differential data input signal until the second switch is turned on before transmitting the signal to the data driving unit.

[0012] This technical solution provides a pre-on power tube connected to the clock drive circuit in the data drive circuit. After the clock drive circuit is started, the pre-on power tube can be turned on before switching to the data drive circuit, thereby increasing the gate voltage of the switch of the data drive circuit to quickly complete the conduction of the second switch. In addition, through the delay module, it can further ensure that the path of the data drive unit is opened after the second switch is ready, greatly reducing the voltage drop caused by the early start of the path, thereby improving the circuit switching speed and reducing the voltage drop at the conversion moment.

[0013] The drive enable signal transmission tube is formed by connecting an N-channel transistor and a P-channel transistor in parallel. The drive enable signal includes a positive-phase drive enable signal and a negative-phase drive enable signal. The two gates of the drive enable signal transmission tube are respectively used to receive one of the positive-phase drive enable signal and the negative-phase drive enable signal. The input of the drive enable signal transmission tube is coupled to the output of the comparator, and the output of the drive enable signal transmission tube is coupled to the gate of the second switch. Using a pair of transmission tubes to receive the drive enable signal can increase the range of receivable signals. At the same time, the corresponding relationship between the positive-phase drive enable signal and the negative-phase drive enable signal can be used to realize the opening and closing of the pre-pass power tube.

[0014] The data drive circuit also includes a first compensation capacitor, a first end of which is coupled to the gate of the second switch, and a second end of which is connected to the positive-phase drive enable signal. The addition of the first compensation capacitor converts the stored charge into the voltage of the gate of the second switch, rapidly increasing the gate voltage and resolving the issues of slow charging and large voltage drop associated with loop charging.

[0015] The data drive circuit also includes a second compensation capacitor, a first end of which is coupled to the input of the drive enable signal transmission tube, and a second end of which is connected to the positive-phase drive enable signal. Similarly, the added second compensation capacitor can provide the stored charge to the differential input pair, thereby rapidly increasing the voltage at the gate of the second switch.

[0016] The clock driving circuit includes a coupled first switch and a clock driving unit; the input end of the first switch is coupled to a voltage source, the output end of the first switch is coupled to one end of the clock driving circuit, and the other end of the clock driving circuit is grounded.

[0017] The gate of the pre-pass power tube is connected to the inverting drive enable signal, the input end of the pre-pass power tube is coupled to the drain of the first switch, and the output end of the pre-pass power tube is coupled to the gate of the second switch.

[0018] It also includes an I0 module, which includes a receiving port for receiving the positive phase drive enable signal; the I0 module is turned on under the control of the positive phase drive enable signal, generates the differential data input signal and provides it to the data driving unit.

[0019] The delay module, located before the receiving port, delays the positive-phase drive enable signal before inputting it into the receiving port. This delay activates the I0 module after the second switch is turned on, generating the differential data input signal and providing it to the data driver unit. The delay time of the delay module is adjustable. By delaying the activation of the I0 module, the data driver unit path is opened only after the second switch is ready, significantly reducing the voltage drop caused by premature activation of the path. Furthermore, before the I0 module is activated, both swp and swn are low, ensuring that there is no leakage path in the corresponding branch.

[0020] The comparator is an operational amplifier, a first input terminal of the operational amplifier is used to input the reference voltage, a second input terminal of the operational amplifier is used to input the loop operating voltage, and an output terminal of the operational amplifier is respectively coupled to the gate of the first switch and the input terminal of the drive enable signal transmission tube; the loop operating voltage is the voltage at the connection point between the first switch and the clock driving unit and the connection point between the second switch and the data driving unit.

[0021] The data driving circuit further includes a voltage-stabilizing capacitor, a first end of the voltage-stabilizing capacitor is coupled to the output end of the second switch, and a second end of the voltage-stabilizing capacitor is grounded.

[0022] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) when the clock driving circuit is operating normally and before the data driving circuit is started, the pre-pass power tube is turned on, and the gate terminal of the second switch and the first compensation capacitor are charged to the loop operating voltage in advance, thereby reducing the voltage value that the second switch needs to pull up; 2) when the data driving circuit is in operation, the electricity stored on the first compensation capacitor will be converted into the voltage of the gate terminal of the second switch, which starts the function of quickly increasing the gate terminal voltage, solving the problem of slow speed and large voltage drop caused by charging through the loop; 3) by delaying the start of the I0 module, it can be further ensured that the path of the data driving unit is opened only after the second switch is ready, greatly reducing the voltage drop caused by the early start of the path; and before the I0 module is started, swp and swn are both low levels, ensuring that there is no leakage path in the corresponding branch. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 The invention relates to an existing clock and data driving circuit.

[0025] Figure 2 The present invention provides a clock and data driving circuit. DETAILED DESCRIPTION

[0026] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0027] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0028] The steps in the following embodiments do not correspond one-to-one to the steps in the summary of the invention.

[0029] Example 1

[0030] Figure 1 This is an existing clock and data driving circuit. Figure 1 As shown, the clock and data driving circuit is mainly composed of a comparator, a clock driving circuit (Lane0) and a data driving circuit (Lane1); the comparator, the clock driving circuit and the data driving circuit form a loop; in this embodiment, the comparator is an operational amplifier, the first input terminal (i.e., the positive input terminal) of the comparator is used to access the reference voltage (vref), the second input terminal (i.e., the negative input terminal) is used to access the loop operating voltage (vreg), and the output terminal of the comparator is respectively connected to the gate coupled to the first switch and one end of the differential input pair of the drive enable signal. The comparator can perform feedback adjustment on the loop by comparing the input reference voltage with the loop operating voltage to ensure the stability of the loop operating voltage; the clock driving circuit is used to generate a corresponding differential clock output signal according to the input differential clock input signal (i.e., Swn0 and Swp0) and then send it; the data driving circuit is used to generate a corresponding differential data output signal according to the input differential data input signal (i.e., Swn and Swp) and then send it.

[0031] refer to Figure 1 The clock drive circuit consists of a first switch (i.e., M10) and a clock drive unit (i.e., M20-M50). The first switch controls the on / off switching of the clock drive unit. The first terminal of the clock drive unit is coupled to the first switch, and the second terminal of the clock drive unit is grounded. The drive unit consists of four MOSFETs, including two parallel branches, each with two MOSFETs connected in series. Between the two branches are the two output terminals of the clock drive circuit, and a first resistor R0 is also provided at both output terminals.

[0032] Specifically, in this embodiment, transistors m10 to m50 are all N-channel transistors. In other embodiments, P-channel transistors may also be used. The gate of the first switch m10 is coupled to the output terminal of the comparator, the input terminal (i.e., drain, the same below) of m10 is coupled to the voltage source vp, and the output terminal (i.e., source, the same below) of m10 is coupled to the first terminal of the clock driving unit; the clock driving unit includes a first branch formed by m20 and m40 connected in series and a second branch formed by m30 and m50 connected in series, wherein the input terminal (i.e., drain) of m20 is coupled to the output terminal (i.e., source) of m10, the input terminal (i.e., drain) of m30 is coupled to the output terminal (i.e., source) of m10, and the output terminal (i.e., source) of m40 is coupled to the output terminal (i.e., source) of m10. ) is grounded, and the output end (i.e., the source) of m50 is grounded; the gates of m20 and m50 are used to access the first differential clock input signal Swp0, and the gates of m30 and m40 are used to access the second differential clock input signal Swn0; a first resistor R0 is provided between the first branch and the second branch, and the first end of the first resistor is coupled to the source of m20 and the drain of m40 (i.e., the first end of the first resistor is the first clock output end), and the second end of the first resistor is coupled to the source of m30 and the drain of m50 (i.e., the second end of the first resistor is the second clock output end).

[0033] After m10 is turned on, the clock driving unit is turned on according to the action of the differential clock input signal. For example, the initial first differential clock input signal Swp0 is in a low level state. When the first differential clock input signal Swp0 changes to a high level, m20 and m50 in the clock driving unit will be turned on under the action of the first differential clock input signal Swp0 (at this time, m30 and m40 are correspondingly in the closed state), then the clock driving unit is turned on, and the current flows through m10, m20, the first resistor, and m50 in sequence. At this time, the voltage at the first end of the first resistor is greater than the voltage at the first end, that is, the output of its first end is a high level, realizing the conversion of Swp0 to Dpclk0 and then sending it; similarly, when m30 and m40 are turned on under the action of the second clock differential signal Swn0 (at this time, m20 and m50 are closed), the clock driving unit is turned on, and the current flows through m10, m30, the first resistor, and m40 in sequence. At this time, the voltage at the second end of the first resistor is less than the voltage at the first end, that is, the output of the second end is a high level, realizing the conversion of Swn0 to Dn clk0; this can convert the input differential clock input signals (Swn0 and Swp0) into corresponding differential clock output signals (Dp clk0 and Dn clk0).

[0034] The data driving circuit includes a driving enable signal transmission tube (i.e., m6 and m7) for receiving a driving enable signal, a second switch (i.e., m1), a data driving unit (i.e., m2-m5), and a voltage stabilizing capacitor (c1). Specifically, in this embodiment, transistors m1 to m5 are all N-channel transistors, and m6 and m7 are an N-channel transistor and a P-channel transistor respectively; a transmission tube structure is formed by connecting m6 and m7 in parallel, and the two gates of the transmission tube are respectively used to receive the positive phase driving enable signal (drv-en) and the negative phase driving enable signal (drv-enz). The input end of the transmission tube (i.e., the drain of m6 and the source of m7) is coupled to the output end of the comparator, and the output end of the transmission tube (i.e., the source of m6 and the drain of m7) is coupled to the gate coupled to m1 to control the opening and closing of m1; the input end of m1 is coupled to a voltage source (vp), and the output end of m1 is coupled to the first end of the data driving unit; the structure and function of the data driving unit are the same as those of the above-mentioned clock driving unit. The data driving unit includes a first branch formed by m2 and m4 connected in series, and a second branch formed by m3 and m5 connected in series. The input of m2 is coupled to the output of m1, the input of m3 is coupled to the output of m1, the output of m4 is grounded, and the output of m5 is grounded. The gates of m2 and m5 are connected to the first differential data input signal Swp, and the gates of m3 and m4 are connected to the second differential data input signal Swn. A second resistor R1 is provided between the first and second branches. The first end of the second resistor is coupled to the source of m2 and the drain of m4 (i.e., the first end of the second resistor serves as the first data output end), and the second end of the second resistor is coupled to the source of m3 and the drain of m5 (i.e., the second end of the second resistor serves as the second data output end). The data driving unit also includes a voltage-stabilizing capacitor c1. The first end of c1 is coupled to the output of m1 and the inputs of m2 and m3, and the second end of c1 is grounded. The operating principles of the data driving unit here are the same as those of the clock driving unit in the clock driving circuit, and will not be elaborated on here.

[0035] In addition, the data driving circuit also includes an I0 module, which includes a receiving port for receiving a positive-phase driving enable signal and a receiving port for receiving differential input signals (sp and sn), as well as a transmitting port for outputting differential data input signals (i.e., Swn and Swp); specifically, the I0 module can be turned on under the control of the positive-phase driving enable signal, and generates a corresponding differential data input signal based on the received differential input signal and sends it to the data driving unit, so that the data driving unit can convert it and send it.

[0036] In existing circuit structures, switching from a clock drive circuit to a data drive circuit can cause some problems. For example, when the data drive circuit receives a drive enable signal, m6 and m7 turn on, pulling up the gate voltage of m1 to enable m1 to turn on. At the same time, for example, m2 and m5 in the data drive unit turn on under the action of the first differential data input signal Swp, and the data drive unit is turned on. At this time, since it takes a certain amount of time for m1 to fully turn on, and the data drive unit is already turned on, the current consumed by the data drive unit can only be drawn from m10 and C1, which may reduce the loop operating voltage (vreg). If the loop operating voltage is reduced too much, it will affect the normal operation of the clock drive circuit. It can be understood that the loop operating voltage is the voltage at the connection point between the first switch and the clock drive unit and the connection point between the second switch and the data drive unit.

[0037] To reduce the voltage drop in the loop operating voltage vreg, one common approach is to increase the capacity of the voltage-stabilizing capacitor C1. The greater the charge stored in C1, the smaller the voltage drop in vreg. However, increasing the capacity of C1 requires a large device area, which is costly.

[0038] In order to solve the above problems, the present invention provides a clock and data driving circuit, referring to Figure 2 shown.

[0039] like Figure 2 As shown, the present invention improves the existing data driving circuit structure from the perspective of circuit structure and startup timing, so that the circuit can be quickly charged at the moment of switching, leakage is reduced, and the voltage drop is prevented from affecting the working state of the clock driving circuit, while the area of ​​the voltage stabilizing capacitor can be reduced.

[0040] Specifically, from a circuit structure perspective, a pre-on power transistor m8 is first added. The pre-on power transistor is turned on after the clock drive circuit is started and before the data drive circuit is started, and is used to increase the gate voltage of the second switch to the loop operating voltage. Specifically, in this embodiment, the pre-on power transistor m8 is an N-channel transistor, the gate of the pre-on power transistor m8 is coupled to the gate of m7 and the inverted drive enable signal (drv-enz), the input end of m8 is coupled to the output end of m10, and the output end of m8 is coupled to the gate of m1; compensation capacitors are also added, including a first compensation capacitor C2 and a second compensation capacitor C3, the first end of the first compensation capacitor C2 is coupled to the gate of m1, and the second end of the first compensation capacitor C2 is coupled to the positive phase drive enable signal drv-en; the first end of the second compensation capacitor C3 is coupled to the input end of the transmission tube, and the second end of the second compensation capacitor C3 is coupled to the positive phase drive enable signal drv-en. In terms of startup timing, a delay module can be added before the positive-phase drive enable signal drv-en is sent to the enable signal receiving end (en) of the I0 module. This delay module can adjust the delay time of the positive-phase drive enable signal drv-en, so that the I0 module is started later to give the second switch sufficient reaction time.

[0041] In the circuit provided by the present invention, the clock drive circuit is first activated and operates normally. At this time, the pre-pass power transistor m8 in the data drive circuit is also turned on. It can be understood that the positive-phase drive enable signal drv-en and the negative-phase drive enable signal drv-enz are a pair of opposing signals. That is, when the positive-phase drive enable signal drv-en is high, the negative-phase drive enable signal drv-enz is low, and vice versa. Therefore, before switching to the data drive circuit, the positive-phase drive enable signal drv-en is always low, and the negative-phase drive enable signal drv-enz is always high. This allows the pre-pass power transistor m8 to be turned on to charge point A to the loop operating voltage. It can be understood that the operating voltage of the second switch m1 (denoted as the target voltage) should be greater than the loop operating voltage vreg. In the prior art, it is necessary to pull the voltage applied to the gate of m1 from 0 to the target voltage. However, in this circuit, before starting the data driving circuit, the pre-pass power tube m8 has already increased the voltage applied to the gate of m1 to the loop operating voltage. Therefore, when turning on, it is only necessary to pull the voltage from the loop operating voltage to the target voltage. Therefore, the second switch m1 can be fully turned on more quickly, thereby reducing the possible impact on the clock driving circuit.

[0042] When the data driver circuit needs to be activated, the positive-phase drive enable signal drv_en is pulled high, turning on m6 and m7 and turning off m8. This raises the voltage at the second terminals of capacitors C2 and C3. Because the relative voltage across the capacitors (the potential difference between their plates) cannot change suddenly, when the capacitors are not directly grounded, their voltages relative to ground will jump simultaneously, causing the voltages at the first terminals of capacitors C2 and C3 to increase simultaneously. At this point, the gate-source voltage of m1 only needs to be pulled up from the loop operating voltage to the target voltage. The presence of the compensation capacitor further increases the gate-source voltage of m1. A higher gate-source voltage increases m1's drive capability, allowing it to quickly pull up to the target voltage and prevent the loop operating voltage vreg from dropping. Furthermore, after a delay, drv_en activates the I0 module. Initially, swn and swp are both 0. Only after activation does the output differential data input signals (i.e., swn and swp) be sent to the data driver unit, turning on the data driver unit (for example, turning on m2 and m5, or m3 and m4). Since a certain delay is set for the start of the data driving unit, it can further ensure that the second switch m1 will form a path only after it is fully ready, greatly reducing the voltage drop caused by the early start of the path. Swp and swn are both low before I0 is started, ensuring that there is no leakage path in the corresponding branch.

[0043] By adding a pre-pass power tube and compensation capacitor and adjusting the turn-on timing, the present invention allows for rapid charging at the moment of switching between different lanes, reduces leakage, and prevents voltage drops from affecting the operating state. Compared to increasing the area of ​​the voltage-stabilizing capacitor, although the present invention adds a pre-pass power tube and two compensation capacitors, it does not occupy too much device area. This is because the capacity of the compensation capacitor is very large, typically tens to hundreds of picofarads (pF), and the corresponding area is very large; while the capacity of the additional compensation capacitor is usually a few picofarads, or even femtofarads (fF), which can meet the requirements. It is one to two orders of magnitude smaller than the compensation capacitor and does not occupy too much area. In addition, the solution of the present invention can also reduce the capacity of the compensation capacitor to a certain extent. Depending on the design requirements, it can sometimes be reduced to tens of picofarads, reducing the device area.

[0044] In order to facilitate the description of the present invention, some common English nouns or letters are used for illustrative reference only and are not intended to be restrictive or specific. The scope of protection of the present invention should not be limited by their possible Chinese translations or specific letters.

[0045] It should also be noted that, in this article, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A clock and data driving circuit, characterized in that: including a comparator, a clock driving circuit and a data driving circuit; The comparator, the clock driving circuit and the data driving circuit form a loop circuit, which is used to stabilize the loop operating voltage according to the reference voltage; The clock driving circuit includes a first switch and a clock driving unit coupled to each other, and the clock driving circuit is used to convert a differential clock input signal into a differential clock output signal and send the signal; The data driving circuit includes a driving enable signal transmission tube, a second switch and a data driving unit coupled in sequence. The data driving circuit is used to start under the control of a driving enable signal, convert a differential data input signal into a differential data output signal and send it. The driving enable signal includes a positive phase driving enable signal and a negative phase driving enable signal. The data driving circuit further includes a pre-pass power tube, wherein a gate of the pre-pass power tube is connected to the inverted drive enable signal, an input end of the pre-pass power tube is coupled to the drain of the first switch, and an output end of the pre-pass power tube is coupled to the gate of the second switch. The pre-pass power tube is turned on after the clock driving circuit is started, and is used to increase the gate voltage of the second switch to the loop operating voltage; The data driving circuit further includes a first compensation capacitor and a second compensation capacitor, wherein a first end of the first compensation capacitor is coupled to the gate of the second switch, and a second end of the first compensation capacitor is connected to the positive phase drive enable signal; a first end of the second compensation capacitor is coupled to the input end of the drive enable signal transmission tube, and a second end of the second compensation capacitor is connected to the positive phase drive enable signal; The data driving circuit further includes a delay module, which can delay the differential data input signal until the second switch is turned on before transmitting the signal to the data driving unit.

2. A clock and data driving circuit according to claim 1, characterized in that: The drive enable signal transmission tube is formed by connecting an N-channel transistor and a P-channel transistor in parallel; The two gates of the drive enable signal transmission tube are respectively used to receive one of the positive phase drive enable signal and the negative phase drive enable signal, the input end of the drive enable signal transmission tube is coupled to the output end of the comparator, and the output end of the drive enable signal transmission tube is coupled to the gate of the second switch.

3. A clock and data driving circuit according to claim 2, characterized in that: An input terminal of the first switch is coupled to a voltage source, an output terminal of the first switch is coupled to one terminal of the clock driving circuit, and the other terminal of the clock driving circuit is grounded.

4. A clock and data driving circuit according to claim 2, characterized in that: Also included is an I0 module, the I0 module including a receiving port for receiving the positive phase drive enable signal; The I0 module is turned on under the control of the positive phase driving enable signal to generate the differential data input signal and provide it to the data driving unit.

5. A clock and data driving circuit according to claim 4, characterized in that: The delay module is provided before the receiving port, and is used to delay the positive phase drive enable signal and input it into the receiving port, so as to turn on the I0 module after the second switch is turned on, generate the differential data input signal, and provide it to the data driving unit; The delay time of the delay module is adjustable.

6. A clock and data driving circuit according to claim 5, characterized in that: The comparator is an operational amplifier, a first input terminal of the operational amplifier is used to input the reference voltage, a second input terminal of the operational amplifier is used to input the loop operating voltage, and an output terminal of the operational amplifier is coupled to the gate of the first switch and the input terminal of the drive enable signal transmission tube respectively; The loop operating voltage is a voltage at a connection point between the first switch and the clock driving unit and a voltage at a connection point between the second switch and the data driving unit.

7. The clock and data driving circuit according to claim 1, wherein: The data driving circuit further includes a voltage-stabilizing capacitor, a first end of the voltage-stabilizing capacitor is coupled to the output end of the second switch, and a second end of the voltage-stabilizing capacitor is grounded.

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