Processor system, operating method of processor system, and electronic device

Abstract

The embodiment of the invention provides a processor system, an operation method of the processor system and electronic equipment, relates to the technical field of electronics, and aims at improving the running stability of the processor system. According to the specific scheme, the processor system comprises a common input end, a plurality of delay circuits and a plurality of processor cores, wherein each delay circuit in the plurality of delay circuits corresponds to at least one processor core in the plurality of processor cores. The common input end is used for receiving a wake-up signal, each delay circuit is used for acquiring the wake-up signal from the common input end and randomly delaying the wake-up signal to obtain a delayed wake-up signal, and the at least one processor core is used for converting from a dormant state or a low-power-consumption state to a working state based on the delayed wake-up signal. The embodiment of the invention is used for the process that the processor core responds to the wake-up signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technologies, and in particular, to a processor system, an operation method of the processor system, and an electronic device. Background Art

[0002] A processor system may include multiple processor cores, and data processing may be performed between the multiple processor cores based on instructions or interaction signals. When multiple processor cores in a chip receive instructions or interaction signals simultaneously, the multiple processor cores need to respond to the instructions or interaction signals and perform certain data processing operations. Each processor core depends on a power supply module for power supply when performing data processing operations. As the number of processor cores increases, the problem of supply voltage becomes more prominent.

[0003] When multiple processor cores are working simultaneously, changes in the load will cause the load current of the multiple processor cores to change violently. Due to the presence of inductance in the power distribution network (PDN), it will cause ripples in the supply voltage, resulting in problems with current changes. Among them, a sudden upward change in the load current will cause a voltage drop. When the voltage drops to the lowest voltage at which the digital circuits in the processor system can work normally, the digital circuits will malfunction, which will cause the processor system to malfunction and reduce the operating stability. Summary of the Invention

[0004] The embodiments of the present application provide a processor system, an operation method of the processor system, and an electronic device, which improve the operating stability of the processor system.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions.

[0006] In a first aspect, the embodiments of the present application provide a processor system, which includes: a common input terminal, multiple delay circuits, and multiple processor cores, and each delay circuit in the multiple delay circuits corresponds to at least one processor core in the multiple processor cores. The common input terminal is used to receive a wake-up signal, each delay circuit is used to obtain the wake-up signal from the common input terminal and perform random delay on the wake-up signal to obtain a delayed wake-up signal, and at least one processor core is used to convert from a sleep state or a low-power state to a working state based on the delayed wake-up signal.

[0007] Thus, for the processor system provided by the embodiments of the present application, after receiving a wake-up signal through a common input terminal, the wake-up signal can be randomly delayed by a delay circuit, so that the times when at least one processor core receives the wake-up signal will be randomly different, that is, multiple processor cores will usually be woken up at different times, which can avoid the problem of voltage drop caused by sudden changes in load current, prevent the processor system from malfunctioning, and improve the operating stability.

[0008] In a possible design, each delay circuit includes: a random number generator and a delay counter. The random number generator is used to generate random numbers, and the delay counter is used to delay the wake-up signal based on the random numbers to obtain a delayed wake-up signal. Thus, by generating random numbers with the random number generator, the delay counter can randomly delay the wake-up signal, and multiple processor cores will usually be woken up at different times, avoiding the problem of voltage drop caused by sudden changes in load current and preventing the processor system from malfunctioning.

[0009] In a possible design, among the multiple random numbers generated by the multiple random number generators in the multiple delay circuits, due to randomness, at least some of the random numbers are different. Thus, the difference of at least some random numbers can avoid conflicts between the delayed wake-up signals output by different delay circuits, thereby avoiding the problem that a relatively large number of processor cores are woken up simultaneously.

[0010] In a possible design, at least some of the random numbers are within different numerical ranges. Thus, it can be ensured that at least some of the random numbers are different, avoiding conflicts between the delayed wake-up signals output by different delay circuits, thereby avoiding the problem that a relatively large number of processor cores are woken up simultaneously.

[0011] In a possible design, the processor system further includes an arbiter. If the time difference between at least two delayed wake-up signals from at least two delay circuits is less than a preset threshold, the arbiter is used to allow the first delayed wake-up signal among the at least two delayed wake-up signals to be output to at least one first processor core corresponding to the first delayed wake-up signal, and control the second delayed wake-up signal among the at least two delayed wake-up signals other than the first delayed wake-up signal to be further delayed. Since the randomly generated delays may cause the at least two delayed wake-up signals to be close or even the same in time, the arbiter can arbitrate the at least two delayed wake-up signals at this time to ensure that the at least two delayed wake-up signals do not conflict, avoiding the problem that multiple processor cores are woken up simultaneously.

[0012] In a possible design, the arbiter is specifically configured to feedback the second delayed wake-up signal to the second delay circuit corresponding to the second delayed wake-up signal. The second delay circuit is further configured to further delay the second delayed wake-up signal to obtain a new delayed wake-up signal, and the new delayed wake-up signal is provided to at least one second processor core corresponding to the second delay circuit. Thus, the processor system further delays the second delayed wake-up signal through the second delay circuit, and then provides the new delayed wake-up signal to at least one second processor core corresponding to the second delay circuit, which can ensure that the first delayed wake-up signal and the second delayed wake-up signal do not reach the processor core simultaneously, and avoid the problem that multiple processor cores are woken up simultaneously.

[0013] In a second aspect, an embodiment of the present application provides an operation method for a processor system, and the method includes: a common input terminal in the processor system receives a wake-up signal. Each of multiple delay circuits in the processor system obtains the wake-up signal from the common input terminal, and performs a random delay on the wake-up signal to obtain a delayed wake-up signal, and each delay circuit corresponds to at least one processor core among multiple processor cores in the processor system. At least one processor core is converted from a sleep state or a low-power state to a working state based on the delayed wake-up signal.

[0014] In a possible design, performing a random delay on the wake-up signal includes: generating a random number by using a random number generator, and delaying the wake-up signal based on the random number by using a delay counter.

[0015] In a possible design, among multiple random numbers generated by multiple random number generators in multiple delay circuits, at least some random numbers are different.

[0016] In a possible design, at least some random numbers are located in different numerical ranges.

[0017] In a possible design, the method further includes: if the time difference between at least two delayed wake-up signals from at least two delay circuits is less than a preset threshold, allowing the first delayed wake-up signal among the at least two delayed wake-up signals to be output to at least one first processor core corresponding to the first delayed wake-up signal, and controlling the second delayed wake-up signal other than the first delayed wake-up signal among the at least two delayed wake-up signals to be further delayed.

[0018] In a possible design, further delaying a second delayed wake-up signal among at least two delayed wake-up signals except the first delayed wake-up signal includes: feeding back the second delayed wake-up signal to a second delay circuit corresponding to the second delayed wake-up signal. The second delay circuit is used to further delay the second delayed wake-up signal to obtain a new delayed wake-up signal, and the new delayed wake-up signal is provided to at least one second processor core corresponding to the second delay circuit.

[0019] For the beneficial effects of the second aspect, reference can be made to the description of the first aspect.

[0020] In a third aspect, an embodiment of the present application provides an electronic device, which includes one or more memories, and one or more processor systems. The one or more memories and the one or more processor systems are coupled. The one or more memories are used to store computer instructions, and the processor system is used to execute the computer instructions to implement the operation method of the processor system.

[0021] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions run on an electronic device, the electronic device is caused to execute the operation method of the processor system in any of the above aspects and any possible implementation manners.

[0022] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a computer or a processor, the computer or the processor is caused to execute the operation method of the processor system in any of the above aspects and any possible implementation manners.

[0023] It can be understood that any of the above provided processor systems, electronic devices, computer-readable storage media, or computer program products can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods, and will not be elaborated here.

[0024] These aspects or other aspects of the present application will be more clearly understood in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of a power distribution network of a processor system provided by an embodiment of the present application;

[0026] Figure 2 is an equivalent schematic diagram of a power distribution network provided by an embodiment of the present application;

[0027] Figure 3 is a schematic structural diagram of a multi-core processor provided by an embodiment of the present application;

[0028] Figure 4 A flowchart for processing an interrupt signal provided by an embodiment of the present application;

[0029] Figure 5 A flowchart for processing a power integrity management decision provided by an embodiment of the present application;

[0030] Figure 6 A schematic structural diagram of a processor system provided by an embodiment of the present application;

[0031] Figure 7 Another schematic structural diagram of a processor system provided by an embodiment of the present application;

[0032] Figure 8 A flowchart of a random number generator provided by an embodiment of the present application;

[0033] Figure 9 A schematic structural diagram of a delay circuit provided by an embodiment of the present application;

[0034] Figure 10 A timing diagram of a delay circuit provided by an embodiment of the present application;

[0035] Figure 11 Another schematic structural diagram of a processor system provided by an embodiment of the present application;

[0036] Figure 12 A flowchart of an operation method of a processor system provided by an embodiment of the present application;

[0037] Figure 13 Another flowchart of an operation method of a processor system provided by an embodiment of the present application. Detailed implementation manners

[0038] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this embodiment, unless otherwise specified, "a plurality of" means two or more than two.

[0039] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, unless otherwise specified, " / " means "or", for example, A / B may mean A or B; "and / or" herein is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0040] First, the power distribution network involved in the embodiments of the present application will be described. As Figure 1 shown, Figure 1 is a schematic structural diagram of the power distribution network of the processor system provided by the embodiments of the present application. Figure 1 The printed circuit board (PCB) 10 is shown in . A power supply module (voltage regulator model, VRM) 11, a first decoupling capacitor 12, and a package structure 13 are integrated on the printed circuit board 10. Among them, the package structure 13 is soldered on the printed circuit board 10. A second decoupling capacitor 14 and a silicon chip 15 are integrated in the package 13, and the processor core is integrated on the silicon chip 15. Among them, the power supply module 11, the first decoupling capacitor 12, and the second decoupling capacitor 14 form the main power supply network. In addition to the above structure, although not shown in Figure 1 , in the power distribution network, there are also other resistors, inductors, and capacitors. These resistors, inductors, and capacitors can be resistors, inductors, and capacitor devices manufactured in the chip, or equivalent resistors, equivalent inductors, and equivalent capacitors obtained by equivalent transformation of some processing structures of the chip (such as metal traces for power supply, etc.). Therefore, there will also be resistors, inductors, etc. on the transmission path between the power supply module 11, the first decoupling capacitor 12, the second decoupling capacitor 14, and the processor core. Based on the above devices, an equivalent schematic diagram of the power distribution network when the processor core works as shown in Figure 2 can be obtained. Specifically, Figure 1 the power supply module 11 in is equivalent to Figure 2 the power supply in . The power supply module 11 is coupled to the decoupling capacitor 12 through resistors and inductors, and the power supply module 11 is also coupled to the on-package decoupling capacitor 14 through resistors and inductors. Among them, the presence of the capacitor has a compensating effect on the voltage ripple. However, the presence of the inductor will cause voltage ripple when the current changes suddenly.

[0041] Secondly, the scenario of load current mutation involved in the embodiments of the present application will be described. When multiple processor cores are in the low-power mode or the sleep state, if an interrupt signal generated by the interrupt controller or a broadcast signal of an event is received, the multiple processor cores will be awakened, that is, they will be switched from the low-power mode or the sleep state to the working state (or the running state) to respond to the interrupt signal or the broadcast signal, and each processor core will complete the corresponding operations.

[0042] For example, as Figure 3 shown, Figure 3An interrupt source 31 and multiple processor cores 32 are shown. Among them, the interrupt events generated by the interrupt source 31 can be broadcast to the multiple processor cores 32, and the multiple processor cores 32 will be awakened by the interrupt events. Also, for example, the interrupt source can be replaced by a wake-up event source, and the wake-up event source can generate a certain notification signal to wake up the multiple processor cores.

[0043] Among them, multiple processor cores in the low-power mode or sleep state have relatively low power consumption, and the supply current of the power supply module is relatively small at this time. When the multiple processor cores are awakened, the multiple processor cores have relatively large operating power consumption, and the supply current of the power supply module is relatively large at this time. Since the supply current of the power supply module has a sudden change from small to large, and there is an inductor in the loop of the power distribution network as Figure 2 shown, the supply voltage of the power supply module will drop. In an extreme scenario, the supply voltage of the power supply module will drop below the minimum operating voltage required for the normal operation of the digital circuit, and the digital circuit will malfunction, which will cause the processor system to malfunction and affect the stable operation of the system.

[0044] In a possible implementation manner, as Figure 4 shown, Figure 4 is a processing flowchart of an interrupt signal provided by an embodiment of the present application. Among them, a register can obtain a delay value through a data bus and temporarily store the delay value. A counter starts counting when it receives an interrupt signal, and a comparator compares the count value of the counter with the delay value. When the count value is equal to the delay value, the delayed interrupt signal is sent to the processor core. However, in this solution, only the interrupt signal is delayed, and a fixed configurable delay is adopted, which cannot completely solve the power integrity problem of the processor core system.

[0045] In a possible implementation manner, as Figure 5 shown, Figure 5A processing flowchart for power integrity management decision-making provided by an embodiment of this application. Among them, the processor core may include a remote noise indicator, a local noise indicator, and a droop mitigation system. Among them, the droop mitigation system may include multiple sensors, such as a measurement component, a noise level analysis component, an instruction component, and a feedback component, etc. Specifically, the droop mitigation system can obtain the disturbances of other processor cores through the remote noise indicator, and can obtain the data of this processor core through the local noise indicator. Thus, the processor core can make power integrity management decisions. However, this solution is relatively complex, requires obtaining the disturbances of other processor cores, and requires multiple sensors to cooperate to make power integrity management decisions.

[0046] To solve the problem of processor system operation failures and improve operation stability, an embodiment of this application provides a processor system. After receiving a wake-up signal through a common input terminal, the processor system can randomly delay the wake-up signal through a delay circuit. Then, the random delay causes at least one processor core to receive the wake-up signal at different times, that is, multiple processor cores are usually woken up at different times, which can avoid the problem of voltage drop caused by sudden changes in load current and prevent the processor system from malfunctioning.

[0047] In some embodiments, the processor system provided by an embodiment of this application may be a system on a chip (SoC) or a server chip, etc. The device to which the processor system provided by an embodiment of this application is applied may be an execution device, and the execution device may be a terminal, such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality (AR) device, a virtual reality (VR) device, and a vehicle-mounted terminal, etc., or may also be a server cluster, etc. It should be understood that although the foregoing, such as Figure 1 , takes the processor system being located on the same chip or silicon wafer, that is, the system is applied to an SOC as an example for illustration, the actual processor system may be distributed on multiple chips, or located in a module including multiple chips. This embodiment does not limit the physical form of the processor system.

[0048] The processor system provided by an embodiment of this application will be introduced in detail below. As Figure 6As shown Figure 6 FIG. 0 is a schematic structural diagram of a processor system provided by an embodiment of the present application. The processor system 60 may include a common input terminal 61, a plurality of delay circuits 62, and a plurality of processor cores 63. Each delay circuit 62 in the plurality of delay circuits 62 corresponds to at least one processor core 63 in the plurality of processor cores 63. Figure 6 m delay circuits 62 and n processor cores 63 are shown in FIG. 1. m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. The m delay circuits 62 are respectively a delay circuit 62_1, a delay circuit 62_2,..., a delay circuit 62_m. Assume that one or more of the delay circuits 62 correspond to i processor cores 63, that is, the delay circuit 62_1 corresponds to the processor cores 63_1 to the processor cores 63_i, the delay circuit 62_2 corresponds to the processor cores 63_i + 1 to the processor cores 63_2i. In addition, the delay circuit 62_m corresponds to the processor core 63_n. Wherein, i is an integer greater than or equal to 1, and the specific value of i may be related to the change rate of the load current of the processor system 60. In addition, the number of processor cores 63 corresponding to each delay circuit 62 may also be different.

[0049] The common input terminal 61 is used to receive a wake-up signal. Exemplarily, the wake-up signal is a signal that needs to be broadcast to the plurality of processor cores 63. Specifically, the wake-up signal may be Figure 3 an interrupt signal generated by an interrupt source in FIG. 2, and the wake-up signal may also be a certain notification signal generated by a wake-up event source. In one example, assume that a certain processor core writes a data into the cache, then the processor core will generate a certain notification signal to other processor cores to ensure cache consistency. The notification signal may be an example of the interrupt signal. It can be understood that the interrupt signal may have other forms, and the wake-up event source may also be a software or hardware unit outside the processor core, such as a peripheral device. The embodiment is not limited thereto.

[0050] Each delay circuit 62 is used to obtain the wake-up signal from the common input terminal 61 and perform a random delay on the wake-up signal to obtain a delayed wake-up signal. Exemplarily, in order to avoid the plurality of processor cores 63 being simultaneously awakened by the wake-up signal, resulting in a sudden change in the load current of the processor system 60, the delay circuit 62 may perform a random delay on the wake-up signal, that is, the plurality of processor cores are usually awakened at different times.

[0051] For example, for the first wake-up signal, through respective random delays, delay circuit 62_1 can delay the first wake-up signal by 20 nanoseconds (ns), delay circuit 62_2 can delay the first wake-up signal by 30 ns, and delay circuit 62_m can delay the first wake-up signal by 36 ns. For the second wake-up signal, through respective random delays, delay circuit 62_1 can delay the second wake-up signal by 24 ns, delay circuit 62_2 can delay the second wake-up signal by 28 ns, and delay circuit 62_m can delay the second wake-up signal by 36 ns. That is, the delay time of each delay circuit 62 for the wake-up signal is random. The delay times of multiple delay circuits 62 for the same wake-up signal can be different, and the delay times of the same delay circuit for multiple wake-up signals can also be different, thereby reducing the possibility that the wake-up signals delayed respectively wake up the corresponding processor cores simultaneously.

[0052] At least one processor core 63 is used to convert from a sleep state or a low-power state to a working state based on the delayed wake-up signal. Exemplarily, the sleep state means that the processor core stores all running real-time data in the memory and turns off unnecessary hardware to save power. When the processor core 63 is in the sleep state, the operations on the processor system 60 are invalid operations, that is, data or instructions are not actually processed. Only when the processor core 63 is in the working state can it process service data and instructions. The processor core 63 in the low-power state runs at a lower clock speed, and its power supply is also at a lower level. Continuing with the example of the first wake-up signal, starting from the input of the first wake-up signal at the common input terminal 61, processor cores 63_1 to processor cores 63_i need to wait 20 ns to receive the first wake-up signal, processor cores 63_i + 1 to processor cores 63_2i need to wait 30 ns to receive the first wake-up signal, and processor cores 63_n need to wait 36 ns to receive the first wake-up signal. Thus, multiple processor cores receive the wake-up signal at different times, that is, multiple processor cores are woken up at different times, which can avoid the problem of voltage drop caused by sudden changes in load current and prevent the processor system 60 from malfunctioning. In addition, due to the reduction in the amplitude of the voltage drop, the power supply system of the processor system 60 can reduce the voltage protection area, thereby overall reducing the power supply voltage of the processor system 60 and obtaining energy efficiency benefits.

[0053] Optionally, as Figure 7 shown, Figure 7 is a schematic structural diagram of another processor system provided by an embodiment of the present application. Figure 7Multiple delay circuits 62 and multiple processor cores 63 are shown, where the multiple delay circuits 62 are respectively a delay circuit 62_1, a delay circuit 62_2, and a delay circuit 62_3, and the multiple processor cores 63 are respectively a processor core 63_1, a processor core 63_2, and a processor core 63_3. It is assumed that each delay circuit 62 corresponds to a processor core 63, that is, the delay circuit 62_1 corresponds to the processor core 63_1, the delay circuit 62_2 corresponds to the processor core 63_2, and the delay circuit 62_3 corresponds to the processor core 63_3. Each delay circuit 62 may include a random number generator 621 and a delay counter 622. The input end of the random number generator 621 is coupled to the common input end 61, and the output end of the random number generator 621 is coupled to the input end of the delay counter.

[0054] The random number generator 621 is used to generate random numbers. Exemplarily, the random number generator 621 is used to generate a random value each time, where there is no relationship between the previous value and the next value generated.

[0055] Exemplarily, the random number generator 621 can be implemented by a linear feedback shift register (LFSR), the random number generator 621 can also be implemented by cellular automata (CA), and the random number generator 621 can also be implemented in other ways.

[0056] In one implementation, based on the Figure 7 embodiment, the processor system 60 may further include a random entropy source 64. Figure 7 A random entropy source 64_1, a random entropy source 64_2, and a random entropy source 64_3 are shown. Each random entropy source 64 corresponds to a delay circuit 62, that is, the random entropy source 64_1 corresponds to the delay circuit 62_1, the random entropy source 64_2 corresponds to the delay circuit 62_2, and the random entropy source 64_3 corresponds to the delay circuit 62_3. The random entropy source 64 can provide a "seed" for the random number generator 621. The "seed" is a random seed, and the random number generator 621 can continuously iterate to generate random numbers with the random seed as the initial condition.

[0057] Exemplarily, the input end of the random entropy source 64 is also coupled to the output end of the processor core 63. In Figure 7Based on the embodiments, the output end of the processor core 63_1 is coupled to the input end of the random entropy source 64_1, the output end of the processor core 63_2 is coupled to the input end of the random entropy source 64_2, and the output end of the processor core 63_3 is coupled to the input end of the random entropy source 64_3. Among them, the random entropy source 64 can generate a random seed based on events of the processor core 63. The events are signals such as a mispredicted jump instruction or a cache miss, and such events can also be understood as random entropy source events. In addition, the input end of the random entropy source 64 can also be coupled to the common input end 61, and the random entropy source 64 can also generate a random seed based on the wake-up signal received by the common input end 61. Among them, when the random entropy source 64 receives a new signal, it will drive the random number generator 621 to generate a new random number.

[0058] Exemplarily, as Figure 8 shown, Figure 8 is a flowchart of a random number generator provided by an embodiment of the present application. Among them, the process of the random number generator 621 can include: S801, reset the random number generator. S802, determine whether a random entropy source event occurs. If a random entropy source event does not occur, execute S803; if a random entropy source event occurs, execute S805. S803, determine whether a wake-up signal occurs. If a wake-up signal does not occur, execute S804; if a wake-up signal occurs, execute S805. S804, keep the random number of the random number generator. S805, update the random number of the random number generator. Among them, the processes of S801 to S805 are continuously performed to update the random number of the random number generator 621 in real time.

[0059] Exemplarily, among the multiple random numbers generated by the multiple random number generators 621 in the multiple delay circuits 62, at least some of the random numbers are different. Exemplarily, among the multiple random numbers generated by the multiple random number generators 621 in the multiple delay circuits 62, all the random numbers can also be different. Exemplarily, the number of allowable identical random numbers is related to the change rate of the load current allowed by the processor system 60.

[0060] Exemplarily, at least some of the random numbers are in different numerical ranges. Exemplarily, the processor system 60 can add different delay offsets to different random number generators 621 to avoid waking up the processor cores 63 simultaneously. For example, assume that the processor system 60 includes m delay circuits 62, and the range of the random numbers generated by the random number generator 621 is 0 to 16. Then, the delay offset of the first random number generator 621 can be 0, the delay offset of the second random number generator 621 can be 16, the delay offset of the third random number generator 621 can be 32, and so on. The delay offset of the mth random number generator 621 can be 16*(m - 1). Thus, at least some of the random numbers are in different numerical ranges, and the delayed wake-up signals obtained based on at least some of the random numbers will not conflict, avoiding the problem that multiple processor cores are woken up simultaneously.

[0061] The delay counter 622 is used to delay the wake-up signal based on the random number to obtain a delayed wake-up signal. Exemplarily, when the delay counter 622 receives the wake-up signal, the delay counter 622 starts counting. When the count value is equal to the random number, the wake-up signal is output. For the processor system 60, at least some of the random numbers of each delay counter 622 are different, so that multiple processor cores 63 will not be woken up simultaneously.

[0062] Taking the random number generator 621 as a linear feedback shift register as an example, on the basis of the embodiments of Figure 7 and Figure 8 , as shown in Figure 9 shown, Figure 9 is a schematic structural diagram of a delay circuit provided by an embodiment of the present application. Both the random number generator 621 and the delay counter 622 can include a plurality of D-type flip-flops (DFF). Among them, when receiving any one of the signals of jump instruction prediction error, data buffer miss, and wake-up signal, the random entropy source 64 will generate a random seed, and the random number generator 621 will generate a new random number based on the random seed, and this random number can be used as a delay threshold. When receiving the wake-up signal, the delay counter 622 will be initialized and load the random number generated by the random number generator 621 as the initial value. The delay counter 622 can subtract 1 every fixed time. When the delay counter 622 subtracts from the random number to 1, the wake-up signal is output, that is, the delayed wake-up signal is output.

[0063] Exemplarily, the timing diagram of the delay circuit 62 is as shown in Figure 10As shown, the random number generated by the random number generator 621 is 37. When the delay counter 622 receives the wake-up signal, the delay counter 622 loads 37 as the initial value. For each clock cycle run, the count value of the delay counter 622 decreases by 1. When the count value of the delay counter 622 decreases to 1, the delayed wake-up signal is output. When the count value of the delay counter 622 decreases to 0, the delay counter 622 stops working.

[0064] Optionally, as Figure 11 shown, Figure 11 is a schematic structural diagram of another processor system provided by an embodiment of the present application. The processor system 60 may further include an arbiter 65. Among them, the input end of the arbiter 65 is coupled to the output ends of a plurality of delay circuits 62, the output end of the arbiter 65 is coupled to a plurality of processor cores 63, and the output end of the arbiter 65 is also coupled to the input ends of a plurality of delay circuits 62. Figure 11 The delay circuit 62_1 and the delay circuit 62_2 are shown in Figure 11 . The delay circuit 62_1 corresponds to the processor core 63_1, and the delay circuit 62_2 corresponds to the processor core 63_2. In addition, Figure 11 the random number generator 621_1 and the delay counter 622_1 in the delay circuit 62_1, and the random number generator 621_2 and the delay counter 622_2 in the delay circuit 62_2 are also shown. The arbiter 65 can be equivalently considered to include two arbitration channels, namely arbitration channel 1 and arbitration channel 2. Among them, arbitration channel 1 is used to arbitrate the wake-up signals of the delay circuit 62_1, and arbitration channel 2 is used to arbitrate the wake-up signals of the delay circuit 62_2.

[0065] Among them, the arbiter 65 is used to, if the time difference between at least two delayed wake-up signals from at least two delay circuits is less than a preset threshold, allow the first delayed wake-up signal among the at least two delayed wake-up signals to be output to at least one first processor core corresponding to the first delayed wake-up signal, and control the second delayed wake-up signal among the at least two delayed wake-up signals other than the first delayed wake-up signal to be further delayed. That is, the randomly generated delay cannot guarantee that the delay times of different signals are necessarily different. When the times of different delayed wake-up signals are close or even may be the same, the arbiter 65 ensures that these signals are not output simultaneously.

[0066] Exemplarily, the above preset threshold may be a small time window. The arbiter 65 can obtain the delayed wake-up signals from multiple delay circuits 62. If there is no conflict among the multiple delayed wake-up signals, that is, the time difference between these multiple delayed wake-up signals is greater than or equal to the preset threshold, then these multiple delayed wake-up signals can be directly transmitted to the corresponding processor cores 63. If there is a conflict among the multiple delayed wake-up signals, that is, the time difference between these multiple delayed wake-up signals is less than the preset threshold, then the arbiter 65 can arbitrate among these multiple delayed wake-up signals. The successfully arbitrated delayed wake-up signals can be directly transmitted to the corresponding processor cores 63, and the failed arbitrated delayed wake-up signals are further delayed to avoid conflicts and ensure that multiple wake-up signals reach their respective corresponding processor cores at different times.

[0067] Exemplarily, continuing to refer to Figure 11 , assuming that the time difference between the delayed wake-up signal from the delay circuit 62_1 and the delayed wake-up signal from the delay circuit 62_2 is less than the preset threshold, the arbiter 65 can arbitrate between the delayed wake-up signal from the delay circuit 62_1 and the delayed wake-up signal from the delay circuit 62_2. Assuming that the delayed wake-up signal from the delay circuit 62_1 is the successfully arbitrated signal, then the delayed wake-up signal from the delay circuit 62_1 is used as the first delayed wake-up signal and transmitted to the processor core 63_1, and the delayed wake-up signal from the delay circuit 62_2 is used as the second delayed wake-up signal and further delayed.

[0068] For example, the arbiter 65 can arbitrate among multiple delayed wake-up signals according to the priority order. The arbiter 65 can transmit the delayed wake-up signal with a higher priority order to the corresponding processor core, and further delay the delayed wake-up signal with a lower priority order. Specifically, the arbiter 65 can determine the priority order of the delayed wake-up signals from each delay circuit 62 in a polling manner. For example, at a certain moment, the delayed wake-up signal from the delay circuit 62_1 has a high priority, and the delayed wake-up signal from the delay circuit 62_2 has a low priority. At the next moment after a certain moment, the delayed wake-up signal from the delay circuit 62_1 has a low priority, and the delayed wake-up signal from the delay circuit 62_2 has a high priority.

[0069] In addition, the further delay method may include waiting for a preset number of clock cycles for the second delayed wake-up signal to be transmitted to the corresponding processor core 63. For example, waiting for 4 clock cycles for the second delayed wake-up signal to be transmitted to the corresponding processor core.

[0070] Optionally, the arbiter 65 is specifically configured to feedback the second delayed wake-up signal to the second delay circuit corresponding to the second delayed wake-up signal. The second delay circuit is further configured to further delay the second delayed wake-up signal to obtain a new delayed wake-up signal, and the new delayed wake-up signal is provided to at least one second processor core 63 corresponding to the second delay circuit, so as to have no conflict with other delayed signals.

[0071] Exemplarily, the further delay method may further include transmitting the second delayed wake-up signal to the corresponding second delay circuit to obtain a new delayed wake-up signal. Continuing to refer to Figure 11 , for each arbitration channel, the delayed wake-up signal with arbitration failure may be transmitted to the corresponding delay counter 622, and the delay counter 622 will be restarted and continue to decrement by 1 at a fixed time. When the delay counter 622 decrements to 1, a new delayed wake-up signal will be output, and the new delayed wake-up signal may wake up at least one second processor core 63 corresponding to the second delay circuit.

[0072] It can be understood that the second delayed wake-up signal is equivalent to the enable signal of the delay counter 622. In addition, the wake-up signal may also be equivalent to the enable signal of the delay counter 622. When the delay counter 622 receives the wake-up signal or the delayed wake-up signal, it will start counting.

[0073] Applied to the above processor system, the operation method of the processor system provided in the embodiments of the present application will be introduced below. As Figure 12 shown, Figure 12 is a flowchart of an operation method of a processor system provided in an embodiment of the present application. The method includes S1201 to S1203.

[0074] S1201. The common input terminal in the processor system receives a wake-up signal. Exemplarily, the wake-up signal may be an interrupt signal generated by an interrupt source, or the wake-up signal may be a certain notification signal generated by a wake-up event source. The specific implementation manner of S1201 may refer to the above description of the common input terminal.

[0075] S1202. Each delay circuit in the multiple delay circuits in the processor system obtains the wake-up signal from the common input terminal, randomly delays the wake-up signal to obtain a delayed wake-up signal, and each delay circuit corresponds to at least one processor core in the multiple processor cores in the processor system. Exemplarily, the delay time of each delay circuit for the wake-up signal is random, the delay times of multiple delay circuits for the same wake-up signal may be different, and the delay times of the same delay circuit for multiple wake-up signals may also be different. The specific implementation manner of S1202 may refer to the above description of the delay circuit.

[0076] S1203. At least one processor core transitions from a sleep state or a low-power state to a working state based on the delayed wake-up signal. Exemplarily, the multiple processor cores receive the wake-up signal at different times, that is, the multiple processor cores are awakened at different times, which can avoid the problem of voltage drop caused by sudden changes in load current and prevent the processor system from malfunctioning.

[0077] Optionally, S1202 may include: generating a random number using a random number generator, and delaying the wake-up signal based on the random number using a delay counter.

[0078] Exemplarily, the processor system can use a random number generator to generate a random number, enabling the delay counter to randomly delay the wake-up signal to ensure that multiple processor cores are not awakened simultaneously, avoiding the problem of voltage drop caused by sudden changes in load current and preventing the processor system from malfunctioning.

[0079] Optionally, the method further includes: if the time difference between at least two delayed wake-up signals from at least two delay circuits is less than a preset threshold, allowing the first delayed wake-up signal among the at least two delayed wake-up signals to be output to at least one first processor core corresponding to the first delayed wake-up signal, and controlling the second delayed wake-up signal among the at least two delayed wake-up signals other than the first delayed wake-up signal to be further delayed.

[0080] Optionally, controlling the second delayed wake-up signal among the at least two delayed wake-up signals other than the first delayed wake-up signal to be further delayed includes: feeding back the second delayed wake-up signal to the second delay circuit corresponding to the second delayed wake-up signal, and using the second delay circuit to further delay the second delayed wake-up signal to obtain a new delayed wake-up signal, and the new delayed wake-up signal is provided to at least one second processor core corresponding to the second delay circuit.

[0081] Exemplarily, the processor system can use an arbiter to arbitrate at least two delayed wake-up signals to ensure that the at least two delayed wake-up signals do not conflict and avoid the problem of multiple processor cores being awakened simultaneously.

[0082] Applied to the above processor system, the delay process of the wake-up signal by the processor system is as Figure 13 shown, Figure 13 which is a flowchart of another operation method of the processor system provided in an embodiment of the present application. The method includes S1301 to S1310.

[0083] S1301. Reset the delay counter to 0.

[0084] S1302. Whether a wake-up signal is input at the common input terminal. If a wake-up signal is input at the common input terminal, then execute S1303.

[0085] S1303. The delay counter loads a random number from the random number generator.

[0086] S1304. The count value of the delay counter starts to decrease by 1 from the random number.

[0087] S1305. Whether the count value of the delay counter is equal to 1. If the count value of the delay counter is not equal to 1, then execute S1304. If the count value of the delay counter is equal to 1, then execute S1306.

[0088] S1306. Output the delayed wake-up signal to the arbiter.

[0089] S1307. The arbiter determines whether there is a conflict among multiple delayed wake-up signals. If there is a conflict among multiple delayed wake-up signals, then execute S1303. If there is no conflict among multiple delayed wake-up signals, then execute S1308 and S1309.

[0090] S1308. Output the delayed wake-up signal to the processor core.

[0091] S1309. Reset the delay counter to 0, and then execute S1302.

[0092] S1310. Wake up the processor core.

[0093] An embodiment of this application further provides an electronic device, which includes one or more memories, and one or more processor systems. The one or more memories and the one or more processor systems are coupled. The one or more memories are used to store computer instructions, and the processor system is used to execute the computer instructions to implement the operation method of the processor system.

[0094] An embodiment of this application further provides a computer storage medium, in which computer instructions are stored. When the computer instructions run on the electronic device, the electronic device is enabled to execute the above relevant method steps to implement the operation method of the processor system in the above embodiment.

[0095] An embodiment of this application further provides a computer program product. When the computer program product runs on a computer, the computer is enabled to execute the above relevant steps to implement the operation method of the processor system executed by the electronic device in the above embodiment.

[0096] In addition, an embodiment of the present application further provides a device, which may specifically be a chip, a component, or a module. The device may include a processor and a memory connected to each other. The memory is used to store computer-executable instructions. When the device runs, the processor may execute the computer-executable instructions stored in the memory, so that the chip executes the operation methods of the processor system executed by the electronic device in the above method embodiments.

[0097] Among them, the processor system, the electronic device, the computer storage medium, the computer program product, or the chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be elaborated here.

[0098] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and simplicity of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0099] In several embodiments provided in the present application, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the module or unit is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0100] The unit described as a separate component may or may not be physically separated. The component displayed as a unit may be a physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, each functional unit in each embodiment of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0102] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0103] The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A processor system, characterized in that, Comprising: A common input terminal, a plurality of delay circuits, and a plurality of processor cores, wherein each delay circuit in the plurality of delay circuits corresponds to at least one processor core in the plurality of processor cores; The common input terminal is configured to: receive a wake-up signal; Each of the delay circuits is configured to: obtain the wake-up signal from the common input terminal and perform a random delay on the wake-up signal to obtain a delayed wake-up signal; The at least one processor core is configured to: transition from a sleep state or a low-power state to a working state based on the delayed wake-up signal.

2. The processor system according to claim 1, wherein Each of the delay circuits includes: A random number generator configured to: generate a random number; A delay counter configured to: delay the wake-up signal based on the random number to obtain the delayed wake-up signal.

3. The processor system according to claim 2, wherein Among the plurality of random numbers generated by the plurality of random number generators in the plurality of delay circuits, at least some of the random numbers are different.

4. The processor system according to claim 3, wherein The at least some of the random numbers are in different numerical ranges.

5. The processor system according to any one of claims 1-4, characterized in that, Further comprising: An arbiter configured to: if the time difference between at least two delayed wake-up signals from at least two delay circuits is less than a preset threshold, allow the first delayed wake-up signal among the at least two delayed wake-up signals to be output to at least one first processor core corresponding to the first delayed wake-up signal, and control the second delayed wake-up signal among the at least two delayed wake-up signals other than the first delayed wake-up signal to be further delayed.

6. The processor system according to claim 5, wherein Specifically, the arbiter is configured to: feedback the second delayed wake-up signal to the second delay circuit corresponding to the second delayed wake-up signal; The second delay circuit is further configured to: further delay the second delayed wake-up signal to obtain a new delayed wake-up signal, and the new delayed wake-up signal is provided to at least one second processor core corresponding to the second delay circuit.

7. A method for operating a processor system, characterized in that, Comprising: The common input terminal in the processor system receives a wake-up signal; Each of the plurality of delay circuits in the processor system obtains the wake-up signal from the common input terminal, performs a random delay on the wake-up signal to obtain a delayed wake-up signal, and each delay circuit corresponds to at least one processor core in the plurality of processor cores in the processor system; The at least one processor core transitions from a sleep state or a low-power state to a working state based on the delayed wake-up signal.

8. The method according to claim 7, wherein The performing a random delay on the wake-up signal includes: Generating a random number using a random number generator; Delaying the wake-up signal based on the random number using a delay counter.

9. The method according to claim 8, wherein Among the plurality of random numbers generated by the plurality of random number generators in the plurality of delay circuits, at least some of the random numbers are different.

10. The method according to claim 9, wherein The at least some of the random numbers are in different numerical ranges.

11. The method according to any one of claims 7-9, characterized in that, The method further includes: If the time difference between at least two delayed wake-up signals from at least two delay circuits is less than a preset threshold, allow the first delayed wake-up signal among the at least two delayed wake-up signals to be output to at least one first processor core corresponding to the first delayed wake-up signal, and control the second delayed wake-up signal among the at least two delayed wake-up signals, except the first delayed wake-up signal, to be further delayed.

12. The method according to claim 11, wherein The controlling the second delayed wake-up signal among the at least two delayed wake-up signals, except the first delayed wake-up signal, to be further delayed includes: feeding back the second delayed wake-up signal to a second delay circuit corresponding to the second delayed wake-up signal; using the second delay circuit to further delay the second delayed wake-up signal to obtain a new delayed wake-up signal, and the new delayed wake-up signal is provided to at least one second processor core corresponding to the second delay circuit.

13. An electronic device, characterized in that, comprising one or more memories, and one or more processor systems as claimed in any one of claims 1-6, the one or more memories being coupled to the one or more processor systems, the one or more memories being configured to store computer instructions, and the processor system being configured to execute the computer instructions to implement the method as claimed in any one of claims 7-12.

14. A computer-readable storage medium, characterized in that, comprising computer instructions which, when run on an electronic device, cause the electronic device to execute the method as claimed in any one of claims 7-12 above.

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