Method and device for determining device target value of chip, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a method and device for determining a device target value of a chip, electronic equipment and a storage medium, relates to the technical field of chip design, and can effectively improve the evaluation accuracy of the device target value of the chip. The method comprises the following steps: determining estimated power consumption of each chip in a target chip set; determining a target static leakage current of each chip in the target chip set according to the estimated power consumption of each chip in the target chip set and the test value of the static leakage current of each chip in the target chip set; selecting to-be-optimized device parameters of the target chip set; and determining a reference value of the to-be-optimized device parameter according to the target static leakage current, and taking the reference value of the to-be-optimized device parameter as a device target value of the target chip set. The method is suitable for chip design and production scenes.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and particularly to a method, device, electronic device, and storage medium for determining the device target value of a chip. Background Art

[0002] In the actual chip design process, chips are often designed and produced according to typical device target values. After the chips are produced, functional and performance tests need to be carried out to determine whether the chips are qualified. Considering the fluctuations in the processing technology during the production process, there will be deviations between the measured values and the designed values of the chip functions and performances. In order to obtain the optimal product yield, it is often necessary to evaluate whether the initial device target values of the chips are reasonable and whether the device target values need to be optimized.

[0003] The traditional analysis method is to perform single-variable correlation analysis on the test data of the packaged chips and process-related parameters. This method requires a large amount of packaged test data, has a time lag, and the analysis results using the single-variable method are relatively rough. Generally, only the interval range of the key parameters can be initially judged, so that the optimal performance of the chip devices is not fully utilized. Summary of the Invention

[0004] In view of this, this application provides a method, device, electronic device, and storage medium for determining the device target value of a chip to improve the accuracy of evaluating the device target value of the chip.

[0005] In a first aspect, an embodiment of the present invention provides a method for determining the device target value of a chip, including: determining the estimated power consumption of each chip in the target chip group; determining the target static leakage current of each chip in the target chip group according to the estimated power consumption of each chip in the target chip group and the measured value of the static leakage current of each chip in the target chip group; selecting the device parameters to be optimized in the target chip group; determining the reference value of the device parameter to be optimized according to the target static leakage current, and using the reference value of the device parameter to be optimized as the device target value of the target chip group.

[0006] In a specific implementation, the determining the estimated power consumption of each chip in the target chip group includes: using a power consumption estimation model and the measured values of the power consumption influence parameters of each chip in the target chip group to obtain the estimated power consumption of each chip in the target chip group.

[0007] In a specific implementation, before determining the estimated power consumption of each chip in the target chip group, the method further includes: obtaining the test values of the power consumption impact parameters of each chip in the first chip sample, where each chip in the first chip sample has the same specifications as each chip in the target chip group; using the power consumption estimation model and the test values of the power consumption impact parameters of each chip in the first chip sample to obtain the estimated power consumption of each chip in the first chip sample; and calibrating the power consumption estimation model according to the estimated power consumption of each chip in the first chip sample and the measured power consumption of each chip in the first chip sample.

[0008] In a specific implementation, determining the target static leakage current of each chip in the target chip group according to the estimated power consumption of each chip in the target chip group and the test value of the static leakage current of each chip in the target chip group includes: performing a regression analysis on the estimated power consumption of each chip in the target chip group and the test value of the static leakage current of each chip in the target chip group to obtain a regression model; and determining the target power consumption of each chip in the target chip group and the target static leakage current corresponding to the target power consumption according to the regression model, where the target power consumption is the minimum power consumption determined according to the regression model.

[0009] In a specific implementation, determining the reference value of the device parameter to be optimized according to the target static leakage current includes: obtaining the test values of the device parameters to be optimized of each chip in the second chip sample and the test values of the static leakage current of each chip in the second chip sample, where each chip in the second chip sample has the same specifications as each chip in the target chip group; training a neural network model using the test values of the device parameters to be optimized of each chip in the second chip sample and the test values of the static leakage current of each chip in the second chip sample; and determining the reference value of the device parameter to be optimized corresponding to the target static leakage current using the trained neural network model.

[0010] In a specific implementation, determining the reference value of the device parameter to be optimized corresponding to the target static leakage current using the trained neural network model includes: inputting multiple preset values of the device parameter to be optimized into the trained neural network model to obtain corresponding multiple calculated values of the static leakage current; selecting the calculated value of the static leakage current closest to the target static leakage current from the multiple calculated values of the static leakage current; and using the preset value of the device parameter to be optimized corresponding to the closest calculated value of the static leakage current as the reference value of the device parameter to be optimized.

[0011] In a specific implementation, before inputting the multiple sets of preset values of the device parameters to be optimized into the trained neural network model, the method further includes: determining the multiple sets of preset values of the device parameters to be optimized according to the performance constraints of the basic circuit units of the target chip group.

[0012] In a specific implementation, the device parameters to be optimized include at least one of the following: the threshold voltage of the NMOS of the chip, the threshold voltage of the PMOS of the chip.

[0013] In a second aspect, an embodiment of the present invention further provides a device for determining the device target value of a chip. The device for determining the device target value of the chip includes: an estimated power consumption unit for determining the estimated power consumption of each chip in the target chip group; a target static leakage current determination unit for determining the target static leakage current of each chip in the target chip group according to the estimated power consumption of each chip in the target chip group and the measured value of the static leakage current of each chip in the target chip group; a device parameter to be optimized selection unit for selecting the device parameters to be optimized of the target chip group; and a device target value determination unit for determining the reference value of the device parameters to be optimized according to the target static leakage current and using the reference value of the device parameters to be optimized as the device target value of the target chip group.

[0014] In a specific implementation, the estimated power consumption unit is configured to: use the power consumption estimation model and the measured values of the power consumption impact parameters of each chip in the target chip group to obtain the estimated power consumption of each chip in the target chip group.

[0015] In a specific implementation, it further includes a power consumption estimation model calibration unit. The power consumption estimation model calibration unit includes: a first acquisition module for acquiring the measured values of the power consumption impact parameters of each chip in the first chip sample before determining the estimated power consumption of each chip in the target chip group, where the chips in the first chip sample have the same specifications as the chips in the target chip group; an estimation module for using the power consumption estimation model and the measured values of the power consumption impact parameters of each chip in the first chip sample to obtain the estimated power consumption of each chip in the first chip sample; and a calibration module for calibrating the power consumption estimation model according to the estimated power consumption of each chip in the first chip sample and the measured power consumption of each chip in the first chip sample.

[0016] In a specific implementation, the target static leakage current determination unit includes: a regression model module, configured to perform regression analysis on the estimated power consumption of each chip in the target chip group and the test values of the static leakage current of each chip in the target chip group, so as to obtain a regression model; a target power consumption determination module, configured to determine the target power consumption of each chip in the target chip group and the target static leakage current corresponding to the target power consumption according to the regression model; wherein, the target power consumption is the minimum power consumption determined according to the regression model.

[0017] In a specific implementation, the device target value determination unit includes: a second acquisition module, configured to acquire the test values of the device parameters to be optimized of each chip in the second chip sample and the test values of the static leakage current of each chip in the second chip sample, wherein each chip in the second chip sample has the same specification as each chip in the target chip group; a neural network model training module, configured to train a neural network model by using the test values of the device parameters to be optimized of each chip in the second chip sample and the test values of the static leakage current of each chip in the second chip sample; a reference value determination module, configured to determine the reference value of the device parameters to be optimized corresponding to the target static leakage current by using the trained neural network model.

[0018] In a specific implementation, the reference value determination module includes: a preset value input sub-block, configured to input multiple groups of preset values of the device parameters to be optimized into the trained neural network model to obtain corresponding multiple static leakage current calculation values; a calculation value selection sub-block, configured to select the static leakage current calculation value closest to the target static leakage current from the multiple static leakage current calculation values; a numerical value correspondence sub-block, configured to use the preset value of the device parameters to be optimized corresponding to the closest static leakage current calculation value as the reference value of the device parameters to be optimized.

[0019] In a specific implementation, the reference value determination module further includes: a preset value determination sub-block, configured to determine multiple groups of preset values of the device parameters to be optimized according to the performance constraints of the basic circuit units of the target chip group before inputting the multiple groups of preset values of the device parameters to be optimized into the trained neural network model.

[0020] In a specific implementation, the device parameters to be optimized include at least one of the following: the threshold voltage of the NMOS of the chip, the threshold voltage of the PMOS of the chip.

[0021] In a third aspect, an embodiment of the present invention further provides an electronic device, which includes a processor and a memory. The memory is used to store executable program code, and the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the method for determining the device target value of any chip provided by the embodiment of the present invention.

[0022] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for determining the device target value of any chip provided by the embodiment of the present invention.

[0023] The method, device, electronic device and storage medium for determining the device target value of a chip provided by the embodiment of the present invention determine the estimated power consumption of each chip in the target chip group; then, according to the estimated power consumption of each chip in the target chip group and the test value of the static leakage current of each chip in the target chip group, determine the target static leakage current of each chip in the target chip group; then select the device parameters to be optimized in the target chip group; according to the target static leakage current, determine the reference value of the device parameters to be optimized, and use the reference value of the device parameters to be optimized as the device target value of the target chip group. This method can effectively improve the evaluation accuracy of the device target value of the chip. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0025] Figure 1 It is a flowchart of a method for determining the device target value of a chip provided by an embodiment of the present application; Figure 2 It is a flowchart of calibrating the power consumption estimation model of a method for determining the device target value of a chip provided by an embodiment of the present application; Figure 3 It is a flowchart of a method for determining the reference value of the device parameters to be optimized in a method for determining the device target value of a chip provided by an embodiment of the present application; Figure 4 It is a flowchart of a specific calculation method for the reference value of the device parameters to be optimized in a method for determining the device target value of a chip provided by an embodiment of the present application; Figure 5Flowchart of a specific example of a method for determining device target values of a chip provided by an embodiment of the present application; Figure 6 Structural schematic diagram of a device for determining device target values of a chip provided by an embodiment of the present application; Figure 7 Structural schematic diagram of a power consumption prediction model calibration unit of a device for determining device target values of a chip provided by an embodiment of the present application; Figure 8 Structural schematic diagram of a device target value determination unit of a device for determining device target values of a chip provided by an embodiment of the present application; Figure 9 Structural schematic diagram of a reference value determination module of a device for determining device target values of a chip provided by an embodiment of the present application; Figure 10 Structural schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0026] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0028] In the process of chip design and production, due to fluctuations in the processing technology during production, there will be deviations between the measured values and the design values of chip functions and performances. In order to obtain the optimal product yield, it is often necessary to evaluate whether the initial device target values of the chip are reasonable and whether the device target values need to be optimized. The traditional analysis method is to perform single-variable correlation analysis on the test data of the packaged chip and process-related parameters. This method requires a large amount of packaged test data, has a lag in timeliness, and the analysis results using the single-variable method are relatively rough. Generally, only the interval range of key parameters can be initially judged, so that the optimal performance of the chip device is not fully utilized. To solve the above problems, on the one hand, as Figure 1 shown, the embodiments of the present invention provide a method for determining device target values of a chip, and the method may include: S11. Determine the estimated power consumption of each chip in the target chipset. During the design and production of chips, for different performance requirements, chips often have different OPNs (Order Part Number, which is used to define the model and specifications of the chip). The target chipset can be a set of multiple chips with the same OPN, that is, with the same model and specifications. During the manufacturing process of chips, a large number of performance tests need to be carried out, such as parameters like voltage, current, frequency, and load capacitance of the chip under corresponding conditions. Therefore, the estimated power consumption of each chip in the target chipset can be determined by using the performance test parameters of the chips. The estimated power consumption of each chip can provide a parameter basis for further performance analysis or process optimization of the chip.

[0029] S12. Determine the target static leakage current of each chip in the target chipset according to the estimated power consumption of each chip in the target chipset and the test value of the static leakage current of each chip in the target chipset. According to the electrical characteristics of the chip and practical verification, the static leakage current (Sidd, Static leakage) of the chip has a strongly correlated influence on the power consumption of the chip. The static leakage current of the chip can be obtained through testing. Therefore, during the performance test of the chip in the production process, the test value of the static leakage current of each chip in the target chipset can be obtained. Then, according to the test value of the static leakage current of each chip and the estimated power consumption of each chip, the data statistical method can be used to determine the dependent correlation relationship. Furthermore, based on this dependent correlation relationship, the target static leakage current of each chip in the target chipset can be determined, where the target static leakage current is the static leakage current that is expected to be achieved for each chip in the target chip. The target static leakage current can be the static leakage current corresponding to the target power consumption that is expected to be achieved for each chip in the target chip. For example, the target power consumption can be the minimum power consumption or the optimal power consumption determined based on this dependent correlation relationship, or it can be the achievable power consumption or the acceptable power consumption determined based on this dependent correlation relationship and combined with the process manufacturing capabilities.

[0030] S13. Select the device parameters to be optimized for the target chip group. The device parameters to be optimized are parameters that have a correlation with the static leakage current of the chip, and the device parameters to be optimized can affect the magnitude of the static leakage current of the chip. For example, devices such as transistors, MOS (Metal Oxide Semiconductor Field Effect Transistor), and CMOS (Complementary Metal Oxide Semiconductor) in the chip. The relevant electrical parameters of these devices, such as voltage, current, active power consumption, reactive power consumption, resistance, capacitance, inductance, conductance, etc., often have a greater impact on the static leakage current of the chip. Therefore, in combination with the electrical characteristics of the chip and practical verification, the relevant electrical parameters of these devices can be selected as the device parameters to be optimized, so as to optimize the device parameters to be optimized for these devices in combination with the target static leakage current of each chip in the target chip.

[0031] S14. According to the target static leakage current, determine the reference value of the device parameter to be optimized, and use the reference value of the device parameter to be optimized as the device target value of the target chip group. It can be understood that after selecting the device parameters to be optimized for the target chip group, based on the relationship model between the device parameter to be optimized and the static leakage current of the chip, the reference value of the device parameter to be optimized corresponding to the target static leakage current can be determined, and the reference value of the device parameter to be optimized is used as the device target value of the target chip group. Among them, the relationship model between the device parameter to be optimized and the static leakage current of the chip can also be constructed by using data statistical methods according to the test values of a certain amount of device parameters to be optimized and the test values of the static leakage current. In this embodiment, the device parameter to be optimized can be any performance parameter in the chip production process. For example, the device parameter to be optimized can be the leakage current Ioff when the MOS is in the off state, the equivalent current Ieff when the MOS is in the on state, the leakage current Iddq when the ring oscillator is in the off state in the Wafer Acceptance Test (WAT), or electrical parameters such as the threshold voltage, resistance, current, frequency, equivalent capacitance, metal layer resistance, and Via resistance of the chip-related devices, or it can also be the relevant electrical parameters of the chip in the Wafer Sort (WS) or Final Test (FT).

[0032] The method for determining the device target value of a chip provided by an embodiment of the present invention includes determining the estimated power consumption of each chip in the target chip group; then, based on the estimated power consumption of each chip in the target chip group and the measured value of the static leakage current of each chip in the target chip group, determining the target static leakage current of each chip in the target chip group; then selecting the device parameters to be optimized for the target chip group; determining the reference value of the device parameters to be optimized according to the target static leakage current, and using the reference value of the device parameters to be optimized as the device target value of the target chip group. This method can effectively improve the accuracy of evaluating the device target value of the chip.

[0033] Optionally, in an embodiment of the present invention, step S11 of determining the estimated power consumption of each chip in the target chip group includes: using a power consumption estimation model and the measured values of the power consumption impact parameters of each chip in the target chip group to obtain the estimated power consumption of each chip in the target chip group.

[0034] The power consumption estimation model can be a function of the power consumption impact parameters. Based on the measured values of the power consumption impact parameters of the chip, the estimated power consumption of the chip can be calculated. Specifically, parameters that have an important impact on the chip's energy consumption can be selected from parameters such as the voltage, current, frequency, and load capacitance of the chip in the corresponding state as the power consumption impact parameters, and a power consumption estimation model can be constructed. For example, in this embodiment, the power consumption impact parameters may include the effective load capacitance of the chip, the operating frequency of the chip, and the operating voltage of the chip at the operating frequency. The power consumption estimation model is: , where Power is the estimated power consumption; F is the operating frequency of the chip; C eff is the effective load capacitance of the chip; V is the operating voltage of the chip at the operating frequency F; T is the time; I is the static leakage current of the chip at the operating voltage V, where the static leakage current I is a function of the operating voltage V and time T; in this formula, can be regarded as the dynamic power of the chip, can be regarded as the static power of the chip, that is, the estimated power consumption of the chip includes dynamic power and static power.

[0035] Based on this power consumption estimation model, it can be known that after obtaining the measured values of the power consumption impact parameters, that is, the measured values of the effective load capacitance C eff of the chip, the operating frequency F of the chip, and the operating voltage V of the chip at the operating frequency, inputting them into the power consumption estimation model can calculate the estimated power consumption of the chip; among them, the effective load capacitance C eff, the operating frequency F of the chip, and the measured value of the operating voltage V of the chip at the operating frequency can be obtained during the wafer sort (WS) stage of the chip. In some embodiments, the power consumption prediction model can be other mathematical functions; the power consumption impact parameter can also be the effective load capacitance C eff , one parameter or two parameters of the operating frequency F and the operating voltage V, or the power consumption impact parameter can also include more other chip electrical parameters.

[0036] Since chips with different OPN specifications often have different electrical parameters and performance characteristics, when using the power consumption prediction model to calculate the predicted power consumption of chips with different OPN specifications, in order to improve the accuracy of the results, it is necessary to calibrate the power consumption prediction model. Therefore, optionally, as Figure 2 shown, in an embodiment of the present invention, before determining the predicted power consumption of each chip in the target chip group in step S11, the method further includes: P101. Obtain the measured values of the power consumption impact parameters of each chip in the first chip sample, where the specifications of each chip in the first chip sample are the same as those of each chip in the target chip group.

[0037] P102. Use the power consumption prediction model and the measured values of the power consumption impact parameters of each chip in the first chip sample to obtain the predicted power consumption of each chip in the first chip sample.

[0038] P103. Calibrate the power consumption prediction model according to the predicted power consumption of each chip in the first chip sample and the measured power consumption of each chip in the first chip sample.

[0039] The first chip sample can belong to the same OPN specification as the target chip group, so as to calibrate the power consumption prediction model based on a limited number of first chip samples, so that the calibrated power consumption prediction model can calculate the predicted power consumption of each chip in the target chip group more accurately. For example, in this embodiment, the measured values of the power consumption impact parameters of each chip in the first chip sample are input into the power consumption prediction model to calculate the predicted power consumption of each chip in the first chip sample, and then compared and analyzed with the measured power consumption of each chip in the first chip sample, and the calibration coefficient of the power consumption prediction model for this OPN specification chip can be obtained. In this way, when calculating other chips of this OPN specification, such as the target chip group, based on the calibrated power consumption prediction model, the measured values of the power consumption impact parameters of each chip in the target chip group can be input to calculate the corresponding predicted power consumption. It can be understood that the calibrated power consumption prediction model for different chip specifications can obtain more accurate predicted power consumption compared with the uncalibrated power consumption prediction model; in addition, during the calibration process of the power consumption prediction model, only an appropriate amount of first chip samples are selected for test analysis, which is beneficial to improving the evaluation operation efficiency on the premise of ensuring the evaluation accuracy.

[0040] Optionally, in an embodiment of the present invention, step S12 determines the target static leakage current of each chip in the target chip group according to the estimated power consumption of each chip in the target chip group and the test value of the static leakage current of each chip in the target chip group, including: performing a regression analysis on the estimated power consumption of each chip in the target chip group and the test value of the static leakage current of each chip in the target chip group to obtain a regression model; determining the target power consumption of each chip in the target chip group and the target static leakage current corresponding to the target power consumption according to the regression model; wherein, the target power consumption is the minimum power consumption determined according to the regression model.

[0041] There is a correlation between the static leakage current and the power consumption of the chip. Therefore, in this embodiment, in order to determine the dependent correlation between the estimated power consumption and the static leakage current, after calculating the target power consumption of each chip in the target chip group according to the power consumption estimation model, the target power consumption of each chip can be further subjected to a data regression analysis with the test value of the static leakage current to obtain a regression model; wherein, the test value of the static leakage current of each chip in the target chip group can be obtained during the wafer sort (WS) stage of the chip. For example, in the coordinate system of the regression model, the abscissa can be used to represent the test value of the static leakage current of each chip, and the ordinate can be used to represent the estimated power consumption of each chip. According to the test value of the static leakage current and the estimated power consumption of each chip, the coordinate position points of each chip in the coordinate system can be determined. Based on the coordinate position points of each chip in the coordinate system, a regression model such as a regression curve or a regression function about the estimated power consumption and the test value of the static leakage current of each chip can be fitted.

[0042] After obtaining the regression model, the target power consumption of each chip in the target chip group and the target static leakage current corresponding to the target power consumption can be determined according to the regression model; in this embodiment, the target power consumption is the minimum power consumption determined according to the regression model, and the target static leakage current is the static leakage current corresponding to the target power consumption. For example, after fitting the regression curve, the minimum power consumption value of the regression curve in the coordinate system can be used as the target power consumption, and the static leakage current corresponding to the minimum power consumption value can be used as the target static leakage current. In some other embodiments, the target power consumption and the corresponding target static leakage current can also be determined according to the production yield and the process manufacturing capacity.

[0043] Optionally, in an embodiment of the present invention, as Figure 3 shown, step S14 determines the reference value of the device parameter to be optimized according to the target static leakage current, including: S141. Obtain the test value of the device parameter to be optimized of each chip in the second chip sample and the test value of the static leakage current of each chip in the second chip sample, wherein each chip in the second chip sample has the same specification as each chip in the target chip group.

[0044] S142. Train the neural network model by using the test values of the device parameters to be optimized for each chip in the second chip sample and the test values of the static leakage current for each chip in the second chip sample.

[0045] S143. Use the trained neural network model to determine the reference values of the device parameters to be optimized corresponding to the target static leakage current.

[0046] Since the device parameters to be optimized for a chip are often correlated with the static leakage current, in this embodiment, in order to obtain a relationship model between the device parameters to be optimized and the static leakage current, a certain amount of second chip samples are selected. Each chip in the second chip sample has the same specifications as each chip in the target chip group. In some embodiments, the second chip sample and the first chip sample can also be the same chip sample. Through testing, obtain the test values of the device parameters to be optimized for each chip in the second chip sample and the test values of the static leakage current for each chip in the second chip sample; then train the neural network model based on the test values of the device parameters to be optimized and the test values of the static leakage current for each chip in the second chip sample.

[0047] A neural networks model (NNM) is a computational model that mimics biological neural networks such as the structure and function of the brain, used to estimate or approximate functions, and has important applications especially in the fields of machine learning and artificial intelligence. The neural network model can consist of multiple layers, including an input layer, hidden layers, and an output layer. Each layer is composed of multiple neurons, and signals are transmitted between neurons through weighted connections. The adjustment of the weights is achieved through learning algorithms so that the network can learn how to correctly perform specific tasks. The working principle of a neural network can be analogous to a linear regression model, where each neuron can be regarded as a model with inputs, weights, biases, and outputs. The input data is multiplied by the weights, summed, added with the bias, and then processed through an activation function to produce an output. If the output exceeds a certain threshold, the neuron is activated and the signal is transmitted to the next layer. This process starts from the input layer and goes all the way to the output layer, forming a feedforward network. During the training process, the neural network adjusts the weights and biases to minimize the loss function to improve the prediction accuracy.

[0048] When training the neural network model with the data set composed of the test values of the device parameters to be optimized for each chip in the second chip sample and the test values of the static leakage current of each chip in the second chip sample, the data set can be specifically divided into a training set and a test set. The training set is used to train and fit the model, and the test set is used to evaluate the model effect. In some embodiments, the test data of relevant samples can be further obtained as a validation set to ensure that the trained neural network model has better stability and robustness. It can be understood that the neural network model is constructed based on the device parameters to be optimized and the static leakage current of the chip as the data processing object. After the model training is completed, the trained neural network model can be used to determine the reference value of the device parameter to be optimized corresponding to the target static leakage current, and then the reference value of the device parameter to be optimized is used as the device target value of the target chip group.

[0049] Optionally, in an embodiment of the present invention, the device parameters to be optimized include at least one of the following: the threshold voltage of the NMOS of the chip, the threshold voltage of the PMOS of the chip. NMOS (N-Metal-Oxide-Semiconductor) is N-type metal-oxide-semiconductor; PMOS (Positive Channel Metal Oxide Semiconductor) is P-channel metal oxide semiconductor. For example, if the threshold voltage of the NMOS of the chip and the threshold voltage of the PMOS of the chip are selected as the device parameters to be optimized, when training the neural network model, the threshold voltage of the NMOS of the chip and the threshold voltage of the PMOS of the chip can be used as the input parameters of the neural network model, and the static leakage current of the chip can be used as the output parameter of the neural network model for model training. In this way, using the trained neural network model, the target value of the threshold voltage of the NMOS and the target value of the threshold voltage of the PMOS corresponding to the target static leakage current of the chip can be determined.

[0050] Optionally, in an embodiment of the present invention, as Figure 4 shown, step S143 uses the trained neural network model to determine the reference value of the device parameter to be optimized corresponding to the target static leakage current, including: S1431. Input multiple preset values of the device parameter to be optimized into the trained neural network model to obtain corresponding multiple static leakage current calculated values.

[0051] S1432. Select the static leakage current calculated value closest to the target static leakage current from the multiple static leakage current calculated values.

[0052] S1433. Use the preset value of the device parameter to be optimized corresponding to the closest static leakage current calculated value as the reference value of the device parameter to be optimized.

[0053] The data values of the device parameters to be optimized often have a certain range of distribution. Therefore, in this embodiment, multiple sets of preset values of the device parameters to be optimized can be selected based on the reasonable range of the device parameters to be optimized to ensure the rationality of the preset values. By selecting multiple sets of preset values of the device parameters to be optimized, then using the trained neural network model to obtain corresponding multiple static current calculation values, and then selecting the preset value of the device parameter corresponding to the static current calculation value closest to the target static leakage current as the reference value of the device parameter to be optimized. In some other embodiments, if the static leakage current and the selected device parameter to be optimized can be characterized by a functional analytical formula, a functional analytical formula of the static leakage current with respect to the device parameter to be optimized can also be constructed. Based on this functional analytical formula, the value of the device parameter to be optimized corresponding to the target static leakage current is used as the reference value of the device parameter to be optimized, that is, the device target value of the target chipset.

[0054] Since the data values of the device parameters to be optimized often need to meet corresponding constraint conditions, optionally, in an embodiment of the present invention, before step S1431 inputs multiple sets of preset values of the device parameters to be optimized into the trained neural network model, the method further includes: determining multiple sets of preset values of the device parameters to be optimized according to the circuit basic unit performance constraints of the target chipset.

[0055] The circuit basic unit performance constraints can be considered based on aspects such as device type, driving ability, and load size, and specifically can include electrical constraints, physical constraints, layout and routing constraints, power consumption constraints, timing constraints, area constraints, etc. For example, electrical constraints include Ohm's law, Kirchhoff's law, the characteristics of capacitors and inductors, etc., to ensure that the chip circuit can operate in the expected manner under normal working conditions; physical constraints involve the laws of thermodynamics, electromagnetic field theory, and material characteristics, etc., to ensure that the chip circuit can meet the requirements of physical conditions during actual manufacturing and use, and ensure the physical stability and reliability of the chip circuit; layout and routing constraints are used to specify the positions of the chip I / O pins and guide the software to perform layout and routing in specific physical areas of the chip to ensure that the physical layout and electrical connections of the chip meet the design requirements; power consumption constraints are to ensure that the chip does not consume too much energy during operation, so as to extend the service life of the chip and improve its energy efficiency; timing constraints are the key to ensuring the normal operation of the gate-level circuit, to ensure that data can be stably transmitted when triggered by the clock and avoid the occurrence of metastability; area constraints are to limit the physical size of the chip design, ensure that the chip can complete the design requirements within the given space, and at the same time optimize cost and performance.

[0056] It can be understood that determining multiple preset values of the device parameters to be optimized according to the performance constraints of the basic circuit units of the target chipset can make the value range of the preset values more reasonable, ensure that the circuit can operate in the expected manner under normal working conditions, and guarantee the reliability and stability of the chip circuit.

[0057] Optionally, in an embodiment of the present invention, before step S1431 inputs multiple preset values of the device parameters to be optimized into the trained neural network model, the method further includes: determining multiple preset values of the device parameters to be optimized according to the correlation between the parameters in the device parameters to be optimized. For example, the device parameters to be optimized selected in this embodiment, that is, the threshold voltage of the NMOS of the chip and the threshold voltage of the PMOS of the chip, have a linear correlation. Therefore, when determining the preset values, multiple preset values of the threshold voltage of the NMOS of the chip and the threshold voltage of the PMOS of the chip can be determined according to this linear correlation. In some other embodiments, the multiple device parameters to be optimized may have a linear correlation or a non-linear correlation. Determining the preset values according to the correlation between the device parameters to be optimized can make the preset values more in line with the physical characteristics and actual working conditions of the device, which is beneficial to improving the accuracy of the calculation results and the data processing efficiency.

[0058] In summary, this embodiment specifically gives an example of a method for determining the target value of the device of a chip, as Figure 5 shown, this example includes the following steps: First, in step T101, according to the wafer sort (WS), obtain the test values of the power consumption impact parameters and the test values of the static leakage current of each chip in the target chipset, where the power consumption impact parameters may specifically include the effective load capacitance C eff of the chip, the operating frequency F of the chip, and the operating voltage V of the chip at the operating frequency, etc. In step T102, use the power consumption prediction model and the test values of the power consumption impact parameters of each chip in the first chip sample to calculate the predicted power consumption of each chip in the first chip sample, and calibrate the power consumption prediction model according to the measured power consumption of each chip in the first chip sample, where the OPN specifications of each chip in the first chip sample are the same as those of each chip in the target chipset. In this way, in step T103, the predicted power consumption of each chip in the target chipset can be determined according to the calibrated power consumption prediction model and the test values of the power consumption impact parameters of each chip in the target chipset, and a regression model is established with the test values of the static leakage current of each chip in the target chipset. According to the regression model, the target static leakage current is determined. For example, the target static leakage current may be the static leakage current corresponding to the minimum power consumption value of the chip in the regression model.

[0059] In step T104, according to the wafer acceptance test (WAT), the relationship between the WAT test parameters and the static leakage current is analyzed. Through step T105, the device parameters to be optimized with relatively high correlation with the static leakage current are selected from the WAT test parameters. For example, the device parameters to be optimized may specifically include the threshold voltage of the NMOS of the chip and the threshold voltage of the PMOS of the chip. Furthermore, in step T106, a neural network model is trained using the test values of the device parameters to be optimized for each chip in the second chip sample and the test values of the static leakage current for each chip in the second chip sample, where each chip in the second chip sample has the same OPN specification as each chip in the target chip group.

[0060] Then, based on the performance constraints of the basic circuit units in step T107 and the reasonable value range of the device parameters to be optimized determined in step T108, in step T109, the trained neural network model is used to obtain multiple calculated values of the static leakage current corresponding to multiple preset values of the device parameters to be optimized, and the preset value of the device parameter corresponding to the calculated value of the static leakage current closest to the target static leakage current is used as the reference value of the device parameter to be optimized, that is, the device target value of the target chip group.

[0061] In a second aspect, an embodiment of the present invention further provides a device for determining the device target value of a chip, which can effectively improve the evaluation accuracy of the device target value of the chip.

[0062] As Figure 6 shown, the device for determining the device target value of a chip provided in the embodiment of the present application may include: An estimated power consumption unit 31, configured to determine the estimated power consumption of each chip in the target chip group; A target static leakage current determination unit 32, configured to determine the target static leakage current of each chip in the target chip group according to the estimated power consumption of each chip in the target chip group and the test value of the static leakage current of each chip in the target chip group; A device parameter to be optimized selection unit 33, configured to select the device parameters to be optimized of the target chip group; A device target value determination unit 34, configured to determine the reference value of the device parameter to be optimized according to the target static leakage current, and use the reference value of the device parameter to be optimized as the device target value of the target chip group.

[0063] The device for determining the device target value of a chip provided by an embodiment of the present invention determines the estimated power consumption of each chip in the target chip group; then, based on the estimated power consumption of each chip in the target chip group and the measured value of the static leakage current of each chip in the target chip group, determines the target static leakage current of each chip in the target chip group; then selects the device parameters to be optimized for the target chip group; determines the reference value of the device parameters to be optimized according to the target static leakage current, and uses the reference value of the device parameters to be optimized as the device target value of the target chip group. This method can effectively improve the accuracy of evaluating the device target value of the chip.

[0064] Optionally, in an embodiment of the present invention, the estimated power consumption unit 31 is configured to: use the power consumption estimation model and the measured values of the power consumption influence parameters of each chip in the target chip group to obtain the estimated power consumption of each chip in the target chip group.

[0065] Optionally, in an embodiment of the present invention, as Figure 7 shown, it further includes a power consumption estimation model calibration unit, and the power consumption estimation model calibration unit includes: The first acquisition module 301 is configured to, before determining the estimated power consumption of each chip in the target chip group, acquire the measured values of the power consumption influence parameters of each chip in the first chip sample, where each chip in the first chip sample has the same specification as each chip in the target chip group; The estimation module 302 is configured to use the power consumption estimation model and the measured values of the power consumption influence parameters of each chip in the first chip sample to obtain the estimated power consumption of each chip in the first chip sample; The calibration module 303 is configured to calibrate the power consumption estimation model according to the estimated power consumption of each chip in the first chip sample and the measured power consumption of each chip in the first chip sample.

[0066] Optionally, in an embodiment of the present invention, the target static leakage current determination unit 32 includes: The regression model module is configured to perform a regression analysis on the estimated power consumption of each chip in the target chip group and the measured value of the static leakage current of each chip in the target chip group to obtain a regression model; The target power consumption determination module is configured to, according to the regression model, determine the target power consumption of each chip in the target chip group and the target static leakage current corresponding to the target power consumption; where the target power consumption is the minimum power consumption determined according to the regression model.

[0067] Optionally, in an embodiment of the present invention, as Figure 8 shown, the device target value determination unit 34 includes: The second acquisition module 341 is configured to acquire the test values of the device parameters to be optimized for each chip in the second chip sample, and the test values of the static leakage current for each chip in the second chip sample, where each chip in the second chip sample has the same specifications as each chip in the target chip group; The neural network model training module 342 is configured to train the neural network model by using the test values of the device parameters to be optimized for each chip in the second chip sample and the test values of the static leakage current for each chip in the second chip sample; The reference value determination module 343 is configured to determine the reference values of the device parameters to be optimized corresponding to the target static leakage current by using the trained neural network model.

[0068] Optionally, in an embodiment of the present invention, as Figure 9 shown, the reference value determination module 343 includes: The preset value input sub-block 3431 is configured to input multiple groups of preset values of the device parameters to be optimized into the trained neural network model to obtain corresponding multiple static leakage current calculation values; The calculated value selection sub-block 3432 is configured to select the static leakage current calculation value closest to the target static leakage current from the multiple static leakage current calculation values; The numerical value corresponding sub-block 3433 is configured to use the preset value of the device parameter corresponding to the closest static leakage current calculation value as the reference value of the device parameter to be optimized.

[0069] Optionally, in an embodiment of the present invention, the reference value determination module 343 further includes: a preset value determination sub-block, configured to determine multiple groups of preset values of the device parameters to be optimized according to the performance constraints of the basic circuit units of the target chip group before inputting the multiple groups of preset values of the device parameters to be optimized into the trained neural network model.

[0070] Optionally, in an embodiment of the present invention, the device parameters to be optimized include at least one of the following: the threshold voltage of the NMOS of the chip, the threshold voltage of the PMOS of the chip.

[0071] In a third aspect, an embodiment of the present invention further provides an electronic device. The electronic device includes: a processor 52 and a memory 53. The memory 53 is configured to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, and is configured to execute any method for determining the device target value of a chip provided by the embodiment of the present invention.

[0072] As Figure 10As shown in the figure, the electronic device provided by the embodiment of the present application includes: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55. Among them, the circuit board 54 is arranged inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to each circuit or device of the above-mentioned electronic device; the memory 53 is used to store executable program codes; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, and is used to execute the method for determining the device target value of any one of the chips provided by the embodiment of the present invention.

[0073] For the specific execution process of the above steps by the processor 52 and the further steps executed by the processor 52 by running the executable program code, reference can be made to the description of the foregoing embodiments, and details will not be repeated here.

[0074] The above-mentioned electronic devices exist in various forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by having mobile communication functions and mainly aim to provide voice and data communication. Such terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones, etc.

[0075] (2) Ultra-mobile personal computer devices: These devices belong to the category of personal computers, have computing and processing functions, and generally also have the characteristic of mobile Internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as iPad.

[0076] (3) Portable entertainment devices: These devices can display and play multimedia content. Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, and smart toys and portable vehicle navigation devices.

[0077] (4) Servers: Devices that provide computing services. The composition of a server includes a processor, a hard disk, a memory, a system bus, etc. Servers are similar to general computer architectures, but due to the need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0078] (5) Other electronic devices with data interaction functions.

[0079] Fourthly, an embodiment of the present application further provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the method for determining the device target value of any kind of chip provided by the embodiments of the present invention, and thus can also achieve the corresponding technical effects. The details have been described in the foregoing, and will not be repeated here.

[0080] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0081] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments.

[0082] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiment.

[0083] For the convenience of description, the above device is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0084] Those of ordinary skill in the art can understand that all or part of the processes of implementing the above method embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), etc.

[0085] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for determining a device target value of a chip, characterized in that: include: Determine the estimated power consumption of each chip in the target chipset; Determining a target static leakage current of each chip in the target chipset according to an estimated power consumption of each chip in the target chipset and a test value of a static leakage current of each chip in the target chipset; Selecting device parameters to be optimized of the target chipset; According to the target static leakage current, a reference value of the device parameter to be optimized is determined, and the reference value of the device parameter to be optimized is used as a device target value of the target chipset.

2. The method for determining a device target value of a chip according to claim 1, characterized in that: Determining the estimated power consumption of each chip in the target chipset includes: using a power consumption estimation model and a test value of a power consumption influencing parameter of each chip in the target chipset to obtain the estimated power consumption of each chip in the target chipset.

3. The method for determining a device target value of a chip according to claim 1, characterized in that: Before determining the estimated power consumption of each chip in the target chipset, the method further includes: Acquire a test value of a power consumption influencing parameter of each chip in a first chip sample, wherein the specification of each chip in the first chip sample is the same as that of each chip in the target chipset; Obtaining the estimated power consumption of each chip in the first chip sample by using the power consumption estimation model and the test value of the power consumption influencing parameter of each chip in the first chip sample; The power consumption estimation model is calibrated according to the estimated power consumption of each chip in the first chip sample and the measured power consumption of each chip in the first chip sample.

4. The method for determining a device target value of a chip according to claim 1, characterized in that: Determining the target static leakage current of each chip in the target chipset according to the estimated power consumption of each chip in the target chipset and the test value of the static leakage current of each chip in the target chipset includes: Performing regression analysis on the estimated power consumption of each chip in the target chipset and the test value of the static leakage current of each chip in the target chipset to obtain a regression model; According to the regression model, the target power consumption of each chip in the target chipset and the target static leakage current corresponding to the target power consumption are determined; wherein the target power consumption is the minimum power consumption determined according to the regression model.

5. The method for determining a device target value of a chip according to claim 1, wherein: Determining the reference value of the device parameter to be optimized according to the target static leakage current includes: Acquire test values ​​of device parameters to be optimized of each chip in the second chip sample and test values ​​of static leakage current of each chip in the second chip sample, wherein the specifications of each chip in the second chip sample and each chip in the target chipset are the same; Training a neural network model using the test values ​​of the device parameters to be optimized of each chip in the second chip sample and the test values ​​of the static leakage current of each chip in the second chip sample; The trained neural network model is used to determine a reference value of the device parameter to be optimized corresponding to the target static leakage current.

6. The method for determining a device target value of a chip according to claim 5, characterized in that: The method of using the trained neural network model to determine the reference value of the device parameter to be optimized corresponding to the target static leakage current includes: Inputting the multiple sets of preset values ​​of the device parameters to be optimized into the trained neural network model to obtain corresponding multiple static leakage current calculation values; Selecting a static leakage current calculated value closest to the target static leakage current from the plurality of static leakage current calculated values; The preset value of the parameter of the device to be optimized corresponding to the closest static leakage current calculation value is used as a reference value of the parameter of the device to be optimized.

7. The method for determining a device target value of a chip according to claim 6, characterized in that: Before inputting the multiple sets of preset values ​​of the device parameters to be optimized into the trained neural network model, the method also includes: determining the multiple sets of preset values ​​of the device parameters to be optimized based on the performance constraints of the basic circuit units of the target chipset.

8. The method for determining a device target value of a chip according to claim 1, characterized in that: The device parameter to be optimized includes at least one of the following: a threshold voltage of an NMOS chip and a threshold voltage of a PMOS chip.

9. A device for determining a device target value of a chip, characterized in that: include: An estimated power consumption unit, used to determine the estimated power consumption of each chip in the target chipset; a target static leakage current determination unit, configured to determine a target static leakage current of each chip in the target chipset according to an estimated power consumption of each chip in the target chipset and a test value of the static leakage current of each chip in the target chipset; A device parameter selection unit to be optimized, used for selecting device parameters to be optimized of the target chipset; The device target value determination unit is used to determine the reference value of the device parameter to be optimized according to the target static leakage current, and use the reference value of the device parameter to be optimized as the device target value of the target chipset.

10. The device for determining a device target value of a chip according to claim 9, characterized in that: The power consumption estimation unit is used to obtain the estimated power consumption of each chip in the target chipset by using the power consumption estimation model and the test value of the power consumption influencing parameter of each chip in the target chipset.

11. The device for determining a device target value of a chip according to claim 9, characterized in that: It also includes a power consumption estimation model calibration unit, and the power consumption estimation model calibration unit includes: A first acquisition module, configured to acquire a test value of a power consumption influencing parameter of each chip in a first chip sample before determining an estimated power consumption of each chip in a target chipset, wherein the specification of each chip in the first chip sample is the same as that of each chip in the target chipset; An estimation module, configured to obtain an estimated power consumption of each chip in the first chip sample by using a power consumption estimation model and a test value of a power consumption influencing parameter of each chip in the first chip sample; A calibration module is used to calibrate the power consumption estimation model according to the estimated power consumption of each chip in the first chip sample and the measured power consumption of each chip in the first chip sample.

12. The device for determining a device target value of a chip according to claim 9, characterized in that: The target static leakage current determination unit comprises: A regression model module, used for performing regression analysis on the estimated power consumption of each chip in the target chipset and the test value of the static leakage current of each chip in the target chipset to obtain a regression model; The target power consumption determination module is used to determine the target power consumption of each chip in the target chipset and the target static leakage current corresponding to the target power consumption according to the regression model; wherein the target power consumption is the minimum power consumption determined according to the regression model.

13. The device for determining a device target value of a chip according to claim 9, characterized in that: The device target value determination unit comprises: A second acquisition module, used to acquire a test value of a device parameter to be optimized of each chip in a second chip sample and a test value of a static leakage current of each chip in the second chip sample, wherein the specification of each chip in the second chip sample is the same as that of each chip in the target chipset; A neural network model training module, used to train a neural network model using the test values ​​of the device parameters to be optimized of each chip in the second chip sample and the test values ​​of the static leakage current of each chip in the second chip sample; The reference value determination module is used to determine the reference value of the device parameter to be optimized corresponding to the target static leakage current by using the trained neural network model.

14. The device for determining a device target value of a chip according to claim 13, characterized in that: The reference value determination module comprises: A preset value input sub-block is used to input multiple groups of preset values ​​of the device parameters to be optimized into the trained neural network model to obtain corresponding multiple static leakage current calculation values; A calculated value selection sub-block, used to select a static leakage current calculated value closest to the target static leakage current from the multiple static leakage current calculated values; The value corresponding sub-block is used to use the preset value of the parameter of the device to be optimized corresponding to the closest static leakage current calculation value as the reference value of the parameter of the device to be optimized.

15. The device for determining a device target value of a chip according to claim 14, characterized in that: The reference value determination module also includes: a preset value determination sub-block, which is used to determine the multiple sets of preset values ​​of the device parameters to be optimized according to the performance constraints of the basic circuit units of the target chipset before inputting the multiple sets of preset values ​​of the device parameters to be optimized into the trained neural network model.

16. The device for determining a device target value of a chip according to claim 9, characterized in that: The device parameter to be optimized includes at least one of the following: a threshold voltage of an NMOS chip and a threshold voltage of a PMOS chip.

17. An electronic device, characterized in that: The electronic device includes: a processor and a memory, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method for determining the device target value of the chip described in any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for determining the device target value of the chip according to any one of the preceding claims 1-8.

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