Power grid model construction method and system, simulation method, electronic equipment and medium

Abstract

The invention provides a power grid model construction method and system, a simulation method, electronic equipment and a medium. The power grid model construction method comprises the steps of obtaining a power grid layer graph of a superconducting integrated circuit layout; classifying the power grid layer graph to obtain a bright field region graph and a dark field region graph; performing power grid modeling on the bright field area graph to obtain a bright field area power grid model; and performing power grid modeling on the dark field area graph to obtain a dark field area power grid model. According to the method and the device, an efficient modeling strategy is adopted, so that consumption of computing resources is effectively reduced. Besides, simulation analysis based on the model constructed by the invention can accurately describe the change of the electrical property of the superconducting active device, so that the applicability of the model is improved. In addition, the method has the capability of converting the layout design of the superconducting integrated circuit under various superconducting processes into an impedance network, and shows relatively high universality.

Description

Technical Field

[0001] This application belongs to the technical field of superconducting integrated circuits, and relates to a method and system for constructing a power grid model, a simulation method, an electronic device, and a medium. Background Art

[0002] A superconducting integrated circuit refers to an integrated circuit based on Josephson junctions and superconducting materials, including a Single-Flux-Quantum (SFQ) circuit. The SFQ circuit is mainly composed of Josephson junctions, and represents digital logic "0" and "1" by the presence or absence of the magnetic flux quantum Ф0 in a superconducting loop. Compared with traditional semiconductor CMOS (Complementary Metal Oxide Semiconductor) circuits, the tiny and quantized nature of the magnetic flux quantum significantly reduces the impact of crosstalk and power consumption, and the narrow voltage pulses generated in the junction when the magnetic flux quantum enters and exits the loop also enable it to obtain an extremely high frequency. This advantage of both ultra-high operating speed and extremely low power consumption makes this circuit have significant prospects in applications such as ultra-wideband analog-to-digital converters (ADCs) and superconducting computers.

[0003] In order to deeply understand the electrical characteristics and behavior patterns of superconducting integrated circuits under different power grid operating conditions, it is necessary to conduct power grid modeling and simulation research on them.

[0004] Currently, most of the power grid modeling of superconducting integrated circuits uses the finite element method. However, when dealing with large-scale superconducting integrated circuits, the finite element method faces several challenges: on the one hand, it requires a large amount of computing resources; on the other hand, the power grid model constructed based on the finite element method cannot describe the electrical property changes of superconducting active devices, such as Josephson junctions, which to a certain extent limits the applicability of the power grid model. Summary of the Invention

[0005] The purpose of this application is to provide a method and system for constructing a power grid model, a simulation method, an electronic device, and a medium for superconducting integrated circuits, so as to solve the technical problem of large computing resource requirements in the prior art when constructing a power grid model for large-scale superconducting integrated circuits.

[0006] In a first aspect, this application provides a method for constructing a power grid model of a superconducting integrated circuit, including: obtaining the power grid layer graphics of the superconducting integrated circuit layout; classifying the power grid layer graphics to obtain bright field area graphics and dark field area graphics; performing power grid modeling on the bright field area graphics to obtain a bright field area power grid model; performing power grid modeling on the dark field area graphics to obtain a dark field area power grid model.

[0007] In one implementation of the first aspect, power grid modeling is performed on the bright field area pattern, and obtaining the bright field area power grid model includes: dividing the bright field area pattern into several non-connected power supply domain patterns, each of the power supply domain patterns including several subordinate logic units; for each of the power supply domain patterns, constructing a corresponding power supply domain power grid model; combining all the power supply domain power grid models to obtain the bright field area power grid model.

[0008] In one implementation of the first aspect, power grid modeling is performed on the dark field area pattern, and obtaining the dark field area power grid model includes: establishing an initial grid for the dark field area based on the coverage of the dark field area pattern; the initial grid for the dark field area includes a plurality of grid units; determining the grid area covered by the dark field area pattern according to the position coordinates of the dark field area pattern; the grid area corresponds to at least two of the grid units; removing the connections between all the grid units within the grid area to obtain the dark field area network model.

[0009] In one implementation of the first aspect, dividing the bright field area pattern into several non-connected power supply domain patterns includes: establishing a union-find set structure for the bright field area pattern; based on the union-find set structure, determining the connectivity relationship between different subordinate logic units within the bright field area pattern; based on the connectivity relationship, dividing the bright field area pattern into several of the power supply domain patterns, where the mutually connected subordinate logic units are located in the same power supply domain pattern, and the non-connected subordinate logic units are located in different power supply domain patterns.

[0010] In one implementation of the first aspect, for each of the power supply domain patterns, constructing a corresponding power supply domain power grid model includes: establishing an initial grid for the bright field area based on the coverage of the subordinate logic units; the initial grid for the bright field area includes a plurality of grid units; marking the grid units covered by the power supply domain pattern on the initial grid for the bright field area; removing the unmarked grid units from the initial grid for the bright field area and retaining the marked grid units to obtain a new grid for the bright field area; traversing all the subordinate logic units within the power supply domain pattern, obtaining the power supply source point coordinates of each of the subordinate logic units, and inserting the power supply source point coordinates into the new grid for the bright field area; finding the grid units adjacent to the power supply port position in the new grid for the bright field area and establishing connections between the power supply port and the adjacent grid units.

[0011] In one implementation of the first aspect, establishing an initial grid based on the coverage of the power supply domain pattern includes: obtaining the position coordinates of all the subordinate logic units within the power supply domain; based on the position coordinates, parsing out the track coordinates where each of the subordinate logic units is located; determining a standardized range according to the track coordinates and the coverage of the power supply domain pattern; establishing the initial grid within the standardized range.

[0012] In a second aspect, the present application provides a power grid model construction system for a superconducting integrated circuit, including: a graphic acquisition module for acquiring the graphic of the power grid layer of the superconducting integrated circuit layout; a graphic classification module for classifying the graphic of the power grid layer to obtain a bright field area graphic and a dark field area graphic; a bright field area modeling module for performing power grid modeling on the bright field area graphic to obtain a bright field area power grid model; and a dark field area modeling module for performing power grid modeling on the dark field area graphic to obtain a dark field area power grid model.

[0013] In a third aspect, the present application provides a power grid model simulation method for a superconducting integrated circuit, including: acquiring the bright field area power grid model and the dark field area power grid model constructed according to the method described above; converting the bright field area power grid model into a bright field area power grid SPICE netlist, and converting the dark field area power grid model into a dark field area ground layer SPICE netlist; connecting the bright field area power grid SPICE netlist and the dark field area ground layer SPICE netlist to the original logic circuit SPICE netlist respectively; and performing SPICE dynamic simulation based on the bright field area power grid SPICE netlist, the dark field area ground layer SPICE netlist and the original logic circuit SPICE netlist, and recording the simulation results.

[0014] In a fourth aspect, the present application provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, so that the electronic device executes the power grid model construction method and / or the power grid model simulation method of the superconducting integrated circuit described above.

[0015] In a fifth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the power grid model construction method and / or the power grid model simulation method of the superconducting integrated circuit described above.

[0016] As described above, the power grid model construction method and system, simulation method, electronic device and medium of the present application effectively reduce the consumption of computing resources by adopting an efficient modeling strategy. In addition, the simulation analysis based on the model constructed by the present application can accurately describe the changes in the electrical properties of superconducting active devices, thereby improving the applicability of the model. In addition, the present application has the ability to convert the layout design of superconducting integrated circuits under various superconducting processes into impedance networks, showing strong universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a schematic diagram of the computer terminal described in the embodiment of the present application for the application name described above.

[0018] Figure 2 Shown is a flowchart of the method for constructing the power grid model of the superconducting integrated circuit described in this application in one embodiment.

[0019] Figure 3 Shown is a schematic diagram of the layout of the superconducting integrated circuit described in this application in one embodiment.

[0020] Figure 4 Shown is a schematic structural diagram of the bright field area and the dark field area described in this application in one embodiment.

[0021] Figure 5 Shown is a schematic diagram of the dark field area constructed by the quadtree structure described in this application in one embodiment.

[0022] Figure 6a Shown is a schematic diagram of the bright field area pattern described in this application in one embodiment.

[0023] Figure 6b Shown is a schematic diagram of the power grid model of the bright field area described in this application in one embodiment.

[0024] Figure 7a Shown is a schematic diagram of the initial grid of the bright field area described in this application in one embodiment.

[0025] Figure 7b Shown is a schematic diagram of the new grid of the bright field area described in this application in one embodiment.

[0026] Figure 8a Shown is a schematic diagram of the dark field area pattern described in this application in one embodiment.

[0027] Figure 8b Shown is a schematic diagram of the power grid model of the dark field area described in this application in one embodiment.

[0028] Figure 9a Shown is a schematic diagram of the initial grid of the dark field area described in this application in one embodiment.

[0029] Figure 9b Shown is a schematic diagram of the power grid model of the dark field area described in this application in one embodiment.

[0030] Figure 10 Shown is a schematic structural diagram of the power grid model construction system of the superconducting integrated circuit described in this application in one embodiment.

[0031] Figure 11 Shown is a flowchart of the method for simulating the power grid model of the superconducting integrated circuit described in this application in one embodiment.

[0032] Figure 12a Shown is a schematic diagram of the power supply excitation setting of the power grid model of the bright field area described in this application in one embodiment.

[0033] Figure 12b It shows a schematic diagram of the power supply excitation setting in an embodiment of the dark field area power grid model described in this application.

[0034] Figure 13 It shows a schematic diagram of the connection relationship in an embodiment of the SPICE netlist described in this application.

[0035] Figure 14a It shows a schematic diagram of the simulation result in an embodiment of the bright field area described in this application.

[0036] Figure 14b It shows a schematic diagram of the simulation result in an embodiment of the dark field area described in this application.

[0037] Figure 15 It shows a schematic diagram of the structure in an embodiment of the electronic device described in this application. Detailed implementation manners

[0038] The following uses specific specific examples to illustrate the implementation manners of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0039] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of this application in a schematic manner. Therefore, only the components related to this application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0040] In addition, in this application, descriptions such as "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by this application.

[0041] The following embodiments of the present application provide a power grid model construction method and system, a simulation method, an electronic device, and a medium. By adopting an efficient modeling strategy, the consumption of computing resources is effectively reduced. In addition, the simulation analysis based on the model constructed in the present application can accurately describe the changes in the electrical properties of superconducting active devices, thereby improving the applicability of the model. In addition, the present application has the ability to convert the layout designs of superconducting integrated circuits under multiple superconducting processes into impedance networks, showing strong universality.

[0042] The technical solution protected by the present application can be regarded as a pre-technology in the field of current and magnetic field analysis. Based on the model constructed in the present application and the simulation results obtained by using the constructed model, an analysis basis can be provided for the current and magnetic field distributions under static and dynamic conditions.

[0043] The power grid model construction method and the simulation method provided by the embodiments of the present application can run on similar devices such as mobile terminals and computer terminals. Taking running on the computer terminal as an example, Figure 1 is the hardware structure block diagram of the computer terminal, as Figure 1 shown, the computer terminal may include: a processor and a memory. The processor may be a central processing unit, and the memory is used to store data. Figure 1 The computer terminal in is only for illustration and does not limit the specific structure of the computer terminal.

[0044] Optionally, the computer terminal may further include: a communication transmission device and an input / output device.

[0045] Optionally, the memory may be used to store computer programs, such as software programs and modules of application software. The memory may include a high-speed random access memory, and may further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory may further include a memory remotely disposed relative to the processor, and these remote memories may be connected to the computer terminal through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0046] Optionally, the communication transmission device may be used to receive or send data via a network. The network may include a wireless network provided by a communication provider of the mobile terminal. The communication transmission device may include a NIC (Network Interface Controller), which can be connected to other network devices through a base station and thus communicate with the Internet.

[0047] Next, the technical solutions in the embodiments of the present application will be described in detail with reference to the accompanying drawings in the embodiments of the present application.

[0048] Please refer to Figure 2 , which shows a flowchart of the method for constructing the power grid model of the superconducting integrated circuit according to the present application in an embodiment.

[0049] As Figure 2 shown, the present application provides a method for constructing a power grid model of a superconducting integrated circuit, including the following steps S100 to S400.

[0050] In step S100, obtain the power grid layer graphics of the superconducting integrated circuit layout.

[0051] The superconducting integrated circuit layout is a planar geometric shape description of the physical situation of the actual superconducting integrated circuit.

[0052] The power grid layer graphics are the graphics of a specific layer or layer in the superconducting integrated circuit layout, used to describe the components within the power grid structure and their connection relationships.

[0053] In an embodiment of the present application, a professional electronic design automation (EDA) tool can be used to obtain the power grid layer graphics of the superconducting integrated circuit layout.

[0054] Please refer to Figure 3 , which shows a schematic diagram of the power grid layer graphics according to the present application in an embodiment.

[0055] In step S200, classify the power grid layer graphics to obtain bright field area graphics and dark field area graphics.

[0056] Specifically, the bright field area graphics refer to the graphic areas retained after lithography and etching in the process. The dark field area refers to the graphics that need to be lithographed and etched in the process, that is, the areas without graphics will be retained.

[0057] Please refer to Figure 4 , which shows a schematic structural diagram of the bright field area and the dark field area according to the present application in an embodiment.

[0058] In an embodiment of the present application, based on a preset integrated circuit process file, classify the power grid layer graphics to obtain the bright field area graphics and the dark field area graphics.

[0059] It should be noted that whether it is the bright field area graphics or the dark field area graphics, from the perspective of the algorithm, they are both regarded as ordinary graphics. However, there are significant differences in the actual physical structures of the bright field area and the dark field area. These differences in physical structures have an important impact on the performance and functions of the hardware. Therefore, in the modeling process, it is necessary to take into account these differences in physical structures and model the bright field area graphics and the dark field area graphics separately.

[0060] In addition, in large-scale superconducting integrated circuits, due to the large circuit scale and complex structure, there are numerous components and connection relationships. Traditional methods for constructing power grid models may require a comprehensive and detailed analysis and processing of the entire circuit, involving a large amount of data processing and complex calculation processes. This leads to a sharp increase in the demand for computing resources, including a large amount of memory occupation, long CPU operations, etc. In this application, through classification, the power grid layer graphics are divided into two relatively independent parts: bright field area graphics and dark field area graphics. In this way, subsequent modeling processes can be carried out separately for the bright field area and the dark field area, avoiding the huge computational pressure brought about by processing the entire power grid layer graphics simultaneously. Through partitioned modeling, the most suitable modeling algorithm and parameter settings can also be selected according to the characteristics of each area, thereby improving the modeling efficiency, reducing unnecessary computational volume, and ultimately achieving the purpose of reducing computing resource consumption.

[0061] In an embodiment of this application, before performing steps S300 and S400 described in this application, it further includes: hierarchically establishing a spatial index structure for the power grid layer graphics; based on the spatial index structure, retrieving specific bright field area graphics and dark field area graphics; and separately performing power grid modeling on the retrieved bright field area graphics and dark field area graphics.

[0062] Specifically, the spatial index structure is a data structure used to accelerate spatial query operations. For example, if it is known that there may be graphics of interest within a certain area, the spatial index structure can quickly narrow down the search range, reduce the time overhead of finding graphics, and thus improve efficiency.

[0063] In an embodiment of this application, the spatial index structure can be a quadtree structure. Each node of the quadtree represents a rectangular or polygonal area. The division rule of the quadtree is to evenly divide the spatial range represented by the root node into four quadrants, and each quadrant corresponds to a child node. This process can be carried out recursively until a predetermined depth is reached or other stopping conditions are met. The indexing method of the quadtree is to determine whether a certain graphic is located within the input rectangular range through rectangular range search. In addition to simple inclusion relationships, the quadtree also has the ability to handle more complex spatial relationship analyses. For example, it is used to determine whether two rectangles intersect or overlap. In addition, after selecting a certain graphic, the quadtree can be used to determine the graphics around the graphic and check the connection relationship between the graphic and other graphics.

[0064] Please refer to Figure 5 , which shows a schematic diagram of the quadtree structure described in this application in an embodiment. As Figure 5As shown, the rectangular range A corresponds to a specific index area. By performing a spatial index on the rectangular range A, it can be determined that the rectangular blocks a, b, c, d, and e are all located in the internal area of the rectangular range A, that is, the corresponding results of the rectangular blocks a, b, c, d, and e are the index results.

[0065] It should be noted that the quadtree structure described in the embodiments of the present application can be replaced by other spatial index structures, such as R-trees, KD-trees, spatial hashing, etc. The present application does not impose any restrictions on the spatial index structure.

[0066] In step S300, a power grid model of the bright field area pattern is established to obtain a bright field area power grid model.

[0067] Please refer to Figure 6a , which shows a schematic diagram of the bright field area pattern described in the present application in an embodiment. Please refer to Figure 6b , which shows a schematic diagram of the bright field area power grid model described in the present application in an embodiment.

[0068] In an embodiment of the present application, establishing a power grid model of the bright field area pattern to obtain a bright field area power grid model includes the following steps S301 to S303.

[0069] In step S301, the bright field area pattern is divided into several non-connected power supply domain patterns.

[0070] Specifically, each power supply domain pattern includes several subordinate logic units. Each power supply domain pattern is a closed area that contains necessary load points but has no direct electrical connection with other power supply domain patterns.

[0071] In an embodiment of the present application, dividing the bright field area pattern into several non-connected power supply domain patterns includes: establishing a union-find set structure of the bright field area pattern; based on the union-find set structure, determining the connectivity relationship between different subordinate logic units within the bright field area pattern; based on the connectivity relationship, dividing the bright field area pattern into several power supply domain patterns, where the mutually connected subordinate logic units are located in the same power supply domain pattern, and the non-connected subordinate logic units are located in different power supply domain patterns.

[0072] Specifically, the union-find set structure is a data structure that can dynamically maintain several non-overlapping sets and support merging and querying.

[0073] In the embodiment of the present application, each basic graphic element in the bright field area graphic is regarded as a node. These basic graphic elements can be polygons, lines, etc. According to the connection relationship between the basic graphic elements, a union-find structure corresponding to the bright field area graphic is constructed. By using the characteristics of the union-find, it is possible to efficiently query whether any two graphic elements belong to the same connected subset, and further determine whether they are electrically connected. The graphic elements in the bright field area graphic are grouped according to the connected subsets to which they belong, and each connected subset corresponds to a power supply domain. By traversing all graphic elements, the number of non-connected connected subsets in the entire bright field area graphic, that is, the number of power supply domains, is counted.

[0074] In this implementation method, by dividing the bright field area graphic into multiple independent power supply domain graphics, each power supply domain graphic can be independently modeled and calculated. This can avoid processing the entire bright field area graphic at one time during the modeling process, thereby greatly reducing the scale of operations and time overhead.

[0075] In step S302, for each of the power supply domain graphics, a corresponding power supply domain power grid model is constructed.

[0076] In an embodiment of the present application, constructing a corresponding power supply domain power grid model for each of the power supply domain graphics includes: establishing an initial bright field area grid based on the coverage range of the subordinate logic units; the initial bright field area grid includes multiple grid units; marking the grid units covered by the power supply domain graphic on the initial bright field area grid; removing the unmarked grid units from the initial bright field area grid and retaining the marked grid units to obtain a new bright field area grid; traversing all subordinate logic units within the power supply domain graphic, obtaining the power supply source point coordinates of each subordinate logic unit, and inserting the power supply source point coordinates into the new bright field area grid; finding the grid units adjacent to the position of the power supply port in the new bright field area grid and establishing a connection between the power supply port and the adjacent grid units.

[0077] In an embodiment of the present application, establishing an initial bright field area grid based on the coverage range of the subordinate logic units includes: obtaining the position coordinates of all subordinate logic units within the power supply domain; based on the position coordinates, parsing out the track coordinates where each subordinate logic unit is located; determining a standardized range according to the track coordinates and the coverage range of the power supply domain graphic; and establishing the initial bright field area grid within the standardized range.

[0078] Please refer to Figure 7a , which shows a schematic diagram of the initial bright field area grid described in the present application in an embodiment. Please refer to Figure 7b , which shows a schematic diagram of the new bright field area grid described in the present application in an embodiment. As Figure 7a andFigure 7b As shown, the shaded area represents the coverage of the subordinate logic unit.

[0079] Specifically, in the process of establishing the initial grid in the bright field area, it is first necessary to obtain the lower left corner coordinates and the upper right corner coordinates of the shaded area. Subsequently, within the area defined by these two coordinates, a square or rectangular grid structure is established. In this structure, each square or rectangular grid represents an independent grid unit, and the spacing between the grids directly determines the fineness of the grid. This specific parameter can be determined according to the process library information.

[0080] In the process of establishing a new grid in the bright field area, it is necessary to traverse all the power supply domain graphics in the bright field area. Based on the coordinate information of each power supply domain graphic, locate the corresponding specific area on the initial grid and mark it accordingly. The finally marked grid units are the grid units that need to be retained, while those unmarked grid units will be discarded. As Figure 7a and Figure 7b shown, the squares inside the grid unit represent the marking points.

[0081] When establishing the connection between the power supply port and the grid unit adjacent to its position, the nearest edge of the adjacent grid unit can be selected and connected to it.

[0082] In step S303, combine all the power supply domain power grid models to obtain the power grid model of the bright field area.

[0083] In step S400, perform power grid modeling on the dark field area graphics to obtain the power grid model of the dark field area.

[0084] In the embodiment of the present application, since the dark field area graphics itself has connectivity, there is no need to perform power supply domain grouping.

[0085] In an embodiment of the present application, performing power grid modeling on the dark field area graphics to obtain the power grid model of the dark field area includes the following steps S401 to S403.

[0086] Please refer to Figure 8a , which shows a schematic diagram of the dark field area graphics described in the present application in an embodiment. Please refer to Figure 8b , which shows a schematic diagram of the power grid model of the dark field area described in the present application in an embodiment.

[0087] In step S401, based on the coverage of the dark field area graphics, establish an initial grid for the dark field area.

[0088] Specifically, the initial grid of the dark field area includes multiple grid units.

[0089] In one embodiment of the present application, based on the coverage range of the dark field area pattern, establishing an initial grid for the dark field area includes: obtaining the position coordinates of all subordinate logic units within the dark field area pattern; based on the position coordinates, parsing out the track coordinates where each subordinate logic unit is located; according to the track coordinates and the coverage range of the dark field area pattern, determining a standardized range; and establishing the initial grid for the dark field area within the standardized range.

[0090] Please refer to Figure 9a , which shows a schematic diagram of the initial grid for the dark field area described in the present application in one embodiment. As Figure 9a shown, the shaded area represents the coverage range of the dark field area pattern.

[0091] Specifically, during the process of establishing the initial grid for the dark field area, it is first necessary to obtain the lower left coordinate and the upper right coordinate of the shaded area. Subsequently, within the area defined by these two coordinates, a square or rectangular grid structure is established. In this structure, each square or rectangular grid represents an independent grid unit, and the spacing between the grids directly determines the fineness of the grid, and this specific parameter can be determined according to the process library information.

[0092] In step S402, according to the position coordinates of the dark field area pattern, determine the grid area covered by the dark field area pattern.

[0093] Please refer to Figure 9b , which shows a schematic diagram of the power grid model for the dark field area described in the present application in one embodiment. As Figure 9b shown, the grid area covered by the dark field area pattern corresponds to at least two of the grid units.

[0094] In step S403, remove the connections between all grid units within the grid area to obtain the dark field area network model.

[0095] The present application effectively reduces the consumption of computing resources by adopting an efficient modeling strategy.

[0096] It should be noted that the protection scope of the method for constructing the power grid model of the superconducting integrated circuit described in the embodiments of the present application is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or reducing steps of the prior art and replacing steps according to the principle of the present application is included in the protection scope of the present application.

[0097] Please refer to Figure 10 , which shows a schematic structural diagram of the system for constructing the power grid model of the superconducting integrated circuit described in the present application in one embodiment.

[0098] As Figure 10As shown in the figure, the present application provides a power grid model construction system for a superconducting integrated circuit, including a graphic acquisition module, a graphic classification module, a bright field area modeling module, and a dark field area modeling module.

[0099] The graphic acquisition module is used to acquire the power grid layer graphics of the superconducting integrated circuit layout.

[0100] The graphic classification module is used to classify the power grid layer graphics to obtain bright field area graphics and dark field area graphics.

[0101] The bright field area modeling module is used to perform power grid modeling on the bright field area graphics to obtain a bright field area power grid model.

[0102] The dark field area modeling module is used to perform power grid modeling on the dark field area graphics to obtain a dark field area power grid model.

[0103] It should be noted that the structures and principles of the graphic acquisition module, the graphic classification module, the bright field area modeling module, and the dark field area modeling module correspond one by one to the steps in the above-mentioned power grid model construction method for the superconducting integrated circuit, so they will not be elaborated here.

[0104] The power grid model construction system for the superconducting integrated circuit provided by the embodiments of the present application can implement the power grid model construction method for the superconducting integrated circuit described in the present application. However, the implementation devices of the power grid model construction method for the superconducting integrated circuit described in the present application include but are not limited to the structures of the power grid model construction system for the superconducting integrated circuit listed in this embodiment. Any structural deformation and replacement of the prior art made according to the principles of the present application are included in the protection scope of the present application.

[0105] Please refer to Figure 11 , which shows the flowchart of the power grid model simulation method for the superconducting integrated circuit described in the present application in an embodiment. As Figure 11 shown, the present application provides a power grid model simulation method for a superconducting integrated circuit, including the following steps S500 to step S800.

[0106] In step S500, obtain the bright field area power grid model and the dark field area power grid model constructed according to the methods described in the above steps S100 to S400.

[0107] In view of the fact that the embodiments of steps S100 to S400 have been described in detail above, they will not be repeated here.

[0108] In step S600, convert the bright field area power grid model into a bright field area power grid SPICE (Simulation Program with Integrated Circuit Emphasis) netlist, and convert the dark field area power grid model into a dark field area ground layer SPICE netlist.

[0109] In an embodiment of the present application, both the constructed bright field area power grid model and the dark field area power grid model are impedance networks. An impedance network is a network model that takes into account electrical parameters such as resistance, inductance, and capacitance. This model can be used to simulate the distribution and flow of current, voltage, and power in the power grid. By constructing an impedance network in the present application, the distribution of current and voltage and the power flow in the power system can be simulated and analyzed.

[0110] The present application has the ability to convert the layout design of superconducting integrated circuits under various superconducting processes into impedance networks, showing strong universality.

[0111] In an embodiment of the present application, the nodes in the SPICE netlist correspond to the network nodes in the impedance network. According to the design requirements, the connection lengths between different network nodes can be proportionally converted into resistor or inductor components and connected to the corresponding nodes.

[0112] As Figure 6b shown, in the bright field area power grid model, the length between every two network nodes represents the connection length.

[0113] In an embodiment of the present application, the step of proportionally converting the connection lengths between different network nodes into resistor or inductor components includes: obtaining a preset unit inductance value or unit resistance value; calculating the inductance value of the inductor component using the formula L = l × Lunit, where L represents the inductance value, l represents the connection length, and Lunit represents the unit inductance; calculating the resistance value of the resistor component using the formula R = l × Runit, where R represents the resistance value, l represents the connection length, and Runit represents the unit resistance value.

[0114] In an embodiment of the present application, the power grid model simulation method of the superconducting integrated circuit described in the present application further includes: adding a power supply excitation to the bright field area power grid model and the dark field area power grid model.

[0115] Specifically, the type of the power supply excitation can be an input current excitation or an input voltage excitation. The value of the power supply excitation can be positive or negative. The positive value represents power supply input, while the negative value represents power supply extraction, aiming to effectively control the distribution of current.

[0116] Please refer to Figure 12a, which shows a schematic diagram of the power supply excitation setting of the bright field area power grid model described in this application in an embodiment. As Figure 12a shown, a current source can be added at the node in the upper left corner or the upper right corner, and this current source is the power supply excitation.

[0117] Please refer to Figure 12b , which shows a schematic diagram of the power supply excitation setting of the dark field area power grid model described in this application in an embodiment. As Figure 12b shown, a voltage source can be added at the node in the lower right corner, and this voltage source is the power supply excitation.

[0118] It should be noted that the user can freely choose the setting position of the power supply excitation, and this application does not impose any restrictions on this.

[0119] In step S700, the bright field area power grid SPICE netlist and the dark field area ground layer SPICE netlist are respectively connected to the original logic circuit SPICE netlist.

[0120] Please refer to Figure 13 , which shows a schematic diagram of the connection relationship of the SPICE netlist described in this application in an embodiment. As Figure 13 shown, the original logic circuit SPICE netlist is provided by the superconducting integrated circuit layout, including the circuit model and the circuit connection relationship. The circuit model refers to the device structure and its connection method inside each logic gate, and these devices mainly include inductors, resistors, and capacitors, etc. The circuit connection relationship describes the connection situation between the logic gates at the current level.

[0121] The top-level SPICE netlist is connected to the original logic circuit SPICE netlist. The top-level SPICE netlist is used to add some simulation settings to the original logic circuit SPICE netlist, such as simulation accuracy, simulation bias coefficient, etc.

[0122] In step S800, based on the bright field area power grid SPICE netlist, the dark field area ground layer SPICE netlist, and the original logic circuit SPICE netlist, SPICE dynamic simulation is performed, and the simulation results are recorded.

[0123] In an embodiment of this application, the SPICE dynamic simulation can be implemented in a SPICE simulator. The content of the SPICE simulation is to simulate devices such as inductors and resistors in the actual circuit, and a real current analysis result can be obtained by providing a real current.

[0124] In one embodiment of the present application, the power grid model simulation method for the superconducting integrated circuit provided by the present application further includes: obtaining current timing data from the simulation results; parsing the current timing data to obtain the maximum and minimum values of the current; for the current value of any node in the bright field power grid model or the dark field power grid model, calculating the relative position of the current value within the range of the maximum and minimum values; based on the relative position, looking up the corresponding index number in a predefined color mapping table, and obtaining the corresponding rendering color from the color mapping table according to the index number; mapping the rendering color to the superconducting integrated circuit layout.

[0125] Please refer to Figure 14a , which shows a schematic diagram of the simulation results of the bright field area described in the present application in one embodiment. Please refer to Figure 14b , which shows a schematic diagram of the simulation results of the dark field area described in the present application in one embodiment.

[0126] Based on the simulation analysis performed on the model constructed according to the present application, the electrical properties of superconducting active devices can be accurately described, thereby improving the applicability of the model.

[0127] It should be noted that the protection scope of the power grid model simulation method for the superconducting integrated circuit described in the embodiments of the present application is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or subtracting steps of the prior art and replacing steps according to the principle of the present application is included in the protection scope of the present application.

[0128] Please refer to Figure 15 , which shows a schematic structural diagram of the electronic device described in the present application in one embodiment. As Figure 15 shown, the present application provides an electronic device, including a memory and a processor.

[0129] The memory is used to store computer programs.

[0130] The processor is used to execute the computer programs stored in the memory, so that the electronic device executes the above-mentioned power grid model construction method and / or power grid model simulation method for the superconducting integrated circuit.

[0131] In an embodiment of the present application, the processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The memory may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory, erasable programmable read-only memory, programmable read-only memory, read-only memory, magnetic memory, flash memory, a magnetic disk, or an optical disc.

[0132] This embodiment further includes one or more of a multimedia component, an input / output (I / O) interface, and a communication component.

[0133] The multimedia component may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory or transmitted through the communication component. The audio component further includes at least one speaker for outputting audio signals. The I / O interface provides an interface between the processor and other interface modules, and the other interface modules may be a keyboard, a mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component may adopt wireless communication, such as Wi-Fi, Bluetooth, near field communication (NFC), 2G, 3G, or 4G, or a combination of one or more of them. Accordingly, the communication component may include: a Wi-Fi module, a Bluetooth module, and an NFC module.

[0134] In several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules / units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of devices or modules or units can be in electrical, mechanical, or other forms.

[0135] The modules / units described as separate components may or may not be physically separated. The components shown as modules / units may or may not be physical modules, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the objectives of the embodiments of the present application. For example, in each embodiment of the present application, the functional modules / units can be integrated in a processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated in one module / unit.

[0136] Those of ordinary skill in the art should further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0137] The embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the methods for constructing the power grid model of the superconducting integrated circuit and / or the method for simulating the power grid model of the superconducting integrated circuit described above are implemented. Those of ordinary skill in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing a processor through a program. The program can be stored in a computer-readable storage medium. The storage medium is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid state drive, magnetic tape, floppy disk, optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrating one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid state disk (SSD)).

[0138] The embodiments of the present application can also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions according to the embodiments of the present application are fully or partially generated. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, or a data center to another website, a computer, or a data center in a wired manner (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (e.g., infrared, wireless, microwave, etc.).

[0139] When the computer program product is executed by a computer, the computer executes the methods described in the foregoing method embodiments. The computer program product can be a software installation package. In the case where the foregoing methods are required, the computer program product can be downloaded and executed on the computer.

[0140] The descriptions of the processes or structures corresponding to the above respective drawings have their own emphases. For parts not detailed in a certain process or structure, reference can be made to the relevant descriptions of other processes or structures.

[0141] The above embodiments are only illustrative of the principles and effects of the present application and are not intended to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present application should still be covered by the claims of the present application.

Claims

1. A method for constructing a power grid model of a superconducting integrated circuit, characterized in that: include: Obtaining the power grid layer graphics of the superconducting integrated circuit layout; Classifying the power grid layer graphics to obtain bright field area graphics and dark field area graphics; Performing power grid modeling on the bright field area graph to obtain a bright field area power grid model; A power grid model is performed on the dark field area graph to obtain a dark field area power grid model.

2. The method according to claim 1, characterized in that The grid modeling is performed on the bright field area graph to obtain the bright field area grid model including: Dividing the bright field area graph into a plurality of power supply domain graphs that are not interconnected, each of the power supply domain graphs comprising a plurality of subordinate logic units; For each of the power supply domain graphs, construct a corresponding power supply domain power grid model; All the power supply domain power grid models are combined to obtain the bright field area power grid model.

3. The method according to claim 1, characterized in that The dark field area graph is subjected to power grid modeling to obtain a dark field area power grid model including: Based on the coverage of the dark field area pattern, an initial dark field area grid is established; the initial dark field area grid includes a plurality of grid units; Determine a grid area covered by the dark field area graphic according to the position coordinates of the dark field area graphic; the grid area corresponds to at least two of the grid units; The connections between all grid cells in the grid area are removed to obtain the dark field area network model.

4. The method according to claim 2, characterized in that: Dividing the bright field area graph into a plurality of power supply domain graphs which are not interconnected includes: Establishing a union-find structure of the bright field area graphics; Based on the union-find structure, determining the connectivity relationship between different subordinate logic units in the bright field area graph; Based on the connectivity relationship, the bright field area graph is divided into a plurality of the power supply domain graphs, wherein the interconnected subordinate logic units are located in the same power supply domain graph, and the unconnected subordinate logic units are located in different power supply domain graphs.

5. The method according to claim 2, characterized in that: For each of the power supply domain graphs, constructing a corresponding power supply domain power grid model includes: Based on the coverage of the subordinate logic unit, an initial grid of the bright field area is established; the initial grid of the bright field area includes a plurality of grid units; Marking the grid cells covered by the power supply domain pattern on the initial grid of the bright field area; Removing unmarked grid cells from the initial grid of the bright field area, retaining the marked grid cells, and obtaining a new grid of the bright field area; Traversing all subordinate logic units in the power supply domain graph, obtaining the power supply source point coordinates of each subordinate logic unit, and inserting the power supply source point coordinates into the new grid of the bright field area; A grid unit adjacent to the power supply port is searched in the new grid of the bright field area, and a connection is established between the power supply port and the grid unit adjacent to the power supply port.

6. The method according to claim 5, characterized in that Based on the coverage of the power supply domain graph, establishing an initial grid includes: Obtaining position coordinates of all subordinate logic units in the power supply domain; Based on the position coordinates, parsing the orbital coordinates of each of the slave logic units; Determining a standardized range according to the track coordinates and the coverage of the power supply domain graph; Within the standardized range, the initial grid is established.

7. A superconducting integrated circuit power grid model construction system, characterized in that: include: A graphics acquisition module, used to acquire the power grid layer graphics of the superconducting integrated circuit layout; A graphics classification module, used to classify the graphics of the power grid layer to obtain bright field graphics and dark field graphics; A bright field area modeling module, used for performing power grid modeling on the bright field area graphics to obtain a bright field area power grid model; The dark field area modeling module is used to perform power grid modeling on the dark field area graphics to obtain a dark field area power grid model.

8. A method for simulating a power grid model of a superconducting integrated circuit, characterized in that: include: Obtaining a bright field area power grid model and a dark field area power grid model constructed according to the method of any one of claims 1 to 6; Converting the bright field area power grid model into a bright field area power grid SPICE netlist, and converting the dark field area power grid model into a dark field area ground layer SPICE netlist; Connecting the bright field area power grid SPICE netlist and the dark field area ground layer SPICE netlist to the original logic circuit SPICE netlist respectively; Based on the SPICE netlist of the bright field area power grid, the SPICE netlist of the dark field area ground layer and the SPICE netlist of the original logic circuit, a SPICE dynamic simulation is performed, and the simulation results are recorded.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program stored in the memory so that the electronic device executes the method for constructing a power grid model of a superconducting integrated circuit as described in any one of claims 1 to 6 and / or the method for simulating a power grid model of a superconducting integrated circuit as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method for constructing a power grid model of a superconducting integrated circuit according to any one of claims 1 to 6 and / or the method for simulating a power grid model of a superconducting integrated circuit according to any one of claim 8 are implemented.

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