Integrated circuit buffer insertion method and device and storage medium

Abstract

The invention discloses an integrated circuit buffer insertion method, and relates to an integrated circuit buffer design technology. The method comprises the following steps: acquiring original data of all nodes in a target integrated circuit; based on a multi-head self-attention mechanism, aggregating the original data of all nodes, and generating a coding representation corresponding to each node; selecting an unaccessed node and an accessed node based on the pointer network, generating a connection function between the unaccessed node and the accessed node, and constructing an edge between the unaccessed node and the accessed node; determining a peak value of a simple harmonic function corresponding to the edge as a buffer candidate position, and constructing a Steiner tree structure containing the buffer candidate position; and based on a dynamic programming algorithm, judging whether a buffer needs to be inserted into each buffer candidate position. The method does not depend on manual setting of candidate points, and meanwhile, the insertion of the buffer can be considered when the Steiner tree structure is generated, so that an integrated circuit buffer insertion scheme with a better effect is generated more stably.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit buffer design, and particularly to an integrated circuit buffer insertion method, device, and storage medium. Background Art

[0002] With the continuous development of the ultra-large scale integrated circuit industry, the feature size of integrated devices has been significantly reduced, and the delay problem has become one of the main factors to be considered in chip design. In terms of the delay problem, inserting buffers has become a common technical means. A buffer is usually a gate composed of two inverters in series, which regenerates a signal without changing its function.

[0003] Generally speaking, in a chip, the clock signal output by the clock source needs to drive a large number of registers. However, relying solely on the signal driving ability of the clock source is obviously not enough to support such a large fan-out. Therefore, a large number of buffers need to be added to the circuit, and these buffers are connected in series or in parallel one by one to form a clock tree, and each sub-node is divided into a new branch. After the clock tree is formed, the clock source directly drives the buffer, and the buffer drives the subsequent registers. This is equivalent to reducing the load quantity of each branch of the clock tree by inserting buffers, so the driving ability of each branch of the clock tree is enhanced, thereby reducing the delay of the clock signal.

[0004] More importantly, inside the chip, components are connected by wires, and the delay of the wires is usually proportional to the square of their length. Suppose a certain path is very long, then the load capacitance of the wire itself will also be very large, which will cause a large delay. If a buffer is inserted in the middle of the wire to divide the wire into multiple segments, then the load capacitance of each segment will be a smaller value. At a given voltage, since the load capacitance of the circuit decreases, the charging speed of the capacitance will increase, making the rising edge of the signal steeper; similarly, when the capacitance discharges, since the load capacitance becomes less, the discharging speed of the capacitance will also increase, making the falling edge of the signal steeper. Therefore, since the signal transition time becomes smaller, the delay of the path also becomes smaller. So even though the buffer itself will also introduce delay, if the delay reduced after inserting the buffer is greater than the delay introduced by the buffer itself, the timing can still be optimized.

[0005] In summary, reasonable buffer insertion can help manage signal integrity and transmission time, thereby reducing signal delay. The number and position of buffers are two key factors to be considered in constructing an ideal circuit. Improper placement or overuse of buffers may even increase the delay. As Figure 1 shown, in the figure, the circle represents the clock source, the square represents the register, and the triangle represents the buffer. Figure 1The reasonable buffer insertion in [ ] reduces the time delay, while Figure 1 the buffer insertion in [ ] and [ ] increases the time delay instead. How to design the optimal buffer placement scheme has been proven to be an NP-hard problem.

[0006] The existing scheme closest to the present invention was proposed by Van Ginneken (Van Ginneken L P P P. Buffer placement in distributed RC-tree networks for minimal Elmore delay[C] / / 1990 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1990: 865-868.). It requires a predefined clock tree topology without buffer insertion. This topology usually takes the form of a rectilinear Steiner tree, with the root node being the clock source and the leaf nodes being the registers. The rectilinear Steiner tree is defined as a tree that uses straight line segments (i.e., vertical and horizontal line segments) and additional auxiliary points (i.e., Steiner points) to connect a given set of nodes on a plane. The rectilinear Steiner tree is also called the "Steiner tree".

[0007] Van Ginneken proposed a dynamic programming method for buffer insertion. This technique uses a Steiner tree and a set of buffer insertion candidate points on the tree as inputs, and based on the dynamic programming algorithm, provides the final buffer insertion positions as outputs. A schematic diagram of the insertion result can be seen in Figure 2 . The optimization objective of this technique is to maximize the minimum value among the slack values of each register. The slack value is defined as the difference between the signal arrival time and the signal delay. For each register, there is a given signal arrival time and a delay calculated according to the buffer insertion scheme (i.e., the time for the signal to transmit from the clock source to the register). There are various methods for estimating the signal delay, and this technique uses the Elmore delay to approximate the signal delay, which is a second-order approximation estimation method for delay. This technique uses a bottom-up order and judges each buffer candidate point with the goal of optimizing the slack value.

[0008] The specific judgment criteria are as follows: The topological structure between the previous candidate point and the currently to-be-judged candidate point is divided into three cases: The topological structure is that a section of wire is added, and in this case, the slack value will decrease by the wire delay of this wire; The topological structure is that a buffer is inserted, and in this case, the slack value will decrease by the self-delay of this buffer; The topological structure is that two subtrees converge at a node, and in this case, the slack value is the smaller one of the slack values of the two subtrees. After the judgment of all candidate points is completed, a complete buffer insertion scheme is generated.

[0009] The main disadvantages of the prior art are as follows: The prior art makes buffer insertion judgments based on the Steiner tree of the existing clock tree and the candidate positions of buffers, and the two steps are carried out separately. Therefore, when constructing the Steiner tree, the prior art simply takes the wire length as the optimization goal and does not take into account the signal delay problem. At the same time, relying on manual setting of buffer candidate positions makes the quality of the candidate positions have strong uncertainty. And the quality of the candidate positions directly affects the effect of the final buffer insertion scheme, resulting in strong uncertainty in the effect of the buffer insertion scheme generated by this technology. Summary of the Invention

[0010] The present invention provides an integrated circuit buffer insertion method, device, and storage medium for more stably generating an integrated circuit buffer insertion scheme with better effects.

[0011] To solve the above technical problems, the first aspect of the present invention discloses an integrated circuit buffer insertion method, and the method includes: Obtain the original data of all nodes in the target integrated circuit, where the nodes include a clock source and registers, and the original data includes position data and capacitance data; Based on the multi-head self-attention mechanism, aggregate the original data of all the nodes to generate an encoded representation corresponding to each node; According to the encoded representations corresponding to all the nodes, select unvisited nodes and visited nodes based on the pointer network, generate a connection function between the unvisited nodes and the visited nodes, and construct edges between the unvisited nodes and the visited nodes; For the edges between the unvisited nodes and the visited nodes, determine the peak value of the corresponding harmonic function of the edge as the buffer candidate position, and construct a Steiner tree structure including the buffer candidate position; According to the Steiner tree structure including the buffer candidate position, based on the dynamic programming algorithm, judge whether a buffer needs to be inserted at each buffer candidate position, and generate a target Steiner tree, where the target Steiner tree is used to indicate the insertion quantity and insertion position of the buffers in the target integrated circuit.

[0012] As an alternative implementation, in the first aspect of the present invention, the original data is 3D data, including x-axis coordinate values, y-axis coordinate values, and capacitance values; the encoded representation is 128D data.

[0013] As an alternative implementation, in the first aspect of the present invention, based on the encoded representations corresponding to all the nodes, an unvisited node and a visited node are selected based on a pointer network, a connection function between the unvisited node and the visited node is generated, and an edge between the unvisited node and the visited node is constructed, including: Each time a node t is added as a visited node, the following steps are executed once: Select an unvisited node based on the pointer network and a visited node , and an unvisited node and a visited node are generated, and a connection function between them is generated, where the connection function represents the connection order between the unvisited node and the visited node ; A sub-Steiner tree is constructed according to all the visited nodes, where the sub-Steiner tree corresponds to a topological information vector and a buffer position vector , the topological information vector is used to represent the topological information of the sub-Steiner tree, and the buffer position vector is used to represent the candidate positions for buffer insertion; The topological information vector is updated to , where is a parameter obtained through sample training, represents the encoding of the newly constructed edge between the unvisited node and the visited node; The buffer position vector is updated to , where is a parameter obtained through sample training; Among them, is determined by the following formula:

[0014] Among them is a parameter obtained through sample training, are the encoded representations of nodes and respectively.

[0015] As an alternative implementation, in the first aspect of the present invention, every time a node t is added as the visited node, the following steps are also executed once: Calculate the first query vector according to the following formula :

[0016] wherein, the first query vector is used to indicate the selection of unvisited nodes ; Calculate the second query vector according to the following formula :

[0017] wherein, the second query vector is used to indicate the selection of visited nodes , where is a parameter obtained through sample training.

[0018] As an alternative implementation, in the first aspect of the present invention, for the edge between the unvisited node and the visited node, determining the peak value of the corresponding harmonic function of the edge as the buffer candidate position includes: For the edge between the unvisited node and the visited node, determine the corresponding harmonic function of the edge as:

[0019] In the above formula, L is the wire length corresponding to the edge between the unvisited node and the visited node, and are the unit resistance and unit capacitance of the wire, and are the resistance and capacitance of the buffer to be inserted, is the harmonic function phase; Determine the peak value of the harmonic function as the buffer candidate position.

[0020] As an alternative implementation, in the first aspect of the present invention, the phase of the harmonic function is determined by the following formula:

[0021] In the above formula, h is a parameter obtained through sample training.

[0022] As an alternative implementation, in the first aspect of the present invention, selecting unvisited nodes based on the pointer network and the visited nodes , including: For all n visited nodes, based on the pointer network, an n-dimensional probability vector is determined ; where PTM is the pointer network, is the encoded representation corresponding to the node, is the parameter obtained through sample training, q is the query vector, and the n-dimensional probability vector is used to indicate the selection of unvisited nodes and the visited nodes .

[0023] The second aspect of the present invention discloses an integrated circuit buffer insertion device, and the device includes: An acquisition module, configured to acquire the original data of all nodes in the target integrated circuit, where the nodes include a clock source and a register, and the original data includes position data and capacitance data; An encoder, configured to aggregate the original data of all the nodes based on the multi-head self-attention mechanism to generate an encoded representation corresponding to each node; An edge selection network, configured to select unvisited nodes and visited nodes based on the pointer network according to the encoded representations corresponding to all the nodes, generate a connection function between the unvisited nodes and the visited nodes, and construct an edge between the unvisited nodes and the visited nodes; A buffer network, configured to determine, for the edge between the unvisited nodes and the visited nodes, that the peak value of the harmonic function corresponding to the edge is the buffer candidate position, and construct a Steiner tree structure including the buffer candidate position; A post-processor, configured to determine whether a buffer needs to be inserted at each buffer candidate position based on the dynamic programming algorithm according to the Steiner tree structure including the buffer candidate position, and generate a target Steiner tree, where the target Steiner tree is used to indicate the insertion quantity and insertion position of the buffers in the target integrated circuit.

[0024] As an optional implementation manner, in the second aspect of the present invention, the original data is 3D data, including an x-axis coordinate value, a y-axis coordinate value, and a capacitance value; the encoded representation is 128D data.

[0025] As an optional implementation manner, in the second aspect of the present invention, the specific operation manner of the edge selection network for selecting unvisited nodes and visited nodes based on the pointer network according to the encoded representations corresponding to all the nodes, generating a connection function between the unvisited nodes and the visited nodes, and constructing an edge between the unvisited nodes and the visited nodes includes: Each time a node t is added as a visited node, the following steps are executed once: Selecting unvisited nodes based on a pointer network and visited nodes and generating a connection function between the unvisited nodes and the visited nodes , where the connection function represents the connection order between the unvisited nodes and the visited nodes; Constructing a sub - Steiner tree based on all visited nodes, where the sub - Steiner tree corresponds to a topological information vector and a buffer position vector , the topological information vector is used to represent the topological information of the sub - Steiner tree, and the buffer position vector is used to represent the candidate positions for buffer insertion; Updating the topological information vector to , where is a parameter obtained through sample training, represents the encoding of the edge between the newly constructed unvisited nodes and visited nodes; Updating the buffer position vector to , where is a parameter obtained through sample training; where is determined by the following formula: , where is a parameter obtained through sample training, are the encoding representations of nodes and respectively.

[0026] As an alternative implementation, in the second aspect of the present invention, the edge - selection network is further used for: Each time a node t is added as a visited node, the following steps are also executed once: Calculating a first query vector according to the following formula:

[0027] where the first query vector is used to indicate the selection of unvisited nodes ; Calculating a second query vector according to the following formula:

[0028] where the second query vector For indicating the selection of the visited node , where are parameters obtained by sample training.

[0029] As an alternative implementation, in the second aspect of the present invention, the specific manner in which the buffer network determines the peak of the harmonic function corresponding to the edge between the unvisited node and the visited node as the buffer candidate position includes:[[]] For the edge between the unvisited node and the visited node, determine the corresponding harmonic function of the edge as:[[]]

[0030] In the above formula, L is the wire length corresponding to the edge between the unvisited node and the visited node, and are the unit resistance and unit capacitance of the wire, and are the resistance and capacitance of the buffer to be inserted, is the harmonic function phase; Determine the peak of the harmonic function as the buffer candidate position.

[0031] As an alternative implementation, in the second aspect of the present invention, the phase of the harmonic function is determined by the following formula:[[]]

[0032] In the above formula, h are parameters obtained by sample training.

[0033] As an alternative implementation, in the second aspect of the present invention, the specific operation manner in which the edge selection network selects the unvisited node and the visited node includes:[[]] For all n visited nodes, based on the pointer network, determine the n-dimensional probability vector ; where PTM is the pointer network, is the encoded representation corresponding to the node, are parameters obtained by sample training, q is the query vector, and the n-dimensional probability vector is used to indicate the selection of the unvisited node and the visited node .

[0034] The third aspect of the present invention discloses another integrated circuit buffer insertion system, and the system includes: A memory storing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory and executes the integrated circuit buffer insertion method disclosed in the first aspect of the present invention.

[0035] The fourth aspect of the present invention discloses a computer storage medium, and the computer storage medium stores computer instructions, which are used to execute the integrated circuit buffer insertion method disclosed in the first aspect of the present invention when called.

[0036] Compared with the prior art, the present invention no longer relies on manual setting of candidate points, and can take into account the insertion of buffers when generating the Steiner tree structure, generating a better Steiner tree topology structure, and thus more stably generating an integrated circuit buffer insertion scheme with better effects. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0038] Figure 1 It is a schematic diagram of the buffer and signal delay; Figure 2 It is a schematic diagram of the buffer insertion result; Figure 3 It is a flowchart of an integrated circuit buffer insertion method disclosed in an embodiment of the present invention Figure 4 It is a schematic diagram of the node connection method; Figure 5 It is a schematic diagram of the buffer candidate position function of the overlapping edge; Figure 6 It is a graph of the performance comparison results of each technology under the simulated data set; Figure 7 It is a graph of the performance comparison results of each technology under the industrial data; Figure 8 It is a schematic diagram of the structure of an integrated circuit buffer insertion device disclosed in an embodiment of the present invention; Figure 9 It is a schematic diagram of the structure of an integrated circuit buffer insertion system disclosed in an embodiment of the present invention. Detailed Embodiments

[0039] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solution in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0040] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or terminal that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or terminals.

[0041] Referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0042] The present invention discloses an integrated circuit buffer insertion method, device, and storage medium for more stably generating an integrated circuit buffer insertion scheme with better effects.

[0043] Embodiment 1 Please refer to Figure 3 , Figure 3 which is a flowchart of an integrated circuit buffer insertion method disclosed in an embodiment of the present invention. Among them, Figure 3 the described integrated circuit buffer insertion method can be implemented in an integrated circuit buffer insertion device, and the integrated circuit buffer insertion device can be integrated in a cloud server or a local server. As Figure 3 shown, the integrated circuit buffer insertion method may include the following operations: Step 101, obtain the original data of all nodes in the target integrated circuit.

[0044] Among them, the nodes may include a clock source and registers, and the original data may include position data and capacitance data; optionally, the original data is 3D data, which may include the x-axis coordinate value, y-axis coordinate value, and capacitance value; the encoded representation is 128D data. For example, the original data may include position data (x-axis coordinate value, y-axis coordinate value) and capacitance data. For example, in a specific integrated circuit design, assuming the clock source is located at the coordinates (0, 0), and the registers are located at the coordinates (10, 5), (20, 10), etc., and the corresponding capacitance values are 10 pF, 20 pF, etc. respectively. These data can be organized into a table form for subsequent processing.

[0045] Step 102: Aggregate the original data of all nodes based on the multi-head self-attention mechanism to generate an encoded representation corresponding to each node.

[0046] In the embodiment of the present invention, the original data of all nodes is aggregated based on the multi-head self-attention mechanism. For example, the original data of each node (3D data, including the x-axis coordinate value, y-axis coordinate value, and capacitance value) is input into the multi-head self-attention model. Through the calculation of the model, an encoded representation corresponding to each node is generated, and the encoded representation is 128D data. For example, for the above clock source node, after being processed by the multi-head self-attention mechanism, a 128D encoded vector is obtained, such as [0.1, 0.2,..., 0.9] (only some dimensions are shown here); for the register node, a 128D encoded vector of each is also obtained.

[0047] Step 103: Based on the encoded representations corresponding to all nodes, select unvisited nodes and visited nodes based on the pointer network, generate a connection function between the unvisited nodes and the visited nodes, and construct an edge between the unvisited nodes and the visited nodes.

[0048] In the embodiment of the present invention, one node is added in each step, and then the unvisited nodes and the visited nodes are selected through the pointer network, a connection function between the unvisited nodes and the visited nodes is generated, and an edge between the unvisited nodes and the visited nodes is constructed. Then, one more node is added in the next step and the above operations are repeated. Finally, after all nodes are processed, the operation of this step is completed.

[0049] Step 104: For the edge between the unvisited node and the visited node, determine the peak value of the corresponding harmonic function of the edge as the buffer candidate position, and construct a Steiner tree structure including the buffer candidate position.

[0050] In the prior art, usually, a Steiner tree structure is first constructed, and then a suitable buffer insertion position is considered. However, the method for determining the buffer insertion position is unstable. Therefore, in the embodiments of the present invention, the construction of the Steiner tree and the selection of the candidate positions for buffer insertion are carried out simultaneously, and the peak value of the harmonic function corresponding to the edge between the unvisited node and the visited node is determined as the buffer candidate position. The following will provide the proof for determining the peak value of the harmonic function corresponding to the edge between the unvisited node and the visited node as the buffer candidate position: The embodiments of the present invention find that: Conclusion 1: Buffers uniformly distributed along the wire can minimize the delay between two nodes. Conclusion 2: The optimal number of inserted buffers can be accurately calculated as , where L is the wire length, and are the unit resistance and unit capacitance of the wire, and are the resistance and capacitance of the buffer. Based on the above conclusions, the distribution of the buffer candidate positions can be parameterized and approximated as the peak of the harmonic function.

[0051] Step 105: According to the Steiner tree structure including the buffer candidate positions, based on the dynamic programming algorithm, determine whether each buffer candidate position needs to insert a buffer, and generate a target Steiner tree, which is used to indicate the insertion number and insertion position of the target integrated circuit buffer.

[0052] In the embodiments of the present invention, based on the dynamic programming algorithm, the Steiner tree structure including the buffer candidate positions is analyzed, and finally the optimal insertion number and position of the buffer are output. Among them, the optimization objective of the dynamic programming algorithm can be set as: for n registers, the optimization objective is expressed as , where is the delay of each register.

[0053] It can be seen that the embodiments of the present invention no longer rely on manual setting of candidate points, and can consider the insertion of buffers when generating the Steiner tree structure, generate a better Steiner tree topology, and thus more stably generate an integrated circuit buffer insertion scheme with better effects.

[0054] In an optional embodiment, according to the encoded representations corresponding to all nodes, based on the pointer network, select unvisited nodes and visited nodes, generate a connection function between the unvisited nodes and the visited nodes, and construct an edge between the unvisited nodes and the visited nodes, which may include: Each time a node t is added as a visited node, the following steps are executed once: Select unvisited nodes based on the pointer network and visited nodes , and generate unvisited nodes and the visited nodes connection function between , where the connection function represents the unvisited nodes and the visited nodes connection order between; Specifically, if the connection order is Figure 4 the connection method in a of , if the connection order is Figure 4 the connection method in b of , is the encoding representation of nodes and .

[0055] Construct a sub - Steiner tree according to all the visited nodes, where the sub - Steiner tree corresponds to a topological information vector and a buffer position vector , the topological information vector is used to represent the topological information of the sub - Steiner tree, and the buffer position vector is used to represent the candidate positions for buffer insertion; Update the topological information vector to , where is a parameter obtained through sample training, represents the encoding of the edge between the newly constructed unvisited nodes and the visited nodes; Specifically, all the parameters obtained through sample training in the present invention are preset with initial values according to specific situations, and then the specific values of each parameter are determined after neural network training using a large number of training samples.

[0056] Update the buffer position vector to , where, is a parameter obtained through sample training; where, is determined by the following formula:

[0057] where is a parameter obtained through sample training, are respectively the encoding representations of nodes and .

[0058] In another alternative embodiment, every time a node t is added as a visited node, the following steps are also executed once: Calculate the first query vector according to the following formula :

[0059] Among them, the first query vector is used to indicate the selection of unvisited nodes ; The second query vector is calculated according to the following formula :

[0060] Among them, the second query vector is used to indicate the selection of visited nodes , where are parameters obtained through sample training.

[0061] In yet another alternative embodiment, for the edge between an unvisited node and a visited node, determining the peak of the harmonic function corresponding to the edge as the buffer candidate position may include: For the edge between an unvisited node and a visited node, determining the harmonic function corresponding to the edge as:

[0062] In the above formula, L is the wire length corresponding to the edge between the unvisited node and the visited node, and are the unit resistance and unit capacitance of the wire, and are the resistance and capacitance of the buffer to be inserted, is the harmonic function 's phase; Determine the peak of the harmonic function as the buffer candidate position.

[0063] Among them, further optionally, the phase of the harmonic function is determined by the following formula:

[0064] In the above formula, h are parameters obtained through sample training.

[0065] In yet another alternative embodiment, selecting unvisited nodes and visited nodes based on the pointer network may include: For all n visited nodes, based on the pointer network, determine the n-dimensional probability vector ; Among them, PTM is the pointer network, is the encoded representation corresponding to the node, is a parameter obtained through sample training, q is a query vector, and it is an n-dimensional probability vector used to indicate the selection of unvisited nodes and visited nodes .

[0066] Embodiment 2 The embodiment of the present invention discloses a specific integrated circuit buffer insertion method, and the description of this method is as follows: The embodiment of the present invention models the buffer insertion problem as a problem of minimizing the maximum value of the Elmore delay of each register, and finally generates a Steiner tree with buffer insertion. For each circuit, the Elmore delay of each register can be calculated from the basic circuit information and topological information. The basic circuit information is known parameters, including: the coordinates and capacitance of the registers, the inherent delay, capacitance, and resistance of the buffers, and the unit capacitance and resistance of the wires. The topological information of the circuit is the problem to be solved, including the number and position of buffer insertions, and the Steiner tree structure of the clock source, registers, and buffers. For n registers, the optimization objective of the embodiment of the present invention can be expressed as , where is the delay of each register.

[0067] The embodiment of the present invention mainly utilizes reinforcement learning, and the specific technical process is an encoder, an action network, a post-processing process, and an evaluation network. Among them, the action network can be further divided into an edge selection network and a candidate point network.

[0068] Specifically, the embodiment of the present invention relies on the following operations to implement: The encoder receives nodes (i.e., the clock source and registers) as inputs and generates encodings for each node. The original input for each node is 3D data, including its xy coordinate values and capacitance, and this input is then fed into the encoder module. Based on the multi-head self-attention mechanism, the encoder module uses multi-head self-attention layers to aggregate information from different nodes, thereby creating a new encoding representation for each node. After encoding, the encoding representation of each node is 128-dimensional.

[0069] The action network. The action network receives the encoding of each node generated by the encoder as input and finally outputs a Steiner tree structure with buffer candidate positions. During the construction process, the visited nodes together form a subtree, and on this basis, a new node is added at each step. To distinguish the selected unvisited nodes and visited nodes in step , we represent them as and respectively. At the same time, two key vector pairs are used to encode the information related to this subtree, which are and respectively. Pay attention to the topological information of the tree Focus on the candidate positions for buffer insertion. Both are initialized as zero vectors.

[0070] In each step of the edge selection network, the construction of the edge involves selecting unvisited nodes and connecting them to visited nodes. This task is similar to the task in the REST technique, whose purpose is to construct a Steiner tree with the minimum wire length. Embodiments of the present invention adopt the same network structure to select unvisited nodes and visited nodes . This selection is based on the Point Network, which can select specific components from the input and is a method commonly used to solve combinatorial problems. Assuming the input nodes, using the pointer mechanism, an n-dimensional probability vector can be obtained to represent the probability of selecting n nodes. Where PTM is the pointer network, is the output of the encoder, are the parameters to be trained, and q is the query vector representing the encoding environment.

[0071] In step t, the edge selection network first selects an unvisited node , then selects a visited node , and at the same time generates a connection function connect() indicating the connection order of nodes and . If the connection order is the connection method in a in Figure 4 , then , if the connection order is the connection method in b in Figure 4 , then , is the encoded representation of nodes and . For step t + 1, the topological information vector is updated to . Where are the parameters to be trained, represents the encoding of the newly constructed edge, and the calculation method is: , where are the parameters to be trained.

[0072] The query vector q plays a key role in the network. In step t, the query vector used to select the unvisited node is calculated as: , and the query vector used to select the visited node is calculated as: , where are the parameters to be trained.

[0073] Buffer network: For the case of only two nodes, the embodiments of the present invention find that: Conclusion 1: Buffers evenly distributed along the wire can minimize the delay between two nodes. Conclusion 2: The optimal number of inserted buffers can be accurately calculated as , where L is the wire length, and are the unit resistance and unit capacitance of the wire, and are the resistance and capacitance of the buffer. Based on the above conclusions, the distribution parameters of the buffer candidate positions can be parametrically approximated as the peaks of a harmonic function.

[0074] In step t, for the edge connected by and , the function for determining the buffer candidate position is: . Where is the phase of the harmonic function, predicted by the neural network, , where h is the parameter to be trained. For step t + 1, the buffer information vector is updated to , is the parameter to be trained. After constructing the complete Steiner tree, some edges will overlap topologically. For the overlapping edges, the final buffer candidate position function is the sum of the harmonic functions of its overlapping edges. This summation produces a new harmonic function with the same frequency but different amplitudes and phases, as shown in Figure 5 .

[0075] The post - processing process is based on the Steiner tree containing buffer candidate positions generated by the action network, determines whether each candidate position should insert a buffer, and generates the final Steiner tree. For whether each candidate position should insert a buffer, the judgment criterion can be the same as that of the dynamic programming algorithm in the prior art.

[0076] Evaluation network and loss function: The evaluation network is used to assist the learning process of the action network. Based on the encoding results of each node, the evaluation network predicts the minimum possible value of the maximum Elmore delay of the register to set a baseline.

[0077] Assume that based on the Steiner tree generated by the action network and the post - processing process, the maximum Elmore delay of the register is Del, and the value predicted by the comment network is Pre. Then the difference Del - Pre will be used to judge the performance of the action network at this specific point set. This indicates how much better the performance of the action network is than expected.

[0078] For N groups of training samples, the loss function of the action network is defined as:

[0079] Among them, represents an element in the probability vector, and the loss function of the evaluation network is defined as:

[0080] Optionally, both the action network and the evaluation network use the stochastic gradient descent method for parameter update.

[0081] The following shows the detailed comparison results between the embodiments of the present invention and other technologies. The result label of the embodiments of the present invention is "HarRL". Figure 6 Table 1 shows the comparison results between the embodiments of the present invention and other technologies based on a simulated data set. Figure 6 The comparison results of the maximum register delay (Max Delay), skew, and total wire length (Total Wire Length) are shown. Among them, the maximum delay is the optimization goal of the embodiments of the present invention, and the skew and total wire length are also considered as important indicators in the field of circuit design. In terms of the maximum delay, the embodiments of the present invention perform significantly better than other technologies. In terms of skew, the embodiments of the present invention also achieve the second-best performance, second only to the BCTS technology that specifically optimizes skew. In terms of the total wire length, the embodiments of the present invention perform on par with the FLUTE technology that specifically optimizes the total wire length. Table 1 shows the running time results. The embodiments of the present invention are only slightly slower than the REST technology, which is due to the slightly more complex network structure of the embodiments of the present invention compared to REST, but the embodiments of the present invention are significantly faster than other technologies.

[0082] Table 1: Comparison of the running times of various technologies under the simulated data set.

[0083]

[0084] Figure 7 The comparison results between the embodiments of the present invention and other technologies based on the industrial data ariane136, mempool_tile_wrap, NV_NVDLA_partition_p in the ICCAD 2024 competition are shown. The embodiments of the present invention still achieve the best performance.

[0085] It can be seen that the embodiments of the present invention are an end-to-end method based on reinforcement learning, which simultaneously generates the Steiner tree structure of the clock tree and the buffer candidate positions, and then performs post-processing according to the candidate positions to generate the final buffer insertion scheme, while balancing the wire length target and the delay target. Existing technologies only provide candidate point selection techniques and can only generate the final buffer insertion scheme based on the existing minimum wire length Steiner tree structure and buffer candidate points.

[0086] In the buffer candidate position generation stage, according to the characteristics of the neural network and the distribution characteristics of the buffers, the embodiments of the present invention parameterize the buffer position as a simple harmonic function and use the neural network to generate the number and positions of the candidate points. This solves the problem that the quality of the candidate points is not guaranteed in the prior art.

[0087] Regarding the effect of the generated solution, although the embodiments of the present invention slightly increase the total wire length, they significantly reduce the maximum register signal delay. Regarding the time required for generating the solution, the running speed of the embodiments of the present invention is much faster than that of the prior art.

[0088] In summary, the embodiments of the present invention significantly reduce the maximum register signal delay. And regarding the time required for generating the solution, the running speed of the embodiments of the present invention is much faster than that of the prior art. Different from the traditional heuristic algorithms in the prior art, the embodiments of the present invention use reinforcement learning to implement an end-to-end method. In the action network, the buffer candidate positions are parameterized as simple harmonic functions, and at the same time, the Steiner tree structure of the clock tree and the buffer candidate positions are automatically generated. This sequentially improves the algorithm effect and the calculation speed.

[0089] Embodiment III Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of an integrated circuit buffer insertion device disclosed in the embodiments of the present invention. As Figure 8 shown, the integrated circuit buffer insertion device may include: An acquisition module 201, configured to acquire the original data of all nodes in the target integrated circuit, where the nodes may include a clock source and registers, and the original data may include position data and capacitance data; An encoder 202, configured to aggregate the original data of all nodes based on the multi-head self-attention mechanism to generate an encoded representation corresponding to each node; An edge selection network 203, configured to select unvisited nodes and visited nodes based on the encoded representations corresponding to all nodes according to the pointer network, generate a connection function between the unvisited nodes and the visited nodes, and construct an edge between the unvisited nodes and the visited nodes; A buffer network 204, configured to determine the peak value of the corresponding simple harmonic function of the edge between the unvisited nodes and the visited nodes as the buffer candidate position, and construct a Steiner tree structure including the buffer candidate position; A post-processor 205, configured to determine whether a buffer needs to be inserted at each buffer candidate position based on the Steiner tree structure including the buffer candidate position according to the dynamic programming algorithm, and generate a target Steiner tree, where the target Steiner tree is used to indicate the number and insertion positions of the integrated circuit buffers in the target.

[0090] In an alternative embodiment, the original data is 3D data, which may include x-axis coordinate values, y-axis coordinate values, and capacitance values; the encoded representation is 128D data.

[0091] In yet another alternative embodiment, the edge selection network 203, based on the encoded representations corresponding to all nodes, selects unvisited nodes and visited nodes using a pointer network, generates a connection function between the unvisited nodes and the visited nodes, and constructs the edges between the unvisited nodes and the visited nodes. The specific operation may include: For each added node t as a visited node, the following steps are executed once: Select unvisited nodes using a pointer network and visited nodes , and generate unvisited nodes and visited nodes between the connection function , where the connection function represents the connection order between the unvisited nodes and the visited nodes ; Construct a sub-Steiner tree based on all visited nodes, where the sub-Steiner tree corresponds to a topological information vector and a buffer position vector , the topological information vector is used to represent the topological information of the sub-Steiner tree, and the buffer position vector is used to represent the candidate positions for buffer insertion; Update the topological information vector to , where is a parameter obtained through sample training, represents the encoding of the newly constructed edge between the unvisited nodes and the visited nodes; Update the buffer position vector to , where, is a parameter obtained through sample training; where, is determined by the following formula: , where is a parameter obtained through sample training, are the encoded representations of nodes and respectively.

[0092] In yet another alternative embodiment, the edge selection network 203 is further configured to: For each added node t as a visited node, the following steps are also executed once: Calculate the first query vector according to the following formula :

[0093] Among them, the first query vector is used to indicate the selection of unvisited nodes ; The second query vector is calculated according to the following formula :

[0094] Among them, the second query vector is used to indicate the selection of visited nodes , where is a parameter obtained through sample training.

[0095] In yet another alternative embodiment, for the edge between the unvisited node and the visited node, the specific manner in which the buffer network 204 determines the peak of the harmonic function corresponding to this edge as the buffer candidate position may include: For the edge between the unvisited node and the visited node, determine the harmonic function corresponding to this edge as:

[0096] In the above formula, L is the wire length corresponding to the edge between the unvisited node and the visited node, and are the unit resistance and unit capacitance of the wire, and are the resistance and capacitance of the buffer to be inserted, is the harmonic function phase; Determine the peak of the harmonic function as the buffer candidate position.

[0097] In yet another alternative embodiment, the phase of the harmonic function is determined by the following formula:

[0098] In the above formula, h is a parameter obtained through sample training.

[0099] In yet another alternative embodiment, the specific operation manner in which the edge selection network 203 selects the unvisited node and the visited node based on the pointer network may include: For all n visited nodes, based on the pointer network, determine the n-dimensional probability vector ; Among them, PTM is the pointer network, which is the encoded representation corresponding to the node, where θ is the parameter obtained through sample training, q is the query vector, and p is the n-dimensional probability vector used to indicate the selection of unvisited nodes and visited nodes .

[0100] Example 4 Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of an integrated circuit buffer insertion system disclosed in an embodiment of the present invention. As Figure 9 shown, the integrated circuit buffer insertion system may include: a memory 301 storing executable program code; a processor 302 coupled to the memory 301; The processor 302 calls the executable program code stored in the memory 301 and executes the steps in the integrated circuit buffer insertion method described in Embodiment 1 of the present invention.

[0101] Example 5 An embodiment of the present invention discloses a computer storage medium storing computer instructions that, when called, are used to execute the steps in the integrated circuit buffer insertion method described in Embodiment 1 of the present invention.

[0102] Example 6 An embodiment of the present invention discloses a computer program product including a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the steps in the integrated circuit buffer insertion method described in Embodiment 1.

[0103] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0104] Through the specific descriptions of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, and the storage medium includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc memories, magnetic disc memories, tape memories, or any other medium that can be used to carry or store data and is computer-readable.

[0105] Finally, it should be noted that: what is disclosed in an integrated circuit buffer insertion method, device, and storage medium according to an embodiment of the present invention is only a preferred embodiment of the present invention, and is only used to illustrate the technical solution of the present invention, rather than limiting it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated circuit buffer insertion method, characterized in that: The method comprises: Acquire raw data of all nodes in the target integrated circuit, wherein the nodes include clock sources and registers, and the raw data include position data and capacitance data; Based on the multi-head self-attention mechanism, the raw data of all the nodes are aggregated to generate the encoding representation corresponding to each node; According to the encoding representations corresponding to all the nodes, select unvisited nodes and visited nodes based on a pointer network, generate a connection function between the unvisited nodes and the visited nodes, and construct edges between the unvisited nodes and the visited nodes; For the edge between the unvisited node and the visited node, the peak value of the simple harmonic function corresponding to the edge is determined as the buffer candidate position, and a Steiner tree structure containing the buffer candidate position is constructed; According to the Steiner tree structure containing the buffer candidate positions, based on a dynamic programming algorithm, it is determined whether each buffer candidate position needs to be inserted into a buffer, and a target Steiner tree is generated. The target Steiner tree is used to indicate the insertion quantity and insertion position of the target integrated circuit buffer.

2. The integrated circuit buffer insertion method according to claim 1, characterized in that: The original data is 3-dimensional data, including an x-axis coordinate value, a y-axis coordinate value and a capacitance value; the coded representation is 128-dimensional data.

3. The integrated circuit buffer insertion method according to claim 1, characterized in that: The selecting unvisited nodes and visited nodes based on the pointer network according to the encoding representations corresponding to all the nodes, generating a connection function between the unvisited nodes and the visited nodes, and constructing edges between the unvisited nodes and the visited nodes, includes: Each time a node t is added as a visited node, the following steps are performed once: Selecting unvisited nodes based on pointer network and visited nodes , and generate unvisited nodes and visited nodes The connection function between , where the connection function Indicates that the node has not been visited and visited nodes The connection order between them; A sub-Steiner tree is formed according to all visited nodes, wherein the sub-Steiner tree corresponds to a topological information vector and a buffer position vector , the topology information vector The buffer position vector is used to represent the topology information of the sub-Steiner tree. used to indicate candidate locations for buffer insertion; Update the topology information vector to ,in is the parameter obtained through sample training, Represents the encoding of the newly constructed edges between unvisited nodes and visited nodes; Update the buffer position vector to ,in, It is the parameter obtained through sample training; in, Determined by the following formula: in is the parameter obtained through sample training, The nodes are and The encoding representation of .

4. The integrated circuit buffer insertion method according to claim 3, characterized in that: Each time a node t is added as a visited node, the following steps are performed once: The first query vector is calculated according to the following formula : Wherein, the first query vector Used to indicate the selection of unvisited nodes ; The second query vector is calculated according to the following formula : Wherein, the second query vector Used to indicate the selection of visited nodes ,in It is the parameter obtained through sample training.

5. The integrated circuit buffer insertion method according to claim 3, characterized in that: The step of determining, for an edge between an unvisited node and a visited node, a peak value of a simple harmonic function corresponding to the edge as a candidate buffer position includes: For the edge between an unvisited node and a visited node, the simple harmonic function corresponding to the edge is determined as: In the above formula, L is the length of the wire corresponding to the edge between the unvisited node and the visited node. and are the unit resistance and unit capacitance of the wire, and are the resistor and capacitor to be inserted into the buffer, is a simple harmonic function The phase of Determine the simple harmonic function The peak value is the candidate buffer position.

6. The integrated circuit buffer insertion method according to claim 5, characterized in that: The simple harmonic function Phase Determined by the following formula: In the above formula, h It is the parameter obtained through sample training.

7. The integrated circuit buffer insertion method according to claim 4, characterized in that: The pointer network is used to select unvisited nodes and visited nodes ,include: For all n visited nodes, based on the pointer network, an n-dimensional probability vector is determined ; Among them, PTM is a pointer network. is the encoding representation corresponding to the node, is the parameter obtained through sample training, q is the query vector, and n-dimensional probability vector Used to indicate the selection of unvisited nodes and visited nodes .

8. An integrated circuit buffer insertion device, characterized in that: The device comprises: An acquisition module, used to acquire raw data of all nodes in the target integrated circuit, wherein the nodes include clock sources and registers, and the raw data include position data and capacitance data; An encoder, for aggregating the raw data of all the nodes based on a multi-head self-attention mechanism, and generating a coded representation corresponding to each node; An edge selection network, for selecting unvisited nodes and visited nodes based on a pointer network according to the encoding representations corresponding to all the nodes, generating a connection function between the unvisited nodes and the visited nodes, and constructing edges between the unvisited nodes and the visited nodes; A buffer network is used to determine, for an edge between an unvisited node and a visited node, a peak value of a simple harmonic function corresponding to the edge as a buffer candidate position, and to construct a Steiner tree structure containing the buffer candidate positions; A post-processor is used to determine whether a buffer needs to be inserted into each buffer candidate position based on the Steiner tree structure containing the buffer candidate positions and a dynamic programming algorithm, and generate a target Steiner tree, wherein the target Steiner tree is used to indicate the insertion quantity and insertion position of the target integrated circuit buffer.

9. An integrated circuit buffer insertion system, characterized in that: The system includes: a memory storing executable program code; a processor coupled to the memory; the processor calls the executable program code stored in the memory to execute the integrated circuit buffer insertion method as described in any one of claims 1-7.

10. A computer storage medium, characterized in that: The computer storage medium stores computer instructions, which, when called, are used to execute the integrated circuit buffer insertion method as described in any one of claims 1-7.

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