Device layout generation method and device, computer equipment and storage medium

Abstract

The invention discloses a device layout layout generation method and device, computer equipment and a storage medium, and relates to the technical field of integrated circuits, and the method comprises the following steps: inputting layout parameters of an initial device layout layout into a performance prediction model to obtain performance indexes of the initial device layout layout, and utilizing simulation software to adjust the performance indexes of the initial device layout layout according to the performance indexes and a preset adjustment strategy; and falling down to adjust layout parameters of the initial device layout layout to obtain a target device layout layout. The design efficiency and quality of the quantum chip are remarkably improved, and cost reduction and efficiency improvement are achieved. The intelligent simulation and layout design process is carried out through the performance prediction model and the simulation software, so that the design error and the number of iterations are reduced, and the overall performance and the production efficiency of the chip are improved. The problems that the period of generating the device layout layout is long, and the generated device layout layout is difficult to meet all requirements are solved. The method has the effect of efficiently generating a target device layout which meets various strict requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a method, device, computer device and storage medium for generating a device layout layout. Background Technique

[0002] As a brand-new technical path, the design of quantum computing devices has begun to receive wide attention. The design process of quantum computing devices is more complex than that of traditional CMOS (Complementary Metal-Oxide-Semiconductor) devices, and there are more requirements for the device layout layout of quantum computing devices, such as: physical parameter target values, wiring space between devices, minimization of the overall layout area, and compliance with DRC (Design Rule Check) rules, etc. Currently, the design process of using EDA (Electronic Design Automation) tools to design a device layout layout that meets the above various requirements is complex, resulting in a long cycle for generating the device layout layout, and the generated device layout layout may not meet a certain requirement.

[0003] Therefore, the related technology has problems such as a long cycle for generating a device layout layout and the generated device layout layout is difficult to meet all requirements. Summary of the Invention

[0004] In view of this, the present invention provides a method, device, computer device and storage medium for generating a device layout layout to solve the problems of a long cycle for generating a device layout layout and the generated device layout layout is difficult to meet all requirements.

[0005] In a first aspect, the present invention provides a method for generating a device layout layout, the method comprising:

[0006] Obtain an initial device layout layout and layout parameters of the initial device layout layout;

[0007] Input the layout parameters into a performance prediction model to obtain performance indicators of the initial device layout layout;

[0008] Use simulation software to adjust the layout parameters of the initial device layout layout according to the performance indicators and a preset adjustment strategy until the performance indicators meet a first preset condition and the layout parameters meet a second preset condition to obtain a target device layout layout.

[0009] In a second aspect, the present invention provides a device for generating a device layout layout, the device comprising:

[0010] An obtaining module, configured to obtain an initial device layout layout and layout parameters of the initial device layout layout;

[0011] A performance determination module, configured to input layout parameters into a performance prediction model to obtain performance indicators of an initial device layout layout.

[0012] A layout adjustment module, configured to use simulation software to adjust the layout parameters of the initial device layout layout according to the performance indicators and a preset adjustment strategy until the performance indicators meet the first preset condition and the layout parameters meet the second preset condition, so as to obtain a target device layout layout.

[0013] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to execute the device layout layout generation method according to the first aspect or any corresponding embodiment thereof.

[0014] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the device layout layout generation method according to the first aspect or any corresponding embodiment thereof.

[0015] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the device layout layout generation method according to the first aspect or any corresponding embodiment thereof.

[0016] Through the present application, the layout parameters of the initial device layout layout are input into the performance prediction model to obtain the performance indicators of the initial device layout layout. Using simulation software, according to the performance indicators and a preset adjustment strategy, the layout parameters of the initial device layout layout are adjusted to obtain the target device layout layout. The design efficiency and quality of the quantum chip are significantly improved, and cost reduction and efficiency increase are achieved. Through the performance prediction model and simulation software for intelligent simulation and layout design processes, design errors and the number of iterations are reduced, thereby improving the overall performance and production efficiency of the chip. It solves the problems of long cycle for generating the device layout layout and the generated device layout layout being difficult to meet all requirements. It has the effect of efficiently generating a target device layout layout that meets multiple strict requirements. Description of the Drawings

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1It is a schematic flowchart of a device layout layout generation method according to an embodiment of the present invention;

[0019] Figure 2 It is a flowchart of a quantum device automated layout simulation design method according to an embodiment of the present invention;

[0020] Figure 3 It is a structural block diagram of a device layout layout generation device according to an embodiment of the present invention;

[0021] Figure 4 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0022] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] EDA tools are an indispensable part of modern integrated circuit design. Every step from simulation verification, logic synthesis to final placement and routing and layout generation depends on the accuracy and efficiency of EDA tools. Currently, EDA tools can achieve automated design at the system level, register transfer level (RTL), gate level, circuit level and even physical level, greatly improving the standardization and automation level of design. However, with the advancement of Moore's law, traditional silicon-based CMOS processes are gradually approaching their physical limits. Therefore, it is necessary to design quantum computing devices. The design process of quantum computing devices is more complex than traditional CMOS, requiring more feedback iterations and a longer development cycle. It is required that EDA tools not only continue to improve the automation and standardization levels, but also adapt to the design requirements of emerging technologies such as quantum computing to promote the continuous development of the integrated circuit design field.

[0024] Based on the above, the embodiments of the present invention provide a method for generating a device layout layout. First, historical simulation design data is collected and preprocessed, including data cleaning, feature extraction, and preprocessing. Subsequently, appropriate machine learning algorithms are used for model training to establish an accurate mapping between design parameters and performance. These data are used to train a machine learning model, such as a linear regression model, to predict the relationship between design parameters and performance. Then, based on the trained machine learning model, combined with physical constraints and real-time feedback from simulation tools, an iterative optimization algorithm is used to automatically adjust the device layout layout until a device layout layout of a quantum device that meets all requirements is generated. The artificial intelligence algorithm is fully utilized to deeply analyze the simulation results, and necessary modifications and optimizations are made to the graphics according to the analysis results. By applying AI (Artificial Intelligence) technology, the design efficiency and quality of quantum chips are significantly improved, achieving cost reduction and efficiency increase. Through the intelligent simulation and layout design process, design errors and the number of iterations are reduced, thereby improving the overall performance and production efficiency of the chip. It has the effect of automatically generating a high-quality device layout layout of a quantum chip under the conditions of meeting strict requirements such as the physical parameters of quantum devices, wiring space requirements, minimization of the overall layout area, and DRC rules.

[0025] According to an embodiment of the present invention, an embodiment of a device layout layout generation is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer device with data processing capabilities, such as a computer, a server, etc. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0026] In this embodiment, a method for generating a device layout layout is provided. Figure 1 It is a flowchart of the method for generating a device layout layout according to an embodiment of the present invention, as Figure 1 shown, and this process includes the following steps:

[0027] Step S101, obtain an initial device layout layout and layout parameters of the initial device layout layout.

[0028] Specifically, in the process of quantum device design, the primary concern is how to automatically generate a target device layout that meets a series of strict requirements. These requirements include, but are not limited to: ensuring that the physical parameters of the quantum device reach the preset target values, setting sufficient wiring space between devices to avoid potential interference and crossovers, optimizing the overall layout area to achieve the most efficient use of resources, and ensuring that the design complies with the Design Rule Check (DRC) standards. The above requirements can be divided into a first preset condition corresponding to performance indicators and a second preset condition corresponding to layout parameters. The second preset condition includes strict requirements such as wiring space requirements, minimization of the overall layout area, and DRC rules; the first preset condition includes that the deviation between the performance indicator and the target value is less than a preset value. For example, taking a simple 12Qbit planar tunable coupling superconducting quantum device as an example, the physical parameters of the device include, for instance, the expected capacitance value Cq of the superconducting qubit capacitor is 80.0fF and the acceptable capacitance error CE is ±3fF (achieved through a cross-capacitor structure), the coupler capacitance is 140fF, the coupling capacitance between qubits is 0.1fF, the coupling capacitance between the coupler and the qubit is 1fF, the cavity frequency value range of the 1 / 4 wavelength resonator is 6.7GHz - 7.2GHz, the impedance value of the wiring is 50Ω, etc. For example, the second preset condition: according to the line width and minimum line spacing of the transmission line and control line of the quantum chip, estimate and set the threshold range of the wiring space between devices. With a wiring impedance of 50Ω, the coplanar waveguide (CPW) control line adopts a "5 - 10 - 5" structure (center line width 5um, gap 10um). If there are 12 bit capacitors, 11 coupling capacitors, 1 transmission line, and 35 control lines in total, then the total wiring width space required between devices is 20um * 35 + control line spacing * 34 (the initial control line spacing is generally assumed to be 80um), and the wiring space between two devices is 20um * 3 + control line spacing * 2 + resonator width. Assume that the overall layout area is not greater than 12mm * 12mm, and minimize the redundant space as much as possible under the condition of meeting the layout. The preset DRC rules include special physical rule restrictions (such as presence or absence of filling, graphic closure, redundant line segments, graphic overlap, residual graphics, number of arc points, number of circular structures, etc.) and general DRC rule requirements (such as layout area, angle size, minimum center spacing, minimum size, area, etc.).

[0029] Randomly generate an initial device layout that meets the above requirements. For example: quickly generate a feasible solution that meets the DRC based on the greedy algorithm, and combine the layer-by-layer wiring algorithm and grid search algorithm for automatic wiring, etc., to generate the initial device layout. Obtain the layout parameters of the initial device layout. For example: graphic area, width, height, gap (energy gap) value, etc.

[0030] Step S102, input the layout parameters into the performance prediction model to obtain the performance indicators of the initial device layout.

[0031] Specifically, a model is created to predict the performance metrics of a quantum device based on layout parameters and trained. After training, the performance prediction model will be able to predict the corresponding performance metrics based on the input layout parameters.

[0032] Input the layout parameters into the performance prediction model to obtain the performance metrics of the initial device layout layout. The performance metrics are, for example: the dielectric constant of the metal material, the metal thickness, the capacitance value, etc.

[0033] Step S103, use simulation software to adjust the layout parameters of the initial device layout layout according to the performance metrics and the preset adjustment strategy until the performance metrics meet the first preset condition and the layout parameters meet the second preset condition, and obtain the target device layout layout.

[0034] Specifically, through the real-time simulation data feedback of the simulation software. Based on the trained performance prediction model. Continuously adjust the position and layout of the device through an iterative optimization algorithm, and use the real-time simulation data feedback of the simulation tool to evaluate the performance of the current layout.

[0035] The preset adjustment strategy is, for example: adjust the initial device layout layout according to the objective function. The objective function is, for example: Minimizeα×Area+β×Wiring_Cost+γ×∣Cq - 80.0∣, where Minimize means minimize; α, β, γ are weight coefficients, dynamically adjusted according to priority; Area represents the area of the quantum device, Wiring_Cost represents the line width of the quantum device, and Cq represents the capacitance value of the quantum device.

[0036] Call a simulation software (such as Sonnet) to perform device simulation and verify the performance metrics. If the deviation between the performance metrics in the simulation result and the target value exceeds the set threshold (such as Cq±3fF), then trigger the geometric adjustment of the layout in the simulation tool, and use the simulation software to adjust the layout parameters of the initial device layout layout according to the performance metrics and the above preset adjustment strategy until the performance metrics meet the first preset condition and the layout parameters meet the second preset condition, and obtain the target device layout layout.

[0037] In each iteration, the current design parameters will be input into the machine learning model for prediction, and the modification of the device design and the adjustment of the layout will be guided according to the prediction results and the limiting conditions. Call the simulation software (such as the ACT API of HFSS) through a Python script to achieve automatic parameter scanning and result extraction, and perform dynamic parameter adjustment. Finally, the target device layout layout that meets all requirements will be obtained.

[0038] It should be noted that the above layout generation process can be encapsulated and designed using PDK (Process Design Kit) components. This component integrates all the tools and functions required for superconducting quantum device design and provides unified standards and interfaces. By using this PDK component, designers can complete the design work more conveniently and efficiently, achieving seamless integration of the layout design software and the simulation software. This not only improves the calculation accuracy but also allows for direct graphic modification in the simulation environment, and finally exports a layout file that meets the GDSII standard, thus avoiding the cumbersome process of switching between different software.

[0039] The device layout generation method provided in this embodiment inputs the layout parameters of the initial device layout into a performance prediction model to obtain the performance indicators of the initial device layout. Then, according to the performance indicators and the preset adjustment strategy, the simulation software adjusts the layout parameters of the initial device layout to obtain the target device layout. This significantly improves the design efficiency and quality of the quantum chip, achieving cost reduction and efficiency improvement. Through the intelligent simulation and layout design process using the performance prediction model and the simulation software, the design errors and the number of iterations are reduced, thereby improving the overall performance and production efficiency of the chip. It solves the problems of the long cycle for generating the device layout and the difficulty of the generated device layout meeting all requirements, and has the effect of efficiently generating a target device layout that meets multiple strict requirements.

[0040] In some alternative embodiments, adjusting the layout parameters of the initial device layout according to the performance indicators and the preset adjustment strategy by using the simulation software includes:

[0041] Judging whether the performance indicators of the initial device layout meet the first preset condition, and determining the abnormal indicators according to the judgment result, where the abnormal indicators are the performance indicators that do not meet the first preset condition;

[0042] Using the simulation software to simulate the initial device layout to obtain the simulation result, and verifying the abnormal indicators according to the simulation result to obtain the verification result;

[0043] In the case that it is determined according to the verification result that the deviation between the abnormal indicator and the target value exceeds the first preset threshold, adjust the layout parameters of the initial device layout according to the preset adjustment strategy until the iteration cut-off condition is met, and then end to obtain the target device layout.

[0044] Specifically, the first preset condition includes: the deviation between the performance index and the target value is less than a preset value. For example, the target value of the capacitance is 85 fF, and the acceptable capacitance error is ±3 fF. Determine whether the performance index of the initial device layout layout meets the first preset condition, and determine the abnormal index according to the judgment result. For example, the capacitance value is 90 fF, exceeding the target value by 5 fF. Therefore, the capacitance value is an abnormal index.

[0045] Simulation software such as Sonnet or HFSS, call the simulation software through Python scripts, use the simulation software to simulate the initial device layout layout, realize automatic parameter scanning and result extraction, obtain the verification result, and perform dynamic parameter adjustment. The code for the above process is as follows:

[0046] import win32com.client / / Import the win32com.client module.

[0047] oDesktop = win32com.client.Dispatch("Ansoft.ElectronicsDesktop") / / Create a COM object through win32com.client.Dispatch and assign it to the variable oDesktop.

[0048] oProject = oDesktop.NewProject() / / Call the NewProject method of the oDesktop object to create a new engineering project. Automatically set geometric parameters and run the simulation.

[0049] Verify the abnormal index according to the simulation result to obtain the verification result. For example, the abnormal index is the capacitance value of 90 fF. Judge whether the value of the abnormal index is the same as the value in the simulation result. If the capacitance value in the simulation result is also 90 fF, then further judge whether the deviation between the abnormal index and the target value exceeds the first preset threshold. The first preset threshold is 3 fF, and the target value is 85 fF. It can be determined that the deviation between the abnormal index and the target value exceeds the first preset threshold.

[0050] When it is determined according to the verification result that the deviation between the abnormal index and the target value exceeds the first preset threshold, the layout parameters of the initial device layout layout are adjusted according to the preset adjustment strategy. For example: triggering a dynamic adjustment operation according to the preset adjustment strategy, reducing the arm length L of the cross capacitor (ΔL = -0.5μm), adjusting the adjacent device spacing, satisfying device coupling while avoiding electromagnetic coupling interference. Iteratively adjust the layout parameters, and in each iteration, the current design parameters will be input into the machine learning model for prediction, and the device design modification and layout adjustment will be guided according to the prediction result and the limiting conditions until the iterative cut-off condition is met, then it ends, and the target device layout layout is obtained.

[0051] In this embodiment, first determine whether the performance index is an abnormal index, and then use simulation software to verify the abnormal index to obtain a verification result. Adjust the layout parameters according to the verification result and the preset adjustment strategy until the iterative cut-off condition is met, and the target device layout layout that meets the requirements is obtained. Significantly improve the design efficiency and quality of quantum devices, and achieve cost reduction and efficiency increase.

[0052] In some optional embodiments, adjusting the layout parameters of the initial device layout layout according to the preset adjustment strategy until the iterative cut-off condition is met, then ending, and obtaining the target device layout layout includes:

[0053] Taking the initial device layout layout as the layout to be adjusted;

[0054] Adjusting the layout parameters of the layout to be adjusted through a preset optimization algorithm to obtain an intermediate device layout layout;

[0055] Determining the intermediate performance index of the intermediate device layout layout and judging whether there is an abnormal index in the intermediate performance index;

[0056] When there is no abnormal index in the intermediate performance index, determining the optimization ratio of the intermediate performance index to the performance index;

[0057] When the optimization ratio is less than the second preset threshold, determining the layout parameters of the intermediate device layout layout, taking the intermediate device layout layout as the layout to be adjusted, and executing the subsequent steps starting from adjusting the layout parameters of the layout to be adjusted through the preset optimization algorithm until the number of iterations reaches the third preset threshold, then ending, and obtaining the target device layout layout.

[0058] Specifically, taking the initial device layout layout as the layout to be adjusted. The preset optimization algorithms are, for example: gradient descent algorithm, algorithm for adjusting the capacitance spacing in the device, GA (genetic) algorithm, layer-by-layer routing algorithm for automatic routing, and grid search algorithm, etc.

[0059] Adjust the layout parameters of the layout to be adjusted through a preset optimization algorithm to obtain an intermediate device layout. For example: first, use the gradient descent algorithm to adjust the arm length and gap value in the layout parameters, then use the spacing adjustment algorithm to adjust the capacitance spacing in the device, and then use the genetic algorithm, the hierarchical routing algorithm for automatic routing, and the grid search algorithm to reassign the device positions to obtain the intermediate device layout.

[0060] Determine the intermediate performance indicators of the intermediate device layout and determine whether there are abnormal indicators among the intermediate performance indicators. The intermediate performance indicators are, for example: the dielectric constant of the metal material, the metal thickness, the capacitance value, etc. Determine whether there are abnormal indicators among the intermediate performance indicators, for example:

[0061] In the case where there are no abnormal indicators among the intermediate performance indicators, determine the optimization ratio of the intermediate performance indicators to the performance indicators. For example: the previous capacitance value was 90 fF, and the optimized capacitance value is 89.5 fF, and the optimization ratio is 0.56%.

[0062] The second preset threshold is, for example: 1%, and the third preset threshold is, for example: 3 times. In the case where the optimization ratio is less than the second preset threshold, determine the layout parameters of the intermediate device layout, use the intermediate device layout as the layout to be adjusted, and start executing the subsequent steps from adjusting the layout parameters of the layout to be adjusted through the preset optimization algorithm. Until the number of iterations reaches the third preset threshold, then end to obtain the target device layout. The iteration termination condition is that the optimization ratio is less than the second preset threshold during multiple iterations, and the iteration process is greater than or equal to the third preset threshold. For example: all parameters meet the constraints and the optimization amplitude is <1% for 3 consecutive iterations.

[0063] It should be noted that during the iteration process, directly modify the simulation graphics of the quantum device in the simulation software, and determine key parameters such as the accurate capacitance value through simulation. This way of directly modifying the graphics in the simulation environment not only improves the calculation accuracy, but also avoids the cumbersome process of switching between different software, improves efficiency, and avoids error accumulation caused by cross-software switching. Export the layout that meets the simulation results as a GDSII format file for subsequent processing.

[0064] In this embodiment, through the intelligent simulation and layout design process, the design errors and the number of iterations are reduced, thereby improving the overall performance and production efficiency of the chip.

[0065] In some alternative embodiments, adjusting the layout parameters of the layout to be adjusted through a preset optimization algorithm to obtain an intermediate device layout includes:

[0066] Determine the size parameters and position parameters of the layout to be adjusted according to the layout parameters of the layout to be adjusted;

[0067] Adjust the size parameters according to the first optimization algorithm to obtain the adjusted size parameters, where the first optimization algorithm is included in the preset optimization algorithm;

[0068] According to the second optimization algorithm, the adjusted size parameters, and the position parameters, obtain the adjusted position parameters, where the second optimization algorithm is included in the preset optimization algorithm;

[0069] According to the adjusted size parameters, the adjusted position parameters, and the layout generation algorithm, generate the intermediate device layout layout, where the layout generation algorithm is included in the preset optimization algorithm.

[0070] Specifically, determine the size parameters and position parameters of the layout to be adjusted according to the layout parameters of the layout to be adjusted. The size parameters are, for example, the arm length (L) of the cross capacitor, the gap distance (S), etc., and the position parameters are, for example, the distance between capacitors.

[0071] The first optimization algorithm is, for example, an optimization algorithm based on the gradient descent method. Adjust the size parameters according to the first optimization algorithm to obtain the adjusted size parameters. Optimize the arm length (L) and gap distance (S) of the cross capacitor by the gradient descent method to make Cq = f(L, S) Cq approach the target value.

[0072] The second optimization algorithm is, for example, an algorithm for adjusting the capacitance distance in the device. Determine the distance between the electronic components in the quantum device according to the adjusted size parameters and position parameters. For example, through the coupling simulation of capacitor and capacitor, optimize the distance between capacitors. If the coupling capacitance between bits is less than 0.1 fF, reduce the distance between bit capacitors without violating DRC to obtain the adjusted position parameters. At the same time, adjust the capacitor shape. If the distance is already the minimum and the minimum coupling capacitance value cannot be satisfied by adjusting the distance, only adjust the capacitor shape to make the coupling capacitance area larger. And other layout adjustments.

[0073] The layout generation algorithm is, for example, a genetic algorithm, a stacked routing algorithm for automatic routing, and a grid search algorithm. According to the adjusted size parameters, the adjusted position parameters, and based on the genetic algorithm, combined with the stacked routing algorithm for automatic routing and the grid search algorithm, etc., reallocate the device positions to reduce wiring crossovers and area, and generate the intermediate device layout layout.

[0074] In some alternative embodiments, adjusting the size parameters according to the first optimization algorithm to obtain the adjusted size parameters includes:

[0075] Determine the gradient of the performance index with respect to the size parameters through the first optimization algorithm;

[0076] Take the product of the gradient and the preset coefficient as the change amount of the size parameters;

[0077] Adjust the dimensional parameters according to the comparison result between the performance index and the target value, as well as the change amount, to obtain the adjusted dimensional parameters.

[0078] Specifically, the first optimization algorithm is, for example, an optimization algorithm based on the gradient descent method. Taking the performance index as Cq and the dimensional parameters as the arm length (L) and the gap spacing (S) as an example for illustration.

[0079] The process of adjusting the dimensional parameters according to the first optimization algorithm is, for example, calculating the gradient of the performance index with respect to the dimensional parameters by the finite difference method, such as and is the gradient of the capacitance with respect to the arm length, is the gradient of the capacitance with respect to the gap spacing. Additionally, if the gradient cannot be calculated, the gradient can be approximated by numerical methods.

[0080] Adjust L and S according to the gradient descent formula. The gradient descent formula is, for example:

[0081]

[0082] where k is a preset coefficient, related to the electric field distribution and the geometric structure; ε r is the dielectric constant, A cross is the effective overlapping area of the capacitance, and d is the device spacing.

[0083] Take the product of the gradient and the preset coefficient as the change amount of the dimensional parameter. Adjust the dimensional parameters according to the comparison result between the performance index and the target value, as well as the change amount, to obtain the adjusted dimensional parameters. For example, the longer the arm length, the larger the capacitance value of the device. If the performance index is greater than the target value, it is necessary to reduce the performance index. Therefore, it is necessary to reduce the arm length and reduce the dimensional parameter by this change amount.

[0084] In this embodiment, by the first optimization algorithm, adjust the dimensional parameters to facilitate the subsequent generation of a device layout pattern that meets a series of strict requirements.

[0085] In some alternative embodiments, adjust the layout parameters of the initial device layout pattern according to a preset adjustment strategy, including:

[0086] Input the simulation result into the first analysis model to obtain the fault information of the initial device layout pattern;

[0087] Input the simulation result into the second analysis model to obtain the geometric adjustment strategy for the fault information;

[0088] Adjust the layout parameters of the initial device layout pattern according to the fault information, the geometric adjustment strategy, and the preset adjustment strategy.

[0089] Specifically, by using artificial intelligence algorithms to analyze the simulation results, potential problems and areas for improvement can be identified. According to the analysis results, we can modify the design of the graphics to optimize the chip performance. These modification operations may include adjusting the device position, modifying the device shape, etc. The first analysis model and the second analysis model are constructed based on artificial intelligence algorithms.

[0090] The first analysis model, for example: a model based on density-based spatial clustering of applications with noise (DBSCAN) for identifying potential short-circuit risks in densely routed areas of the layout; a model based on convolutional neural network (CNN) for detecting design rule check (DRC) violations in the graphics (such as insufficient line width, too small spacing). The second analysis model, for example: a model based on Bayesian optimization for proposing geometric adjustment suggestions for key parameters (such as resonant frequency).

[0091] The process of the model based on density-based spatial clustering of applications with noise for identifying short-circuit risks in the layout, for example: extracting the geometric coordinate data in the layout; calculating the number of wire network intersection points per unit area of each metal layer according to the geometric coordinate data; marking the clustering regions with density exceeding the threshold (such as >5 lines / μm 2 ) to generate a heat map and mark the coordinates of potential short-circuit risks. The process of the model based on convolutional neural network for detecting DRC violations in the graphics, for example: the input layer of the model slices the layout of 1024x1024 pixels (each pixel corresponds to 5nm); the encoder uses 5-level convolution (kernel = 3×3, stride = 2) to extract local features; the decoder uses transposed convolution + skip connection to restore the spatial resolution; the output layer performs multi-channel semantic segmentation (channel 1: line width violation, channel 2: spacing violation) to determine the violation situation.

[0092] According to the above content, input the simulation results into the first analysis model to obtain the fault information of the initial device layout layout, and input the simulation results into the second analysis model to obtain the geometric adjustment strategy for the fault information.

[0093] According to the fault information, geometric adjustment strategy and preset adjustment strategy, adjust the layout parameters of the initial device layout layout, which can shorten the traditional design cycle by 40% and improve the optimization efficiency of key parameters by more than 3 times.

[0094] In this embodiment, the first analysis model and the second analysis model are used to deeply analyze the simulation results, identify problems and areas for improvement, and modify the graphic design according to the analysis results to optimize the performance of the quantum chip.

[0095] In some alternative embodiments, before inputting the layout parameters into the performance prediction model, the method further includes:

[0096] Obtaining historical layout parameters and historical performance indicators corresponding to the historical layout parameters;

[0097] Preprocess the historical layout parameters and historical performance indicators, and generate training samples based on the preprocessed historical layout parameters and preprocessed historical performance indicators;

[0098] Create an initial prediction model according to a preset algorithm;

[0099] Use the training samples and a preset training algorithm to adjust the initial prediction model to obtain a performance prediction model.

[0100] Specifically, in order to train a machine learning model that can accurately predict design performance, it is first necessary to collect and preprocess historical layout design data and simulation design data. These data may include various design parameters such as graphic area, width, height, gap value, etc., which can be represented in the form of an array (e.g., X = np.array([[1],[2],[3],[4],[5]])) and simulation setting data and corresponding performance indicators such as metal material dielectric constant, metal thickness, capacitance value, etc., which are also collected and processed in the form of an array (e.g., Y = np.array([2,4,6,8,10])). The above data are historical layout parameters, and the data sources of historical layout parameters include: the device geometry database of existing projects, and key parameters can also be extracted through the graphic geometric features of other layouts. For the cross-capacitor structure, extract key parameters: for the cross-capacitor structure, extract key parameters: inner region metal cross width (Wmetal), cross height (Hmetal), gap spacing (Wgap), etc. Automatically extract parameters through an image processing algorithm (such as OpenCV contour detection). The parameters also include material and process parameters such as superconducting material dielectric constant (εr), metal layer thickness (t), substrate loss tangent (tanδ), etc.

[0101] In the data preprocessing stage, preprocess the historical layout parameters and historical performance indicators, including: performing operations such as data cleaning, feature extraction, and normalization to ensure the quality and consistency of the data.

[0102] Based on the preprocessed historical layout parameters and preprocessed historical performance indicators, generate training samples. For example: the storage data format of the training samples is o = np.array([[W_metal1, H_metal1, W_gap1], / / sample 1, [[W_metal2, H_metal2, W_gap2]) / / sample 2, Y = np.array([C_q1, C_q2]) / / corresponding capacitance values.

[0103] Create an initial prediction model according to a preset algorithm. For example: create a machine learning model as the initial prediction model. The models that can be selected when creating a machine learning model include: a basic model, Linear Regression for quickly verifying the linear relationship of data; advanced models, Random Forest, used to handle non-linear relationships and high-dimensional features; XGBoost, used to optimize prediction accuracy and training speed; Convolutional Neural Network (CNN), for end-to-end prediction of layout image data (such as GDSII converted to a bitmap).

[0104] Use the training samples and a preset training algorithm to adjust the initial prediction model to obtain a performance prediction model. For example: after preparing the training data, by calling relevant libraries in Python (such as scikit-learn), a model can be created and trained. Use the LinearRegression() class to create a linear regression model and use the fit() method to train the model. After training, the model will be able to predict the corresponding performance metrics based on the input design parameters. That is, for the data sorted out just now, it is simply shown as an ML training model such as model = LinearRegression() model.fit(X, Y).

[0105] In addition, encapsulate the ID of the above-trained machine learning model into an API interface and name this model the AutoLayout model. For example: encapsulate the trained model into a RESTful API (such as the Flask framework), name it AutoLayout, with the input being design parameters in JSON format and the output being the predicted performance metrics. Some code is as follows:

[0106]

[0107] In this embodiment, obtain historical layout parameters and historical performance metrics, preprocess the data to ensure data quality and consistency, and provide a basis for machine learning model training. Based on the preprocessed historical layout parameters and preprocessed historical performance metrics, generate training samples, train the initial prediction model, and obtain a performance prediction model. Guide the layout adjustment through the performance prediction model to generate a quantum device layout diagram that meets all requirements.

[0108] In some alternative embodiments, the performance metric can be the Hamiltonian parameter of the quantum device. The specific process of adjusting the initial device layout layout to obtain the target device layout layout according to the Hamiltonian parameter can include steps A1 to A4.

[0109] Step A1, determine the target Hamiltonian parameter of the quantum device.

[0110] Step A2: Determine the initial device layout layout of the quantum device and the layout parameters of the initial device layout layout.

[0111] Step A3: Determine the target gradient of the Hamiltonian parameters of the quantum device with respect to the geometric parameters of the initial device layout layout.

[0112] Specifically, the Hamiltonian parameters of the quantum device can be predicted according to the layout parameters of the initial device layout layout and the performance prediction model. The initial device layout layout of the quantum device is meshed to obtain the mesh boundary of the initial device layout layout; determine the first gradient of the mesh boundary with respect to the geometric parameters of the initial device layout layout; determine the second gradient of the Hamiltonian parameters of the quantum device with respect to the mesh boundary; based on the first gradient and the second gradient, determine the target gradient of the Hamiltonian parameters of the quantum device with respect to the geometric parameters of the initial device layout layout. After meshing the initial device layout layout of the quantum device, the mesh boundary of the initial device layout layout will be obtained. The change of the mesh boundary will cause the change of the matrix elements of the solution system. Among them, the matrix element is the electromagnetic interaction between the i-th mesh and the j-th mesh, and the change of the matrix element will cause the change of the unknowns to be solved. For example, the number of meshes divided, and the influence of the unknowns to be solved on the change of the Hamiltonian is the gradient.

[0113] Step A4: Based on the target gradient, adjust the layout parameters of the initial device layout layout so that the Hamiltonian parameters of the quantum device are the target Hamiltonian parameters, and obtain the target device layout layout.

[0114] Specifically, by using the method of determining the target gradient of the Hamiltonian parameters of the quantum device with respect to the geometric parameters of the initial device layout layout, since the target gradient reflects the change law of the Hamiltonian parameters of the quantum device with respect to the geometric parameters, therefore, based on this change law, the layout parameters of the quantum device can be adjusted to obtain the target device layout layout corresponding to the target Hamiltonian parameters. Compared with the related technology, by using the electromagnetic simulation method, every time a part of the layout parameters is changed, the entire layout needs to be subjected to an electromagnetic simulation to calculate the Hamiltonian parameters of the quantum model corresponding to the layout, and then the geometric parameters of the layout are adjusted according to the change of the Hamiltonian parameters, and the iteration is repeated until the layout design meets the requirements. By using the method based on the target gradient to determine the change direction of the Hamiltonian parameters with respect to the layout parameters, the ineffective adjustment is effectively avoided, making the adjustment of the geometric parameters effective, greatly improving the technical effect of the optimization efficiency of the device layout layout, and thus solving the technical problems of complex operation and low efficiency when adjusting the device layout layout parameters.

[0115] It should be noted that the geometric parameters in the embodiments of the present invention can be used to describe the device layout layout and the quantum devices in the device layout layout. For example, the geometric parameters can also be the length and width used to describe a rectangular shape, the radius and the center position used to describe a circular shape, etc.

[0116] In this embodiment, after adjusting the target device layout layout to the target geometric parameters, the quantum devices corresponding to the target device layout layout can also reach the target Hamiltonian parameters, thereby realizing the target gradient of the geometric parameters of the initial device layout layout based on the Hamiltonian parameters of the quantum devices, directly adjusting the layout parameters, and improving the technical effect of the device layout layout optimization efficiency. Furthermore, the technical problem of complex operation and low efficiency when adjusting the device layout layout parameters is solved.

[0117] In some alternative embodiments, a method for automated layout simulation design of quantum devices is provided. This method can solve the same technical problems as those in steps S101 to S103. As Figure 2 shown, this method includes:

[0118] The development process of automatic layout and simulation; parameter setting and constraint conditions; automatic generation of the initial layout; iterative optimization of the simulation layout; encapsulation of the trained model; data preprocessing, data collection and data normalization, etc.; training; model encapsulation; generation of the layout diagram based on the encapsulated ML model; multi-objective optimization; dynamic parameter adjustment; AI-assisted analysis; graphic optimization; directly modifying the graphics in the simulation environment; generating the final layout; exporting the GDSII file, and ending.

[0119] In this embodiment, the automated layout of quantum devices significantly improves the design efficiency and quality of quantum chips by applying AI technology, achieving cost reduction and efficiency improvement. Through the intelligent simulation and layout design process, design errors and the number of iterations are reduced, thereby improving the overall performance and production efficiency of the chips. In order to strengthen the design standardization and regularization of quantum design tools, the PDK packaging technology is adopted. The PDK packaging not only provides a unified interface and standard for quantum chip design, but also simplifies the design process, enables different design teams to collaborate more efficiently, and reduces the design difficulty and cost.

[0120] In this embodiment, a device layout layout generation device is also provided. This device is used to implement the above embodiments and preferred embodiments, and those that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0121] This embodiment provides a device layout layout generation device, as Figure 3As shown in the figure, it includes:

[0122] An acquisition module 301, configured to acquire an initial device layout layout and layout parameters of the initial device layout layout;

[0123] A performance determination module 302, configured to input the layout parameters into a performance prediction model to obtain performance indicators of the initial device layout layout;

[0124] A layout adjustment module 303, configured to use simulation software to adjust the layout parameters of the initial device layout layout according to the performance indicators and a preset adjustment strategy until the performance indicators meet the first preset condition and the layout parameters meet the second preset condition, so as to obtain a target device layout layout.

[0125] In some alternative embodiments, the layout adjustment module 303 includes:

[0126] A judgment unit, configured to judge whether the performance indicators of the initial device layout layout meet the first preset condition, and determine an abnormal indicator according to the judgment result, where the abnormal indicator is a performance indicator that does not meet the first preset condition;

[0127] A simulation unit, configured to use simulation software to simulate the initial device layout layout to obtain a simulation result, and verify the abnormal indicator according to the simulation result to obtain a verification result;

[0128] An adjustment unit, configured to, in the case that it is determined according to the verification result that the deviation between the abnormal indicator and the target value exceeds the first preset threshold, adjust the layout parameters of the initial device layout layout according to the preset adjustment strategy until the iteration cutoff condition is met, then end, so as to obtain a target device layout layout.

[0129] In some alternative embodiments, the adjustment unit includes:

[0130] A setting sub-module, configured to use the initial device layout layout as the layout to be adjusted;

[0131] A first adjustment sub-module, configured to adjust the layout parameters of the layout to be adjusted through a preset optimization algorithm to obtain an intermediate device layout layout;

[0132] A judgment sub-module, configured to determine intermediate performance indicators of the intermediate device layout layout and judge whether there are abnormal indicators among the intermediate performance indicators;

[0133] A determination sub-module, configured to determine an optimization ratio between the intermediate performance indicators and the performance indicators in the case that there are no abnormal indicators among the intermediate performance indicators;

[0134] A second adjustment sub-module, configured to determine layout parameters of an intermediate device layout layout when the optimization ratio is less than a second preset threshold, use the intermediate device layout layout as the layout to be adjusted, and start to execute subsequent steps from adjusting the layout parameters of the layout to be adjusted through a preset optimization algorithm until the number of iterations reaches a third preset threshold, and then end to obtain a target device layout layout.

[0135] In some alternative embodiments, the adjustment sub-module includes:

[0136] A determination subunit, configured to determine size parameters and position parameters of the layout to be adjusted according to the layout parameters of the layout to be adjusted;

[0137] A first adjustment subunit, configured to adjust the size parameters according to a first optimization algorithm to obtain adjusted size parameters, where the first optimization algorithm is included in the preset optimization algorithm;

[0138] A second adjustment subunit, configured to obtain adjusted position parameters according to a second optimization algorithm, the adjusted size parameters, and the position parameters, where the second optimization algorithm is included in the preset optimization algorithm;

[0139] A generation subunit, configured to generate an intermediate device layout layout according to the adjusted size parameters, the adjusted position parameters, and a layout generation algorithm, where the layout generation algorithm is included in the preset optimization algorithm.

[0140] In some alternative embodiments, the first adjustment subunit adjusts the size parameters according to the first optimization algorithm to obtain adjusted size parameters, including:

[0141] Determine the gradient of the performance index with respect to the size parameters through the first optimization algorithm;

[0142] Use the product of the gradient and a preset coefficient as the change amount of the size parameters;

[0143] Adjust the size parameters according to the comparison result between the performance index and the target value, and the change amount to obtain adjusted size parameters.

[0144] In some alternative embodiments, the adjustment unit includes:

[0145] A first input sub-module, configured to input the simulation result into a first analysis model to obtain fault information of the initial device layout layout;

[0146] A second input sub-module, configured to input the simulation result into a second analysis model to obtain a geometric adjustment strategy for the fault information;

[0147] An adjustment sub-module, configured to adjust the layout parameters of the initial device layout layout according to the fault information, the geometric adjustment strategy, and a preset adjustment strategy.

[0148] In some alternative embodiments, the apparatus further includes:

[0149] a parameter acquisition module, configured to acquire historical layout parameters and historical performance metrics corresponding to the historical layout parameters;

[0150] a preprocessing module, configured to preprocess the historical layout parameters and the historical performance metrics, and generate training samples based on the preprocessed historical layout parameters and the preprocessed historical performance metrics;

[0151] a creation module, configured to create an initial prediction model according to a preset algorithm;

[0152] a training module, configured to adjust the initial prediction model by using the training samples and a preset training algorithm to obtain a performance prediction model.

[0153] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding foregoing embodiments, and will not be elaborated herein.

[0154] The device layout layout generation device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0155] The embodiment of the present invention further provides a computer device having the above-mentioned Figure 3 shown device layout layout generation device.

[0156] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a computer device provided by an alternative embodiment of the present invention. As shown in Figure 4 , the computer device includes: one or more processors 10, a memory 20, and an interface for connecting each component, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 4 In

[0157] The processor 10 may be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 may further include a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device may be a complex programmable logic device, a field-programmable gate array, a generic array logic, or any combination thereof.

[0158] Among them, the memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiments.

[0159] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely set relative to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0160] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 may also include a combination of the above types of memories.

[0161] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

[0162] Embodiments of the present invention also provide a computer-readable storage medium. The method according to the embodiments of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0163] A part of the present invention can be applied as a computer program product, for example, computer program instructions, which when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should be able to understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0164] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A device layout generation method, characterized in that: The method comprises: Acquire an initial device layout diagram and layout parameters of the initial device layout diagram; Inputting the layout parameters into a performance prediction model to obtain performance indicators of the initial device layout; The layout parameters of the initial device layout are adjusted according to the performance index and the preset adjustment strategy by using simulation software until the performance index meets the first preset condition and the layout parameters meet the second preset condition, thereby obtaining the target device layout.

2. The method according to claim 1, characterized in that The using simulation software to adjust the layout parameters of the initial device layout according to the performance index and the preset adjustment strategy includes: Determine whether the performance index of the initial device layout meets the first preset condition, and determine an abnormal index according to the determination result, wherein the abnormal index is a performance index that does not meet the first preset condition; Using the simulation software to simulate the initial device layout to obtain a simulation result, and verifying the abnormal indicator according to the simulation result to obtain a verification result; When it is determined according to the verification result that the deviation between the abnormal indicator and the target value exceeds a first preset threshold value, the layout parameters of the initial device layout are adjusted according to a preset adjustment strategy until an iteration cutoff condition is met, and then the process ends to obtain the target device layout.

3. The method according to claim 2, characterized in that The step of adjusting the layout parameters of the initial device layout according to a preset adjustment strategy until an iteration cutoff condition is satisfied, and then terminating to obtain the target device layout, includes: Using the initial device layout as the layout to be adjusted; Adjust the layout parameters of the to-be-adjusted layout by using a preset optimization algorithm to obtain an intermediate device layout; Determining an intermediate performance indicator of the intermediate device layout, and judging whether the abnormal indicator exists in the intermediate performance indicator; In the case where the abnormal indicator does not exist in the intermediate performance indicator, determining an optimization ratio of the intermediate performance indicator to the performance indicator; When the optimization ratio is less than the second preset threshold, the layout parameters of the intermediate device layout are determined, and the intermediate device layout is used as the layout to be adjusted. Subsequent steps are performed starting from adjusting the layout parameters of the layout to be adjusted by using a preset optimization algorithm, until the number of iterations reaches a third preset threshold, then the process ends to obtain the target device layout.

4. The method according to claim 3, characterized in that The step of adjusting the layout parameters of the to-be-adjusted layout by a preset optimization algorithm to obtain an intermediate device layout includes: Determine the size parameter and position parameter of the layout to be adjusted according to the layout parameter of the layout to be adjusted; Adjust the size parameter according to a first optimization algorithm to obtain an adjusted size parameter, wherein the first optimization algorithm is included in the preset optimization algorithm; Obtaining adjusted position parameters according to a second optimization algorithm, the adjusted size parameters, and the position parameters, wherein the second optimization algorithm is included in the preset optimization algorithm; The intermediate device layout layout is generated according to the adjusted size parameters, the adjusted position parameters and a layout generation algorithm, wherein the layout generation algorithm is included in the preset optimization algorithm.

5. The method according to claim 4, characterized in that The step of adjusting the size parameter according to the first optimization algorithm to obtain the adjusted size parameter includes: Determining, by means of the first optimization algorithm, a gradient of the performance indicator relative to the size parameter; Taking the product of the gradient and the preset coefficient as the variation of the size parameter; The size parameter is adjusted according to the comparison result between the performance indicator and the target value and the change amount to obtain the adjusted size parameter.

6. The method according to claim 2, characterized in that The step of adjusting the layout parameters of the initial device layout according to a preset adjustment strategy includes: Inputting the simulation result into a first analysis model to obtain fault information of the initial device layout; Inputting the simulation result into a second analysis model to obtain a geometric adjustment strategy for the fault information; The layout parameters of the initial device layout are adjusted according to the fault information, the geometric adjustment strategy and the preset adjustment strategy.

7. The method according to claim 1, characterized in that Before inputting the layout parameters into the performance prediction model, the method further includes: Obtaining historical layout parameters and historical performance indicators corresponding to the historical layout parameters; Preprocessing the historical layout parameters and the historical performance indicators, and generating training samples based on the preprocessed historical layout parameters and the preprocessed historical performance indicators; Create an initial prediction model based on a preset algorithm; The initial prediction model is adjusted using the training samples and a preset training algorithm to obtain the performance prediction model.

8. A device layout generation device, characterized in that: The device comprises: An acquisition module, used to acquire an initial device layout diagram and layout parameters of the initial device layout diagram; A performance determination module, used for inputting the layout parameters into a performance prediction model to obtain performance indicators of the initial device layout; The layout adjustment module is used to use simulation software to adjust the layout parameters of the initial device layout according to the performance index and the preset adjustment strategy, until the performance index meets the first preset condition and the layout parameters meet the second preset condition, so as to obtain the target device layout.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the device layout generation method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the device layout generation method according to any one of claims 1 to 7.

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