Wiring method and system, equipment, storage medium and chip
By cross-connecting storage media and control nodes in a redundant architecture, combining long-distance lines and dynamically configuring physical addresses, the problems of complex design and low scalability of redundant architecture are solved, and more efficient resource utilization and system performance are achieved.
Patent Information
- Application Number
- CN202510200753.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-06-27
AI Technical Summary
The existing redundant architecture is complex in design and low scalability, resulting in low resource utilization, high system complexity and high maintenance difficulties, making it difficult to adapt to dynamically changing load requirements.
By cross-connecting the storage medium with at least two control nodes, the dual ports of the storage medium are connected to different processor ports of different control nodes respectively, the long-distance line is merged using a retimer, and the physical address of the control node line is dynamically configured to keep the physical address consistent.
Under the premise that the physical address is consistent, the routing layout is optimized, the redundant architecture is reduced, and the working efficiency of the entire machine is improved, which solves the problem of too many retimers.
Smart Images
Figure CN120218000A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of PCB trace topology, and relates to a trace method, in particular to a trace method, system, device, storage medium, and chip. Background Art
[0002] In modern data storage and computing systems, redundant architecture design is a key means to ensure high availability and fault tolerance. By deploying multiple independent control nodes or processing units, the system can maintain continuous operation in the event of a single component failure, thus meeting the stringent requirements of enterprise-level applications for stability and reliability. However, while traditional redundant architectures achieve fault tolerance, they are often accompanied by a series of systemic defects that severely limit the improvement of overall performance and resource efficiency. First, existing redundant solutions generally suffer from low resource utilization. To ensure seamless switching between nodes, hardware designs typically adopt symmetric layouts and equalized configurations, resulting in redundant components that cannot be flexibly allocated according to actual needs. Second, the system complexity and maintenance difficulty of redundant architectures increase significantly. Physical connections between multiple nodes usually rely on complex trace topologies to ensure signal synchronization and data consistency. Finally, traditional redundant solutions have obvious shortcomings in terms of scalability and adaptability. With the explosion of data volume and the increase in storage medium density, the system needs to support more device accesses and higher-speed data exchanges, but the rigid design of existing architectures is difficult to adapt to dynamically changing load requirements.
[0003] Therefore, existing redundant architectures sacrifice efficiency, cost, and scalability in the pursuit of reliability, and there is an urgent need for a new design paradigm to provide technical support for the next generation of high-performance storage and computing systems. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of this application is to provide a trace method, system, device, storage medium, and chip, which are used to solve the problems of complex redundant architecture design and low scalability in the prior art.
[0005] In a first aspect, this application provides a trace method. The trace method includes: cross-connecting a storage medium with at least two control nodes so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes; using a retimer to merge long-distance lines between the control nodes and the storage medium; and dynamically configuring the physical addresses corresponding to each line of the control nodes so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0006] In this application, the storage medium is cross-connected with the control nodes, so that the two ports of the storage medium are respectively connected to different processor ports of different control nodes. The retimer is used to merge the long-distance lines, and dynamic configuration is used to keep the physical addresses corresponding to the control node lines consistent. This wiring method can solve the number of retimers on the premise of consistent physical addresses, optimize the wiring layout, reduce the redundant architecture, and improve the working efficiency of the whole machine.
[0007] In one implementation of the first aspect, the control nodes include a first control node and a second control node, and the processor includes a first port and a second port. The implementation of cross-connecting the storage medium with the control nodes so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes includes: the first port of any one of the storage media is connected to the first port of the processor of the first control node, and the end port of the storage medium is connected to the first port of the processor of the second control node; the first port of the storage medium is connected to the second port of the processor of the second control node, and the end port of the storage medium is connected to the second port of the processor of the first control node.
[0008] In one implementation of the first aspect, dynamically configuring the physical addresses corresponding to the lines of each control node so that the physical addresses are consistent when the storage medium is connected to different control nodes includes: using a hardware detection module to identify the physical location of the control node by using a level signal; dynamically configuring the physical addresses corresponding to the lines according to the physical location of the control node so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0009] In one implementation of the first aspect, using a hardware detection module to identify the physical location of the control node by using a level signal includes: connecting a first resistor to the power supply to generate a high-level signal, and connecting a second resistor to the ground to generate a low-level signal; respectively configuring the high-level signal and the low-level signal to different control nodes to identify the physical location of the control node.
[0010] In an implementation of the first aspect, the control node includes a first control node and a second control node. Using the hardware detection module to identify the physical location of the control node by means of a level signal includes: when the hardware detection module identifies the first control node by the level signal, the first port of the first control node processor is configured to be connected to the first port of the storage medium, and the second port of the first control node processor is configured to be connected to the last port of the storage medium; when the hardware detection module identifies the second control node by the level signal, the first port of the second control node processor is configured to be connected to the last port of the storage medium, and the second port of the second control node processor is configured to be connected to the first port of the storage medium.
[0011] In an implementation of the first aspect, the retimer is configured for a long-distance line exceeding a preset threshold.
[0012] In a second aspect, the present application provides a wiring system. The wiring system includes: a line layout module for cross-connecting a storage medium with at least two control nodes so that the two ports of the storage medium correspond to different processor ports of different control nodes respectively; a line merging module for merging and processing the long-distance lines between the control nodes and the storage medium by using a retimer; and an address mapping module for dynamically configuring the physical addresses corresponding to the respective lines of the control nodes so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0013] In a third aspect, the present application provides a chip. The chip includes: a backplane configured to provide a physical connection interface; at least two control nodes configured to execute the wiring method according to any one of the first aspect; and a plurality of dual-port storage media configured to be cross-connected to the control nodes through the backplane, and the two ports of each storage medium are respectively connected to different control nodes.
[0014] In a fourth aspect, the present application provides an electronic device. The electronic device includes: a memory for storing a programmable logic program; a programmable logic device for loading the programmable logic program stored in the memory so that the electronic device executes the wiring method according to any one of the first aspect.
[0015] In a fifth aspect, the present application provides a readable storage medium. A programmable logic program is stored thereon, and when the program is executed by a programmable logic device, the wiring method according to any one of the first aspect is implemented. Description of the Drawings
[0016] Figure 1Shown is a schematic diagram of an application scenario of the routing method described in this application.
[0017] Figure 2 Shown is a schematic diagram of the process of the routing method described in an embodiment of this application.
[0018] Figure 3 Shown is a schematic diagram of the routing method described in an embodiment of this application.
[0019] Figure 4 Shown is a schematic diagram of the process of the routing method described in an embodiment of this application.
[0020] Figure 5 Shown is a schematic diagram of the routing method described in an embodiment of this application.
[0021] Figure 6 Shown is a schematic diagram of the structure of the routing system described in an embodiment of this application.
[0022] Figure 7 Shown is a schematic diagram of the structure of the chip described in an embodiment of this application.
[0023] Figure 8 Shown is a schematic diagram of the structure of the electronic device described in an embodiment of this application.
[0024] Description of Component Labels
[0025] 1 Printed Circuit Board
[0026] 11 Node
[0027] 12 Circuit Backplane
[0028] 13 NVMe Disk
[0029] 100 Routing System
[0030] 110 Circuit Layout Module
[0031] 120 Circuit Merging Module
[0032] 130 Address Mapping Module
[0033] 200 Chip
[0034] 210 Backplane
[0035] 220 Control Node
[0036] 230 Dual-Port Storage Medium
[0037] 800 Electronic Device
[0038] 810 Memory
[0039] 820 Programmable Logic Device
[0040] Steps S11 to S13
[0041] Steps S131 to S132 Detailed implementation manners
[0042] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0043] It should be noted that in the embodiments of the present application, words such as "optionally" or "for example" represent examples, illustrations or explanations. Any embodiment or design solution described as "optionally" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "optionally" or "for example" is intended to present relevant concepts in a specific manner.
[0044] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (piece) of the following" or its similar expression refers to any combination of these items, including any combination of single item (piece) or plural items (pieces). For example, at least one (piece) of a, b or c can represent: a, b, c, a - b, a - c, b - c or a - b - c, where a, b, c can be single or multiple.
[0045] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, quantities and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0046] In the traditional storage server architecture, in order to meet the high availability requirements, a redundant control node design is usually adopted, and redundant fault tolerance is achieved through dual independent hardware. However, in order to achieve the interchangeability of control nodes in the traditional solution, a symmetric routing topology is forced, resulting in the same number of Re-timers being used for short-distance routing and long-distance routing. For example, the routing length of a certain control node only needs to be 5000 mil (meeting the PCIe specification limit), but due to the extremely long routing of another node (14000 mil), Re-timers are uniformly configured, resulting in a sharp increase in hardware redundancy and cost.
[0047] At least for the above problems, an embodiment of the present application provides a routing method. The routing method includes: cross-connecting a storage medium with at least two control nodes, so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes; using Re-timers to merge the long-distance lines between the control nodes and the storage medium; and dynamically configuring the physical addresses corresponding to the respective lines of the control nodes, so that the physical addresses when the storage medium is connected to different control nodes are kept consistent.
[0048] In the embodiment of the present application, the storage medium is cross-connected with the control nodes, so that the two ports of the storage medium are respectively connected to different processor ports of different control nodes, the long-distance lines are merged using Re-timers, and the physical addresses corresponding to the control node lines are kept consistent using dynamic configuration. Such a routing method can solve the number of Re-timers on the premise of consistent physical addresses, optimize the routing layout, reduce the redundant architecture, and improve the working efficiency of the whole machine.
[0049] Figure 1 Shown is a schematic diagram of an application scenario of the routing method described in the present application. The printed circuit board 1 can be used to implement the routing method provided by the embodiment of the present application, but the application scenario of the routing method provided by the embodiment of the present application is not limited to Figure 1 the shown printed circuit board 1. As Figure 1 shown, the printed circuit board 1 includes a node 11, a circuit backplane 12, and an NVMe disk 13. The routing method provided by the embodiment of the present application can be applied to the printed circuit board 1.
[0050] Among them, Figure 1 the printed circuit board 1 in can be a basis for mechanical support and electrical connection, connecting various electronic components (such as resistors, capacitors, chips, etc.) together through conductive paths, and specifically, none of them are limited here. Although Figure 1 only 2 nodes 11, 1 circuit backplane 12, and 1 NVMe disk 13 are shown in, it should be understood that Figure 1 the examples in are only for understanding the present solution, and the specific numbers of nodes 11 and NVMe disks 13 should be flexibly determined according to the actual situation.
[0051] In some other implementations, the printed circuit board 1 may not include the circuit backplane 12, but only include the nodes 11 with interfaces and the NVMe disks 13. The routing method provided by the embodiments of the present application can be applied to the printed circuit board 1. The nodes 11 are a number of identical nodes, and each node has an independently operating CPU. The NVMe disk 13 (Non-Volatile Memory Express) is a dual-port interface standard for solid-state drives and other storage devices, aiming to utilize the high-speed data transmission capability of the PCIe (Peripheral Component Interconnect Express) bus to significantly improve storage performance.
[0052] Next, the technical solutions in the embodiments of the present application will be described in detail with reference to the accompanying drawings in the embodiments of the present application.
[0053] The following embodiments of the present application provide a routing method, which can be implemented, for example, by Figure 1 the printed circuit board 1 shown. Figure 2 It shows a schematic flowchart of the routing method described in the embodiments of the present application. As Figure 2 shown, the routing method includes steps S11 to S13.
[0054] Step S11, cross-connect the storage medium with at least two control nodes so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes. The storage medium is an NVMe disk, which is used to connect to other devices by utilizing the high-speed data transmission capability of the PCIe bus. The control nodes are independent nodes, and each node has an independently operating processor.
[0055] Step S12, use a retimer to merge the long-distance lines between the control nodes and the storage medium. The retimer is used to reconstruct the signal internally through a clock when the signal passes through, enhance the transmission energy of the signal, and increase the transmission distance. Specifically, the retimer requires firmware to operate properly.
[0056] Step S13, dynamically configure the physical addresses corresponding to the lines of each control node so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0057] In some possible implementation manners, the two control nodes are in a left-right architecture with the same hardware design. To meet the 1+1 redundancy requirement that the two control nodes can be swapped so that when any one of the control nodes fails, the other control node can work properly, each of the control nodes is respectively connected to each NVMe disk of the storage medium. For example, the No. 1 NVMe disk is connected to the P0 port of the processors of the two control nodes, and the No. 24 NVMe disk is connected to the P4 port of the processors of the two control nodes. Based on the above architecture, the line A1+A2 from the first port of the NVMe disk to the first control node is 4000 mil + 1000 mil = 5000 mil. The line B1+B2 from the first port of the NVMe disk to the second control node is 13000 mil + 1000 mil = 14000 mil. The line B1+B2 from the last port of the NVMe disk to the first control node is 13000 mil + 1000 mil = 14000 mil. The line A1+A2 from the last port of the NVMe disk to the second control node is 4000 mil + 1000 mil = 5000 mil. Therefore, since the line from the first port of the NVMe disk to the second control node and the line from the last port of the NVMe disk to the first control node are greater than the longest line threshold of the PCIe line, that is, 10000 mil, it is necessary to add retimers to increase the signal strength. Also, since the two control nodes need to be kept consistent, another PCIe line of the two control nodes also needs to add retimers. Therefore, for the lines that do not exceed the longest line threshold of the PCIe line, it causes a waste of the retimer architecture and increases the cost of the redundant architecture. The routing method in the embodiment of the present application cross-connects the storage medium with at least two control nodes so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes. Specifically, the first port of the NVMe disk is connected to the P0 port of the processor of the first control node, the first port of the NVMe disk is connected to the P4 port of the processor of the second control node, the last port of the NVMe disk is connected to the P4 port of the processor of the first control node, and the last port of the NVMe disk is connected to the P0 port of the processor of the second control node. Based on the above architecture, the line A1+A2 from the first port of the NVMe disk to the first control node is 5000 mil. The line B1+B2 from the last port of the NVMe disk to the first control node is 13000 mil + 1000 mil = 14000 mil. The line B1+B2 from the first port of the NVMe disk to the second control node is 17000 mil + 1000 mil = 18000 mil. The line A1+A2 from the last port of the NVMe disk to the second control node is 9000 mil.Therefore, since the line from the first port of the NVMe disk to the second control node and the line from the last port of the NVMe disk to the first control node are longer than the longest line threshold of the PCIe line, which is 10,000 mil, the retimer is used to merge the long-distance lines from the first control node to the last port of the storage medium and the long-distance lines from the second control node to the first port of the storage medium to increase the signal strength and ensure the transmission quality. At this time, the architectures of the two control nodes are consistent, and no additional retimer needs to be added. Dynamically configure the physical addresses corresponding to each line of the control node so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0058] In the embodiment of the present application, the storage medium is cross-connected with the control node, so that the two ports of the storage medium are respectively connected to different processor ports of different control nodes. The retimer is used to merge the long-distance lines, and dynamic configuration is used to keep the physical addresses corresponding to the control node lines consistent. This wiring method can solve the number of retimers on the premise of consistent physical addresses, optimize the wiring layout, reduce redundant architectures, and improve the working efficiency of the whole machine.
[0059] In an embodiment of the present application, the control node includes a first control node and a second control node, and the processor includes a first port and a second port. The implementation method of cross-connecting the storage medium with the control node so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes includes: the first port of any storage medium is connected to the first port of the processor of the first control node, and the last port of the storage medium is connected to the first port of the processor of the second control node.
[0060] The first port of the storage medium is connected to the second port of the processor of the second control node, and the last port of the storage medium is connected to the second port of the processor of the first control node.
[0061] In some possible implementation manners, Figure 3 It shows a schematic diagram of the wiring method described in the embodiment of the present application. As Figure 3As shown in the figure, the control node includes a first control node and a second control node, and the processor includes a first port P0 and a second port P4. The implementation method of cross - connecting the storage medium with the control node so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes includes: the first port 1 of any one of the storage media is connected to the first port P0 of the processor of the first control node, and the end - point port 24 of the storage medium is connected to the first port P0 of the processor of the second control node. The first port 1 of the storage medium is connected to the second port P4 of the processor of the second control node, and the end - point port 24 of the storage medium is connected to the second port P4 of the processor of the first control node. The retimer is configured on the line between the first port 1 of the storage medium and the second port P4 of the processor of the second control node, and on the line between the end - point port 24 of the storage medium and the second port P4 of the processor of the first control node.
[0062] Figure 4 It is shown as a schematic flow diagram of the routing method described in the embodiments of the present application. As Figure 4 shown, step S13 includes steps S131 to S132.
[0063] Step S131, using the hardware detection module to identify the physical location of the control node by using the level signal.
[0064] Step S132, dynamically configuring the physical addresses corresponding to each line according to the physical location of the control node, so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0065] In some possible implementation manners, the first port of the storage medium is connected to the P0 port of the processor of the first control node and the P4 port of the processor of the second control node. The inconsistency of the physical addresses of the two control nodes will cause the confusion of system maintenance. The hardware detection module and software optimization are used to realize the synchronous update of the physical addresses. The hardware detection module judges which control node the signal comes from according to the level signal. For example, the first control node is a low - level signal and the second control node is a high - level signal. The physical addresses corresponding to each line are dynamically configured according to the physical location of the control node, so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0066] In an embodiment of the present application, using the hardware detection module to identify the physical location of the control node by using the level signal includes: connecting the first resistor to the power supply to generate a high - level signal, and connecting the second resistor to the ground to generate a low - level signal. The high - level signal and the low - level signal are respectively configured for different control nodes to identify the physical location of the control node.
[0067] In some possible implementations, Figure 5 It is shown as a schematic diagram of the wiring method described in the embodiments of the present application. As Figure 5 shown, the control node includes a first control node and a second control node, and the processor includes a first port P0 and a second port P4. The first port 1 of the storage medium is connected to the first port P0 of the processor of the first control node, and the last port 24 of the storage medium is connected to the first port P0 of the processor of the second control node. The first port 1 of the storage medium is connected to the second port P4 of the processor of the second control node, and the last port 24 of the storage medium is connected to the second port P4 of the processor of the first control node. Retimers are configured on the line between the first port 1 of the storage medium and the second port P4 of the processor of the second control node, and on the line between the last port 24 of the storage medium and the second port P4 of the processor of the first control node. The port GPI1 of the first control node is connected to a second resistor, and the port GPI1 of the second control node is connected to a first resistor. The first resistor is connected to the power supply to generate a high-level signal, and the second resistor is grounded to generate a low-level signal. The high-level signal is configured for the second control node, and the low-level signal is configured for the first control node. When the first control node is inserted, the second resistor is grounded and connected to the GPI1 of the processor of the first control node, and GPI1 determines that the low-level signal is the first control node. When the second control node is inserted, one end of the first resistor is connected to the power supply, and the other end is connected to the GPI1 of the processor of the second control node, and GPI1 determines that the high-level signal is the second control node.
[0068] In an embodiment of the present application, the control node includes a first control node and a second control node. Using a hardware detection module to identify the physical location of the control node using a level signal includes: when the hardware detection module identifies the first control node using the level signal, the first port of the processor of the first control node is configured to be connected to the first port of the storage medium, and the second port of the processor of the first control node is configured to be connected to the last port of the storage medium.
[0069] When the hardware detection module identifies the second control node using the level signal, the first port of the processor of the second control node is configured to be connected to the last port of the storage medium, and the second port of the processor of the second control node is configured to be connected to the first port of the storage medium.
[0070] In some possible implementation manners, the control node includes a first control node and a second control node. The hardware detection module uses a level signal to identify the physical location of the control node, which includes: when the hardware detection module uses the level signal to identify the first control node, the first port of the first control node processor is configured to be connected to the first port of the storage medium, and the second port of the first control node processor is configured to be connected to the last port of the storage medium. When the hardware detection module uses the level signal to identify the second control node, the first port of the second control node processor is configured to be connected to the last port of the storage medium, and the second port of the second control node processor is configured to be connected to the first port of the storage medium. Table 1 shows the physical addresses of the control nodes in the embodiments of the present application. As shown in Table 1, the BDF (Bus, Device, Function) address corresponding to the P0 port of the first control node processor is 010. When the GPI1 port is 0, it is determined that the corresponding line is connected to the first port slot1 of the storage medium. The BDF address corresponding to the P4 port of the first control node processor is 100. When the GPI1 port is 0, it is determined that the corresponding line is connected to the last port slot24 of the storage medium. The BDF address corresponding to the P0 port of the second control node processor is 010. When the GPI1 port is 1, it is determined that the corresponding line is connected to the last port slot24 of the storage medium. The BDF address corresponding to the P4 port of the second control node processor is 100. When the GPI1 port is 1, it is determined that the corresponding line is connected to the first port slot1 of the storage medium.
[0071] Table 1: Physical Addresses of Control Nodes
[0072]
[0073] In an embodiment of the present application, the retimer is configured for a long-distance line exceeding a preset threshold. Specifically, the preset value is 10000 mil. When it exceeds 10000 mil, a retimer needs to be configured to enhance the signal strength.
[0074] Figure 6 It shows a schematic structural diagram of the wiring system in the embodiments of the present application. As Figure 6 shown, the wiring system 100 includes a line layout module 110, a line merging module 120, and an address mapping module 130.
[0075] The line layout module 110 is used to cross-connect the storage medium with at least two control nodes, so that the dual ports of the storage medium correspond to different processor ports of different control nodes.
[0076] The line merging module 120 is configured to merge the long-distance lines between the control node and the storage medium by using a retimer.
[0077] The address mapping module 130 is configured to dynamically configure the physical addresses corresponding to the lines of each control node, so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0078] In some possible implementation manners, the line layout module 110 is configured to connect the first port of the NVMe disk to the P0 port of the first control node processor, connect the first port of the NVMe disk to the P4 port of the second control node processor, connect the last port of the NVMe disk to the P4 port of the first control node processor, and connect the last port of the NVMe disk to the P0 port of the second control node processor. Based on the above architecture, the line A1+A2 from the first port of the NVMe disk to the first control node is 5000 mil. The line B1+B2 from the last port of the NVMe disk to the first control node is 13000 mil + 1000 mil = 14000 mil. The line B1+B2 from the first port of the NVMe disk to the second control node is 17000 mil + 1000 mil = 18000 mil. The line A1+A2 from the last port of the NVMe disk to the second control node is 9000 mil. Therefore, since the line from the first port of the NVMe disk to the second control node and the line from the last port of the NVMe disk to the first control node are greater than the longest line threshold of the PCIe line, that is, 10000 mil, the line merging module 120 is configured to merge the long-distance lines from the first control node to the last port of the storage medium and from the second control node to the first port of the storage medium by using a retimer, so as to increase the signal strength and ensure the transmission quality. At this time, the architectures of the two control nodes are consistent, and no additional retimer needs to be added. The address mapping module 130 is configured to dynamically configure the physical addresses corresponding to the lines of each control node, so that the physical addresses are consistent when the storage medium is connected to different control nodes.
[0079] In the embodiment of the present application, the line layout module 110 is configured to cross-connect the storage medium and the control node, so that the two ports of the storage medium are respectively connected to different processor ports of different control nodes. The line merging module 120 is configured to merge the long-distance lines by using a retimer. The address mapping module 130 is configured to keep the physical addresses corresponding to the control node lines consistent by using dynamic configuration. Such a routing system 100 can solve the number of retimers on the premise of consistent physical addresses, optimize the routing layout, reduce redundant architectures, and improve the working efficiency of the whole machine.
[0080] Figure 7 Shown is a schematic structural diagram of the chip described in the embodiments of the present application. As Figure 7 shown, the chip 200 includes a backplane 210, a control node 220, and a dual-port storage medium 230.
[0081] The backplane 210 is configured to provide a physical connection interface.
[0082] At least two control nodes 220 are configured to execute the routing method described in any embodiment of the present application.
[0083] A plurality of dual-port storage media 230 are configured to be cross-connected to the control node 220 through the backplane 210, and the two ports of each storage medium 230 are respectively connected to different control nodes 220.
[0084] In several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules / units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of devices or modules or units can be in an electrical, mechanical, or other form.
[0085] The modules / units described as separate components may or may not be physically separated. The components shown as modules / units may or may not be physical modules, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, in each embodiment of the present application, the functional modules / units can be integrated in a processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated in one module / unit.
[0086] Those of ordinary skill in the art should also be further aware that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0087] An embodiment of the present application also provides an electronic device. Figure 8 Shown is a schematic structural diagram of the electronic device 800 described in the embodiments of the present application. As Figure 8 shown, in this embodiment, the electronic device 800 includes a memory 810 and a programmable logic device 820.
[0088] The memory 810 is used to store a programmable logic program. The programmable logic device 820 is used to load the programmable logic program stored in the memory 810, so that the electronic device 800 executes the routing method described in any embodiment of the present application.
[0089] An embodiment of the present application also provides a readable storage medium, on which a programmable logic program is stored. When the program is executed by a processor, it implements the routing method described in any embodiment of the present application.
[0090] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, an application running on a computing device and the computing device can both be components. One or more components can reside in a process and / or an execution thread, and the components can be located on one computer and / or distributed between two or more computers. In addition, these components can execute from various computer-readable media on which various data structures are stored. Components can communicate, for example, through local and / or remote processes according to signals having one or more data packets (such as data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems through signals).
[0091] The descriptions of the processes or structures corresponding to the above respective drawings each have their own focuses. For parts not detailed in a certain process or structure, reference can be made to the relevant descriptions of other processes or structures.
[0092] The above embodiments are only illustrative of the principles and effects of the present application and are not intended to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present application should still be covered by the claims of the present application.
Claims
1. A wiring method, characterized in that: include: Cross-connecting a storage medium to at least two control nodes so that dual ports of the storage medium are respectively connected to different processor ports of different control nodes; Using a retimer to merge long distance lines between the control node and the storage medium; as well as The physical addresses corresponding to the lines of the control node are dynamically configured so that the physical addresses of the storage medium when connected to different control nodes remain consistent.
2. The wiring method according to claim 1, characterized in that: The control node includes a first control node and a second control node, and the processor includes a first port and a second port; the storage medium is cross-connected with the control node so that the dual ports of the storage medium are respectively connected to different processor ports of different control nodes, including: The first port of any of the storage media is connected to the first port of the first control node processor, and the tail port of the storage medium is connected to the first port of the second control node processor; The first port of the storage medium is connected to the second port of the second control node processor, and the tail port of the storage medium is connected to the second port of the first control node processor.
3. The wiring method according to claim 1, characterized in that: Dynamically configuring the physical address corresponding to each line of the control node so that the physical address of the storage medium when connected to different control nodes remains consistent includes: Using a hardware detection module to identify the physical location of the control node using a level signal; The physical address corresponding to each line is dynamically configured according to the physical position of the control node, so that the physical address of the storage medium when connected to different control nodes remains consistent.
4. The wiring method according to claim 3, characterized in that: Using the hardware detection module to use the level signal to identify the physical location of the control node includes: A first resistor is connected to a power supply to generate a high level signal, and a second resistor is connected to a ground to generate a low level signal; The high level signal and the low level signal are respectively configured to different control nodes to identify the physical location of the control node.
5. The wiring method according to claim 3, characterized in that: The control node includes a first control node and a second control node, and using a hardware detection module to use a level signal to identify the physical position of the control node includes: When the hardware detection module identifies the first control node using the level signal, the first port of the processor of the first control node is configured to be connected to the first port of the storage medium, and the second port of the processor of the first control node is configured to be connected to the tail port of the storage medium; When the hardware detection module uses a level signal to identify the second control node, the first port of the second control node processor is configured to be connected to the tail port of the storage medium, and the second port of the second control node processor is configured to be connected to the first port of the storage medium.
6. The wiring method according to claim 1, characterized in that: The retimer is configured for long distance lines exceeding a preset threshold.
7. A wiring system, characterized in that: include: A line layout module, used for cross-connecting the storage medium with at least two control nodes so that the dual ports of the storage medium correspond to different processor ports of different control nodes respectively; A line merging module, used for merging the long distance lines between the control node and the storage medium by using a retimer; as well as The address mapping module is used to dynamically configure the physical addresses corresponding to the lines of the control node so that the physical addresses of the storage medium when connected to different control nodes remain consistent.
8. A chip, characterized in that: include: a backplane configured to provide a physical connection interface; At least two control nodes, configured to execute the routing method according to any one of claims 1 to 6; as well as A plurality of dual-port storage media are configured to be cross-connected to the control node through the backplane, and the two ports of each storage medium are respectively connected to different control nodes.
9. An electronic device, characterized in that: The electronic device comprises: A memory for storing a programmable logic program; A programmable logic device, wherein the programmable logic device is used to load the programmable logic program stored in the memory so that the electronic device executes the routing method according to any one of claims 1 to 6.
10. A readable storage medium having a programmable logic program stored thereon, characterized in that: When the program is executed by a programmable logic device, the routing method described in any one of claims 1 to 6 is implemented.