Bandgap reference voltage source for RRAM device and RRAM device including same

Abstract

The invention relates to a bandgap reference voltage source for an RRAM device and an RRAM device including the same. The bandgap reference voltage source is used for providing a reference voltage for a write current limiting circuit in the RRAM device. And the write current limiting circuit is used for limiting the current of the RRAM in the RRAM equipment in the write process. The band-gap reference voltage source comprises a starting circuit, a biasing circuit, an error amplifier, a band-gap core circuit and a reference output circuit. The starting circuit is used for starting the band-gap reference voltage source. The bias circuit is used for providing bias for the error amplifier. The error amplifier is used for providing negative feedback for the band-gap core circuit. The bandgap core circuit is used to provide a substantially temperature-independent current for the reference output circuit. The reference output circuit is configured to output a substantially temperature-independent reference voltage based on the received substantially temperature-independent current. At least one of the bias circuit and the error amplifier includes at least one MOS transistor configured to operate in a sub-threshold region.

Description

Technical Field

[0001] The present disclosure relates to the field of non - volatile storage technologies, and more particularly, to a bandgap reference voltage source for a resistive random access memory (RRAM) device and an RRAM device including such a bandgap reference voltage source. Background Art

[0002] With the rapid development of semiconductor process nodes, electronic devices have become increasingly miniaturized, and various portable devices such as smart phones and smart wearable devices such as smart watches have emerged. A variety of functional software can be installed on portable devices to facilitate people's lives, but this also increases the demand for large - scale data storage. Traditional storage devices are prone to data loss after power - off, so non - volatile storage devices have come into being. RRAM is a relatively mature non - volatile storage device, which is manufactured based on the principle that the resistance of a non - conductive material can be reversibly converted between a high - resistance state and a low - resistance state under the action of an external electric field. Due to advantages such as simple structure, high integration, and low power consumption, RRAM has always been considered the most promising new device to break through the limitations of traditional devices. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a bandgap reference voltage source for an RRAM device. The bandgap reference voltage source is configured to provide a reference voltage for a write current - limiting circuit in the RRAM device, and the write current - limiting circuit is configured to limit the current of the RRAM in the RRAM device during the write process. The bandgap reference voltage source includes a startup circuit, a bias circuit, an error amplifier, a bandgap core circuit, and a reference output circuit. The startup circuit is configured to start the bandgap reference voltage source. The bias circuit is configured to provide a bias for the error amplifier. The error amplifier is configured to provide negative feedback for the bandgap core circuit. The bandgap core circuit is configured to provide a current that is substantially independent of temperature for the reference output circuit. The reference output circuit is configured to output a reference voltage that is substantially independent of temperature based on the received current that is substantially independent of temperature. In this bandgap reference voltage source, at least one of the bias circuit and the error amplifier includes at least one metal - oxide - semiconductor field - effect transistor (MOSFET) (which may be simply referred to as a MOS transistor in this article) configured to operate in the sub - threshold region.

[0004] In some embodiments, at least one of the bias circuit and the error amplifier includes a cascode structure having at least one MOS transistor configured to operate in the subthreshold region. For example, the cascode transistor in the cascode structure can be configured to operate in the subthreshold region. Additionally or alternatively, the gate transistor in the cascode structure can also be configured to operate in the subthreshold region.

[0005] In some embodiments, the first MOS transistor in the bias circuit is configured to operate in the subthreshold region, and the second MOS transistor in the error amplifier biased by the first MOS transistor in the bias circuit is configured to operate in the subthreshold region. For example, the first MOS transistor can be the cascode transistor in the first cascode structure in the bias circuit, and the second MOS transistor can be the cascode transistor in the second cascode structure in the error amplifier.

[0006] In some embodiments, the bias circuit includes a self - biasing cascode structure having a first cascode current mirror and a second cascode current mirror. The first cascode current mirror is configured to provide a first bias for the MOS transistor with a first conduction type in the error amplifier, and the second cascode structure is configured to provide a second bias for the MOS transistor with a second conduction type in the error amplifier. The first conduction type is different from the second conduction type. For example, the first conduction type can be one of P - type and N - type, and the second conduction type can be the other of P - type and N - type. In some examples, in at least one of the first cascode current mirror and the second cascode current mirror, the cascode transistor is configured to operate in the subthreshold region and the gate transistor is configured to operate in the saturation region. In some examples, in at least one of the first cascode current mirror and the second cascode current mirror, the cascode transistor is configured to operate in the saturation region and the gate transistor is configured to operate in the subthreshold region. In some examples, in at least one of the first cascode current mirror and the second cascode current mirror, both the cascode transistor and the gate transistor are configured to operate in the subthreshold region.

[0007] In some embodiments, the error amplifier includes a single-stage differential-input symmetric cascode transconductance amplifier, which includes a differential-input MOS transistor pair, a first cascode amplifier circuit coupled to the first output terminal of the differential-input MOS transistor pair, and a second cascode amplifier circuit coupled to the second output terminal of the differential-input MOS transistor pair. The single-stage differential-input symmetric cascode transconductance amplifier may include at least one MOS transistor configured to operate in the subthreshold region. For example, the MOS transistors of the differential-input MOS transistor pair may be configured to operate in the subthreshold region. Additionally or alternatively, each of the first cascode amplifier circuit and the second cascode amplifier circuit may also include a cascode structure having at least one MOS transistor configured to operate in the subthreshold region. Exemplarily, each of the first cascode amplifier circuit and the second cascode amplifier circuit may include a cascode current mirror and a cascode amplifier, and the cascode current mirror is configured to mirror the current received from the corresponding output terminal of the differential-input MOS transistor pair into the cascode amplifier for amplification. In some examples, in at least one of the cascode current mirror and the cascode amplifier, the cascode transistor is configured to operate in the subthreshold region and the cascode gate transistor is configured to operate in the saturation region. In some examples, in at least one of the cascode current mirror and the cascode amplifier, the cascode transistor is configured to operate in the saturation region and the cascode gate transistor is configured to operate in the subthreshold region. In some examples, in at least one of the cascode current mirror and the cascode amplifier, both the cascode transistor and the cascode gate transistor are configured to operate in the subthreshold region.

[0008] According to a second aspect of the present disclosure, there is provided a RRAM device, including an RRAM, a write current limiting circuit, and a bandgap reference voltage source according to any one of the embodiments of the first aspect of the present disclosure. The write current limiting circuit is coupled to the RRAM and configured to limit the current of the RRAM during the write process. The bandgap reference voltage source is coupled to the write current limiting circuit and configured to provide a reference voltage for the write current limiting circuit.

[0009] Other features and advantages of the present disclosure will become clearer from the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0011] With reference to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, wherein:

[0012] Figure 1 A schematic diagram of a RRAM device according to an exemplary embodiment of the present disclosure is shown;

[0013] Figure 2 shows a schematic block diagram of a bandgap reference voltage source according to an exemplary embodiment of the present disclosure;

[0014] Figure 3 shows a circuit diagram of a bandgap reference voltage source according to an exemplary embodiment of the present disclosure;

[0015] Figure 4 shows a circuit diagram of a non - limiting example of a startup circuit that can be employed in a bandgap reference voltage source according to an exemplary embodiment of the present disclosure;

[0016] Figure 5A and Figure 5B shows a circuit diagram of a non - limiting example of a cascode current mirror that can be employed in a bandgap reference voltage source according to an exemplary embodiment of the present disclosure;

[0017] Figure 6A and Figure 6B shows a circuit diagram of a non - limiting example of a differential - input cascode amplifier that can be employed in a bandgap reference voltage source according to an exemplary embodiment of the present disclosure;

[0018] Figure 7 shows a circuit diagram of a non - limiting example of a reference voltage generation module that can be employed in a bandgap reference voltage source according to an exemplary embodiment of the present disclosure;

[0019] Figure 8 depicts the operating state of the saturation region of a MOS transistor;

[0020] Figure 9 depicts the operating state of the sub - threshold region of a MOS transistor.

[0021] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0022] For ease of understanding, the positions, sizes, and ranges, etc. of the various structures shown in the drawings, etc. sometimes do not represent the actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings, etc. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show the details of specific components. Detailed Embodiments

[0023] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0024] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way serves as a limitation to the present disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways. In addition, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0025] In addition, technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification.

[0026] In all the examples shown and discussed here, any specific values should be construed as merely exemplary, rather than as a limitation. Thus, other examples of the exemplary embodiments may have different values.

[0027] RRAM is prone to overwriting during the writing process, resulting in a reduction in the storage reliability of RRAM. To this end, a write current limiting circuit has been provided to limit the current of RRAM during the writing process. However, the introduction of the write current limiting circuit causes voltage margin loss, such that the power supply voltage of the RRAM device has to be increased, thereby causing an undesired increase in the power consumption of the RRAM device.

[0028] The write current limiting circuit requires a reference voltage when operating, which can be provided by a reference voltage source. The present disclosure provides a low-input and low-output bandgap reference voltage source, which can provide a reduced reference voltage for the write current limiting circuit of the RRAM device, thereby alleviating the voltage margin loss problem brought about by the write current limiting circuit. The bandgap reference voltage source of the present disclosure may have characteristics such as a low operating power supply voltage, a low output voltage, low power consumption, high current accuracy, a high power supply rejection ratio, and a low temperature coefficient. The bandgap reference voltage source according to various embodiments of the present disclosure and the RRAM device including such a bandgap reference voltage source will be described in detail below with reference to the accompanying drawings. It should be understood that an actual device may also include other components, but in order to avoid obscuring the key points of the present disclosure, these other components are not discussed herein and are not shown in the drawings.

[0029] Figure 1 RRAM device 100 according to an exemplary embodiment of the present disclosure is schematically shown. RRAM device 100 includes RRAM 102 for providing non-volatile storage. AsFigure 1 As shown, the gate of MOS transistor M0 is connected to word line WL, the source is connected to bit line BL, and the drain is connected to RRAM 102. During the write process, the voltage applied to word line WL turns on MOS transistor M0, and the write voltage applied to bit line BL completes the write process for RRAM 102. In a conventional situation, one end of RRAM 102 opposite to MOS transistor M0 (as shown, the lower end of RRAM 102) can be grounded. In contrast, in Figure 1 the situation shown, RRAM device 100 further includes a write current limiting circuit 104, which is coupled to RRAM 102 and is configured to limit the current in RRAM 102 during the write process. As Figure 1 shown, write current limiting circuit 104 can be coupled between RRAM 102 and ground, thereby raising the potential of the lower end of RRAM 102 from the ground potential to V0. Therefore, it can be understood that although write current limiting circuit 104 can help prevent overwriting of RRAM 102, it will introduce additional voltage overhead, thereby causing voltage margin loss, resulting in an increase in the operating power supply voltage required for RRAM device 100.

[0030] As Figure 1 shown, RRAM device 100 further includes a bandgap reference voltage source 200, which is coupled to write current limiting circuit 104 and is configured to provide a reference voltage V ref to write current limiting circuit 102. In the present disclosure, bandgap reference voltage source 200 is specifically configured to provide a low reference voltage to write current limiting circuit 102. Specifically, the reduction of the reference voltage V ref provided by bandgap reference voltage source 200 can cause the potential V0 of the lower end of RRAM 102 to decrease, thereby alleviating the voltage margin loss problem brought by write current limiting circuit 102 and reducing the requirement of RRAM device 100 for the operating power supply voltage.

[0031] Figure 2 shows a schematic block diagram of bandgap reference voltage source 200 according to an exemplary embodiment of the present disclosure. As Figure 2 shown, bandgap reference voltage source 200 includes a startup circuit 210, a bias circuit 220, an error amplifier 230, a bandgap core circuit 240, and a reference output circuit 250. Startup circuit 210 is configured to start bandgap reference voltage source 200. Bias circuit 220 is configured to provide a bias for error amplifier 230. Error amplifier 230 is configured to provide negative feedback to bandgap core circuit 240. Bandgap core circuit 240 is configured to provide a current that is substantially independent of temperature to reference output circuit 250. Reference output circuit 250 is configured to output a reference voltage that is substantially independent of temperature based on the received current that is substantially independent of temperature. It should be understood that, Figure 2The coupling relationships between the components shown are merely exemplary and not restrictive. Other suitable coupling relationships are also feasible as long as the components can achieve their respective functions and cooperate with each other to provide a bandgap reference voltage source.

[0032] The startup circuit 210 can be used as a startup module for the bandgap reference voltage source 200. The bias circuit 220 and the error amplifier 230 can be combined to be used as a bias current generation module for the bandgap reference voltage source 200. The bandgap core circuit 240 and the reference output circuit 250 can be combined to be used as a reference voltage generation module for the bandgap reference voltage source 200.

[0033] Specifically, when the bandgap reference voltage source 200 is powered on, the entire circuit of the bandgap reference voltage source 200 is in the 0 state. At this time, the startup circuit 210 can first receive the input power supply voltage and then inject current into the bias current generation module (or more specifically, the bias circuit 220) and the reference voltage generation module (or more specifically, the bandgap core circuit 240) respectively, so that the entire circuit of the bandgap reference voltage source 200 gets out of the 0 state. After the bandgap reference voltage source 200 enters the startup process, the bias circuit 220 can generate a current mirror for the error amplifier 230 and provide bias so that the error amplifier 230 gradually starts to work. At the same time, the bandgap core circuit 240 also gradually starts to work after being injected with current by the startup circuit 210. In some alternative embodiments, the startup circuit 210 can also only inject current into the bias current generation module (or more specifically, the bias circuit 220), and then as the error amplifier 230 gradually starts to work, current is injected into the reference voltage generation module (or more specifically, the bandgap core circuit 240), making the bandgap core circuit 240 also gradually start to work.

[0034] The bandgap core circuit 240 can include a positive temperature coefficient current generation sub-circuit and a negative temperature coefficient current generation sub-circuit. Under the negative feedback action of the error amplifier 230, the PTAT (Proportional to Absolute Temperature) current in the positive temperature coefficient current generation sub-circuit of the bandgap core circuit 240 and the CTAT (Complementary to Absolute Temperature) current in the negative temperature coefficient current generation sub-circuit can be added together to form a current that basically does not change with temperature. After receiving this current that basically does not change with temperature formed by the bandgap core circuit 240, the reference output circuit 250 can output a reference voltage that is basically independent of temperature.

[0035] After the circuit of the bandgap reference voltage source 200 stabilizes, the startup circuit 210 will be able to turn off at least partially after detecting the stable output of the reference output circuit 250, thus ending the startup process. Thereby, the bandgap reference voltage source 200 can enter the normal working state and stably provide the reference voltage V for the write current limiting circuit 104. ref In some alternative embodiments, the startup circuit 210 can also remain turned on after the bandgap reference voltage source 200 enters the normal working state. For example, the startup circuit 210 may not detect whether the circuit output is stable.

[0036] It can be understood that "substantially independent of temperature" can include being completely independent of temperature or weakly related to temperature. For example, it can be expressed as including a low temperature coefficient including zero temperature coefficient. The temperature coefficient is usually expressed in ppm / °C. For a reference voltage source, 1 ppm / °C means that when the ambient temperature changes by 1°C at a certain reference point (usually 25°C), its output voltage deviates from its nominal value by one millionth. For example, if the nominal value of a reference voltage source is 2.5V and the temperature coefficient is ±10 ppm / °C, then when the ambient temperature changes by 1°C based on 25°C, its output voltage will be 2.5V ± 0.000025V. Thus, "substantially independent of temperature" can be considered that the absolute value of the temperature coefficient does not exceed 100 ppm / °C, for example, within dozens of ppm / °C.

[0037] Generally, the MOS transistors in the part of the bandgap reference voltage source 200 other than the startup circuit 210 (the MOS transistors in the startup circuit 210 can usually work in any non-saturation region) can be configured to work in the saturation region. Refer to Figure 8 , which shows the working state of the MOS transistor in the saturation region. As Figure 8 shown, when the gate voltage V GS of the MOS transistor is greater than the threshold voltage V th , and the drain voltage V DS is greater than or equal to V GS -V th , the MOS transistor enters the saturation region. In the saturation region, the current I D basically does not change with V DS . The magnitude of I D is mainly determined by V GS . In the saturation region, I D will increase as V GS increases. The required V DS to enter the saturation region will also increase as V GS increases and finally tends to be constant. The middle region of the output characteristic curve of the MOS transistor is the saturation region. In the saturation region, the MOS transistor is in a controlled constant current state, so its saturation region is also called the constant current region.

[0038] In particular, in the bandgap reference voltage source 200, at least one of the bias circuit 220 and the error amplifier 230 includes at least one MOS transistor configured to operate in the subthreshold region. This advantageously reduces the voltage margin consumption. Refer to Figure 9 , which shows the operating state of the MOS transistor in the subthreshold region. As Figure 9 shown, the operating state of the MOS transistor in the subthreshold region is a state where the gate voltage V GS of the MOS transistor is below the threshold voltage V th and no conductive channel appears, that is, V GS ≤ V th , and the surface potential ψs ≈ Fermi potential ψb (i.e., the surface is in weak inversion). At this time, there is still a small current I D flowing through the MOS transistor, and this current is called the subthreshold current. Although the subthreshold current is small, it can be well controlled by the gate voltage V GS , and it also increases with the increase of V GS . The subthreshold current will basically not change with V DS when V th exceeds 3V DS . It can be seen that compared with operating in the saturation region, the MOS transistor operating in the subthreshold region is more beneficial for low-voltage and low-power applications.

[0039] In the bandgap reference voltage source 200, MOS transistors operating in the subthreshold region can be set in the bias current generation module (i.e., the bias circuit 220 and the error amplifier 230), and MOS transistors operating in the subthreshold region can not be set in the reference voltage generation module (i.e., the bandgap core circuit 240 and the reference output circuit 250). The MOS transistors in the reference voltage generation module can be configured to operate in the saturation region, so as to reduce the noise influence and make the circuit output more stable.

[0040] For example, the bias circuit 220 and / or the error amplifier 230 may adopt a cascode structure. In this case, the cascode structure may be made to include at least one MOS transistor configured to operate in the subthreshold region. Exemplarily, the cascode transistor in the cascode structure may be configured to operate in the subthreshold region. Additionally or alternatively, the gate transistor in the cascode structure may also be configured to operate in the subthreshold region. In some cases, it may be advantageous that the cascode transistor in the cascode structure is configured to operate in the subthreshold region while the gate transistor is configured to operate in the saturation region, which can achieve a good balance among aspects such as reducing voltage margin loss, decreasing the influence of noise, and saving chip area. This is because when the gate transistor is configured to operate in the subthreshold region, although its power consumption is reduced, if its current is to be stabilized, it needs to be designed with a sufficiently large (both long and wide) channel, which undesirably increases its footprint in the chip.

[0041] By combining MOS transistors operating in the subthreshold region and MOS transistors operating in the saturation region in the bias current generation module, particularly in the error amplifier 230, the accuracy and reliability of the current for the bandgap core circuit 240 are improved, the input supply voltage of the bandgap reference voltage source is reduced, the voltage margin loss is decreased, the power consumption is saved, and it is also beneficial for miniaturizing the circuit.

[0042] MOS transistors configured to operate in the subthreshold region may be correspondingly arranged in the bias circuit 220 and the error amplifier 230, thereby making the circuit more stable. Exemplarily, when the first MOS transistor in the bias circuit 220 is configured to operate in the subthreshold region, the second MOS transistor in the error amplifier 230 biased by the first MOS transistor in the bias circuit 220 may also be configured to operate in the subthreshold region. For example, the first MOS transistor may be the cascode transistor in the first cascode structure in the bias circuit 220, and the second MOS transistor may be the cascode transistor in the second cascode structure in the error amplifier 230.

[0043] For non-limiting illustrative purposes, the following Figures 3 to 7 further describes the application of MOS transistors operating in the subthreshold region in the bandgap reference voltage source 200. It can be understood that the present disclosure is applicable to any suitable circuit implementation of the bandgap reference voltage source 200 that is currently known or developed in the future, and is not limited to Figures 3 to 7 the specific circuit shown.

[0044] As Figure 3As shown, the startup circuit 210 may include a first inverter composed of a P-type MOS transistor (hereinafter referred to as a PMOS transistor for short in this article) M1 and an N-type MOS transistor (hereinafter referred to as an NMOS transistor for short in this article) M2, a second inverter composed of a PMOS transistor M3 and an NMOS transistor M4, a first pull-up transistor composed of a PMOS transistor M5, and a second pull-up transistor composed of a PMOS transistor M6. The input terminal of the first inverter is coupled to a detection point in the reference output circuit 250 (i.e., the upper end of the resistor R8) to detect the sampling voltage in the reference output circuit 250. The input terminal of the second inverter is coupled to the output terminal of the first inverter, so as to invert the output of the first inverter again and provide it to the gates of the first pull-up transistor and the second pull-up transistor. The first inverter and the second inverter can be used to provide load driving capability for the circuit. If more load driving capability is required, more inverters can be added as long as the input of the first-stage inverter is in phase with the output of the last-stage inverter.

[0045] When the bandgap reference voltage source 200 is powered on, the entire circuit of the bandgap reference voltage source 200 is in the 0 state. The input received by the first inverter is at a low potential, the input received by the second inverter is the high potential output by the first inverter, and the first pull-up transistor and the second pull-up transistor respectively receive the low potential output by the second inverter at their gates and thus turn on, so as to inject current into the bias circuit 220 and the bandgap core circuit 240 respectively. After the bandgap reference voltage source 200 is stabilized, the upper end of the resistor R8 in the reference output circuit 250 will be stabilized at a high potential, which makes the input received by the first inverter at a high potential, the input received by the second inverter at the low potential output by the first inverter, and the first pull-up transistor and the second pull-up transistor respectively receive the high potential output by the second inverter at their gates and thus turn off, and the startup process ends here.

[0046] The bias circuit 220 may include a self - biasing cascode structure for generating an accurate current mirror and providing the required bias for the error amplifier 230. Such a self - biasing cascode structure can save circuit area and reduce branch current consumption. For example, the self - biasing cascode structure may include a first cascode current mirror and a second cascode current mirror. The first cascode current mirror is configured to provide a first bias for the MOS transistors of the first conductivity type in the error amplifier 230, and the second cascode structure is configured to provide a second bias for the MOS transistors of the second conductivity type in the error amplifier 230. The first conductivity type is different from the second conductivity type. The first conductivity type may be one of P - type and N - type, while the second conductivity type may be the other of P - type and N - type. Exemplarily, in each of the first cascode current mirror and the second cascode current mirror, the cascode transistors may be configured to operate in the sub - threshold region, and the cascode - gate transistors may be configured to operate in the saturation region. It can be understood that in some examples, the cascode transistors may be configured to operate in the saturation region, and the cascode - gate transistors may be configured to operate in the sub - threshold region. In some examples, both the cascode transistors and the cascode - gate transistors may be configured to operate in the sub - threshold region.

[0047] The error amplifier 230 may include a single-stage differential-input symmetric cascode transconductance amplifier for improving gain, matching, stability, and power supply rejection ratio of a reference. Such a single-stage differential-input symmetric cascode transconductance amplifier may include, for example, a differential-input MOS transistor pair, a first cascode amplifier circuit coupled to a first output terminal of the differential-input MOS transistor pair, and a second cascode amplifier circuit coupled to a second output terminal of the differential-input MOS transistor pair. The single-stage differential-input symmetric cascode transconductance amplifier may include at least one MOS transistor configured to operate in a subthreshold region. For example, the MOS transistors of the differential-input MOS transistor pair may be configured to operate in a subthreshold region. Additionally or alternatively, each of the first cascode amplifier circuit and the second cascode amplifier circuit may also include a cascode structure having at least one MOS transistor configured to operate in a subthreshold region. For example, the cascode transistor of the cascode structure may be configured to operate in a subthreshold region, and its common-gate transistor may also be configured to operate in a subthreshold region additionally or alternatively. Exemplarily, each of the first cascode amplifier circuit and the second cascode amplifier circuit may include a cascode current mirror and a cascode amplifier, the cascode current mirror being configured to mirror the current received from the corresponding output terminal of the differential-input MOS transistor pair into the cascode amplifier for amplification. It can be understood that the cascode current mirror may also amplify the current by a certain ratio when mirroring the current, but mainly it is the cascode amplifier that amplifies the current. For example, the cascode current mirror may amplify the current by 5 times when mirroring the current, and the cascode amplifier may amplify the current by 1000 times. Then, the cascode amplifier circuit can amplify the current by 5000 times in total. In some examples, in at least one of the cascode current mirror and the cascode amplifier, the cascode transistor is configured to operate in a subthreshold region, and the common-gate transistor is configured to operate in a saturation region. In some examples, the cascode transistor is configured to operate in a saturation region, and the common-gate transistor is configured to operate in a subthreshold region. In some examples, both the cascode transistor and the common-gate transistor are configured to operate in a subthreshold region.

[0048] Specifically, referring to Figure 3, the self - biasing cascode structure of the bias circuit 220 has a first cascode current mirror composed of NMOS transistors M8, M9, M12, M13 and resistor R1, and a second cascode current mirror composed of PMOS transistors M10, M11 and resistor R2. NMOS transistors M8 and M9 form a cascode structure. NMOS transistors M12 and M13 form a cascode structure. PMOS transistors M11 and M10 form a cascode structure. Resistor R1 is used to provide different biases for NMOS transistors M8, M12 and NMOS transistors M9, M13, while resistor R2 is used to provide different biases for PMOS transistor M10 and PMOS transistor M11. The bias circuit 220 may also have a PMOS transistor M7, which is used to provide an input current for the bias circuit 220 after the second pull - up transistor M6 of the startup circuit 210 is turned off. The gates of PMOS transistor M7 and M10 can be coupled to each other to achieve self - biasing, which can reduce the circuit area compared with receiving a gate voltage from other external circuit elements. The bias circuit 220 may also have a capacitor C1, which is used to compensate the feedback loop to enhance stability. Note that NMOS transistors M8, M12 and PMOS transistor M11 are cascode transistors, which can be advantageously configured to operate in the sub - threshold region to reduce the voltage margin consumption. NMOS transistors M9, M13 and PMOS transistor M10, which are used as common - gate transistors, can also be selected to operate in the sub - threshold region, but in some cases, it may be advantageous for them to operate in the saturation region, which can reduce the noise effect and increase the circuit stability.

[0049] The single-stage differential input cascode transconductance amplifier of the error amplifier 230 includes a differential input MOS transistor pair composed of PMOS transistors M19 and M22, a cascode current mirror composed of NMOS transistors M20 and M21, and a first cascode amplifier circuit of a cascode amplifier composed of PMOS transistors M14 and M15 and NMOS transistors M16 and M17, as well as a second cascode amplifier circuit of a cascode amplifier composed of NMOS transistors M23 and M24 and PMOS transistors M25 and M26. NMOS transistors M16 and M17 form a cascode structure. The error amplifier 230 may also have a PMOS transistor M18 before the differential input MOS transistor pair to limit the input current. NMOS transistors M20 and M21 form a cascode structure. NMOS transistors M23 and M24 form a cascode structure. NMOS transistors M27 and M28 form a cascode structure. PMOS transistors M15 and M14 form a cascode structure. PMOS transistors M26 and M25 form a cascode structure. Note that NMOS transistors M16, M20, M23, M27 and PMOS transistors M15, M26 are cascode transistors, which can be advantageously configured to operate in the subthreshold region to reduce the voltage margin consumption, reduce the requirement for the input power supply voltage VDD, and at the same time reduce the power consumption of the error amplifier 230. As cascode transistors, NMOS transistors M17, M21, M24, M28 and PMOS transistors M14, M25 can also be selected to operate in the subthreshold region, but in some cases it may be advantageous for them to operate in the saturation region, which can reduce the noise impact and increase the circuit stability, and is beneficial to improving the core circuit current accuracy. In addition, PMOS transistors M19 and M22 can also be advantageously configured to operate in the subthreshold region to reduce the voltage margin consumption of the bandgap core circuit 240 and avoid the low yield caused by process fluctuations.

[0050] The first cascode current mirror of the bias circuit 220 is configured to provide bias for the NMOS transistors M16, M20, M23, M27 of the error amplifier 230. Specifically, the gates of the NMOS transistors M8, M12 are commonly coupled to the gates of the NMOS transistors M16, M20, M23, M27. Thus, it can be advantageous that the NMOS transistors M16, M20, M23, M27 are also configured to operate in the subthreshold region when the NMOS transistors M8, M12 are configured to operate in the subthreshold region. The second cascode current mirror of the bias circuit 220 is configured to provide bias for the PMOS transistors M15, M26, M18 of the error amplifier 230. Specifically, the gate of the PMOS transistor M11 is commonly coupled to the gates of the PMOS transistors M15, M26, and the gate of the PMOS transistor M10 is commonly coupled to the gate of the PMOS transistor M18. Thus, it can be advantageous that the PMOS transistors M15, M26 are also configured to operate in the subthreshold region when the PMOS transistor M11 is configured to operate in the subthreshold region. Additionally, the gates of the PMOS transistors M14 and M25 can be coupled to each other to achieve self - biasing, thereby advantageously reducing the circuit area.

[0051] Continuing to refer to Figure 3 , the bandgap core circuit 240 includes resistors R3, R4, R5, R6, R7, PMOS transistors M29 and M30, and bipolar junction transistors (which can be abbreviated as BJT transistors in this article) Q1 and Q2. The bandgap core circuit 240 adopts a resistor branch structure (R3, R4, R5, R6, R7) to reduce the margin consumption of the input common - mode voltage of the error amplifier 230 so that the error amplifier 230 can operate at a lower supply voltage VDD. The resistors R3, R4, R6, R7 are used to generate a CTAT current, where R3 is the same as R6, and R4 is the same as R7. The resistor R5 is used to generate a PTAT current. The gates of the PMOS transistors M29 and M30 of the bandgap core circuit 240 are commonly coupled to the output terminal of the cascode amplifier of the second cascode amplifier circuit of the error amplifier 230. The error amplifier 230 clamps the drains of the PMOS transistors M29 and M30 to the same potential through negative feedback. Specifically, it is well - known that if two BJT transistors operate at unequal currents, the difference ΔV BE in their base - emitter voltages is proportional to the absolute temperature. Therefore, when the error amplifier 230 clamps the drains of the PMOS transistors M29 and M30 to the same potential, the base - emitter voltage V BE1 of the BJT transistor Q1 and the base - emitter voltage V BE2 of the BJT transistor Q2 have a difference ΔV BE which is the voltage drop across the resistor R5. Thus, the current flowing through the resistor R5 is a ΔV BEThe generated PTAT current. Additionally, it is well known that the base-emitter voltage V of the BJT transistor BE itself is negatively correlated with temperature. Therefore, the voltage drop across the series resistors R6 and R7 provided by the base-emitter voltage V of the BJT transistor Q2 BE2 is inversely proportional to the absolute temperature. When the error amplifier 230 clamps the drains of the PMOS transistors M29 and M30 to the same potential, the voltage drop across the series resistors R3 and R4 is equal to the voltage drop across the series resistors R6 and R7 and is thus also inversely proportional to the absolute temperature. Therefore, the current flowing through the series resistors R3 and R4 is the CTAT current generated by V BE which is inversely proportional to the absolute temperature. Thus, the PTAT current and the CTAT current can be added together to form a current that is substantially independent of temperature. This current that is substantially independent of temperature can be mirrored to the PMOS transistor M31 whose gate is commonly coupled to the gates of the PMOS transistors M29 and M30. In some alternative embodiments, R3 and R6 can be omitted, and in this case, the gates of the differential input MOS transistor pair of the error amplifier 230 are respectively connected to the drains of the PMOS transistors M29 and M30 to clamp them to the same potential.

[0052] The reference output circuit 250 includes the PMOS transistor M31 and the resistors R8 and R9. The current that is substantially independent of temperature mirrored from the PMOS transistor M29 to the PMOS transistor M31 flows through the resistors R8 and R9, thereby forming a sampling voltage at the upper end of the resistor R8, and this sampling voltage is provided as the input to the first inverter of the startup circuit 210. When the circuit is stable, the sampling voltage at the upper end of the resistor R8 will stabilize at a high potential, and in response, the first inverter and the second inverter of the startup circuit 210 will output a high potential to turn off the first pull-up transistor M5 and the second pull-up transistor M6. At the same time, a stable reference voltage V that is substantially independent of temperature is formed at the upper end of the resistor R9 through the voltage division of the resistors R8 and R9 ref . In some alternative embodiments, R8 can be omitted, and in this case, the V at the upper end of R9 ref can be directly used as the sampling voltage and fed back to the startup circuit 210, or the feedback loop between the reference output voltage 250 and the startup circuit 210 can also be omitted.

[0053] Each component of the bandgap reference voltage source 200 can be replaced with other circuit implementation methods that are currently known or developed in the future. For purposes of non-limiting illustration, Figures 4 to 7 several circuit implementation methods for each component of the bandgap reference voltage source 200 are provided.

[0054] As Figure 4 shown, the startup circuit 210 can also be composed of the PMOS transistors M s1 , M s2 , M s3 , M s4Connected in series. PMOS transistor M s1 、M s2 、M s3 、M s4 The gates and drains of each PMOS transistor are commonly coupled, the source of PMOS transistor M s1 is coupled to the power supply voltage VDD, and the drain of PMOS transistor M s4 provides the output terminal O of the startup circuit for coupling to the bias circuit 220. In Figure 4 example, even after the entire circuit stabilizes, the startup circuit 210 remains on, continuously providing current to a subsequent circuit such as the bias circuit 220.

[0055] Figure 5A and Figure 5B show two configurations of a cascode current mirror, either of which can be used to replace any cascode current mirror in Figure 3 .

[0056] In Figure 5A , the cascode current mirror is composed of NMOS transistors M m1 、M m2 、M m3 、M m4 . The gates of NMOS transistors M m1 、M m3 are commonly coupled. The gates of NMOS transistors M m2 、M m4 are commonly coupled. The respective drains and gates of NMOS transistors M m1 、M m2 are commonly coupled. The sources of NMOS transistors M m1 、M m3 are grounded to GND. The source of NMOS transistor M m2 is coupled to the drain of NMOS transistor M m1 . The source of NMOS transistor M m4 is coupled to the drain of NMOS transistor M m3 . The drain of NMOS transistor M m1 provides the input terminal I of the cascode current mirror, while the drain of NMOS transistor M m4 provides the output terminal O of the cascode current mirror. NMOS transistors M m1 、M m2 form a cascode structure, where it may be advantageous for the cascode transistor M m2 to be configured to operate in the subthreshold region, and the common-gate transistor M m1 may additionally or alternatively be configured to operate in the subthreshold region, but in some cases it may be advantageous for the common-gate transistor M m1 to be configured to operate in the saturation region. NMOS transistors M m3 、M m4A cascode structure is formed, where the cascode transistor M m4 configured to operate in the subthreshold region can be advantageous, while the common-gate transistor M m3 can additionally or alternatively be configured to operate in the subthreshold region, but in some cases the common-gate transistor M m3 configured to operate in the saturation region can be advantageous.

[0057] In Figure 5B , compared with Figure 5A , the NMOS transistor M m5 is added. The drain of the NMOS transistor M m5 is commonly coupled with its gate and additionally provides the input terminal I'. The gate of the NMOS transistor M m5 is also commonly coupled with the gates of the NMOS transistors M m2 , M m4 . The source of the NMOS transistor M m5 is grounded to GND. In addition, in Figure 5B , compared with Figure 5A , the drain of the NMOS transistor M m2 is changed to be connected to the gate of the NMOS transistor M m1 , instead of being commonly coupled with its own gate. In the case where the cascode transistors M m2 , M m4 are configured to operate in the subthreshold region, it can be advantageous to configure the NMOS transistor M m5 to also operate in the subthreshold region. This is beneficial to increasing the circuit stability.

[0058] Figure 6A and Figure 6B show two configurations of a differential-input cascode amplifier, both of which can be alternatively used to implement Figure 3 the error amplifier 230 in

[0059] In Figure 6A , the differential-input cascode amplifier includes a differential-input MOS transistor pair composed of the NMOS transistors M a1 , M a2 , a first cascode amplification circuit composed of the NMOS transistor M a3 and the PMOS transistors M a5 , M a7 , and a second cascode amplification circuit composed of the NMOS transistor M a4 and the PMOS transistors M a6 , M a8 . The differential-input cascode amplifier may also have an NMOS transistor M a9 before the differential-input MOS transistor pair to limit the input current. The two input terminals I1 and I2 of the differential-input cascode amplifier are respectively provided by the NMOS transistor M a1, M a2 is provided by the gate of, and can be used to be respectively coupled to Figure 3 between R3 and R4 and between R6 and R7 of, so as to Figure 3 clamp the drains of M29 and M30 of to the same potential. The two output terminals O1 and O2 of the differential input cascode amplifier are respectively provided by the drains of NMOS transistors M a5 , M a6 and at least one of the output terminals can be used to be coupled to Figure 3 the gates of M29 and M30 of. The PMOS transistors M a5 , M a7 form a cascode structure, wherein, it can be advantageous that the cascode transistor M a5 is configured to operate in the subthreshold region, while the cascode gate transistor M a7 can additionally or alternatively be configured to operate in the subthreshold region, but in some cases it can be advantageous that the cascode gate transistor M a7 is configured to operate in the saturation region. The PMOS transistors M a6 , M a8 form a cascode structure, wherein, it can be advantageous that the cascode transistor M a6 is configured to operate in the subthreshold region, while the cascode gate transistor M a8 can additionally or alternatively be configured to operate in the subthreshold region, but in some cases it can be advantageous that the cascode gate transistor M a8 is configured to operate in the saturation region. Additionally, in Figure 6A , the gate voltages of the NMOS transistors M a3 , M a4 , M a9 , the PMOS transistors M a5 , M a6 , M a7 , M a8 need to be provided by other external circuit elements.

[0060] In Figure 6B , compared with Figure 6A , the gates of the PMOS transistors M a7 , M a8 are commonly coupled and the gate of the PMOS transistor M a7 is coupled to its drain, the gates of the PMOS transistors M a5 , M a6 are commonly coupled and the gate of the PMOS transistor M a5 is coupled to its drain. This self - biasing structure makes it unnecessary to set other external circuit elements to provide gate voltages for these PMOS transistors, thus reducing the circuit area. Additionally, in Figure 6B , the output terminal O is provided by the drain of the PMOS transistor M a6 , which can be used to be coupled to Figure 3The gates of M29 and M30.

[0061] Figure 7 A configuration of the reference voltage generation module is shown, which can be used to alternatively implement Figure 3 the bandgap core circuit 240 and the reference output circuit 250 in Figure 7 In r1 、M r2 、M r3 、M r4 、resistor R r1 、R r2 、R r3 and BJT transistor Q r1 、Q r2 constitute the bandgap core circuit, and PMOS transistors M r5 、M r6 、resistor R r4 constitute the reference output circuit. The cascode current mirror formed by PMOS transistors M r1 、M r2 can replace the PMOS transistor M29 of the bandgap core circuit 240 in Figure 3 , and the cascode current mirror formed by PMOS transistors M r3 、M r4 can replace the PMOS transistor M30 of the bandgap core circuit 240 in Figure 3 . The cascode current mirror formed by PMOS transistors M r5 、M r6 can replace the PMOS transistor M31 of the reference output circuit 250 in Figure 3 . The gates of PMOS transistors M r2 、M r4 、M r6 can be commonly coupled to the output terminal of the cascode amplifier circuit of the error amplifier 230. The gates of PMOS transistors M r1 、M r3 、M r5 are commonly coupled to form a self-bias. The gate of PMOS transistor M r5 is coupled to its drain. The drains of PMOS transistors M r1 、M r3 can be respectively coupled to the gates of the differential input MOS transistor pair of the error amplifier 230 so as to be clamped to the same potential. Based on a similar principle, the current flowing through resistor R r1 is the PTAT current formed by the difference in the base-emitter voltages of BJT transistors Q r1 、Q r2 , and the current flowing through resistor R r3 is for BJT transistor Q r1The CTAT current is formed by the base-emitter voltage of the PMOS tube. The two currents are added to form a current that is basically independent of temperature. This current that is basically independent of temperature flows from the PMOS tube M r3 、M r4 The cascode current mirror is mirrored to the PMOS tube M r5 、M r6 The cascode current mirror is formed, so that the resistor R r4 The upper end of the voltage V is basically independent of temperature. ref . Figure 7 The cascode transistors and / or common gate transistors in the cascode structure may also be configured to operate in the subthreshold region, but it may be advantageous for them to be configured to operate in the saturation region, which may improve circuit stability and enable a stable reference voltage V to be output. ref .

[0062] The above about Figures 3 to 7 A non-limiting example implementation of the bandgap reference voltage source 200 is described, which is not intended to limit the present disclosure to the specific circuit structure disclosed, but is intended to illustrate that the present disclosure can apply a subthreshold working state to the MOS tube in the bias current generating module of the bandgap reference voltage source 200, and is particularly advantageously applied to the common source and common gate structure of the bias current generating module, especially its common source and common gate tube, and is also advantageously applied to the differential input tube of the error amplifier of the bias current generating module. The present disclosure applies a subthreshold region working state to these MOS tubes, so that the bandgap reference voltage source can reduce the requirements for the input power supply voltage, achieve low power consumption and output a low reference voltage, and can assist in reducing the voltage margin loss of the write current limiting circuit in the RRAM write path in the RRAM device, so as to facilitate reducing the working power supply voltage of the RRAM device. In addition, the present disclosure applies a saturation region working state to the remaining MOS tubes, so as to achieve higher current accuracy and greater power supply rejection ratio, and can enable the bandgap reference voltage source to stably provide a reference voltage with a lower temperature coefficient, thereby providing a guarantee for the write reliability of the RRAM.

[0063] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words so used are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or at other orientations), and the relative spatial relationships will be interpreted accordingly.

[0064] In the specification and claims, when an element is referred to as being “on,” “attached” to, “connected” to, “coupled” to, or “in contact” with another element, the element can be directly on, attached directly to, connected directly to, coupled directly to, or in contact directly with the other element, or there can be one or more intervening elements. In contrast, when an element is referred to as being “directly” on, “directly attached” to, “directly connected” to, “directly coupled” to, or “directly in contact” with another element, there will be no intervening elements. In the specification and claims, a feature being disposed “adjacent” to another feature can mean that the feature has a portion that overlaps with the adjacent feature or portions that are above or below the adjacent feature.

[0065] As used herein, the word “exemplary” means “serving as an example, instance, or illustration,” and not as a “model” to be precisely replicated. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the technical field, background art, summary of the invention, or detailed description.

[0066] As used herein, the word “substantially” means including any minute variations caused by defects in design or manufacture, tolerances of devices or elements, environmental effects, and / or other factors. The word “substantially” also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0067] Additionally, for reference purposes only, terms such as “first,” “second,” etc. may also be used herein, and are thus not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical words referring to a structure or element do not imply an order or sequence.

[0068] It should also be understood that when the term “comprising / including” is used herein, it indicates the presence of the stated features, wholes, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or combinations thereof.

[0069] In addition, as used in this application, the words "here", "above", "below", "hereinafter", "above-mentioned" and words of similar import shall refer to the whole of this application rather than to any particular part of this application. Further, unless expressly stated otherwise or otherwise understood in the context in which it is used, conditional language used herein, such as "can", "may", "for example", "such as", etc., is generally intended to mean that certain embodiments include, while other embodiments do not include, certain features, elements and / or states. Thus, such conditional language is not generally intended to imply that one or more embodiments require, in any way, the features, elements and / or states, or whether they include such features, elements and / or states or perform such features, elements and / or states in any particular embodiment.

[0070] In the present disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0071] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0072] Those skilled in the art should appreciate that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed over additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be varied in various other embodiments. However, other modifications, variations and substitutions are also possible. Aspects and elements of all embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Accordingly, this specification and the drawings are to be regarded as illustrative rather than restrictive. In fact, the novel devices, methods and systems described herein may be embodied in various other forms. Further, various omissions, substitutions and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these blocks may be implemented in a variety of different ways.

[0073] The various embodiments of the present disclosure can be described in a progressive manner. For the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In the present disclosure, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0074] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. The various embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A bandgap reference voltage source for an RRAM device, the bandgap reference voltage source being configured to provide a reference voltage for a write current limiting circuit in the RRAM device, the write current limiting circuit being configured to limit the current of the RRAM in the RRAM device during a write process, the bandgap reference voltage source comprising: A startup circuit configured to start the bandgap reference voltage source; A bias circuit configured to provide a bias for an error amplifier; The error amplifier configured to provide negative feedback for a bandgap core circuit; The bandgap core circuit configured to provide a current substantially independent of temperature for a reference output circuit; And The reference output circuit configured to output a reference voltage substantially independent of temperature based on the received current substantially independent of temperature, and wherein at least one of the bias circuit and the error amplifier includes at least one MOS transistor configured to operate in the subthreshold region.

2. The bandgap reference voltage source according to claim 1, wherein At least one of the bias circuit and the error amplifier includes a cascode structure having at least one MOS transistor configured to operate in the subthreshold region.

3. The bandgap reference voltage source according to claim 2, wherein, The cascode transistor in the cascode structure is configured to operate in the subthreshold region.

4. The bandgap reference voltage source according to claim 2 or 3, wherein, The cascode gate transistor in the cascode structure is configured to operate in the subthreshold region.

5. The bandgap reference voltage source according to claim 1, wherein, The first MOS transistor in the bias circuit is configured to operate in the subthreshold region, and the second MOS transistor in the error amplifier biased by the first MOS transistor in the bias circuit is configured to operate in the subthreshold region.

6. The bandgap reference voltage source according to claim 5, wherein, The first MOS transistor is the cascode transistor in the first cascode structure in the bias circuit, and the second MOS transistor is the cascode transistor in the second cascode structure in the error amplifier.

7. The bandgap reference voltage source according to claim 1, wherein, The bias circuit includes a self-biased cascode structure having a first cascode current mirror and a second cascode current mirror, the first cascode current mirror being configured to provide a first bias for a MOS transistor of a first conduction type in the error amplifier, the second cascode structure being configured to provide a second bias for a MOS transistor of a second conduction type in the error amplifier, the first conduction type being different from the second conduction type, wherein in each of the first cascode current mirror and the second cascode current mirror, the cascode transistor is configured to operate in the subthreshold region and the cascode gate transistor is configured to operate in the saturation region.

8. The bandgap reference voltage source according to claim 1, wherein The error amplifier includes a single-stage differential input symmetric cascode transconductance amplifier, the single-stage differential input symmetric cascode transconductance amplifier including a differential input MOS transistor pair, a first cascode amplifier circuit coupled to a first output terminal of the differential input MOS transistor pair, and a second cascode amplifier circuit coupled to a second output terminal of the differential input MOS transistor pair, wherein the single-stage differential input symmetric cascode transconductance amplifier includes at least one MOS transistor configured to operate in the subthreshold region.

9. The bandgap reference voltage source according to claim 8, wherein, The MOS transistors of the differential input MOS transistor pair are configured to operate in the subthreshold region.

10. The bandgap reference voltage source according to claim 8, wherein, Each of the first cascode amplifier circuit and the second cascode amplifier circuit includes a cascode structure having at least one MOS transistor configured to operate in the subthreshold region.

11. The bandgap reference voltage source according to any one of claims 8 to 10, wherein, Each of the first cascode amplifier circuit and the second cascode amplifier circuit includes a cascode current mirror and a cascode amplifier, the cascode current mirror being configured to mirror the current received from the corresponding output terminal of the differential input MOS transistor pair into the cascode amplifier for amplification thereof. Wherein, in each of the cascode current mirror and the cascode amplifier, the cascode transistor is configured to operate in the subthreshold region and the common-gate transistor is configured to operate in the saturation region.

12. A RRAM device, comprising: RRAM; A write current limiting circuit, coupled to the RRAM and configured to limit the current of the RRAM during a write process; And A bandgap reference voltage source according to any one of claims 1 to 11, coupled to the write current limiting circuit and configured to provide a reference voltage for the write current limiting circuit.

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