Multi-phase power supply and phase number control circuit and control circuit thereof

Abstract

The invention discloses a multi-phase power supply and a phase number control circuit and control circuit thereof. The phase number control circuit compares a current sampling signal of the first power level circuit with a phase increasing threshold value and a phase reducing threshold value, generates a phase increasing signal and a phase reducing signal according to a comparison result, and then increases / decreases a count value in each cycle period according to whether logic states of the phase increasing signal and the phase reducing signal increase / decrease. According to the counting value, the starting number of the power level circuits in the multiphase power supply is controlled, complex mathematical operation and a large amount of logic judgment are not needed, the operation speed of multiphase power supply phase increase and decrease control is greatly improved, a system can rapidly adjust the phase number according to load changes, real-time control over the power supply is achieved, and the system reliability is improved. The requirement of quick response of the load to the power supply is met.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and more specifically, to a multi-phase power supply and a phase number control circuit and a control circuit thereof. Background Art

[0002] The exponential growth of the scale of Internet of Things (IoT) cloud services has driven significant advances in data centers, networks, and telecommunications equipment. At the same time, the continued increase in data and information has posed new challenges to the processing efficiency of servers in data centers. Therefore, how to efficiently power and dissipate heat for these devices while minimizing power consumption has become an important issue in the existing power supply technology field.

[0003] Multiphase power supply is a technology that connects multiple power stage circuits in parallel and distributes the switching modulation process to different phases to achieve the adjustment and control of the power supply. The PWM (pulse width modulation) signals between phases in a multiphase power supply can be the same or staggered by a certain phase, so that the fluctuation frequency seen by the output and input is the product of the switching frequency in each phase and the number of phases, thereby reducing the need for filter capacitors and the current impact on the input, while speeding up the response to load changes.

[0004] Figure 1 FIG. 2 shows a schematic circuit diagram of a multi-phase power supply according to the prior art. Figure 1 As shown, the existing multi-phase power supply 100 includes a multi-phase power supply controller 110, a multi-phase power stage circuit 101-103 ( Figure 1 The power stage circuit of each phase includes a driving unit, a transistor T1, a transistor T2, an inductor Ls, a resistor R4 and a capacitor C3. The transistor T1 and the transistor T2 are sequentially coupled in series between the input voltage Vin and the ground. The first end of the inductor Ls is coupled to the middle node of the transistor T1 and the transistor T2, and the second end is connected to the first end of the resistor R4. The first end of the capacitor C3 is coupled to the second end of the resistor R4, and the second end is grounded. The driving unit receives the enable signal ENn. When the enable signal ENn is in an effective state, the driving units in each power stage circuit 101-103 respectively receive the pulse width modulation signals PWM1-PWM3 provided by the multi-phase power supply controller 110, and control the conduction and shutdown of the corresponding transistor according to the received pulse width modulation signal. The output voltages of the multi-phase power stage circuits 101-103 are combined into an output voltage Vout to drive the load RL. When the enable signal ENn is in an invalid state, the driving unit turns off the transistor T1 and the transistor T2, thereby shutting down the power stage circuit of this phase.

[0005] The feedback control circuit 120 includes a resistor R1, a resistor R2, an error amplifier 121, and a signal processing unit 122. The resistor R1 and the resistor R2 are sequentially connected in series between the output voltage Vout and the ground. The negative input terminal of the error amplifier 121 is coupled to the intermediate node of the resistor R1 and the resistor R2 to receive the feedback signal VFB after the output voltage Vout is divided, and its positive input terminal receives the reference voltage signal VREF. The error amplifier 121 is adapted to generate an error amplified signal Vc according to the comparison result of the feedback signal VFB and the reference voltage signal VREF. The signal processing unit 122 processes the error amplified signal Vc, such as amplitude modulation and filtering, to generate a feedback control signal Vc1, and provides the feedback control signal Vc1 to the multi-phase power control circuit 110, so that each PWM controller 111-113 respectively determines the operating sequence of the multi-phase power stage circuits 101-103 according to the feedback control signal Vc1, thereby providing the pulse width modulation signals PWM1-PWM3.

[0006] In the control circuit of the existing multi-phase power conversion circuit and the multi-phase power supply, the error amplified signal Vc is respectively compared with the upper threshold voltage VH and the lower threshold voltage VL to change the effective states of the respective enable signals, thereby controlling the number of power stage circuits that are turned on. For example, when the error amplified signal Vc is greater than the upper threshold voltage VH, a power stage circuit in the off state is switched to the on state; when the error amplified signal Vc is less than the lower threshold voltage VL, a power stage circuit in the on state is switched to the off state. However, when the number of phases is relatively large (for example, 16 phases), the change in the error amplified signal Vc when the number of phases changes is very small. On the one hand, it causes the upper threshold voltage VH and the lower threshold voltage VL to be unable to be accurately set. On the other hand, the low precision of the comparator is also likely to cause control failure. When the multi-phase power supply makes a relatively large phase number switch, such as switching from 16 phases to 15 phases, the above problems are particularly obvious.

[0007] Therefore, an improved control circuit, control method, and multi-phase power supply for a multi-phase power conversion circuit are expected to solve the above problems. Summary of the Invention

[0008] In view of the above problems, the purpose of the present invention is to provide a multi-phase power supply, its phase number control circuit, and control circuit, which can not only reduce the circuit scale and cost of the controller, but also improve the control accuracy of the multi-phase power supply when the number of phases increases or decreases.

[0009] According to an aspect of the present invention, there is provided a phase number control circuit for a multiphase power supply. The multiphase power supply includes a plurality of power stage circuits connected in parallel, each power stage circuit being one phase. The plurality of power stage circuits are configured to switch at least one power transistor within the phase according to a corresponding pulse width modulation signal to jointly convert an input voltage into an output voltage. Wherein, the phase number control circuit includes: a comparison module configured to compare a current sampling signal of a first power stage circuit among the plurality of power stage circuits with a phase increasing threshold and a phase decreasing threshold respectively, and generate a phase increasing signal and a phase decreasing signal according to the comparison results; and a phase number control module configured to judge whether to increase / decrease a count value according to the logic states of the phase increasing signal and the phase decreasing signal in each cycle period to adjust the number of enabled power stage circuits in the multiphase power supply. Wherein, the phase number control module is configured to increase / decrease the count value in each cycle period when the logic states of the phase increasing signal and the phase decreasing signal are the same, and maintain the count value unchanged when the logic states of the phase increasing signal and the phase decreasing signal are different.

[0010] Optionally, the phase number control circuit further includes: a phase processing module configured to control the phase number control module to operate for a dead time after each increase / decrease of the count value. During the dead time, the phase number control module does not perform the operation of increasing / decreasing the count value.

[0011] Optionally, the phase processing module is further configured to control the phase number control module not to perform the operation of decreasing the count value when only one power stage circuit is enabled in the multiphase power supply, and the phase processing module is further configured to control the phase number control module not to perform the operation of increasing the count value when all power stage circuits in the multiphase power supply are enabled.

[0012] Optionally, the phase number control module includes: a first logic unit configured to perform an exclusive OR logic operation on the phase increasing signal and the phase decreasing signal to obtain a first logic signal; a second logic unit configured to perform an AND logic operation on the phase increasing signal and the phase decreasing signal to obtain a second logic signal; a synchronization signal generation unit configured to generate a synchronization signal according to the first logic signal, a first pulse width modulation signal of the first power stage circuit, and a count control signal from the phase processing module; an up / down counter configured to perform an up / down operation according to the pulse edges of the second logic signal and the synchronization signal to adjust the count value; and a logic unit configured to perform a logic operation on the output of the up / down counter to control the effective states of a plurality of phase number control signals, each phase number control signal being configured to control the enabling of a corresponding number of power stage circuits.

[0013] Optionally, the first logic unit is configured to generate the first logic signal at a high level when the logic states of the increment phase signal and the decrement phase signal are different, and generate the first logic signal at a low level when the logic states of the increment phase signal and the decrement phase signal are the same.

[0014] Optionally, the synchronization signal generation unit is configured to generate a valid pulse of the synchronization signal according to the first pulse width modulation signal when both the first logic signal and the count control signal are at a low level, and set the synchronization signal to a high level when at least one of the first logic signal and the count control signal is at a high level.

[0015] Optionally, the synchronization signal generation unit includes: a D flip-flop, where the data terminal and the negative output terminal of the D flip-flop are connected, the clock terminal is configured to receive the first pulse width modulation signal, and the reset terminal is configured to receive the first logic signal; and a first OR gate, where the first input terminal of the first OR gate is configured to receive the count control signal, the second input terminal is connected to the positive output terminal of the D flip-flop, and the output terminal is configured to provide the synchronization signal.

[0016] Optionally, the output of the up / down counter includes a multi-bit binary number, and the logic unit includes at least one of a NOR gate, an AND gate, or an AND gate with a negative input terminal.

[0017] Optionally, at least the first phase number control signal, the second phase number control signal, and a plurality of third phase number control signals are included in the plurality of phase number control signals. When the first phase number control signal is valid, only the first power stage circuit among the plurality of power stage circuits is turned on. When the second phase number control signal is valid, all of the plurality of power stage circuits are turned on. Wherein, the phase processing module includes: a first AND gate, a first input terminal of the first AND gate is configured to receive the first phase number control signal, a second input terminal is configured to receive an inverted signal of the second logic signal, and the first AND gate is configured to set the count control signal to a high level when the first phase number control signal is at a high level and the second logic signal is at a low level. The phase processing module further includes: a second OR gate, a first input terminal of the second OR gate is configured to receive the phase increment signal, a second input terminal is configured to receive the phase decrement signal; and a second AND gate, a first input terminal of the second AND gate is configured to receive the second phase number control signal, a second input terminal is connected to an output terminal of the second OR gate, and the second AND gate is configured to set the count control signal to a high level when the phase increment signal, the phase decrement signal, and the second phase number control signal are all at a high level. The phase processing module further includes: a plurality of dead zone control units corresponding to the plurality of third phase control signals, and each dead zone control unit includes: a one-sided delay unit, an input terminal of the one-sided delay unit is configured to receive a corresponding third phase control signal; and a NOR gate, a first input terminal of the NOR gate is connected to an output terminal of the one-sided delay unit, a second input terminal is configured to receive an inverted signal of a corresponding third phase control signal, and the NOR gate is configured to set the count control signal to a high level when a corresponding third phase control signal is at a high level and set the count control signal to a low level after the dead zone time ends.

[0018] Optionally, the phase number control circuit further includes: a current sampling module, configured to sample the switching node voltage of the first power stage circuit to generate the current sampling signal, wherein the current sampling module includes: a first switch, a first end of the first switch is connected to the switching node voltage of the first power stage circuit, and a control end of the first switch is configured to receive a first pulse width modulation signal of the first power stage circuit; a first resistor, a first end of the first resistor is connected to a second end of the first switch; a first capacitor, a first end of the first capacitor is connected to a second end of the first resistor, and a second end of the first capacitor is grounded; a second resistor, a first end of the second resistor is connected to the second end of the first resistor; an operational amplifier, a positive input terminal of the operational amplifier is connected to a second end of the second resistor, and an output terminal of the operational amplifier is configured to provide the current sampling signal; a third resistor, a first end of the third resistor is connected to a negative input terminal of the operational amplifier, and a second end of the third resistor is grounded; and a fourth resistor, the fourth resistor is connected between the positive input terminal and the output terminal of the operational amplifier.

[0019] Optionally, the comparison module includes: a first comparator, a positive input terminal of the first comparator is connected to the current sampling signal, a negative input terminal of the first comparator is connected to the phase increasing threshold, and an output terminal of the first comparator is configured to provide the phase increasing signal; and a second comparator, a positive input terminal of the second comparator is connected to the current sampling signal, a negative input terminal of the second comparator is connected to the phase decreasing threshold, and an output terminal of the second comparator is configured to provide the phase decreasing signal.

[0020] According to another aspect of the present invention, there is provided a control circuit for a multi-phase power supply, the multi-phase power supply including a plurality of power stage circuits connected in parallel, each power stage circuit being a phase, the plurality of power stage circuits being configured to switch at least one power transistor within the phase according to corresponding pulse width modulation signals to jointly convert an input voltage into an output voltage, the control circuit including: a switch control circuit, configured to generate the pulse width modulation signals of the plurality of power stage circuits; and the above-mentioned phase number control circuit.

[0021] According to another aspect of the present invention, there is provided a multi-phase power supply, including: a plurality of power stage circuits connected in parallel, each power stage circuit being a phase, the plurality of power stage circuits being configured to switch at least one power transistor within the phase according to corresponding pulse width modulation signals to jointly convert an input voltage into an output voltage; and the above-mentioned control circuit.

[0022] In summary, in the phase number control circuit of the polyphase power supply provided by the embodiment of the present invention, the current sampling signal of the first power stage circuit is compared with the phase increasing threshold and the phase decreasing threshold, and the phase increasing signal and the phase decreasing signal are generated according to the comparison result. Then, in each cycle period, the count value is increased / decreased according to the logic states of the phase increasing signal and the phase decreasing signal, and then the number of enabled power stage circuits in the polyphase power supply is controlled according to the count value. Without complex mathematical operations and a large number of logical judgments, the operation speed of the polyphase power supply for phase increase and decrease control is greatly improved, enabling the system to quickly adjust the phase number according to the load change, realizing real-time control of the power supply, and meeting the requirement of the load for fast response of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features and advantages of the present invention will become more apparent. In the drawings:

[0024] Figure 1 A schematic circuit diagram of a polyphase power supply according to the prior art is shown.

[0025] Figure 2 A schematic circuit diagram of a polyphase power supply according to an embodiment of the present invention is shown.

[0026] Figure 3 A schematic circuit diagram of a current sampling module according to an embodiment of the present invention is shown.

[0027] Figure 4 A schematic circuit diagram of a comparison module according to an embodiment of the present invention is shown.

[0028] Figure 5 A schematic circuit diagram of a phase number control module according to an embodiment of the present invention is shown.

[0029] Figure 6 A schematic circuit diagram of a phase processing module according to an embodiment of the present invention is shown.

[0030] Figure 7 A schematic waveform diagram of the polyphase power supply during the phase increase and decrease process according to an embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0032] It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one component or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or when an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0033] In the present application, a switching transistor is a transistor that operates in a switching mode to provide a current path and includes one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switching transistor are respectively the high-potential end and the low-potential end on the current path, and the control end is used to receive a driving signal to control the on and off of the switching transistor.

[0034] The present invention can be presented in various forms, and some examples will be described below.

[0035] Figure 2 A schematic circuit diagram of a multi-phase power supply according to an embodiment of the present invention is shown. The multi-phase power supply according to the embodiment of the present invention includes N power stage circuits and a control circuit arranged in parallel, where N is an integer greater than 1, each power stage circuit is a phase, and the N power stage circuits share the same control loop. The control circuit is used to control the working timing and charging time of the N power stage circuits to jointly convert the input voltage Vin into the output voltage Vout.

[0036] Specifically, referring to Figure 2 , the multi-phase power supply 200 includes N power stage circuits 201-20N arranged in parallel (N is the number of phases set for the multi-phase power supply, and N is an integer greater than 1), and taking each power stage circuit as a buck converter as an example for illustration.

[0037] Taking the power stage circuit 201 as an example, each power stage circuit includes a driver DRV, a switching transistor T1 (also known as the high-side switching transistor), a switching transistor T2 (also known as the low-side switching transistor), and an inductor Lx. Among them, the drains of the high-side switching transistor T1 and the low-side switching transistor T2 are connected to each other, and the common terminal of the two forms a switching node SW. The source of the low-side switching transistor T2 is connected to the ground terminal, and the source of the high-side switching transistor T1 is connected to the input voltage Vin. The first end of the inductor Lx is connected to the switching node Lx, and the second end of the inductor Lx is connected to the output voltage Vout. The drivers DRV in each of the power stage circuits 201-20N respectively receive the pulse width modulation signal PWM provided by the control circuit, and control the on and off of the corresponding power switching transistors according to the received pulse width modulation signal PWM. It should be understood that in this embodiment, the high-side switching transistor T1 is the main power transistor, and the low-side switching transistor T2 is the synchronous rectifier transistor. The switching transistors T1 and T2 can be any type of field effect transistor, such as a metal oxide semiconductor field effect transistor (MOSFET). Within the scope not departing from the teachings of the present invention, other types of field effects and / or other types of transistors known to those skilled in the art can also be used.

[0038] It should be understood that although each power stage circuit can be understood with reference to Figure 2 the structure of the power stage circuit 201 in. And in this embodiment, each phase inductor corresponding to each of the N power stage circuits 201-20N can be discrete or mutually coupled (for example, the first-phase inductor and the second-phase inductor are coupled; the third-phase inductor and the fourth-phase inductor are coupled, and so on). At the same time, although the power stage circuit 201 is described as having a buck topology layout, the technical solution of the present invention can be applied to any type of layout design, such as boost, flyback, buck-boost, Cuk, Sepic, and Zeta.

[0039] The multi-phase power supply 200 further includes an output capacitor Cout, which is disposed between the output terminal and the ground terminal of the multi-phase power supply 200 to generate an output voltage Vout across its two ends.

[0040] Specifically, the control circuit includes a feedback control circuit 210, a switching control circuit 220, and a phase number control circuit 230. Among them, the feedback control circuit 210 is used to generate a feedback control signal Vc1 according to the feedback signal FB of the output voltage Vout and the reference voltage signal VREF. The switching control circuit 220 is used to generate a plurality of pulse width modulation signals PWM1-PWMN according to the feedback control signal Vc1 to control the working timing of the N power stage circuits 201-20N.

[0041] Exemplarily, any existing constant on-time control (COT) scheme can be adopted to control the multi-phase power supply. Under this COT control scheme, there are various implementation manners of the feedback control circuit 210. For example, in one embodiment, the reference voltage signal VREF is directly compared with the feedback signal FB to generate the feedback control signal Vc1. In another embodiment, the error between the reference voltage signal VREF and the feedback signal FB is compensated to obtain a feedback compensation signal, and the feedback compensation signal is compared with a current feedback signal characterizing the change trend of the sum of the inductive currents of each phase, so as to generate the feedback control signal Vc1, where the current feedback signal can be a current sampling signal characterizing the inductive current of each phase obtained by sampling, or a current ripple signal simulating the change of the inductive current of each phase, that is, any control manner and its deformation of COT in the prior art can be applied herein. In addition, control manners of power converters in other prior arts, such as adaptive on-time control (compared with COT, the on-time Ton is not fixed but is adjusted according to the input voltage and / or output voltage), are also applicable to this solution, that is, the present invention places no limitation on the control manner.

[0042] Further, the phase number control circuit 230 is configured to control the number of power stage circuits turned on in each cycle period of the multi-phase power supply 200. Exemplarily, the phase number control circuit 230 is configured to provide a plurality of phase number control signals PH1-PHN to the switch control circuit 220, and the switch control circuit 220 is configured to generate corresponding pulse width modulation signals PWM according to the received phase number control signals PH to control the corresponding number of power stage circuits to be turned on in this cycle period. For example, when the phase number control signal PH1 is valid, the switch control circuit 220 provides a valid pulse of the pulse width modulation signal PWM1 in the current cycle period to cause the first power stage circuit 201 to be turned on in the current cycle period. When the phase number control signal PH2 is valid, the switch control circuit 220 provides valid pulses of the pulse width modulation signals PWM1 and PWM2 in the current cycle period to cause the first power stage circuit 201 and the second power stage circuit 202 to be turned on in the current cycle period, and so on. When the phase number control signal PHN is valid, the switch control circuit 220 provides valid pulses of the pulse width modulation signals PWM1-PWMN in the current cycle period to cause N power stage circuits to be turned on in the current cycle period.

[0043] Further, the phase number control circuit 230 has a count value. The phase number control circuit 230 is configured to determine whether to increase / decrease the count value according to the current sampling signal Vs1 of the first power stage circuit 201 in each cycle period, so as to implement the phase increasing / phase decreasing operation. For example, since the multi-phase power supply has a current sharing function, that is, the current of each phase of the multi-phase power supply is equal during operation, therefore, by using the current sampling signal of the first power stage circuit of the multi-phase power supply to determine whether to increase or decrease the phase can reduce costs and improve efficiency. For example, the phase number control circuit 230 is configured to compare the current sampling signal Vs1 with an increasing phase threshold ILH and a decreasing phase threshold ILL in each cycle period. When the current sampling signal Vs1 is greater than the increasing phase threshold ILH, the count value is increased, and when the current sampling signal Vs1 is less than the decreasing phase threshold ILL, the count value is decreased.

[0044] Further, the phase number control circuit 230 includes a current sampling module 231, a comparison module 232, a phase number control module 233, and a phase processing module 234.

[0045] Among them, the current sampling module 231 is configured to generate the current sampling signal Vs1 according to the pulse width modulation signal PWM1 and the switch node voltage Vsw1 of the first power stage circuit 201. Further, the current sampling module 231 is configured to sample the switch node voltage Vsw1 of the first power stage circuit 201 when the invalid pulse (for example, a low-level pulse) of the pulse width modulation signal PWM1 arrives, so as to generate the current sampling signal Vs1.

[0046] The comparison module 232 is configured to compare the current sampling signal Vs1 with the increasing phase threshold ILH and the decreasing phase threshold ILL respectively, and generate an increasing phase signal P1 and a decreasing phase signal P2 according to the comparison results. In an exemplary embodiment, the increasing phase signal P1 and the decreasing phase signal P2 have different logic level states, and the increasing phase threshold ILH is greater than the decreasing phase threshold ILL. Therefore, when the current sampling signal Vs1 is greater than the increasing phase threshold ILH, both the increasing phase signal P1 and the decreasing phase signal P2 are in a logic high level state. When the current sampling signal Vs1 is less than the decreasing phase threshold ILL, both the increasing phase signal P1 and the decreasing phase signal P2 are in a logic low level state. When the current sampling signal Vs1 is between the increasing phase threshold ILH and the decreasing phase threshold ILL, the increasing phase signal P1 is in a logic low level, and the decreasing phase signal P2 is in a logic high level.

[0047] The phase number control module 233 is used to judge whether to increase / decrease the count value according to the logic states of the phase increase signal P1 and the phase decrease signal P2 in each cycle, so as to adjust the number of power stage circuits turned on in the multi-phase power supply 200. Exemplarily, the phase number control module 233 is used to, in each cycle, when the logic states of the phase increase signal P1 and the phase decrease signal P2 are different, not perform the increase / decrease operation on the count value, that is, keep the count value unchanged; while when the logic states of the phase increase signal P1 and the phase decrease signal P2 are the same, perform the increase / decrease operation on the count value to perform the phase addition / phase subtraction operation in the current cycle.

[0048] Further, as described above, when both the phase increase signal P1 and the phase decrease signal P2 are at the logic high level, it indicates that the current sampling signal Vs1 is greater than the phase increase threshold ILH. Therefore, at this time, the multi-phase power supply needs to perform the phase addition operation; when both the phase increase signal P1 and the phase decrease signal P2 are at the logic low level, it indicates that the current sampling signal Vs1 is less than the phase decrease threshold ILL. Therefore, at this time, the multi-phase power supply needs to perform the phase subtraction operation. Accordingly, the phase number control module 233 is further used to decrease the count value when both the phase increase signal P1 and the phase decrease signal P2 are at the logic low level; and increase the count value when both the phase increase signal P1 and the phase decrease signal P2 are at the logic high level.

[0049] The phase processing module 234 is used to implement different delay or hold processing for different phases of the multi-phase power supply to ensure the stable operation of the multi-phase power supply 200. Exemplarily, the phase processing module 234 is used to control the phase number control module 233 to work in a dead time after each increase / decrease of the count value. During the dead time, the phase number control module 233 no longer performs the operation of increasing / decreasing the count value. For example, when the number of power stage circuits to be turned on in the multi-phase power supply 200 increases from 1 to 2, the phase processing module 234 controls the phase number control module 233 to work in the dead time. During the dead time, even if the phase processing module 234 detects that phase addition or phase subtraction is required, it will not adjust the count value to ensure the balanced output current of the 2 turned-on power stage circuits. Exemplarily, the dead time is at least greater than 1 switching cycle. In an exemplary embodiment, the dead time is equal to 10 switching cycles.

[0050] Further, the phase processing module 234 is further used to control the phase number control module 233 not to perform the operation of decreasing the count value when only one power stage circuit is turned on in the multi-phase power supply, and control the phase number control module 233 not to perform the operation of increasing the count value when all the power stage circuits in the multi-phase power supply are turned on.

[0051] In this embodiment, the switch control circuit 220 is configured to increase the phase in ascending order according to the sequence numbers of multiple power stage circuits, and decrease the phase in descending order. For example, when the first power stage circuit 201 is turned on, if the switch control circuit 220 detects that the phase number control signal PH2 is valid in a certain cycle, the switch control circuit 220 controls the first power stage circuit 201 and the second power stage circuit 202 in the multiple power stage circuits to be turned on. If the switch control circuit 220 detects that the phase number control signal PH3 is valid in a subsequent cycle, the switch control circuit 220 controls the power stage circuits 201 - 203 to be turned on, and so on.

[0052] Figure 3 The schematic circuit diagram of the current sampling module 231 according to an embodiment of the present invention is shown. As Figure 3 shown, the current sampling module 231 of this embodiment includes a switch S1, resistors R1 - R4, a capacitor C1, and an operational amplifier 2311. One end of the switch S1 is connected to the switch node voltage Vsw1 of the first power stage circuit 201. The control end of the switch S1 is configured to receive a pulse width modulation signal PWM1. The second end of the switch S1 is connected to the first end of the resistor R1. The second end of the resistor R1 is connected to the first end of the capacitor C1 and the first end of the resistor R2. The second end of the capacitor C1 is grounded. The second end of the resistor R2 is connected to the positive input terminal of the operational amplifier 2311. One end of the resistor R3 is connected to the negative input terminal of the operational amplifier 2311. The other end of the resistor R3 is grounded. The resistor R4 is connected between the positive input terminal and the output terminal of the operational amplifier 2311. The output terminal of the operational amplifier 2311 is configured to output the current sampling signal Vs1.

[0053] According to the previous description, it can be known that the first power stage circuit 201 is always in the on state in each cycle. Therefore, the phase number control circuit 230 of this embodiment can accurately obtain the inductor current situation of each phase power stage circuit according to the switch node voltage Vsw1 of the first power stage circuit 201. By way of example, when the pulse width modulation signal PWM1 flips to a low level, the switch S1 conducts, and the switch node voltage Vsw1 is filtered by the RC filter network composed of the resistor R1, the resistor R2, and the capacitor C1. Then, the filtered voltage is inversely proportionally amplified by the operational amplifier 2311. Finally, the current sampling signal Vs1 representing the inductor current situation of each phase power stage circuit can be obtained. Set the coefficient of the inverting proportional amplification circuit formed by the operational amplifier 2311 to be k, and the on - resistance of the synchronous power transistor in the first power stage circuit to be R. The circuit is initially in the default state where only the first power stage circuit is in the on state. Then the load current at this time is Vs1 / (k*R). When the synchronous power transistor in the first power stage circuit is turned off, the current sampling circuit 231 is in the hold state.

[0054] Figure 4 Shows a schematic circuit diagram of the comparison module 232 according to an embodiment of the present invention. As Figure 4 shown, the comparison module 232 of this embodiment includes a comparator 2321 and a comparator 2322. Among them, the positive input terminal of the comparator 2321 is connected to the current sampling signal Vs1, the negative input terminal of the comparator 2321 is connected to the phase increase threshold ILH, and the output terminal of the comparator 2321 is used to output the phase increase signal P1. The positive input terminal of the comparator 2322 is connected to the current sampling signal Vs1, the negative input terminal of the comparator 2322 is connected to the phase decrease threshold ILL, and the output terminal of the comparator 2322 is used to output the phase decrease signal P2.

[0055] Figure 5 Shows a schematic circuit diagram of the phase number control module 233 according to an embodiment of the present invention. It should be noted that in the following embodiments, a 4-phase power supply is taken as an example for illustration. The phase number control circuit 230 of the embodiments of the present invention can also be applied to multi-phase power supplies with more or fewer power stage circuits, such as 8-phase power supplies, 16-phase power supplies, etc. The present invention does not limit this.

[0056] As Figure 5 shown, the phase number control module 233 of this embodiment includes a logic unit 2331, a logic unit 2332, a synchronization signal generation unit 2333, an addition and subtraction counter 2334, and a logic unit 2335.

[0057] Among them, the logic unit 2331 is implemented by an exclusive OR gate, for example, and is used to perform an exclusive OR logical operation on the phase increase signal P1 and the phase decrease signal P2 to obtain a logic signal Q1. For example, when the logic states of the phase increase signal P1 and the phase decrease signal P2 are different (for example, one signal is high level and the other signal is low level), the logic signal Q1 is high level, and when the logic states of the phase increase signal P1 and the phase decrease signal P2 are the same (for example, both signals are high level or both signals are low level), the logic signal Q1 is low level.

[0058] The logic unit 2332 is implemented by an AND gate, for example, and is used to perform an AND logical operation on the phase increase signal P1 and the phase decrease signal P2 to obtain a logic signal Q2. For example, when both the phase increase signal P1 and the phase decrease signal P2 are high level, the logic signal Q2 is high level, and when one of the phase increase signal P1 and the phase decrease signal P2 is low level, the logic signal Q2 is low level.

[0059] The synchronization signal generation unit 2333 is configured to generate a synchronization signal Q3 according to the logic signal Q1, the pulse width modulation signal PWM1, and the count control signal CTL from the phase processing module 234. Exemplarily, the synchronization signal generation unit 2333 is configured to generate a valid pulse of the synchronization signal Q3 according to the pulse width modulation signal PWM1 when both the logic signal Q1 and the count control signal CTL are at a low level, that is, the rising edge of the synchronization signal Q3 is synchronized with the rising edge of the pulse width modulation signal PWM1. When one of the logic signal Q1 and the count control signal CTL is at a high level, the synchronization signal Q3 is set to a high level.

[0060] Further, the synchronization signal generation unit 2333 includes a D flip-flop DFF1 and an OR gate OR1. Among them, the data terminal and the negative output terminal of the D flip-flop DFF1 are connected. The clock terminal of the D flip-flop DFF1 is used to receive the pulse width modulation signal PWM1. The reset terminal of the D flip-flop DFF1 is used to receive the logic signal Q1. The output terminal of the D flip-flop is connected to one input terminal of the OR gate OR1. The other input terminal of the OR gate OR1 is used to receive the count control signal CTL. The output terminal of the OR gate OR1 is used to provide the synchronization signal Q3.

[0061] Exemplarily, in the case where the count control signal CTL is at a low level, when the logic signal Q1 is at a high level, the D flip-flop DFF1 is reset, and the output of the D flip-flop DFF1 is always at a low level. When the logic signal Q1 is at a low level, the reset state of the D flip-flop DFF1 is cancelled. When the rising edge of the pulse width modulation signal PWM1 arrives, the output of the D flip-flop DFF1 flips to a high level, that is, the synchronization signal Q3 also flips to a high level.

[0062] The up / down counter 2334 is configured to perform an up / down operation according to the level state of the logic signal Q2 and the pulse edge of the synchronization signal Q3 to adjust the count value. Exemplarily, the up / down counter 2334 is configured to subtract 1 from the count value whenever the rising edge of the synchronization signal Q3 is detected when the logic signal Q2 is at a low level, and add 1 to the count value whenever the rising edge of the synchronization signal Q3 is detected when the logic signal Q2 is at a high level.

[0063] The logic unit 2335 is used to perform a logic operation on the output of the addition and subtraction counter 2334 to control the active states of a plurality of phase control signals PH1 - PH4. By way of example, the output of the addition and subtraction counter 2334 includes a multi-bit binary number. Taking a 4-phase power supply as an example, the output of the addition and subtraction counter 2334 includes 2-bit binary numbers D1 and D2. Of course, the present invention is not limited thereto. In other embodiments, those skilled in the art can adjust the output of the addition and subtraction counter 2334 according to specific circumstances. For example, in an 8-phase power supply, the output of the addition and subtraction counter 2334 is adjusted to 3-bit binary numbers D1 - D3, and in a 16-phase power supply, the output of the addition and subtraction counter 2334 is adjusted to 4-bit binary numbers D1 - D4, etc.

[0064] Further, the logic unit 2335 includes at least one of a NOR gate, an AND gate, or an AND gate with a negative input terminal. Taking a 4-phase power supply as an example, both outputs D1 and D2 of the addition and subtraction counter 2334 have two logic states, namely "0" (e.g., logic low level) and "1" (e.g., logic high level). Therefore, D1 and D2 constitute 4 logic states, that is, (D2, D1) has 4 states: (0, 0), (0, 1), (1, 0), and (1, 1). Assume that the first power stage circuit 201 is turned on when D2 and D1 are (0, 0), the first 2 power stage circuits 201 and 202 are turned on when D2 and D1 are (0, 1), the first 3 power stage circuits 201 - 203 are turned on when D2 and D1 are (1, 0), and so on. When D2 and D1 are (1, 1), all the power stage circuits 201 - 204 are turned on. Thus, the Figure 5 logic unit 2335 can be obtained.

[0065] As Figure 5 shown, the logic unit 2335 includes a NOR gate NOR1 and AND gates AND1 - AND3. Among them, the input terminals of the NOR gate NOR1 are used to receive signals D1 and D2, and the output terminal of the NOR gate NOR1 is used to output a phase control signal PH1; the positive input terminal of the AND gate AND1 receives signal D1, the negative input terminal of the AND gate AND1 is used to receive signal D2, and the output terminal of the AND gate AND1 is used to output a phase control signal PH2; the negative input terminal of the AND gate AND2 is used to receive signal D1, the positive input terminal of the AND gate AND2 is used to receive signal D2, and the output terminal of the AND gate AND2 is used to output a phase control signal PH3; both input terminals of the AND gate AND3 are used to receive signals D1 and D2, and the output terminal of the AND gate AND3 is used to output a phase control signal PH4.

[0066] Exemplarily, when both signals D1 and D2 are 0, the phase number control signal PH1 is at a high level, and the remaining phase number control signals are at a low level, then the first power stage circuit 201 in the multiphase power supply 200 is turned on; when signal D1 is 1 and signal D2 is 0, the phase number control signal PH2 is at a high level, and the remaining phase number control signals are at a low level, then the power stage circuits 201 and 202 in the multiphase power supply 200 are turned on, and so on. When both signals D1 and D2 are 1, the phase number control signal PH4 is at a high level, and the remaining phase number control signals are at a low level, then all the power stage circuits 201-204 in the 4-phase power supply are turned on.

[0067] Figure 6 Shows a schematic circuit diagram of a phase processing module according to an embodiment of the present invention. As Figure 6 shown, the phase processing module 234 of this embodiment includes AND gates AND4 and AND5, OR gates OR2 and OR3, NOR gates NOR2 and NOR3, and dead zone control units 2341 and 2342. It should be noted that this embodiment takes a 4-phase power supply as an example for illustration. Therefore, the OR gate OR3 is a 4-input OR gate circuit. Of course, the present invention is not limited thereto. For a 6-phase power supply or an 8-phase power supply, the OR gate OR3 can also be correspondingly set to 6 inputs or 8 inputs.

[0068] Among them, one input terminal of the AND gate AND4 is used to receive the phase number control signal PH1, and the other input terminal of the AND gate AND4 is used to receive the inverted signal of the logic signal Q2. The output terminal of the AND gate AND4 is connected to the first input terminal of the OR gate OR3, and the output terminal of the OR gate OR3 is used to output the count control signal CTL. Among them, when the phase number control signal PH1 is at a high level and the logic signal Q2 is at a low level, the output of the AND gate AND4 is at a high level. Therefore, the count control signal CTL is set to a high level, so that when only one power stage circuit in the multiphase power supply 200 is turned on, it can be controlled that the phase number control module 233 no longer performs the operation of reducing the count value.

[0069] Further, one input terminal of the OR gate OR2 is used to receive the positive phase signal P1, and the other input terminal of the OR gate OR2 is used to receive the negative phase signal P2. The output of the OR gate OR2 is connected to one input terminal of the AND gate AND5. The other input terminal of the AND gate AND5 is used to receive the phase number control signal PH4. The output terminal of the AND gate AND5 is connected to the second input terminal of the OR gate OR3. Wherein, when the phase number control signal PH4 is at a high level, and both the positive phase signal P1 and the negative phase signal P2 are at high levels, the output of the AND gate AND5 is at a high level, and then the count control signal CTL is set to a high level, so that when all the power stage circuits in the polyphase power supply 200 are turned on, it can be controlled that the phase number control module 233 no longer performs the operation of increasing the count value.

[0070] Further, the dead zone control units 2341 and 2342 are respectively used to receive the phase number control signals PH2 and PH3, and set the count control signal CTL to a high level when the phase number control signal PH2 or PH3 is at a high level, and the high level time of the count control signal CTL is equal to the dead zone time.

[0071] Further, the circuit structures of the dead zone control units 2341 and 2342 are the same. Exemplarily, the dead zone control unit 2341 includes a single-sided delay unit DEL1 and a NOR gate NOR2. Wherein, the input of the single-sided delay unit DEL1 is connected to the phase number control signal PH2, the output of the single-sided delay unit DEL1 is connected to one input terminal of the NOR gate NOR2, the other input terminal of the NOR gate NOR2 is used to receive the inverted phase signal of the phase number control signal PH2, and the output terminal of the NOR gate NOR2 is connected to the third input terminal of the OR gate OR3. The dead zone control unit 2342 includes a single-sided delay unit DEL2 and a NOR gate NOR3. Wherein, the input of the single-sided delay unit DEL2 is connected to the phase number control signal PH3, the output of the single-sided delay unit DEL2 is connected to one input terminal of the NOR gate NOR3, the other input terminal of the NOR gate NOR3 is used to receive the inverted phase signal of the phase number control signal PH3, and the output terminal of the NOR gate NOR3 is connected to the fourth input terminal of the OR gate OR3.

[0072] Further, the phase processing module 234 of this embodiment has the same working principle for the phase number control signals PH2 and PH3. Hereinafter, the phase number control signal PH2 will be taken as an example for illustration. When the phase number control signal PH2 changes from low level to high level, the output of the NOR gate NOR2 is high level, and then the count control signal CTL is set to high level, so that the phase number control module 233 no longer performs the phase increasing or decreasing operation. After the dead time ends, the output of the NOR gate NOR2 and the count control signal CTL are inverted to low level, and then the phase number control module 233 continues to perform the phase increasing or decreasing operation. Thus, after the multi-phase power supply 200 of this embodiment turns on the first and second power stage circuits, it can delay for a period of time. During this period, after the currents of the first and second power stage circuits are balanced, the phase increasing / decreasing operation is continued, improving the current balance and stability of the multi-phase power supply.

[0073] Figure 7 FIG. shows a schematic waveform diagram of the multi-phase power supply 200 according to an embodiment of the present invention during the phase increasing and decreasing process. Among them, the multi-phase power supply 200 performs a phase increasing operation between time t1 - t3, and the multi-phase power supply 200 performs a phase decreasing operation between time t4 - t6. The following will be combined with Figures 2 to 7 to illustrate the working principle of the phase number control circuit for a 4-phase power supply according to an embodiment of the present invention.

[0074] Specifically, as Figure 7 shown, in the initial state of the circuit, the phase number control signal PH1 is at high level, while the phase number control signals PH2 - PH4 are all at low level. Therefore, only the first power stage circuit 201 in the multi-phase power supply 200 is in the on state, and the remaining power stage circuits are all shielded.

[0075] As the load increases, at time t1, the current sampling signal Vs1 rises to the phase increasing threshold ILH. Therefore, both the phase increasing signal P1 and the phase decreasing signal P2 are at high level, the reset terminal of the D flip-flop DFF1 is at low level, and the D flip-flop DFF1 exits the reset state. At the same time, a pulse is generated at the output terminal of the D flip-flop DFF1 under the action of the pulse width modulation signal PWM1. Since the count control signal CTL is at low level, a rising edge of a pulse signal is synchronously generated on the synchronous signal Q3. Then, the up / down counter 2335 adds 1 to the count value according to the pulse edge of the synchronous signal Q3, making the phase number control signal PH2 become high level, and the remaining phase number control signals become low level. Therefore, both the first power stage circuit 201 and the second power stage circuit 202 in the multi-phase power supply 200 are turned on. After adding one phase of the power stage circuit, the inductor current decreases, so the current sampling signal Vs1 decreases accordingly.

[0076] As the load continues to increase, at time t2, the current sampling signal Vs1 rises to the phase increase threshold ILH again, so the phase number control circuit 230 repeats the above process, so that the count value of the up-down counter 2335 is increased by 1 again, so the phase number control signal PH3 becomes a high level, so that the power stage circuits 201-203 in the multi-phase power supply 200 are all turned on.

[0077] As the load increases again, at time t3, the current sampling signal Vs1 rises to the phase increase threshold ILH again, and at this time, the phase number control circuit 230 makes the count value of the up-down counter 2335 increase by 1 again, so the phase number control signal PH4 becomes high level, and the power stage circuits 201-204 in the multi-phase power supply 200 are all turned on. After all the power stage circuits in the multi-phase power supply 200 are turned on, even if the current sampling signal Vs1 rises to the phase increase threshold ILH again, the count value of the up-down counter 2335 will not increase again, and at this time, the multi-phase power supply 200 always keeps all the power stage circuits turned on.

[0078] As the load decreases, at time t4, the current sampling signal Vs1 decreases to the phase reduction threshold ILL, so the phase increase signal P1 and the phase reduction signal P2 are both low level, the reset end of the D flip-flop DFF1 is low level, the D flip-flop DFF1 exits the reset state, and at the same time, the output end of the D flip-flop DFF1 generates a pulse under the action of the pulse width modulation signal PWM1. Since the counting control signal CTL is low level, a rising edge of a pulse signal is synchronously generated on the synchronization signal Q3. Then the up-down counter 2335 subtracts the count value by 1 according to the pulse edge of the synchronization signal Q3, so that the phase control signal PH3 becomes high level, and the remaining phase control signals become low level, so the power stage circuit 204 in the multi-phase power supply 200 is shielded, and the power stage circuits 201-203 remain in the on state. After reducing one phase of the power stage circuit, the inductor current rises, so the current sampling signal Vs1 increases accordingly. As the load continues to decrease, at time t5, the current sampling signal Vs1 decreases again to the phase reduction threshold ILL. At this time, the phase number control circuit 230 decreases the count value by 1 again when the pulse rising edge of the synchronization signal Q3 is generated according to the low level state of the phase increase signal P1 and the phase reduction signal P2, so the phase number control signal PH2 becomes high level, and then the power stage circuit 203 in the multi-phase power supply 200 continues to be shielded, and the power stage circuits 201-202 remain in the on state. As the load decreases again, until time t6, the count value of the up-down counter 2335 in the phase number control circuit 230 decreases to 1, at which time only the first power stage circuit 201 in the multi-phase power supply 200 is turned on, and the phase number control circuit 230 no longer performs the phase reduction operation.

[0079] In summary, in the phase number control circuit of the multi-phase power supply provided by the embodiment of the present invention, the current sampling signal of the first power stage circuit is compared with the phase-increasing threshold and the phase-decreasing threshold, and a phase-increasing signal and a phase-decreasing signal are generated according to the comparison result. Then, in each cycle period, the count value is increased / decreased according to the logical states of the phase-increasing signal and the phase-decreasing signal, and then the number of power stage circuits turned on in the multi-phase power supply is controlled according to the count value. Without complex mathematical operations and a large number of logical judgments, the operation speed of the phase increase and decrease control of the multi-phase power supply is greatly improved, enabling the system to quickly adjust the phase number according to the load change, realizing real-time control of the power supply, and meeting the requirements of the load for the rapid response of the power supply.

[0080] In addition, the phase number control circuit of the present invention can adopt a relatively simple current sampling circuit structure, without a complex multi-channel sampling module and a large number of auxiliary components, reducing the number of components such as resistors, capacitors, and amplifiers in the circuit, thereby reducing the hardware cost. And because the structure and algorithm of the phase number control circuit of the present invention are simpler, it is easier to integrate and be compatible with other power management modules and load devices, and can be conveniently applied to various different types of multi-phase power supply systems, such as server power supplies, communication power supplies, industrial power supplies, etc., with strong versatility and adaptability.

[0081] In addition, the phase number control circuit of the embodiment of the present invention also provides a certain delay time after each phase-increasing / phase-decreasing operation. During this delay time, the phase number control circuit no longer controls the multi-phase power supply to perform phase-increasing / phase-decreasing operations, ensuring the current balance between the already turned-on power stage circuits, and improving the stability and performance of the system.

[0082] In the above description, no detailed description is made of the well-known structural elements and steps. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0083] According to the embodiments of the present invention as above, these embodiments do not elaborate on all details and do not limit the invention to only the specific embodiments. Obviously, according to the above description, many modifications and variations can be made. The present specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modified use based on the present invention. The protection scope of the present invention should be defined by the scope of the claims of the present invention.

Claims

1. A phase number control circuit of a multi-phase power supply, the multi-phase power supply comprising a plurality of power stage circuits connected in parallel, each power stage circuit being a phase, the plurality of power stage circuits being used to switch at least one power transistor in the phase according to a corresponding pulse width modulation signal, so as to convert an input voltage into an output voltage together, wherein: The phase number control circuit comprises: a comparison module, configured to compare the current sampling signal of the first power stage circuit among the plurality of power stage circuits with the phase increase threshold and the phase decrease threshold, respectively, and generate a phase increase signal and a phase decrease signal according to the comparison result; and A phase quantity control module is used to determine whether to increase / decrease the count value according to the logic states of the phase increase signal and the phase reduction signal in each cycle to adjust the number of power stage circuits in the multi-phase power supply. The phase quantity control module is used to increase / decrease the count value in each cycle when the logic states of the phase increase signal and the phase subtraction signal are the same, and to maintain the count value unchanged when the logic states of the phase increase signal and the phase subtraction signal are different.

2. The phase number control circuit according to claim 1, further comprising: The phase processing module is used to control the phase quantity control module to operate within a dead time after each increase / decrease of the count value, and the phase quantity control module no longer performs the operation of increasing / decreasing the count value within the dead time.

3. The phase number control circuit according to claim 2, wherein: The phase processing module is further configured to control the phase quantity control module to stop performing the operation of reducing the count value when only one power stage circuit in the multi-phase power supply is turned on, and The phase processing module is also used to control the phase quantity control module to no longer perform the operation of increasing the count value when all power stage circuits in the multi-phase power supply are turned on.

4. The phase number control circuit according to claim 3, wherein: The phase quantity control module comprises: a first logic unit, configured to perform an XOR logic operation on the phase-increasing signal and the phase-reducing signal to obtain a first logic signal; A second logic unit, used for performing an AND logic operation on the phase-increasing signal and the phase-reducing signal to obtain a second logic signal; a synchronization signal generating unit, configured to generate a synchronization signal according to the first logic signal, the first pulse width modulation signal of the first power stage circuit, and the counting control signal from the phase processing module; an up-and-down counter, configured to perform an up-and-down operation according to the pulse edges of the second logic signal and the synchronization signal to adjust the count value; and The logic unit is used to perform logic operations on the output of the up-down counter to control the effective state of multiple phase control signals, each phase control signal is used to control the corresponding number of power stage circuits to start.

5. The phase number control circuit according to claim 4, wherein: The first logic unit is used to generate the first logic signal of a high level when the logic states of the phase increase signal and the phase subtraction signal are different, and to generate the first logic signal of a low level when the logic states of the phase increase signal and the phase subtraction signal are the same.

6. The phase number control circuit according to claim 5, wherein: The synchronization signal generating unit is used for generating a valid pulse of the synchronization signal according to the first pulse width modulation signal when the first logic signal and the counting control signal are both at a low level, and When at least one of the first logic signal and the count control signal is at a high level, the synchronization signal is set to a high level.

7. The phase number control circuit according to claim 6, wherein: The synchronization signal generating unit comprises: A D flip-flop, wherein the data terminal and the negative output terminal of the D flip-flop are connected, the clock terminal is used to receive the first pulse width modulation signal, and the reset terminal is used to receive the first logic signal; and A first OR gate, wherein the first input terminal of the first OR gate is used to receive the counting control signal, the second input terminal is connected to the positive output terminal of the D flip-flop, and the output terminal is used to provide the synchronization signal.

8. The phase number control circuit according to claim 4, wherein: The output of the up-down counter includes a multi-bit binary number, and the logic unit includes at least one of a NOR gate, an AND gate, or an AND gate with a negative input terminal.

9. The phase number control circuit according to claim 4, wherein: The multiple phase control signals include at least a first phase control signal, a second phase control signal, and multiple third phase control signals. When the first phase control signal is valid, only the first power stage circuit among the multiple power stage circuits is turned on. When the second phase control signal is valid, all of the multiple power stage circuits are turned on. Wherein, the phase processing module includes: a first AND gate, wherein a first input terminal of the first AND gate is used to receive the first phase control signal, and a second input terminal of the first AND gate is used to receive an inverted signal of the second logic signal, and the first AND gate is used to set the counting control signal to a high level when the first phase control signal is at a high level and the second logic signal is at a low level, The phase processing module also includes: a second OR gate, wherein a first input terminal of the second OR gate is used to receive the phase-increasing signal, and a second input terminal of the second OR gate is used to receive the phase-reducing signal; and a second AND gate, wherein a first input terminal of the second AND gate is used to receive the second phase number control signal, a second input terminal is connected to the output terminal of the second OR gate, and the second AND gate is used to set the counting control signal to a high level when the phase increase signal, the phase reduction signal and the second phase number control signal are all high levels, The phase processing module also includes: A plurality of dead zone control units corresponding to the plurality of third phase control signals, each dead zone control unit comprising: a unilateral delay unit, wherein an input end of the unilateral delay unit is used to receive a corresponding third phase control signal; and An NOR gate, wherein the first input end of the NOR gate is connected to the output end of the unilateral delay unit, and the second input end is used to receive the inverted signal of the corresponding third phase control signal. The NOR gate is used to set the counting control signal to a high level when the corresponding third phase control signal is at a high level, and to set the counting control signal to a low level after the dead time ends.

10. The phase number control circuit according to claim 1, further comprising: a current sampling module, used for sampling the switch node voltage of the first power stage circuit to generate the current sampling signal, Wherein, the current sampling module comprises: a first switch, wherein a first end of the first switch is connected to a switch node voltage of the first power stage circuit, and a control end of the first switch is used to receive a first pulse width modulation signal of the first power stage circuit; a first resistor, wherein a first end of the first resistor is connected to a second end of the first switch; a first capacitor, wherein a first end of the first capacitor is connected to a second end of the first resistor, and a second end of the first capacitor is grounded; a second resistor, a first end of the second resistor being connected to a second end of the first resistor; an operational amplifier, wherein a positive input terminal of the operational amplifier is connected to the second end of the second resistor, and an output terminal of the operational amplifier is used to provide the current sampling signal; a third resistor, a first end of the third resistor being connected to the negative input terminal of the operational amplifier, and a second end of the third resistor being grounded; and A fourth resistor is connected between the positive input terminal and the output terminal of the operational amplifier.

11. The phase number control circuit according to claim 1, wherein: The comparison module comprises: A first comparator, wherein the positive input terminal of the first comparator is connected to the current sampling signal, the negative input terminal is connected to the phase-increasing threshold, and the output terminal is used to provide the phase-increasing signal; and A second comparator, wherein the positive input terminal of the second comparator is connected to the current sampling signal, the negative input terminal is connected to the phase subtraction threshold, and the output terminal is used to provide the phase subtraction signal.

12. A control circuit for a multi-phase power supply, the multi-phase power supply comprising a plurality of power stage circuits connected in parallel, each power stage circuit being a phase, the plurality of power stage circuits being used to switch at least one power transistor in the phase according to a corresponding pulse width modulation signal, so as to convert an input voltage into an output voltage together, the control circuit comprising: A switch control circuit, used for generating a pulse width modulation signal for the plurality of power stage circuits; as well as The phase control circuit according to any one of claims 1 to 11.

13. A multiphase power supply comprising: A plurality of power stage circuits connected in parallel, each power stage circuit being a phase, and the plurality of power stage circuits being used to switch at least one power transistor in the phase according to a corresponding pulse width modulation signal, so as to convert an input voltage into an output voltage together; as well as The control circuit of claim 12.

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