Slope compensation circuit, RBCOT architecture power converter, chip and electronic equipment

Abstract

The invention provides a slope compensation circuit, an RBCOT architecture power converter, a chip and electronic equipment. The ramp voltage generating circuit generates a ramp voltage related to the duty ratio of the pulse width modulation signal according to the pulse width modulation signal. The ramp compensation circuit can transmit at least one compensation current to the ramp voltage generation circuit, so that the ramp voltage generation circuit can obtain the at least one compensation current. Therefore, when the duty ratio of the pulse width modulation signal is greater than the preset duty ratio, the ramp voltage generation circuit can utilize at least one compensation current to compensate the amplitude of the ramp voltage until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold value; the amplitude of the compensated ramp voltage can ensure that the RBCOT architecture power converter has good loop stability and load transient response characteristics. Therefore, whether the duty ratio of the pulse width modulation signal is a large duty ratio or a small duty ratio, both the loop stability and the load transient response characteristic can be considered.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and particularly relates to a slope compensation circuit, an RBCOT architecture power converter, a chip, and an electronic device. Background Art

[0002] With the increasing integration and complexity of functions of electronic devices, higher requirements are put forward for various indicators of power converters, especially important indicators such as the output voltage accuracy, output voltage ripple, load transient response characteristics, stability, and conversion efficiency of power converters. Among many control methods, ripple based constant on time (RBCOT) is widely used in power converters because it can achieve simple and good load transient characteristics.

[0003] Currently, the RBCOT architecture power converter in the related art usually adds a ramp voltage generation circuit during the off-time. In this way, during the off-time, the ramp signal generated by the ramp voltage generation circuit and the feedback voltage of the output voltage of the RBCOT architecture power converter jointly ensure loop stability and take into account the load transient response characteristics. However, since the amplitude of the ramp signal decreases as the off-time decreases. Therefore, when the off-time decreases to the minimum off-time, the amplitude of the ramp voltage is very small, resulting in a decrease in loop stability. If the amplitude of the ramp voltage increases to a preset amplitude when the off-time decreases to the minimum off-time, then when the off-time increases to a very large value, that is, under the working condition of the minimum on-time, the off-time is very large, making the amplitude of the ramp voltage very large, resulting in a decrease in the load transient response characteristics.

[0004] Therefore, no matter what value the off-time is, how to balance loop stability and load transient response characteristics is an urgent issue to be studied currently. Summary of the Invention

[0005] The present application provides a slope compensation circuit, an RBCOT architecture power converter, a chip, and an electronic device, which can change the amplitude of the ramp voltage. Thus, loop stability and load transient response characteristics can be balanced.

[0006] In a first aspect, the present application provides a slope compensation circuit, which is applied to an RBCOT architecture power converter. The RBCOT architecture power converter includes: a ramp voltage generation circuit; the first end of the slope compensation circuit and the first end of the ramp voltage generation circuit are both used to access a pulse width modulation signal, the second end of the slope compensation circuit is electrically connected to the second end of the ramp voltage generation circuit, and the output end of the ramp voltage generation circuit is used to output a ramp voltage;

[0007] The ramp voltage generation circuit is configured to generate the ramp voltage according to the pulse width modulation signal, and the duty cycle of the pulse width modulation signal is related to the amplitude of the ramp voltage;

[0008] The ramp compensation circuit is configured to transmit at least one compensation current to the ramp voltage generation circuit. When the duty cycle of the pulse width modulation signal is less than or equal to a preset duty cycle, the amplitude of the ramp voltage is greater than or equal to an amplitude threshold; when the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, the current value of the compensation current starts from zero and increases as the duty cycle of the pulse width modulation signal increases;

[0009] The ramp voltage generation circuit is further configured to, when the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, use the at least one compensation current to compensate the amplitude of the ramp voltage until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold.

[0010] Through the ramp compensation circuit provided by the first aspect, the ramp voltage generation circuit can generate a ramp voltage related to the duty cycle of the pulse width modulation signal according to the pulse width modulation signal. The ramp compensation circuit can transmit at least one compensation current to the ramp voltage generation circuit so that the ramp voltage generation circuit can obtain at least one compensation current. In this way, when the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, the ramp voltage generation circuit can use the at least one compensation current to compensate the amplitude of the ramp voltage until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold. Since when the duty cycle of the pulse width modulation signal is less than or equal to the preset duty cycle, the amplitude of the ramp voltage is greater than or equal to the amplitude threshold, the amplitude of the ramp voltage can ensure that the RBCOT architecture power converter has good loop stability and load transient response characteristics. When the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, the current value of the compensation current starts from zero and increases as the duty cycle of the pulse width modulation signal increases, so that at least one compensation current adaptively follows the change of the duty cycle of the pulse width modulation signal to compensate the amplitude of the ramp voltage until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold, making the amplitude of the compensated ramp voltage ensure that the RBCOT architecture power converter has good loop stability and load transient response characteristics. Thus, whether the duty cycle of the pulse width modulation signal is a large duty cycle or a small duty cycle, both loop stability and load transient response characteristics can be taken into account.

[0011] In a possible design, when the at least one compensation current includes a first compensation current and a second compensation current, the ramp compensation circuit is specifically configured to transmit the first compensation current and the second compensation current to the ramp voltage generation circuit. When the duty cycle of the pulse width modulation signal is greater than a first preset duty cycle, the current value of the first compensation current starts to increase from zero. When the duty cycle of the pulse width modulation signal is greater than a second preset duty cycle, the current value of the second compensation current starts to increase from zero. The preset duty cycle includes the first preset duty cycle and the second preset duty cycle;

[0012] The ramp voltage generation circuit is specifically configured to, when the duty cycle of the pulse width modulation signal is greater than the first preset duty cycle, use the first compensation current to compensate the amplitude of the ramp voltage to obtain a first ramp voltage. The compensated ramp voltage includes the first ramp voltage and a second ramp voltage. The first preset duty cycle is used to indicate that the amplitude of the ramp voltage is less than the amplitude threshold;

[0013] The ramp voltage generation circuit is further specifically configured to, when the duty cycle of the pulse width modulation signal is greater than the second preset duty cycle, use the second compensation current to compensate the amplitude of the first ramp voltage to obtain the second ramp voltage. The second preset duty cycle is used to indicate that the amplitude of the first ramp voltage is less than the amplitude threshold.

[0014] In a possible design, the ramp compensation circuit includes a current conversion circuit, a compensation current output circuit, and at least one compensation start circuit;

[0015] The first end of the current conversion circuit is used to connect to the pulse width modulation signal. The second end of the current conversion circuit is electrically connected to the first end of the at least one compensation start circuit and the first end of the compensation current output circuit respectively. The second end of the at least one compensation start circuit is used to connect to a reference voltage. The second end of the compensation current output circuit is electrically connected to the second end of the ramp voltage generation circuit. The third end of the current conversion circuit and the third end of the at least one compensation start circuit are both grounded. The power supply ends of the at least one compensation start circuit and the compensation current output circuit are electrically connected;

[0016] The current conversion circuit is configured to convert the pulse width modulation signal into a first current and transmit the first current to the compensation current output circuit;

[0017] The compensation start circuit is configured to generate a second current according to the reference voltage at the preset duty cycle and transmit the second current to the compensation current output circuit;

[0018] The compensation current output circuit is configured to generate the compensation current according to the first current and the second current.

[0019] In a possible design, the current conversion circuit includes: a demodulation circuit and a voltage-current conversion circuit;

[0020] The input end of the demodulation circuit is configured to receive the pulse width modulation signal. The output end of the demodulation circuit is electrically connected to the control end of the voltage-current conversion circuit. The first end of the voltage-current conversion circuit is electrically connected to the first end of the at least one compensation start circuit, and the second end of the voltage-current conversion circuit is grounded;

[0021] The demodulation circuit is configured to demodulate the pulse width modulation signal into a first voltage and transmit the first voltage to the voltage-current conversion circuit;

[0022] The voltage-current conversion circuit is configured to convert the first voltage into the first current.

[0023] In a possible design, the voltage-current conversion circuit includes: a first resistor and a first transistor;

[0024] The gate of the first transistor is electrically connected to the output end of the demodulation circuit. The source of the first transistor is electrically connected to the first end of the at least one compensation start circuit, and the source of the first transistor is grounded.

[0025] In a possible design, the demodulation circuit includes: a second resistor and a first capacitor;

[0026] The first end of the second resistor is configured to receive the pulse width modulation signal. The second end of the second resistor is electrically connected to the control end of the voltage-current conversion circuit. The upper plate of the first capacitor is electrically connected between the second end of the second resistor and the control end of the voltage-current conversion circuit, and the lower plate of the first capacitor is grounded.

[0027] In a possible design, the compensation start circuit includes: a first current mirror, a second transistor, and a third resistor;

[0028] The gate of the second transistor is configured to receive the reference voltage. The drain of the second transistor is electrically connected to the input end of the first current mirror. The power supply end of the first current mirror is electrically connected to the power supply end of the compensation current output circuit. The output end of the first current mirror is electrically connected to the second end of the current conversion circuit. The source of the second transistor is electrically connected to the first end of the third resistor, and the second end of the third resistor is grounded.

[0029] In a possible design, the first current mirror includes: a third transistor and a fourth transistor;

[0030] The source of the third transistor and the source of the fourth transistor are both electrically connected to the power supply terminal of the compensation current output circuit. The gate of the third transistor is electrically connected to the gate of the fourth transistor, the drain of the fourth transistor, and the drain of the second transistor respectively. The drain of the third transistor is electrically connected to the second terminal of the current conversion circuit.

[0031] In a possible design, the compensation current output circuit includes: a fifth transistor and a sixth transistor;

[0032] The source of the fifth transistor and the source of the sixth transistor are both electrically connected to the power supply terminal of the at least one compensation start circuit. The gate of the sixth transistor is electrically connected to the gate of the fifth transistor, the drain of the fifth transistor, and the second terminal of the current conversion circuit respectively. The drain of the sixth transistor is electrically connected to the second terminal of the ramp voltage generation circuit.

[0033] In a possible design, the ramp voltage generation circuit includes: a charging current output circuit and a ramp voltage output circuit;

[0034] The input terminal of the charging current output circuit is electrically connected to the second terminal of the ramp compensation circuit. The output terminal of the charging current output circuit is electrically connected to the first terminal of the ramp voltage output circuit. The second terminal of the ramp voltage output circuit is used to connect to the pulse width modulation signal, and the third terminal of the ramp voltage output circuit is grounded;

[0035] The charging current output circuit is configured to transmit a charging current to the ramp voltage output circuit;

[0036] The ramp voltage output circuit is configured to charge a second capacitor in the ramp voltage output circuit with the charging current according to the pulse width modulation signal, and use the voltage on the second capacitor as the ramp voltage;

[0037] The charging current output circuit is further configured to compensate the charging current with the compensation current to compensate the amplitude of the ramp voltage.

[0038] In a possible design, the ramp voltage output circuit includes: a seventh transistor, an eighth transistor, and a second capacitor;

[0039] The source of the seventh transistor is electrically connected to the output terminal of the charging current output circuit. The gate of the seventh transistor is used to receive a control signal, which is used to indicate whether the inductor current in the RBCOT architecture power converter is zero-crossing. The source of the seventh transistor is electrically connected to the upper plate of the second capacitor. The drain of the eighth transistor is electrically connected between the source of the seventh transistor and the upper plate of the second capacitor. The gate of the eighth transistor is used to receive the pulse width modulation signal. The source of the eighth transistor and the lower plate of the second capacitor are both grounded.

[0040] In a possible design, the charging current output circuit includes: a reference current source and a second current mirror;

[0041] The first end of the reference current source is electrically connected to the input end of the second current mirror. The second end of the ramp compensation circuit is electrically connected between the first end of the reference current source and the input end of the second current mirror. The output end of the second current mirror is electrically connected to the first end of the ramp voltage output circuit;

[0042] The reference current source is used to output a reference current and transmit the reference current to the second current mirror;

[0043] The second current mirror is used to copy the reference current to obtain the charging current.

[0044] In a second aspect, the present application provides an RBCOT architecture power converter, which includes: a power converter, a constant on-time control circuit, a driver, a trigger, a ramp voltage generation circuit, a control circuit, and a ramp compensation circuit in the first aspect and each possible design of the first aspect;

[0045] The output terminal of the trigger is electrically connected to the input terminal of the driver, the input terminal of the constant on-time control circuit, the first end of the ramp compensation circuit, and the first end of the ramp voltage generation circuit respectively. The second end of the ramp compensation circuit is electrically connected to the second end of the ramp voltage generation circuit. The output end of the ramp voltage generation circuit is electrically connected to the first input terminal of the control circuit. The second input terminal of the control circuit is used to receive a feedback voltage, which is used to indicate the change of the output voltage of the RBCOT architecture power converter. The output end of the control circuit is electrically connected to the set terminal of the trigger. The reset terminal of the trigger is electrically connected to the output end of the constant on-time control circuit. The output end of the driver is electrically connected to the control terminal of the power converter. The input terminal of the power converter is used to receive the input voltage of the RBCOT architecture power converter. The output terminal of the power converter is used to output the output voltage of the RBCOT architecture power converter.

[0046] For the RBCOT architecture power converter provided in the second aspect above and each possible design of the second aspect, the beneficial effects can be referred to the beneficial effects brought by the first aspect above and each possible implementation manner of the first aspect, which will not be elaborated here.

[0047] In a third aspect, the present application provides a chip, including: the slope compensation circuit in the first aspect above and each possible design of the first aspect, and / or, the RBCOT architecture power converter in the second aspect above.

[0048] In a fourth aspect, the present application provides an electronic device, including: the chip in the third aspect above.

[0049] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to be able to understand the technical means of the embodiments of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and understandable, the following specifically illustrates the specific implementation manners of the present application. Description of the Drawings

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0051] Figure 1 It is a schematic structural diagram of a RBCOT architecture power converter in the related art;

[0052] Figure 2 It is a schematic structural diagram of another RBCOT architecture power converter in the related art;

[0053] Figure 3 It is a schematic structural diagram of a slope compensation circuit provided by an embodiment of the present application;

[0054] Figure 4 It is a schematic structural diagram of another slope compensation circuit provided by an embodiment of the present application;

[0055] Figure 5 It is a schematic structural diagram of yet another slope compensation circuit provided by an embodiment of the present application;

[0056] Figure 6 It is a schematic structural diagram of yet another slope compensation circuit provided by an embodiment of the present application;

[0057] Figure 7Schematic diagram of the structure of an RBCOT architecture power converter provided by an embodiment of the present application. Detailed implementation manners

[0058] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or a similar expression thereof refers to any combination of these items, including any combination of a single item (item) or plural items (items). For example, at least one (item) of a alone, b alone, or c alone may represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c may be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0059] The orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0060] The terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure may refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it may be directly connected, that is, a physical connection, or indirectly connected through at least one intermediate element, as long as the circuit is connected. It may also be the internal connection of two elements; the signal connection may refer not only to the signal connection through a circuit, but also to the signal connection through a media medium. For example, radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0061] Refer to Figure 1 , Figure 1 is a schematic diagram of the structure of an RBCOT architecture power converter in the related art. As Figure 1As shown, in the RBCOT architecture power converter in the related art, by comparing the valley value of the output voltage ripple, there is a ripple error in the output voltage VOUT, and the ripple error varies with the load and the input voltage VIN. Therefore, an error amplifier EA is added to eliminate the error between the reference voltage VREF and the feedback voltage VFB to generate the reference voltage of the pulse width modulation comparator PWM. Thus, the ripple error can be eliminated to improve the output accuracy of the RBCOT architecture power converter in the related art.

[0062] However, Figure 1 there is a delay between the output voltage ripple and the inductor current in the RBCOT architecture power converter in [reference], resulting in that when the equivalent series resistance Resr of the output capacitor Cout is small, the RBCOT architecture power converter is prone to subharmonic oscillation. If the equivalent series resistance Resr of the output capacitor Cout is increased, the output voltage ripple increases, greatly limiting the application of the RBCOT architecture power converter.

[0063] Based on this, referring to Figure 2 , Figure 2 is a schematic structural diagram of another RBCOT architecture power converter in the related art. As Figure 2 shown, in the RBCOT architecture power converter in the related art, a ramp voltage generation circuit Ramp is added during the off-time Toff. In this way, during the off-time Toff, the loop stability is ensured jointly by the feedback voltage VFB and the ramp voltage Ramp, and the load transient response characteristics are taken into account. However, since the amplitude of the ramp voltage Ramp decreases as the off-time Toff decreases. Therefore, when the off-time Toff decreases to the minimum off-time, the amplitude of the ramp voltage Ramp is very small, resulting in a decrease in loop stability. If the amplitude of the ramp voltage Ramp increases to a preset amplitude when the off-time Toff decreases to the minimum off-time Min-Toff, then when the off-time Toff increases to a very large value, that is, under the operating condition of the minimum on-time Min-ON, the off-time Toff is very large, making the amplitude of the ramp voltage Ramp very large, resulting in a decrease in the load transient response characteristics.

[0064] Based on this, in the related art, if the amplitude of the ramp voltage Ramp is too large, the weight of the feedback voltage VFB will be reduced, resulting in a decline in the load transient response characteristics. If the amplitude of the ramp voltage Ramp is too small, it will lead to a decline in loop stability. At the same time, when the switching frequency of the RBCOT architecture power converter is fixed, as the duty cycle of the RBCOT architecture power converter increases, the turn-off time Toff will decrease, and the amplitude of the ramp voltage Ramp is related to the turn-off time Toff. That is to say, the amplitude of the ramp voltage Ramp is related to the duty cycle. In this way, the amplitude of the ramp voltage Ramp will decrease as the duty cycle increases. And the decrease in the amplitude of the ramp voltage Ramp will lead to a decline in the loop stability.

[0065] Therefore, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than the preset duty cycle in the ramp compensation circuit provided by the embodiment of the present application, that is to say, when the duty cycle of the pulse width modulation signal PWM_CTRL is a small duty cycle, the amplitude of the ramp voltage Ramp' can not only ensure good loop stability but also have good load transient response characteristics. When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the preset duty cycle, that is to say, when the duty cycle of the pulse width modulation signal PWM_CTRL is a large duty cycle, the ramp compensation circuit compensates the ramp voltage generation circuit to increase the amplitude of the compensated ramp voltage Ramp. Thus, the RBCOT architecture power converter can have good loop stability and load transient response characteristics, enabling it to take into account both loop stability and load transient response characteristics whether the duty cycle of the pulse width modulation signal PWM_CTRL is a large duty cycle or a small duty cycle.

[0066] Refer to Figure 3 , Figure 3 is a schematic structural diagram of a ramp compensation circuit provided by an embodiment of the present application. As Figure 3 shown, the first end of the ramp compensation circuit 100 and the first end of the ramp voltage generation circuit 200 are both used to access the pulse width modulation signal PWM_CTRL. The second end of the ramp compensation circuit 100 is electrically connected to the second end of the ramp voltage generation circuit 200, and the output end of the ramp voltage generation circuit 200 is used to output the ramp voltage Ramp'.

[0067] The ramp voltage generation circuit 200 can generate the ramp voltage Ramp' according to the pulse width modulation signal PWM_CTRL.

[0068] Among them, the duty cycle of the pulse width modulation signal PWM_CTRL is related to the amplitude of the ramp voltage Ramp'. When the duty cycle of the pulse width modulation signal PWM_CTRL increases, the amplitude of the ramp voltage Ramp' decreases. When the duty cycle of the pulse width modulation signal PWM_CTRL decreases, the amplitude of the ramp voltage Ramp' increases.

[0069] The slope compensation circuit 100 can transmit at least one compensation current I_COM to the ramp voltage generation circuit 200, so that the ramp voltage generation circuit 200 can obtain at least one compensation current I_COM.

[0070] Wherein, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to a preset duty cycle, the current value of the compensation current I_COM is zero. When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the preset duty cycle, the current value of the compensation current I_COM starts to increase from zero and increases with the increase of the duty cycle of the pulse width modulation signal PWM_CTRL.

[0071] Wherein, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to a preset duty cycle, the amplitude of the ramp voltage Ramp' is greater than or equal to an amplitude threshold.

[0072] Wherein, since the number of the compensation currents I_COM is at least one. Therefore, the slope compensation circuit 100 can perform multi-level compensation on the amplitude of the ramp voltage Ramp'.

[0073] For example, when the number of the compensation currents I_COM is 1, the slope compensation circuit 100 can perform first-level compensation on the amplitude of the ramp voltage Ramp'. For another example, when the number of the compensation currents I_COM is 2, the slope compensation circuit 100 can perform second-level compensation on the amplitude of the ramp voltage Ramp'. For another example, when the number of the compensation currents I_COM is 4, the slope compensation circuit 100 can perform fourth-level compensation on the amplitude of the ramp voltage Ramp'.

[0074] Wherein, the compensation current I_COM can have a linear relationship or a non-linear relationship with the duty cycle of the pulse width modulation signal PWM_CTRL, and the embodiments of the present application do not make specific limitations thereto.

[0075] In this way, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the preset duty cycle, the ramp voltage generation circuit 200 can use at least one compensation current I_COM to compensate the amplitude of the ramp voltage Ramp' until the amplitude of the compensated ramp voltage Ramp' is greater than or equal to the amplitude threshold.

[0076] Wherein, the amplitude of the compensated ramp voltage Ramp' can remain unchanged with the increase of the duty cycle of the pulse width modulation signal PWM_CTRL, or can decrease at a slower speed with the increase of the duty cycle of the pulse width modulation signal PWM_CTRL, or can increase first and then decrease with the increase of the duty cycle of the pulse width modulation signal PWM_CTRL, and the embodiments of the present application do not make specific limitations thereto.

[0077] When the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to the preset duty cycle, since the amplitude of the ramp voltage Ramp' is greater than or equal to the amplitude threshold, the amplitude of the ramp voltage Ramp' can ensure that the RBCOT architecture power converter 1000 has good loop stability and load transient response characteristics.

[0078] When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the preset duty cycle, since the current value of the compensation current I_COM starts to increase from zero and increases with the increase of the duty cycle of the pulse width modulation signal PWM_CTRL, at least one compensation current I_COM adaptively follows the change of the duty cycle of the pulse width modulation signal PWM_CTRL to compensate the amplitude of the ramp voltage Ramp', until the amplitude of the compensated ramp voltage Ramp' is greater than or equal to the amplitude threshold, so that the amplitude of the compensated ramp voltage Ramp' can ensure that the RBCOT architecture power converter 1000 has good loop stability and load transient response characteristics. Furthermore, when the duty cycle of the pulse width modulation signal PWM_CTRL is the minimum duty cycle, that is, when the off-time Toff' in the pulse width modulation signal PWM_CTRL decreases to the minimum off-time Min-Toff', the amplitude of the compensated ramp voltage Ramp' is greater than or equal to the amplitude threshold, so that the RBCOT architecture power converter 1000 has good loop stability.

[0079] Thus, regardless of whether the duty cycle of the pulse width modulation signal PWM_CTRL is a large duty cycle or a small duty cycle, it can take into account both loop stability and load transient response characteristics.

[0080] In some examples, when at least one compensation current I_COM can include: a first compensation current I_COM1 and a second compensation current I_COM2, the ramp compensation circuit 100 can transmit the first compensation current I_COM1 and the second compensation current I_COM2 to the ramp voltage generation circuit 200, so that the ramp voltage generation circuit 200 can obtain the first compensation current I_COM1 and the second compensation current I_COM2.

[0081] Among them, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the first preset duty cycle, the current value of the first compensation current I_COM1 starts to increase from zero. When the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to the first preset duty cycle, the current value of the first compensation current I_COM1 is zero. When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the second preset duty cycle, the current value of the second compensation current I_COM2 starts to increase from zero. When the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to the second preset duty cycle, the current value of the second compensation current I_COM2 is zero. The preset duty cycle may include: the first preset duty cycle and the second preset duty cycle.

[0082] In this way, since the first preset duty cycle is used to represent that the amplitude of the ramp voltage Ramp' is less than the amplitude threshold, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the first preset duty cycle, the ramp voltage generation circuit 200 can use the first compensation current I_COM1 to compensate the amplitude of the ramp voltage Ramp' to obtain the first ramp voltage Ramp1'.

[0083] Among them, the changed ramp voltage Ramp' may include: the first ramp voltage Ramp1' and the second ramp voltage Ramp2'. The first preset duty cycle is used to represent that the amplitude of the ramp voltage Ramp' is less than the amplitude threshold.

[0084] Since the second preset duty cycle is used to represent that the amplitude of the first ramp voltage Ramp1' is less than the amplitude threshold. Therefore, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the second preset duty cycle, the ramp voltage generation circuit 200 can use the second compensation current I_COM2 to compensate the amplitude of the first ramp voltage Ramp1' to obtain the second ramp voltage Ramp2', so that the amplitude of the second ramp voltage Ramp2' is greater than the amplitude threshold.

[0085] Among them, the second preset duty cycle is used to represent that the amplitude of the first ramp voltage Ramp1' is less than the amplitude threshold.

[0086] The ramp compensation circuit, RBCOT architecture power converter, chip and electronic device provided by this application. The ramp voltage generation circuit can generate a ramp voltage related to the duty cycle of the pulse width modulation signal according to the pulse width modulation signal. The ramp compensation circuit can transmit at least one compensation current to the ramp voltage generation circuit, so that the ramp voltage generation circuit can obtain at least one compensation current. In this way, when the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, the ramp voltage generation circuit can use at least one compensation current to compensate the amplitude of the ramp voltage until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold. Since when the duty cycle of the pulse width modulation signal is less than or equal to the preset duty cycle, the amplitude of the ramp voltage is greater than or equal to the amplitude threshold, the amplitude of the ramp voltage can ensure that the RBCOT architecture power converter has good loop stability and load transient response characteristics. When the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, the current value of the compensation current increases from zero and increases with the increase of the duty cycle of the pulse width modulation signal, so that at least one compensation current adaptively follows the change of the duty cycle of the pulse width modulation signal to compensate the amplitude of the ramp voltage until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold, so that the amplitude of the compensated ramp voltage can ensure that the RBCOT architecture power converter has good loop stability and load transient response characteristics. Thus, regardless of whether the duty cycle of the pulse width modulation signal is a large duty cycle or a small duty cycle, the loop stability and load transient response characteristics can be taken into account.

[0087] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the ramp compensation circuit 100. Refer to Figures 4 - 6 , Figures 4 - 6 Both show Figure 3 The structural schematic diagram of the ramp compensation circuit in Figures 4 - 6 As shown in

[0088] The first end of the current conversion circuit 110 is used to access the pulse width modulation signal PWM_CTRL. The second end of the current conversion circuit 110 is electrically connected to the first end of at least one compensation start circuit 120 and the first end of the compensation current output circuit 130 respectively. The second end of at least one compensation start circuit 120 is used to access the first reference voltage VREF'1. The second end of the compensation current output circuit 130 is electrically connected to the second end of the ramp voltage generation circuit 200. The third end of the current conversion circuit 110 and the third end of at least one compensation start circuit 120 are both grounded. The power supply end of at least one compensation start circuit 120 and the power supply end of the compensation current output circuit 130 are electrically connected.

[0089] Among them, the current conversion circuit 110, the compensation current output circuit 130, and at least one compensation start circuit 120 may be separately provided or integrated. The embodiments of the present application do not make specific limitations on this.

[0090] Among them, the first end of the current conversion circuit 110 is the first end of the ramp compensation circuit 100, and the second end of the compensation current output circuit 130 is the second end of the ramp compensation circuit 100.

[0091] The current conversion circuit 110 can convert the pulse width modulation signal PWM_CTRL into a first current I1. Moreover, the current conversion circuit 110 can transmit the first current I1 to the compensation current output circuit 130 so that the compensation current output circuit 130 can obtain the first current I1.

[0092] The compensation start circuit 120 can generate a second current I2 according to the first reference voltage VREF'1 at a preset duty cycle. Moreover, the compensation start circuit 120 can transmit the second current I2 to the compensation current output circuit 130 so that the compensation current output circuit 130 can obtain the second current I2.

[0093] In this way, the compensation current output circuit 130 can generate a compensation current I_COM according to the first current I1 and the second current I2.

[0094] Therefore, the compensation current output circuit 130 can output the compensation current I_COM.

[0095] Among them, when the first current I1 is less than or equal to the second current I2, the current value of the compensation current I_COM is zero. When the first current I1 is greater than the second current I2, the current value of the compensation current I_COM starts to increase from zero.

[0096] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the current conversion circuit 110. As Figures 4 - 6 shown, the current conversion circuit 110 may include: a demodulation circuit 111 and a voltage-current conversion circuit 112.

[0097] The input end of the demodulation circuit 111 is used to access the pulse width modulation signal PWM_CTRL. The output end of the demodulation circuit 111 is electrically connected to the control end of the voltage-current conversion circuit 112. The first end of the voltage-current conversion circuit 112 is electrically connected to the first end of at least one compensation start circuit 120, and the second end of the voltage-current conversion circuit 112 is grounded.

[0098] Among them, the input end of the demodulation circuit 111 is the first end of the current conversion circuit 110, the first end of the voltage-current conversion circuit 112 is the second end of the current conversion circuit 110, and the second end of the voltage-current conversion circuit 112 is the third end of the current conversion circuit 110.

[0099] The demodulation circuit 111 can demodulate the pulse width modulation signal PWM_CTRL into the first voltage V_RC. Moreover, the demodulation circuit 111 can transmit the first voltage V_RC to the voltage-current conversion circuit 112, so that the voltage-current conversion circuit 112 can obtain the first voltage V_RC.

[0100] Furthermore, the voltage-current conversion circuit 112 can convert the first voltage V_RC into the first current I1. Thus, the current conversion circuit 110 can convert the pulse width modulation signal PWM_CTRL into the first current I1.

[0101] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the voltage-current conversion circuit 112. As Figures 4 - 6 shown, the voltage-current conversion circuit 112 may include: a first resistor R1' and a first transistor M1.

[0102] The gate of the first transistor M1 is electrically connected to the output end of the demodulation circuit 111, the source of the first transistor M1 is electrically connected to the first end of at least one compensation starting circuit 120, and the source of the first transistor M1 is grounded.

[0103] Among them, the gate of the first transistor M1 is the control end of the voltage-current conversion circuit 112, the source of the first transistor M1 is the first end of the voltage-current conversion circuit 112, and the source of the first transistor M1 is the second end of the voltage-current conversion circuit 112.

[0104] In some examples, when the threshold voltage of the first transistor M1 is zero, or infinitely close to zero, that is, when the first transistor M1 is a native device, the duty cycle of the pulse width modulation signal PWM_CTRL has a linear relationship with the compensation current I_COM.

[0105] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the demodulation circuit 111. As Figures 4 - 6 shown, the demodulation circuit 111 may include: a second resistor R2' and a first capacitor C1.

[0106] The first end of the second resistor R2' is used to connect to the pulse width modulation signal PWM_CTRL. The second end of the second resistor R2' is electrically connected to the control end of the voltage-current conversion circuit 112. The upper plate of the first capacitor C1 is electrically connected between the second end of the second resistor R2' and the control end of the voltage-current conversion circuit 112, and the lower plate of the first capacitor C1 is grounded.

[0107] Among them, the first end of the second resistor R2' is the input end of the demodulation circuit 111, and the second end of the second resistor R2' is the output end of the demodulation circuit 111.

[0108] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the compensation start circuit 120. As Figures 4 - 6 shown, the compensation start circuit 120 may include: a first current mirror 121, a second transistor M2, and a third resistor R3'.

[0109] The gate of the second transistor M2 is used to connect to the first reference voltage VREF'1. The drain of the second transistor M2 is electrically connected to the input end of the first current mirror 121. The power supply end of the first current mirror 121 is electrically connected to the power supply end of the compensation current output circuit 130. The output end of the first current mirror 121 is electrically connected to the second end of the current conversion circuit 110. The source of the second transistor M2 is electrically connected to the first end of the third resistor R3', and the second end of the third resistor R3' is grounded.

[0110] Among them, the output end of the first current mirror 121 is the first end of the compensation start circuit 120. The gate of the second transistor M2 is the second end of the compensation start circuit 120. The second end of the third resistor R3' is the third end of the compensation start circuit 120. The power supply end of the first current mirror 121 is the power supply end of the compensation start circuit 120.

[0111] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the compensation start circuit 120. As Figures 4 - 6 shown, the first current mirror 121 may include: a third transistor M3 and a fourth transistor M4.

[0112] The sources of the third transistor M3 and the fourth transistor M4 are both electrically connected to the power supply end of the compensation current output circuit 130. The gate of the third transistor M3 is electrically connected to the gate of the fourth transistor M4, the drain of the fourth transistor M4, and the drain of the second transistor M2 respectively. The drain of the third transistor M3 is electrically connected to the second end of the current conversion circuit 110.

[0113] Among them, the sources of the third transistor M3 and the fourth transistor M4 are both the power supply terminals of the first current mirror 121, the drain of the fourth transistor M4 is the input terminal of the first current mirror 121, and the drain of the third transistor M3 is the output terminal of the first current mirror 121.

[0114] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the compensation current output circuit 130. As Figures 4 - 6 shown, the compensation current output circuit 130 includes: a fifth transistor M5 and a sixth transistor M6.

[0115] The sources of the fifth transistor M5 and the sixth transistor M6 are both electrically connected to the power supply terminal of at least one compensation start circuit 120. The gate of the sixth transistor M6 is respectively connected to the gate of the fifth transistor M5, the drain of the fifth transistor M5, and the second terminal of the current conversion circuit 110. The drain of the sixth transistor M6 is connected to the second terminal of the ramp voltage generation circuit 200.

[0116] Among them, the sources of the fifth transistor M5 and the sixth transistor M6 are both the power supply terminals of the compensation current output circuit 130. The drain of the fifth transistor M5 is the first terminal of the compensation current output circuit 130, and the drain of the sixth transistor M6 is the second terminal of the compensation current output circuit 130.

[0117] The following respectively combines Figure 5 and Figure 6 , and takes the first-level compensation and the second-level compensation as examples to illustrate the working principle of the ramp compensation circuit 100 in detail. The content is as follows:

[0118] As Figure 5 shown, when the number of compensation start circuits 120 is 1, the ramp compensation circuit 100 performs first-level compensation on the amplitude of the ramp voltage Ramp'.

[0119] For example, the preset duty cycle is 50%.

[0120] In this way, when the resistance value of the third resistor R3' is equal to the resistance value of the first resistor R1', the first transistor M1 and the second transistor M2 are equal, and the first reference voltage VREF'1 is equal to the first voltage V_RC corresponding to the 50% duty cycle of the pulse width modulation signal PWM_CTRL, the compensation start circuit 120 can generate the second current I2 and transmit the second current I2 to the compensation current output circuit 130, so that the compensation current output circuit 130 can obtain the second current I2.

[0121] Thus, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to 50%, the first current I1 is less than or equal to the second current I2, making the difference between the first current I1 and the second current I2 zero or negative, so that the compensation current I_COM is zero. Therefore, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to 50%, the compensation current I_COM is zero.

[0122] When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than 50%, the first current I1 is greater than the second current I2, making the difference between the first current I1 and the second current I2 positive, so that the compensation current I_COM starts to increase from zero. Furthermore, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than 50%, the compensation current I_COM starts to increase from zero. Thus, the ramp compensation circuit 100 can use the compensation current I_COM to compensate the amplitude of the ramp voltage Ramp', so that the amplitude of the compensated ramp voltage Ramp' is greater than or equal to the amplitude threshold.

[0123] If the amplitude of the compensated ramp voltage Ramp' still decreases rapidly as the duty cycle of the pulse width modulation signal PWM_CTRL increases, then when the turn-off time Toff' of the pulse width modulation signal PWM_CTRL is the minimum turn-off time, the amplitude of the compensated ramp voltage Ramp' is still less than the amplitude threshold. Therefore, as Figure 6 shown, by adding two compensation start circuits 120, the ramp compensation circuit 100 realizes two-stage compensation for the amplitude of the ramp voltage Ramp'.

[0124] For example, the first preset duty cycle is 50%, and the second preset duty cycle is 70%.

[0125] In this way, when the resistance value of the third resistor R3'-1 is equal to the resistance value of the first resistor R1', the first transistor M1 and the second transistor M2-1 are equal, and the first reference voltage VREF'1-1 is equal to the first voltage V_RC corresponding to the duty cycle of the pulse width modulation signal PWM_CTRL being 50%, the compensation start circuit 120 can generate the second current I2-1 and transmit the second current I2-1 to the compensation current output circuit 130, so that the compensation current output circuit 130 can obtain the second current I2-1.

[0126] Thus, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to 50%, the first current I1 is less than or equal to the second current I2-1, making the difference between the first current I1 and the second current I2-1 zero or negative, so that the first compensation current I_COM1 is zero. Therefore, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to 50%, the first compensation current I_COM1 is zero.

[0127] When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than 50%, the first current I1 is greater than the second current I2-1, making the difference between the first current I1 and the second current I2-1 positive, such that the first compensation current I_COM1 starts to increase from zero. Further, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than 50%, the first compensation current I_COM1 starts to increase from zero. Thus, the ramp compensation circuit 100 can use the first compensation current I_COM1 to compensate the amplitude of the ramp voltage Ramp' to obtain the first ramp voltage Ramp1'.

[0128] When the resistance value of the third resistor R3'-2 is equal to the resistance value of the first resistor R1', the first transistor M1 and the second transistor M2-2 are equal, and the first reference voltage VREF'1-2 is equal to the first voltage V_RC corresponding to a duty cycle of 70% of the pulse width modulation signal PWM_CTRL, the compensation start circuit 120 can generate the second current I2-2 and transmit the second current I2-2 to the compensation current output circuit 130, enabling the compensation current output circuit 130 to obtain the second current I2-2.

[0129] In this way, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to 70%, the first current I1 is less than or equal to the second current I2-2, making the difference between the first current I1 and the second current I2-2 zero or negative, such that the second compensation current I_COM2 is zero. Thus, when the duty cycle of the pulse width modulation signal PWM_CTRL is less than or equal to 70%, the second compensation current I_COM2 is zero.

[0130] When the duty cycle of the pulse width modulation signal PWM_CTRL is greater than 70%, the first current I1 is greater than the second current I2-2, making the difference between the first current I1 and the second current I2-2 positive, such that the second compensation current I_COM2 starts to increase from zero. Further, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than 70%, the second compensation current I_COM2 starts to increase from zero. Thus, the ramp compensation circuit 100 can use the second compensation current I_COM2 to compensate the amplitude of the first ramp voltage Ramp1' to obtain the second ramp voltage Ramp2', such that when the duty cycle of the pulse width modulation signal PWM_CTRL is at its maximum, the second ramp voltage Ramp2' is greater than the amplitude threshold.

[0131] Based on the description of the above embodiments, exemplarily, a possible implementation of the ramp voltage generation circuit 200. As Figure 3 shown, the ramp voltage generation circuit 200 may include: a charging current output circuit 210 and a ramp voltage output circuit 220.

[0132] The input end of the charging current output circuit 210 is electrically connected to the second end of the ramp compensation circuit 100. The output end of the charging current output circuit 210 is electrically connected to the first end of the ramp voltage output circuit 220. The second end of the ramp voltage output circuit 220 is used to connect to the pulse width modulation signal PWM_CTRL, and the third end of the ramp voltage output circuit 220 is grounded.

[0133] The charging current output circuit 210 can transmit the charging current Ic to the ramp voltage output circuit 220, so that the ramp voltage output circuit 220 can obtain the charging current Ic.

[0134] In this way, the ramp voltage output circuit 220 can charge the second capacitor Cramp in the ramp voltage output circuit 220 with the charging current Ic according to the pulse width modulation signal PWM_CTRL, so that the voltage on the second capacitor Cramp increases. And the ramp voltage output circuit 220 can use the voltage on the second capacitor Cramp as the ramp voltage Ramp', so that the ramp voltage generation circuit 200 can generate the ramp voltage Ramp' according to the pulse width modulation signal PWM_CTRL.

[0135] The charging current output circuit 210 can compensate the charging current Ic with the compensation current I_COM, so that the compensated charging current Ic increases. In this way, when the duty cycle of the pulse width modulation signal PWM_CTRL is greater than the preset duty cycle, the compensated charging current Ic changes the voltage on the second capacitor Cramp. Thus, the amplitude of the ramp voltage Ramp' can be changed, so that the ramp voltage generation circuit 200 can use the compensation current I_COM to change the amplitude of the ramp voltage Ramp'.

[0136] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the ramp voltage output circuit 220. As Figure 3 shown, the ramp voltage output circuit 220 may include: a seventh transistor M7, an eighth transistor M8, and a second capacitor Cramp.

[0137] The source of the seventh transistor M7 is electrically connected to the output end of the charging current output circuit 210. The gate of the seventh transistor M7 is used to connect to the control signal ZCDb, and the control signal ZCDb is used to characterize whether the inductor current IL in the RBCOT architecture power converter 1000 is zero-crossing. The source of the seventh transistor M7 is electrically connected to the upper plate of the second capacitor Cramp. The drain of the eighth transistor M8 is electrically connected between the source of the seventh transistor M7 and the upper plate of the second capacitor Cramp. The gate of the eighth transistor M8 is used to connect to the pulse width modulation signal PWM_CTRL, and the source of the eighth transistor M8 and the lower plate of the second capacitor Cramp are both grounded.

[0138] Among them, the source of the seventh transistor M7 is the first terminal of the ramp voltage output circuit 220, the gate of the eighth transistor M8 is the second terminal of the ramp voltage output circuit 220, and the source of the eighth transistor M8 and the lower plate of the second capacitor Cramp are both the third terminal of the ramp voltage output circuit 220.

[0139] Exemplarily, when the inductor current IL in the RBCOT architecture power converter 1000 crosses zero, the control signal ZCDb is at a low level. When the inductor current IL in the RBCOT architecture power converter 1000 does not cross zero, the control signal ZCDb is at a high level.

[0140] For example, when the pulse width modulation signal PWM_CTRL is at a low level and the inductor current IL in the RBCOT architecture power converter 1000 does not cross zero, the seventh transistor M7 is turned on and the eighth transistor M8 is turned off. In this way, the charging current Ic can charge the second capacitor Cramp, increasing the voltage on the second capacitor Cramp, so that the ramp voltage output circuit 220 can generate a ramp voltage Ramp'.

[0141] For example, when the pulse width modulation signal PWM_CTRL is at a low level and the inductor current IL in the RBCOT architecture power converter 1000 crosses zero, the seventh transistor M7 is turned off and the eighth transistor M8 is turned off. The voltage on the second capacitor Cramp remains unchanged, so that the ramp voltage Ramp' remains unchanged.

[0142] Based on the description of the above embodiments, an exemplary possible implementation of the charging current output circuit 210 is as follows. Figure 3 As shown, the charging current output circuit 210 may include: a reference current source 211 and a second current mirror 212.

[0143] The first terminal of the reference current source 211 is electrically connected to the input terminal of the second current mirror 212, the second terminal of the ramp compensation circuit 100 is electrically connected between the first terminal of the reference current source 211 and the input terminal of the second current mirror 212, and the output terminal of the second current mirror 212 is electrically connected to the first terminal of the ramp voltage output circuit 220.

[0144] Among them, the input terminal of the charging current output circuit 210 is located between the first terminal of the reference current source 211 and the input terminal of the second current mirror 212, and the output terminal of the second current mirror 212 is the output terminal of the charging current output circuit 210.

[0145] In some examples, the second current mirror 212 may include: a first P-type transistor and a second P-type transistor.

[0146] The sources of the first P-type transistor and the second P-type transistor are both used to connect to the power supply voltage VDD. The gate of the first P-type transistor is electrically connected to the drain of the first P-type transistor, the gate of the second P-type transistor, and the first terminal of the reference current source 211 respectively. The drain of the second P-type transistor is electrically connected to the first terminal of the ramp voltage output circuit 220.

[0147] The reference current source 211 can output a reference current IREF. Moreover, the reference current source 211 can transmit the reference current IREF to the second current mirror 212, enabling the second current mirror 212 to obtain the reference current IREF.

[0148] Thus, the second current mirror 212 can copy the reference current IREF according to a ratio of 1:N to obtain a charging current Ic, enabling the charging current output circuit 210 to obtain the charging current Ic.

[0149] Refer to Figure 7 , Figure 7 which is a schematic structural diagram of an RBCOT architecture power converter provided by an embodiment of the present application. As Figure 7 shown, the RBCOT architecture power converter 1000 may include: a power converter 700, a constant on-time control circuit 300, a driver 500, a trigger 400, a ramp voltage generation circuit 200, a control circuit 600, and a ramp compensation circuit 100.

[0150] The output terminal of the trigger 400 is electrically connected to the input terminal of the driver 500, the input terminal of the constant on-time control circuit 300, the first terminal of the ramp compensation circuit 100, and the first terminal of the ramp voltage generation circuit 200 respectively. The second terminal of the ramp compensation circuit 100 is electrically connected to the second terminal of the ramp voltage generation circuit 200. The output terminal of the ramp voltage generation circuit 200 is electrically connected to the first input terminal of the control circuit 600. The second input terminal of the control circuit 600 is used to connect to a feedback voltage VFB', and the feedback voltage VFB' is used to characterize the change of the output voltage VOUT' of the RBCOT architecture power converter 1000. The output terminal of the control circuit 600 is electrically connected to the set terminal of the trigger 400. The reset terminal of the trigger 400 is electrically connected to the output terminal of the constant on-time control circuit 300. The output terminal of the driver 500 is electrically connected to the control terminal of the power converter 700. The input terminal of the power converter 700 is used to connect to the input voltage VIN' of the RBCOT architecture power converter 1000. The output terminal of the power converter 700 is used to output the output voltage VOUT' of the RBCOT architecture power converter 1000.

[0151] Based on the description of the above embodiment, exemplarily, a possible implementation manner of the control circuit 600. As Figure 7As shown, the control circuit 600 may include: an error amplifier EA', an adder, a third capacitor C3, and a pulse width modulation comparator PWM'.

[0152] The positive input terminal of the error amplifier EA' and the negative input terminal of the pulse width modulation comparator PWM' are both used to connect to the feedback voltage VFB'. The negative input terminal of the error amplifier EA' and the positive input terminal of the adder are both used to connect to the second reference voltage VREF2'. The output terminal of the error amplifier EA' is electrically connected to the negative input terminal of the adder. The upper plate of the third capacitor C3 is electrically connected between the output terminal of the error amplifier EA' and the negative input terminal of the adder. The output terminal of the adder is electrically connected to the first positive input terminal of the pulse width modulation comparator PWM'. The second positive input terminal of the pulse width modulation comparator PWM' is electrically connected to the output terminal of the ramp voltage generation circuit 200. The lower plate of the third capacitor C3 is grounded.

[0153] Among them, within the off-time Toff' of the pulse width modulation signal PWM_CTRL, the ramp voltage generation circuit 200 can generate a ramp voltage Ramp'.

[0154] The error amplifier EA' can integrate the feedback voltage VFB' and the second reference voltage VREF2' to eliminate the error of the output voltage ripple. And, under the action of the third capacitor C3, the error amplifier EA' can generate a second voltage Vc and transmit the second voltage Vc to the adder, so that the adder can obtain the second voltage Vc.

[0155] In this way, the adder can sum the second voltage Vc and the second reference voltage VREF2' to obtain a third reference voltage VREF3'. And the adder can transmit the third reference voltage VREF3' to the pulse width modulation comparator PWM', so that the pulse width modulation comparator PWM' can obtain the third reference voltage VREF3'.

[0156] Among them, the third reference voltage VREF3' can be specifically expressed by formula (1):

[0157] VREF3' = VREF2' - Vc (1)

[0158] Where, VREF3' is the third reference voltage, VREF2' is the second reference voltage, and Vc is the second voltage.

[0159] Furthermore, the pulse width modulation comparator PWM' can generate a first signal FB_Low according to the second reference voltage VREF2', the ramp voltage Ramp', and the feedback voltage VFB'. And the pulse width modulation comparator PWM' can transmit the first signal FB_Low' to the flip-flop 400, so that the flip-flop 400 can obtain the first signal FB_Low'.

[0160] Among them, when the relationship between the second reference voltage VREF2', the ramp voltage Ramp', and the feedback voltage VFB' satisfies the following formula (2), the pulse width modulation comparator PWM' can generate a first signal FB_Low of high level.

[0161] VREF2'+Ramp' = VFB' (2)

[0162] Among them, VREF2' is the second reference voltage, Ramp' is the ramp voltage, and VFB' is the feedback voltage VFB'.

[0163] The constant on-time control circuit 300 can time the on-time Ton' of the pulse width modulation signal PWM_CTRL according to the pulse width modulation signal PWM_CTRL to obtain a third signal. Moreover, the constant on-time control circuit 300 can transmit the third signal to the flip-flop 400 so that the flip-flop 400 can obtain the third signal.

[0164] In this way, the flip-flop 400 can generate the pulse width modulation signal PWM_CTRL according to the first signal FB_Low' and the third signal. Moreover, the flip-flop 400 can transmit the pulse width modulation signal PWM_CTRL to the driver 500 so that the driver 500 can obtain the pulse width modulation signal PWM_CTRL.

[0165] Thus, the driver 500 can control the conduction or cutoff of the power transistor in the power converter 700 according to the pulse width modulation signal PWM_CTRL, so that the power converter 700 can convert the input voltage VIN' of the RBCOT architecture power converter 1000 to obtain the output voltage VOUT' of the RBCOT architecture power converter 1000.

[0166] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the power converter 700. As Figure 7 shown, the power converter 700 may include: a high-side power transistor Q1', a low-side power transistor Q2', an inductor L', a fourth resistor R4', a fifth resistor R5', an output capacitor Cout', an equivalent series resistor Resr' of the output capacitor Cout', a load resistor RL', and an inverter IN'.

[0167] The drain of the high-side power transistor Q1' is used to connect to the input voltage VIN' of the RBCOT architecture power converter 1000. The gate of the high-side power transistor Q1' and the input terminal of the inverter IN' are both electrically connected to the output terminal of the driver 500. The output terminal of the inverter IN' is electrically connected to the gate of the low-side power transistor Q2'. The source of the high-side power transistor Q1' is respectively electrically connected to the drain of the low-side power transistor Q2' and the first end of the inductor L'. The second end of the inductor L' is respectively electrically connected to the first end of the fourth resistor R4', the first end of the equivalent series resistor Resr' of the output capacitor Cout', and the first end of the load resistor RL'. The second end of the fourth resistor R4' is electrically connected to the first end of the fifth resistor R5'. The second end of the fourth resistor R4' is also used to output the feedback voltage VFB'. The first end of the equivalent series resistor Resr' of the output capacitor Cout' is electrically connected to the upper plate of the output capacitor Cout'. The source of the low-side power transistor Q2', the second end of the fifth resistor R5', the lower plate of the output capacitor Cout', and the second end of the load resistor RL' are all grounded.

[0168] During the current switching cycle, after the pulse width modulation signal PWM_CTRL goes high, the high-side power transistor Q1' turns on. At the same time, the constant on-time control circuit 300 is triggered. After the constant on-time control circuit 300 has gone through the on-time Ton', it will set the flip-flop, causing the pulse width modulation signal PWM_CTRL to flip from high to low. Furthermore, the high-side power transistor Q1' turns off, and the low-side power transistor Q2' turns on, causing the RBCOT architecture power converter 1000 to enter the off-time Toff'.

[0169] In addition, after the pulse width modulation signal PWM_CTRL flips from high to low, the ramp voltage generation circuit 200 can generate a ramp voltage Ramp'. In this way, when the pulse width modulation comparator PWM' compares again and causes the first signal FB_Low to flip back to high, the RBCOT architecture power converter 1000 enters the next switching cycle.

[0170] According to Equation (1) and Equation (2), the following Equation (3) can be obtained:

[0171] VREF2' - Vc + Ramp' = VFB' (3)

[0172] Since the error amplifier EA' and the adder make the difference between the ramp voltage Ramp' and the second voltage Vc zero. Therefore, the second reference voltage VREF2' is equal to the feedback voltage VFB'. Thus, the RBCOT architecture power converter 1000 achieves a high-precision output voltage.

[0173] The power converter 1000 with the RBCOT architecture provided by the embodiment of the present application has the same beneficial effects as the ramp compensation circuit 100 provided by the embodiment of the present application, which will not be elaborated here.

[0174] The embodiment of the present application further provides a chip, including: the ramp compensation circuit 100, and / or, the power converter 1000 with the RBCOT architecture.

[0175] Among them, the ramp compensation circuit 100 and the power converter 1000 with the RBCOT architecture can be integrated in one chip or in different chips. The embodiment of the present application does not make specific limitations on this.

[0176] The chip provided by the embodiment of the present application has the same beneficial effects as the ramp compensation circuit 100 provided by the embodiment of the present application, which will not be elaborated here.

[0177] The embodiment of the present application further provides an electronic device, including: a chip.

[0178] In the present application, the electronic device may include, but is not limited to: a tablet computer, a router, an industrial robot, and a television.

[0179] The electronic device provided by the embodiment of the present application has the same beneficial effects as the chip provided by the embodiment of the present application, which will not be elaborated here. Finally, it should be noted that: the above embodiments are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A slope compensation circuit, characterized in that: The slope compensation circuit is applied to a RBCOT architecture power converter, and the RBCOT architecture power converter includes: a slope voltage generating circuit; a first end of the slope compensation circuit and a first end of the slope voltage generating circuit are both used to access a pulse width modulation signal, a second end of the slope compensation circuit is electrically connected to a second end of the slope voltage generating circuit, and an output end of the slope voltage generating circuit is used to output a slope voltage; The ramp voltage generating circuit is used to generate the ramp voltage according to the pulse width modulation signal, and the duty cycle of the pulse width modulation signal is related to the amplitude of the ramp voltage; The slope compensation circuit is used to transmit at least one compensation current to the slope voltage generating circuit, and when the duty cycle of the pulse width modulation signal is less than or equal to a preset duty cycle, the amplitude of the slope voltage is greater than or equal to an amplitude threshold; when the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, the current value of the compensation current increases from zero and increases with the increase of the duty cycle of the pulse width modulation signal; The ramp voltage generating circuit is also used to compensate the amplitude of the ramp voltage using the at least one compensation current when the duty cycle of the pulse width modulation signal is greater than the preset duty cycle, until the amplitude of the compensated ramp voltage is greater than or equal to the amplitude threshold.

2. The slope compensation circuit according to claim 1, characterized in that: In the case where the at least one compensation current includes: a first compensation current and a second compensation current, the slope compensation circuit is specifically used to transmit the first compensation current and the second compensation current to the slope voltage generating circuit, when the duty cycle of the pulse width modulation signal is greater than a first preset duty cycle, the current value of the first compensation current increases from zero, and when the duty cycle of the pulse width modulation signal is greater than a second preset duty cycle, the current value of the second compensation current increases from zero, and the preset duty cycle includes: the first preset duty cycle and the second preset duty cycle; The ramp voltage generating circuit is specifically used to compensate the amplitude of the ramp voltage by using the first compensation current when the duty cycle of the pulse width modulation signal is greater than the first preset duty cycle, so as to obtain a first ramp voltage, wherein the compensated ramp voltage includes: the first ramp voltage and the second ramp voltage, and the first preset duty cycle is used to indicate that the amplitude of the ramp voltage is less than the amplitude threshold; The ramp voltage generating circuit is also specifically used to compensate the amplitude of the first ramp voltage using the second compensation current to obtain the second ramp voltage when the duty cycle of the pulse width modulation signal is greater than the second preset duty cycle, and the second preset duty cycle is used to characterize that the amplitude of the first ramp voltage is less than the amplitude threshold.

3. The slope compensation circuit according to claim 2, characterized in that: The slope compensation circuit comprises: a current conversion circuit, a compensation current output circuit and at least one compensation starting circuit; The first end of the current conversion circuit is used to access the pulse width modulation signal, the second end of the current conversion circuit is electrically connected to the first end of the at least one compensation start circuit and the first end of the compensation current output circuit respectively, the second end of the at least one compensation start circuit is used to access the reference voltage, the second end of the compensation current output circuit is electrically connected to the second end of the ramp voltage generating circuit, the third end of the current conversion circuit and the third end of the at least one compensation start circuit are both grounded, and the power supply end of the at least one compensation start circuit is electrically connected to the power supply end of the compensation current output circuit; The current conversion circuit is used to convert the pulse width modulation signal into a first current and transmit the first current to the compensation current output circuit; The compensation start circuit is used to generate a second current according to the reference voltage when the preset duty cycle is reached, and transmit the second current to the compensation current output circuit; The compensation current output circuit is used to generate the compensation current according to the first current and the second current.

4. The slope compensation circuit according to claim 3, characterized in that: The current conversion circuit comprises: a demodulation circuit and a voltage-current conversion circuit; The input end of the demodulation circuit is used to receive the pulse width modulation signal, the output end of the demodulation circuit is electrically connected to the control end of the voltage-current conversion circuit, the first end of the voltage-current conversion circuit is electrically connected to the first end of the at least one compensation start circuit, and the second end of the voltage-current conversion circuit is grounded; The demodulation circuit is used to demodulate the pulse width modulation signal into a first voltage and transmit the first voltage to the voltage-current conversion circuit; The voltage-current conversion circuit is used to convert the first voltage into the first current.

5. The slope compensation circuit according to claim 4, characterized in that: The voltage-current conversion circuit includes: a first resistor and a first transistor; The gate of the first transistor is electrically connected to the output end of the demodulation circuit, the source of the first transistor is electrically connected to the first end of the at least one compensation start circuit, and the source of the first transistor is grounded.

6. The slope compensation circuit according to claim 4, characterized in that: The demodulation circuit includes: a second resistor and a first capacitor; The first end of the second resistor is used to access the pulse width modulation signal, the second end of the second resistor is electrically connected to the control end of the voltage-current conversion circuit, the upper plate of the first capacitor is electrically connected between the second end of the second resistor and the control end of the voltage-current conversion circuit, and the lower plate of the first capacitor is grounded.

7. The slope compensation circuit according to claim 3, characterized in that: The compensation start circuit comprises: a first current mirror, a second transistor and a third resistor; The gate of the second transistor is used to access the reference voltage, the drain of the second transistor is electrically connected to the input end of the first current mirror, the power supply end of the first current mirror is electrically connected to the power supply end of the compensation current output circuit, the output end of the first current mirror is electrically connected to the second end of the current conversion circuit, the source of the second transistor is electrically connected to the first end of the third resistor, and the second end of the third resistor is grounded.

8. The slope compensation circuit according to claim 7, characterized in that: The first current mirror comprises: a third transistor and a fourth transistor; The source of the third transistor and the source of the fourth transistor are both electrically connected to the power supply terminal of the compensation current output circuit, the gate of the third transistor is electrically connected to the gate of the fourth transistor, the drain of the fourth transistor and the drain of the second transistor respectively, and the drain of the third transistor is electrically connected to the second end of the current conversion circuit.

9. The slope compensation circuit according to claim 3, characterized in that: The compensation current output circuit comprises: a fifth transistor and a sixth transistor; The source of the fifth transistor and the source of the sixth transistor are both electrically connected to the power supply terminal of the at least one compensation starting circuit, the gate of the sixth transistor is electrically connected to the gate of the fifth transistor, the drain of the fifth transistor and the second end of the current conversion circuit respectively, and the drain of the sixth transistor is electrically connected to the second end of the ramp voltage generating circuit.

10. The slope compensation circuit according to any one of claims 1 to 9, characterized in that: The slope voltage generating circuit comprises: a charging current output circuit and a slope voltage output circuit; The input end of the charging current output circuit is electrically connected to the second end of the slope compensation circuit, the output end of the charging current output circuit is electrically connected to the first end of the slope voltage output circuit, the second end of the slope voltage output circuit is used to access the pulse width modulation signal, and the third end of the slope voltage output circuit is grounded; The charging current output circuit is used to transmit the charging current to the ramp voltage output circuit; The ramp voltage output circuit is used to charge a second capacitor in the ramp voltage output circuit using the charging current according to the pulse width modulation signal, and use the voltage on the second capacitor as the ramp voltage; The charging current output circuit is further used to compensate the charging current using the compensation current to compensate for the amplitude of the ramp voltage.

11. The slope compensation circuit according to claim 10, characterized in that: The ramp voltage output circuit comprises: a seventh transistor, an eighth transistor and a second capacitor; The source of the seventh transistor is electrically connected to the output end of the charging current output circuit, the gate of the seventh transistor is used to access a control signal, and the control signal is used to indicate whether the inductor current in the RBCOT architecture power converter passes through zero, the source of the seventh transistor is electrically connected to the upper plate of the second capacitor, the drain of the eighth transistor is electrically connected between the source of the seventh transistor and the upper plate of the second capacitor, the gate of the eighth transistor is used to access the pulse width modulation signal, and the source of the eighth transistor and the lower plate of the second capacitor are both grounded.

12. The slope compensation circuit according to claim 10, characterized in that: The charging current output circuit comprises: a reference current source and a second current mirror; The first end of the reference current source is electrically connected to the input end of the second current mirror, the second end of the slope compensation circuit is electrically connected between the first end of the reference current source and the input end of the second current mirror, and the output end of the second current mirror is electrically connected to the first end of the slope voltage output circuit; The reference current source is used to output a reference current and transmit the reference current to the second current mirror; The second current mirror is used to copy the reference current to obtain the charging current.

13. A RBCOT architecture power converter, characterized in that: The RBCOT architecture power converter comprises: a power converter, a constant on-time control circuit, a driver, a trigger, a ramp voltage generating circuit, a control circuit and a slope compensation circuit as claimed in any one of claims 1 to 12; The output end of the trigger is electrically connected to the input end of the driver, the input end of the constant on-time control circuit, the first end of the slope compensation circuit and the first end of the slope voltage generating circuit respectively; the second end of the slope compensation circuit is electrically connected to the second end of the slope voltage generating circuit; the output end of the slope voltage generating circuit is electrically connected to the first input end of the control circuit; the second input end of the control circuit is used to access a feedback voltage, and the feedback voltage is used to characterize the change of the output voltage of the RBCOT architecture power converter; the output end of the control circuit is electrically connected to the set end of the trigger; the reset end of the trigger is electrically connected to the output end of the constant on-time control circuit; the output end of the driver is electrically connected to the control end of the power converter; the input end of the power converter is used to access the input voltage of the RBCOT architecture power converter; and the output end of the power converter is used to output the output voltage of the RBCOT architecture power converter.

14. A chip, characterized in that: include: The slope compensation circuit according to any one of claims 1 to 12, and / or the RBCOT architecture power converter according to claim 13.

15. An electronic device, characterized in that: include: The chip as claimed in claim 14.

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