Output amplitude limiting device

Abstract

The invention discloses an output amplitude limiting device, which is applied to a switching power supply and comprises an error amplifier, an output resistor, an amplifier and a current bias module, the input end of the error amplifier is connected with the switching power supply, the reference voltage and the current bias module, and the reference voltage is used for limiting the output voltage of the switching power supply within a preset range; the output end of the error amplifier is connected with the first end of the output resistor; the input end of the amplifier is connected with a reference voltage and current bias module; the output end of the amplifier is connected with the second end of the output resistor and the input end of the amplifier; and the current bias module is connected with the reference voltage. The output amplitude limiting voltage is related to the reference voltage and the output resistance, the resistance has good matching performance on the same chip, and the precision of the reference voltage is high, so that the amplitude limiting voltage is slightly influenced by process fluctuation, more accurate amplitude limiting control can be realized, and the influence of size deviation of a traditional MOS (Metal Oxide Semiconductor) tube on the amplitude limiting voltage is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to an output limiting device. Background Art

[0002] With the rapid development of fields such as artificial intelligence, Internet of Things, and aerospace, the number of portable intelligent terminals and communication devices is increasing continuously. All devices require high-efficiency and lightweight power supplies. Switching power supplies (DC-DC) have become the mainstream power supplies. A switching power supply converter with high stability and high efficiency is crucial for effectively maintaining the normal operation of devices for a long time and can ensure the safety of the devices. By limiting the output voltage swing of the error amplifier, it is possible to prevent the output of the error amplifier from being too large and having too large a swing, which may cause a decrease in the efficiency of the switching power supply and damage to the inductor, thereby leading to abnormal operation of the system. Therefore, there is an urgent need for an output swing limiting device to accurately limit the swing voltage.

[0003] However, in the traditional output clamping method using the diode connection of MOS transistors, during actual production, there will be deviations in the size of the MOS transistors, which will cause the output limiting to be greatly affected by the process, and thus the accuracy of the limiting voltage is not high. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art, the purpose of the present invention is to provide an output limiting device whose output limiting voltage is not affected by the size of the MOS transistor, so that the output limiting voltage is less affected by process fluctuations, thereby improving the accuracy of the limiting voltage.

[0005] To solve the above technical problems, the present invention is implemented according to the following solutions: There is provided an output limiting device applied to a switching power supply, including an error amplifier, an output resistor, an amplifier, and a current biasing module; The input end of the error amplifier is connected to the switching power supply, a reference voltage, and the current biasing module. The reference voltage is used to limit the output voltage of the switching power supply within a preset range; the output end of the error amplifier is connected to the first end of the output resistor; the input end of the amplifier is connected to the reference voltage and the current biasing module; the output end of the amplifier is connected to the second end of the output resistor and the input end of the amplifier; the current biasing module is connected to the reference voltage.

[0006] Compared with the prior art, the beneficial effects of an output limiting device of the present invention are as follows: By adopting a limiting device composed of an error amplifier, an output resistor, and an amplifier, the output limiting voltage is related to the reference voltage and the output resistor. Since the resistors have good matching on the same chip and the accuracy of the reference voltage is high, the limiting voltage is less affected by process fluctuations, enabling more accurate limiting control and avoiding the influence of traditional MOS transistor size deviation on the limiting voltage.

[0007] Optionally, the error amplifier includes an input differential pair module, a current distribution module, and a current mirror module; The input differential pair module is connected to the power supply and the current bias module, and the power supply is used to provide the working power supply; the current distribution module is connected to the switching power supply, the reference voltage, the input differential pair module, and the current mirror module; the current mirror module is connected to the output resistor and the power supply.

[0008] Optionally, the input differential pair module includes a first MOS transistor and a second MOS transistor; The power supply is connected to the source electrodes of the first MOS transistor and the second MOS transistor; the drain electrode of the first MOS transistor is connected to the current bias module, the gate electrode of the first MOS transistor, and the gate electrode of the second MOS transistor; the drain electrode of the second MOS transistor is connected to the current distribution module.

[0009] Optionally, the current distribution module includes a third MOS transistor and a fourth MOS transistor; The drain electrode of the second MOS transistor is connected to the source electrodes of the third MOS transistor and the fourth MOS transistor; the switching power supply is connected to the gate electrode of the third MOS transistor; the gate electrode of the fourth MOS transistor is connected to the reference voltage; the current mirror module is connected to the drain electrodes of the third MOS transistor and the fourth MOS transistor.

[0010] Optionally, the current mirror module includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor; The drain electrode of the fifth MOS transistor is connected to the drain electrode of the third MOS transistor, the gate electrode of the fifth MOS transistor, and the gate electrode of the eighth MOS transistor; the drain electrode of the sixth MOS transistor is connected to the drain electrode of the fourth MOS transistor, the gate electrode of the sixth MOS transistor, and the gate electrode of the seventh MOS transistor; The drain electrode of the seventh MOS transistor is connected to the drain electrode of the ninth MOS transistor, the gate electrode of the ninth MOS transistor, and the gate electrode of the tenth MOS transistor; the drain electrode of the eighth MOS transistor is connected to the drain electrode of the tenth MOS transistor and the output resistor; The source electrodes of the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are grounded together; the power supply is connected to the source electrodes of the ninth MOS transistor and the tenth MOS transistor.

[0011] Optionally, the amplifier includes an input module and a distribution module; The input module is connected to the power supply, the current bias module, and the distribution module; the distribution module is connected to the reference voltage and the output resistor.

[0012] Optionally, the input module includes an eleventh MOS transistor and a twelfth MOS transistor; The power supply is connected to the source electrodes of the eleventh MOS transistor and the twelfth MOS transistor; the drain electrode of the eleventh MOS transistor is connected to the current bias module, the gate electrode of the eleventh MOS transistor, and the gate electrode of the twelfth MOS transistor; the drain electrode of the twelfth MOS transistor is connected to the distribution module.

[0013] Optionally, the distribution module includes a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a sixteenth MOS transistor; The drain electrode of the twelfth MOS transistor is connected to the source electrodes of the thirteenth MOS transistor and the fourteenth MOS transistor; The gate electrode of the thirteenth MOS transistor is connected to the reference voltage; the drain electrode of the thirteenth MOS transistor is connected to the drain electrode of the fifteenth MOS transistor, the gate electrode of the fifteenth MOS transistor, and the gate electrode of the sixteenth MOS transistor; The gate electrode of the fourteenth MOS transistor is connected to the drain electrode of the fourteenth MOS transistor, the drain electrode of the sixteenth MOS transistor, and the output resistor; The source electrodes of the fifteenth MOS transistor and the sixteenth MOS transistor are grounded together.

[0014] Optionally, the current bias module includes an amplification unit and a current feedback unit; The amplification unit is connected to the reference voltage and the current feedback unit; the current feedback unit is connected to the error amplifier and the amplifier.

[0015] Optionally, the current feedback unit includes a seventeenth MOS transistor, an eighteenth MMOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, and a reference resistor; The amplification unit is connected to the drain electrode of the seventeenth MOS transistor, the gate electrode of the seventeenth MOS transistor, the gate electrode of the eighteenth MOS transistor, and the reference resistor; The drain of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor, the gate of the nineteenth MOS transistor, the gate of the twentieth MOS transistor, and the gate of the twenty-first MOS transistor; The drain of the twentieth MOS transistor is connected to the error amplifier; the drain of the twenty-first MOS transistor is connected to the amplifier; The sources of the seventeenth MOS transistor and the eighteenth MMOS transistor are grounded together; the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor, and the reference resistor are grounded together. Description of the Drawings

[0016] Figure 1 It is a structural block diagram of the output limiting device of the present invention; Figure 2 It is a circuit schematic diagram of the error amplifier of the present invention; Figure 3 It is a circuit schematic diagram of the amplifier of the present invention; Figure 4 It is a circuit schematic diagram of the current bias module of the present invention.

[0017] Description of the reference numerals: 1, error amplifier; 101, input differential pair module; 102, current distribution module; 103, current mirror module; 2, output resistor; 3, amplifier; 301, input module; 302, distribution module; 4, current bias module; 401, amplification unit; 402, current feedback unit. Detailed Embodiments

[0018] The following describes the preferred embodiments of the present invention with reference to the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0019] When the following description refers to the drawings, unless otherwise indicated, equal numbers in different drawings represent equal or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0020] See Figure 1As shown, the present invention provides an output limiting device applied to a switching power supply, which includes an error amplifier 1, an output resistor 2, an amplifier 3, and a current biasing module 4; the input end of the error amplifier 1 is connected to the switching power supply, a reference voltage V REF , and the current biasing module 4. Specifically, the input end of the error amplifier 1 is connected to the output end of the switching power supply, and the reference voltage V REF is used to limit the output voltage V P of the switching power supply within a preset range, that is, to clamp the output voltage V P of the switching power supply to achieve the limiting of the output voltage V P of the switching power supply; the output end of the error amplifier 1 is connected to the first end of the output resistor 2; the input end of the amplifier 3 is connected to the reference voltage and the current biasing module 4; the output end of the amplifier 3 is connected to the second end of the output resistor 2 and the input end of the amplifier 3; the current biasing module 4 is connected to the reference voltage.

[0021] In an embodiment of the present invention, the output end of the error amplifier 1 serves as the output end of the output limiting device, which is used to output the limited voltage V P after the output voltage V out of the switching power supply is clamped.

[0022] Refer to Figure 2 As shown, the error amplifier 1 includes an input differential pair module 101, a current distribution module 102, and a current mirror module 103; the input differential pair module 101 is connected to a power supply AVDD and the current biasing module 4, and the power supply AVDD is used to provide a working power supply; the current distribution module 102 is connected to the switching power supply, the reference voltage, the input differential pair module 101, and the current mirror module 103; the current mirror module 103 is connected to the output resistor 2 and the power supply AVDD (AVSS is the negative end of the power supply and can be regarded as grounded).

[0023] Among them, the input differential pair module 101 includes a first MOS transistor M1 and a second MOS transistor M2; the power supply AVDD is connected to the source of the first MOS transistor M1 and the source of the second MOS transistor M2; the drain of the first MOS transistor M1 is connected to the current biasing module 4, the gate of the first MOS transistor M1, and the gate of the second MOS transistor M2; the drain of the second MOS transistor M2 is connected to the current distribution module 102.

[0024] The current distribution module 102 includes a third MOS transistor M3 and a fourth MOS transistor M4; the drain of the second MOS transistor M2 is connected to the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4; the switching power supply is connected to the gate of the third MOS transistor M3. Specifically, the output voltage V P of the switching power supply is connected to the gate of the third MOS transistor M3; the gate of the fourth MOS transistor M4 is connected to the reference voltage V REFConnection; The current mirror module 103 is connected to the drains of the third MOS transistor M3 and the fourth MOS transistor M4.

[0025] The current mirror module 103 includes a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10; the drain of the fifth MOS transistor M5 is connected to the drains of the third MOS transistor M3, the gate of the fifth MOS transistor M5, and the gate of the eighth MOS transistor M8; the drain of the sixth MOS transistor M6 is connected to the drains of the fourth MOS transistor M4, the gate of the sixth MOS transistor M6, and the gate of the seventh MOS transistor M7.

[0026] The drain of the seventh MOS transistor M7 is connected to the drains of the ninth MOS transistor M9, the gate of the ninth MOS transistor M9, and the gate of the tenth MOS transistor M10; the drain of the eighth MOS transistor M8 is connected to the drain of the tenth MOS transistor M10 and the output resistor 2.

[0027] The sources of the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are grounded (connected to the negative terminal AVSS of the power supply); the power supply AVDD is connected to the sources of the ninth MOS transistor M9 and the tenth MOS transistor M10.

[0028] The reference voltage V REF is a fixed value that does not change. When the output limiting device operates in a stable state, its output voltage V P is equal to the reference voltage V REF , and the current of the second MOS transistor M2 is evenly divided between the third MOS transistor M3 and the fourth MOS transistor M4.

[0029] Assume that the current output by the current bias module 4 is 2*I, that is, the current flowing through the first MOS transistor M1 is 2*I. The second MOS transistor M2 mirrors the first MOS transistor M1, and the mirror ratio is 1, that is, the current flowing through the second MOS transistor M2 is equal to the current flowing through the first MOS transistor M1. Then the current flowing through the second MOS transistor M2 is also 2*I. Since the current of the second MOS transistor M2 is evenly divided between the third MOS transistor M3 and the fourth MOS transistor M4, the current flowing through the third MOS transistor M3 is I, and the current flowing through the fourth MOS transistor M4 is I.

[0030] The fifth MOS transistor M5 and the sixth MOS transistor M6 are respectively connected in series with the third MOS transistor M3 and the fourth MOS transistor M4, so the current flowing through the third MOS transistor M3 and the current flowing through the fourth MOS transistor M4 are also I respectively.

[0031] The seventh MOS transistor M7 mirrors the sixth MOS transistor M6 with a mirror ratio of 1, that is, the current flowing through the seventh MOS transistor M7 is equal to the current flowing through the sixth MOS transistor M6; the eighth MOS transistor M8 mirrors the fifth MOS transistor M5 with a mirror ratio of 1, that is, the current flowing through the eighth MOS transistor M8 is equal to the current flowing through the fifth MOS transistor M5. Then the currents flowing through the seventh MOS transistor M7 and the eighth MOS transistor M8 are also I respectively.

[0032] The ninth MOS transistor M9 is in series with the seventh MOS transistor M7, so the current flowing through the ninth MOS transistor M9 is also I; the tenth MOS transistor M10 mirrors the ninth MOS transistor M9 with a mirror ratio of 1, that is, the current flowing through the tenth MOS transistor M10 is equal to the current flowing through the ninth MOS transistor M9. Then the current flowing through the tenth MOS transistor M10 is also I.

[0033] At this time, the current flowing through the tenth MOS transistor M10 is equal to the current flowing through the eighth MOS transistor M8. Therefore, no current flows through the output resistor 2. Also, since the negative input terminal of the amplifier 3 is connected to its output terminal and its positive input terminal is connected to the reference voltage V REF connected, the amplifier 3 forms negative feedback. According to the principle of virtual short and virtual open, it can be obtained that the output terminal A1_OUT of the amplifier 3 is equal to the reference voltage V REF equal. At this time, the output voltage V OUT of the error amplifier 1 is V REF , that is, the limiting voltage output by the output limiting device at this time is equal to the reference voltage V REF , that is, the limiting voltage at this time is V REF .

[0034] When the output voltage V P of the switching power supply increases, the current flowing through the third MOS transistor M3 will decrease. The maximum current change of the third MOS transistor M3 is ΔI, and the reduced current will all flow to the fourth MOS transistor M4; when reaching the limit situation, that is, when the current flowing through the third MOS transistor M3 is 0, all the current 2*I of the second MOS transistor M2 will flow through the fourth MOS transistor M4.

[0035] The fifth MOS transistor M5 is in series with the third MOS transistor M3, so the current flowing through the fifth MOS transistor M5 is 0; the sixth MOS transistor M6 is in series with the fourth MOS transistor M4, so the current flowing through the sixth MOS transistor M6 is 2*I.

[0036] The eighth MOS transistor M8 mirrors the fifth MOS transistor M5 with a mirror ratio of 1, that is, the current flowing through the eighth MOS transistor M8 is equal to the current flowing through the fifth MOS transistor M5. Then the current flowing through the eighth MOS transistor M8 is also 0. The seventh MOS transistor M7 mirrors the sixth MOS transistor M6 with a mirror ratio of 1, that is, the current flowing through the seventh MOS transistor M7 is equal to the current flowing through the sixth MOS transistor M6. Then the current flowing through the seventh MOS transistor M7 is 2*I.

[0037] The seventh MOS transistor M7 and the ninth MOS transistor M9 are in series. Then the current flowing through the ninth MOS transistor M9 is also 2*I. The tenth MOS transistor M10 mirrors the ninth MOS transistor M9 with a mirror ratio of 1, that is, the current flowing through the tenth MOS transistor M10 is equal to the current flowing through the ninth MOS transistor M9. Then the current flowing through the tenth MOS transistor M10 is 2*I.

[0038] At this time, the current flowing through the eighth MOS transistor M8 is 0, and the current flowing through the tenth MOS transistor M10 is 2*I. Therefore, the current flowing through the output resistor 2 is 2*I. Assuming the resistance value of the output resistor 2 is , then the voltage across the output resistor 2 is , that is, the output voltage V OUT of the error amplifier 1 at this time is , that is, at this time, the expression of the limiting voltage output by the output limiting device is:

[0039] Among them, is the limiting voltage, is the reference voltage, is the output current of the current bias module 4, is the resistance value of the output resistor 2.

[0040] When the output voltage V P of the switching power supply decreases, the current flowing through the third MOS transistor M3 will increase. The maximum current change of the third MOS transistor M3 is ΔI, and the increased current is split from the fourth MOS transistor M4. When reaching the extreme case, that is, when the current flowing through the fourth MOS transistor M4 is 0, all the current 2*I of the second MOS transistor M2 will flow through the third MOS transistor M3.

[0041] The fifth MOS transistor M5 and the third MOS transistor M3 are in series. Then the current flowing through the fifth MOS transistor M5 is 2*I. The sixth MOS transistor M6 and the fourth MOS transistor M4 are in series. Then the current flowing through the sixth MOS transistor M6 is 0.

[0042] The eighth MOS transistor M8 mirrors the fifth MOS transistor M5, and the mirror ratio is 1, that is, the current flowing through the eighth MOS transistor M8 is equal to the current flowing through the fifth MOS transistor M5. Then the current flowing through the eighth MOS transistor M8 is also 2*I; the seventh MOS transistor M7 mirrors the sixth MOS transistor M6, and the mirror ratio is 1, that is, the current flowing through the seventh MOS transistor M7 is equal to the current flowing through the sixth MOS transistor M6. Then the current flowing through the seventh MOS transistor M7 is 0.

[0043] The seventh MOS transistor M7 is connected in series with the ninth MOS transistor M9. Then the current flowing through the ninth MOS transistor M9 is also 0; the tenth MOS transistor M10 mirrors the ninth MOS transistor M9, and the mirror ratio is 1, that is, the current flowing through the tenth MOS transistor M10 is equal to the current flowing through the ninth MOS transistor M9. Then the current flowing through the tenth MOS transistor M10 is 0.

[0044] At this time, the current flowing through the eighth MOS transistor M8 is 2*I, and the current flowing through the tenth MOS transistor M10 is 0. Therefore, the current flowing through the output resistor 2 is -2*I. Assuming the resistance value of the output resistor 2 is , then the voltage across the output resistor 2 is , that is, the output voltage V OUT of the error amplifier 1 at this time is , that is, the expression of the limiting voltage output by the output limiting device at this time is:

[0045] Among them, is the limiting voltage, is the reference voltage, is the output current of the current bias module 4, is the resistance value of the output resistor 2.

[0046] From the above analysis, it can be seen that when the output current of the current bias module 4 is fixed, the maximum value of the limiting voltage output by the output limiting device is , and the minimum value is . It can be seen that the limiting voltage is only related to the reference voltage and the output resistor 2, and has nothing to do with the process parameters of the MOS transistors.

[0047] Refer to Figure 3 As shown, the amplifier 3 includes an input module 301 and a distribution module 302; the input module 301 is connected to the power supply AVDD (AVSS is the negative terminal of the power supply and can be regarded as grounded), the current bias module 4, and the distribution module 302; the distribution module 302 is connected to the reference voltage V REF , and the output resistor 2.

[0048] Among them, the input module 301 includes the eleventh MOS transistor M11 and the twelfth MOS transistor M12; the power supply AVDD is connected to the source of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12; the drain of the eleventh MOS transistor M11 is connected to the current bias module 4, the gate of the eleventh MOS transistor M11, and the gate of the twelfth MOS transistor M12; the drain of the twelfth MOS transistor M12 is connected to the distribution module 302.

[0049] The distribution module 302 includes the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, and the sixteenth MOS transistor M16; the drain of the twelfth MOS transistor M12 is connected to the source of the thirteenth MOS transistor M13 and the source of the fourteenth MOS transistor M14; the gate of the thirteenth MOS transistor M13 is connected to the reference voltage V REF connection; the drain of the thirteenth MOS transistor M13 is connected to the drain of the fifteenth MOS transistor M15, the gate of the fifteenth MOS transistor M15, and the gate of the sixteenth MOS transistor M16; the gate of the fourteenth MOS transistor M14 is connected to the drain of the fourteenth MOS transistor M14, the drain of the sixteenth MOS transistor M16, and the output resistor 2; the source of the fifteenth MOS transistor M15 and the source of the sixteenth MOS transistor M16 are grounded (connected to the negative terminal AVSS of the power supply).

[0050] See Figure 4 As shown, the current bias module 4 includes an amplification unit 401 and a current feedback unit 402; the amplification unit 401 is connected to the reference voltage V REF , and the current feedback unit 402; the current feedback unit 402 is connected to the error amplifier 1 and the amplifier 3.

[0051] The current feedback unit 402 includes the seventeenth MOS transistor M17, the eighteenth MMOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the twenty-first MOS transistor M21, and the reference resistor R bias ; the amplification unit 401 is connected to the drain of the seventeenth MOS transistor M17, the gate of the seventeenth MOS transistor M17, the gate of the eighteenth MOS transistor M18, and the reference resistor R bias connection; the drain of the eighteenth MOS transistor M18 is connected to the drain of the nineteenth MOS transistor M19, the gate of the nineteenth MOS transistor M19, the gate of the twentieth MOS transistor M20, and the gate of the twenty-first MOS transistor M21; the drain of the twentieth MOS transistor M20 is connected to the error amplifier 1; the drain of the twenty-first MOS transistor M21 is connected to the amplifier 3; the source of the seventeenth MOS transistor M17 and the source of the eighteenth MMOS transistor M18 are grounded; the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the twenty-first MOS transistor M21, and the reference resistor R bias are grounded.

[0052] The amplification unit 401 is specifically an amplifier 3. Assuming that the current EA_IBP output to the error amplifier 1 and the current A1_IBP of the amplifier 3 are both I, since the positive input terminal of the amplification unit 401 is connected to its output terminal and its negative input terminal is connected to the reference voltage, a negative feedback is formed. According to the principle of negative feedback, the expression of the current I output from the current bias module 4 to the error amplifier 1 and the amplifier 3 is V REF / R bias Substituting the expression of the current I into the expression of the limiting voltage, the maximum value of the limiting voltage can be obtained as:

[0053] Among them, is the maximum value of the limiting voltage, is the reference voltage, is the resistance value of the output resistor 2, is the resistance value of the reference resistor.

[0054] The minimum value of the limiting voltage is:

[0055] Among them, is the maximum value of the limiting voltage, is the reference voltage, is the resistance value of the output resistor 2, is the resistance value of the reference resistor.

[0056] It can be seen that the limiting voltage is related to the reference voltage and the resistance value of the output resistor 2 and the resistance value of the reference resistor . The reference voltage can be made very accurate. The resistance value of the output resistor 2 and the resistance value of the reference resistor exist in a ratio. On the layout, the ratio between the resistance value of the output resistor 2 and the resistance value of the reference resistor can be made very accurate. Therefore, the output limiting device proposed by the present invention can accurately limit the output voltage of the switching power supply.

[0057] The above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An output limiting device, applied to a switching power supply, characterized in that: It includes an error amplifier, an output resistor, an amplifier and a current bias module; The input end of the error amplifier is connected to the switching power supply, the reference voltage, and the current bias module, and the reference voltage is used to limit the output voltage of the switching power supply within a preset range; the output end of the error amplifier is connected to the first end of the output resistor; the input end of the amplifier is connected to the reference voltage and the current bias module; the output end of the amplifier is connected to the second end of the output resistor and the input end of the amplifier; The current bias module is connected to the reference voltage.

2. An output limiting device according to claim 1, characterized in that: The error amplifier includes an input differential pair module, a current distribution module and a current mirror module; The input differential pair module is connected to a power supply and the current bias module, and the power supply is used to provide a working power supply; the current distribution module is connected to the switching power supply, the reference voltage, the input differential pair module, and the current mirror module; the current mirror module is connected to the output resistor and the power supply.

3. An output limiting device according to claim 2, characterized in that: The input differential pair module includes a first MOS transistor and a second MOS transistor; The power supply is connected to the source of the first MOS tube and the source of the second MOS tube; the drain of the first MOS tube is connected to the current bias module, the gate of the first MOS tube and the gate of the second MOS tube; the drain of the second MOS tube is connected to the current distribution module.

4. An output limiting device according to claim 3, characterized in that: The current distribution module includes a third MOS tube and a fourth MOS tube; The drain of the second MOS tube is connected to the source of the third MOS tube and the source of the fourth MOS tube; the switching power supply is connected to the gate of the third MOS tube; the gate of the fourth MOS tube is connected to the reference voltage; the current mirror module is connected to the drain of the third MOS tube and the drain of the fourth MOS tube.

5. An output limiting device according to claim 4, characterized in that: The current mirror module includes a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube; The drain of the fifth MOS tube is connected to the drain of the third MOS tube, the gate of the fifth MOS tube, and the gate of the eighth MOS tube; the drain of the sixth MOS tube is connected to the drain of the fourth MOS tube, the gate of the sixth MOS tube, and the gate of the seventh MOS tube; The drain of the seventh MOS tube is connected to the drain of the ninth MOS tube, the gate of the ninth MOS tube, and the gate of the tenth MOS tube; the drain of the eighth MOS tube is connected to the drain of the tenth MOS tube and the output resistor; The source of the fifth MOS tube, the source of the sixth MOS tube, the source of the seventh MOS tube, and the source of the eighth MOS tube are connected to a common ground; The power supply is connected to the source of the ninth MOS tube and the source of the tenth MOS tube.

6. The output limiting device according to claim 1, characterized in that: The amplifier includes an input module and a distribution module; The input module is connected to the power supply, the current bias module and the distribution module; the distribution module is connected to the reference voltage and the output resistor.

7. An output limiting device according to claim 6, characterized in that: The input module includes an eleventh MOS tube and a twelfth MOS tube; The power supply is connected to the source of the eleventh MOS tube and the source of the twelfth MOS tube; the drain of the eleventh MOS tube is connected to the current bias module, the gate of the eleventh MOS tube, and the gate of the twelfth MOS tube; the drain of the twelfth MOS tube is connected to the distribution module.

8. An output limiting device according to claim 7, characterized in that: The distribution module includes a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, and a sixteenth MOS tube; The drain of the twelfth MOS tube is connected to the source of the thirteenth MOS tube and the source of the fourteenth MOS tube; The gate of the thirteenth MOS tube is connected to the reference voltage; the drain of the thirteenth MOS tube is connected to the drain of the fifteenth MOS tube, the gate of the fifteenth MOS tube, and the gate of the sixteenth MOS tube; The gate of the fourteenth MOS tube is connected to the drain of the fourteenth MOS tube, the drain of the sixteenth MOS tube, and the output resistor; The source of the fifteenth MOS tube and the source of the sixteenth MOS tube are connected to a common ground.

9. The output limiting device according to claim 1, characterized in that: The current bias module includes an amplification unit and a current feedback unit; The amplification unit is connected to the reference voltage and the current feedback unit; the current feedback unit is connected to the error amplifier and the amplifier.

10. An output limiting device according to claim 9, characterized in that: The current feedback unit includes a seventeenth MOS tube, an eighteenth MMOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube and a reference resistor; The amplifying unit is connected to the drain of the seventeenth MOS tube, the gate of the seventeenth MOS tube, the gate of the eighteenth MOS tube, and the reference resistor; The drain of the eighteenth MOS tube is connected to the drain of the nineteenth MOS tube, the gate of the nineteenth MOS tube, the gate of the twentieth MOS tube, and the gate of the twenty-first MOS tube; The drain of the 20th MOS tube is connected to the error amplifier; the drain of the 21st MOS tube is connected to the amplifier; The source of the seventeenth MOS tube and the source of the eighteenth MMOS tube are grounded; the nineteenth MOS tube, the twentieth MOS tube, the twenty-first MOS tube and the reference resistor are grounded.

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