Domino type multistage interlocking power consumption management circuit

Abstract

The invention discloses a domino type multi-stage interlocking power consumption management circuit, belongs to the technical field of integrated circuits, and mainly solves the problem that a traditional energy consumption management chip is difficult to adapt to fluctuation of process, voltage and temperature and possibly causes logic locking failure of a chip under special working conditions. The circuit comprises a fuse logic generation circuit, a latch matrix, a post-stage module and a power supply sensing front end, and further comprises a multi-stage timing interlocking circuit with the domino effect. According to the invention, thought optimization is carried out on power consumption management and locking time sequence, power consumption is optimized and managed by adopting a multi-stage interlocking mode, the control effect of an enable signal is abandoned, self-adaptive sequential control is carried out on the dimension of a power supply, the mode is a complementary power-on time sequence management mode, effective logic locking is ensured, and meanwhile, the power-on time sequence management efficiency is improved. And extra power consumption is reduced in a self-adaptive manner, and positive practical significance and practical value are achieved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology, and specifically relates to a domino - type multi - stage interlocking power management circuit. Background Art

[0002] A power management circuit is a hardware design module that optimizes energy utilization efficiency by controlling the power consumption of an electronic device or system. Its core objectives include extending battery life, reducing heat generation, minimizing energy waste, and enhancing system reliability.

[0003] In the prior art, as Figure 1 、 Figure 2 shown, a traditional energy consumption management chip using fuse trimming technology generally has the following power - on sequence stages: Stage 1: Power - on to stabilization The power management module monitors the voltage to ensure that it reaches the stable threshold, and the relevant fuse circuit starts to work.

[0004] Stage 2: Fuse data reading: The fuse logic generation circuit including the fuse array starts to establish the fuse logic. The hardware reads the programmed fuse logic from the fuse array and transmits it to the subsequent module, where it is decoded into specific control signals, such as the reference voltage trimming control word, clock selection control word, check key, etc.

[0005] Stage 3: Logic locking takes effect After the subsequent module updates its working state according to the fuse value, the relevant logic values are locked by the enable signal. At this time, the chip starts to be enabled and enters the working state with the fuse logic value locked.

[0006] Stage 4: Normal operation The chip enters the preset working mode, and all logical behaviors and control words are constrained by the logic values configured by the fuse.

[0007] The above - mentioned power - on stages have problems of ineffective power consumption. After the chip is powered on and the fuse logic is read, the fuse logic decoding circuit and the fuse bias circuit still continue to work in the non - enabled or enabled state. The continuous activation of the fuse programming circuit will cause static power leakage. If the relevant module is turned off after enabling, there will be a problem of relatively large turn - off static power before enabling; if the relevant module is turned off before enabling and the logic establishment is only started after enabling, the chip cannot enter the correct logical initial state after power - on and before enabling, and there will also be a problem of relatively large power consumption during operation.

[0008] If the fuse bias circuit and the fuse logic generation circuit are turned off, there is a risk of timing competition, which may cause the Fuse data latch to fail. Using a fixed delay element to handle this problem makes it difficult to adapt to process, voltage, and temperature fluctuations, which may lead to logic locking failure under special working conditions. Summary of the Invention

[0009] The purpose of the present invention is to provide a domino - type multi - stage interlocking power management circuit, mainly to solve the problem that traditional energy - consumption management chips are difficult to adapt to process, voltage, and temperature fluctuations, which may lead to chip logic locking failure under special working conditions.

[0010] To achieve the above - mentioned purpose, the technical solution adopted by the present invention is as follows: A domino - type multi - stage interlocking power management circuit includes a fuse logic generation circuit, a latch matrix, a subsequent stage module, and a power - sensing front - end, and further includes a multi - stage timing interlocking circuit with a domino effect; wherein, the power - sensing front - end monitors the power state, generates a starting - point control signal through a threshold comparator, the starting - point control signal controls the multi - stage timing interlocking circuit to start sequential timing, and after the timing ends, a fuse logic locking signal is generated to the latch matrix to lock the fuse logic independently of the enable signal and is transmitted to the subsequent stage module; after the fuse logic locking signal is generated, sequential timing generates a turn - off signal to the fuse logic generation circuit, and the turn - off signal is also independent of the enable signal and is used to turn off the fuse logic generation circuit.

[0011] Further, in the present invention, the multi - stage timing interlocking circuit includes a fuse logic timing locking circuit and a turn - off signal timing generation circuit; the fuse logic timing locking circuit is composed of a first timing unit and a first driving unit; the turn - off signal timing generation circuit is composed of a second timing unit and a second driving unit.

[0012] Further, in the present invention, when the first timing unit and the second timing unit are digital circuits, the two timing units are composed of a cascaded shift register and a timing end - point monitoring module; when the power - sensing front - end monitors that the power reaches the threshold level and flips to a high level, the oscillation clock collects the "high - level" information into the cascaded shift register, and pushes the "starting - point signal" to the subsequent stage continuously through the clock. The oscillation clock cooperates with the cascaded length of the cascaded shift register, that is, the timing length. When the "starting - point signal" is pushed to the timing end - point monitoring module, the timing end - point monitoring module outputs a "secondary timing control" signal to the subsequent stage for relay timing, and at the same time generates a timing - off signal to turn off the operation of the cascaded shift register.

[0013] Further, in the present invention, the end-time monitoring module is composed of four NAND gates N1 to N4 and a first RS flip-flop; among them, the start control signal is input from an input terminal of the NAND gate N2, and the output terminal of the NAND gate N2 outputs a signal to an input terminal of the NAND gate N4 and an input terminal of the NAND gate N1. The output terminal of the NAND gate N4 outputs a signal to another input terminal of the NAND gate N2 and the S terminal of the first RS flip-flop. The output terminal of the NAND gate N3 outputs a signal to another input terminal of the NAND gate N1, another input terminal of the NAND gate N4, and the R terminal of the first RS flip-flop. The output terminal of the NAND gate N1 outputs a signal to an input terminal of the NAND gate N3, and an oscillation clock signal is input to another input terminal of the NAND gate N3.

[0014] Further, in the present invention, when the first timing unit is an analog circuit, the first timing unit includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP4 with their gates connected; an NMOS transistor MN2 and a PMOS transistor MP5 with their gates connected to the drain of the PMOS transistor MP1; a resistor R1 connected between the source of the NMOS transistor MN1 and the drain of the PMOS transistor MP5; a PMOS transistor MP2 with its source connected to the source of the PMOS transistor MP4 and its drain connected to the drain of the PMOS transistor MP4 and the source of the PMOS transistor MP5; a PMOS transistor MP3 with its gate connected to the gate of the PMOS transistor MP2 and its source connected to the source of the PMOS transistor MP2; and a capacitor C1 connected between the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN1; among them, the gate and the drain of the PMOS transistor MP2 are interconnected, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP4, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1, the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN2 are both connected to the first driving unit, and the source of the PMOS transistor MP3 is connected to VDD. Further, in the present invention, the first driving unit includes a SMIT1 flip-flop with its input terminal connected to the drain of the PMOS transistor MP3, a PMOS transistor MP6 with its source connected to the source of the PMOS transistor MP3, an NMOS transistor MN3 with its gate connected to the gate of the PMOS transistor MP6 and its source connected to the source of the NMOS transistor MN2 and grounded, and a second RS flip-flop with its R terminal connected to the drain of the NMOS transistor MN3; among them, the drain and the gate of the PMOS transistor MP6 are interconnected, and the output terminal of the SMIT1 flip-flop is connected to the S terminal of the second RS flip-flop.

[0015] Further, in the present invention, when the second timing unit is an analog circuit, the second timing unit includes a PMOS transistor MP7, an NMOS transistor MN4, and a PMOS transistor MP8 with their gates connected; an NMOS transistor MN6 and a PMOS transistor MP11 with their gates connected to the drain of the PMOS transistor MP7; a resistor R2 connected between the source of the NMOS transistor MN4 and the drain of the PMOS transistor MP11; a PMOS transistor MP9 with its source connected to the source of the PMOS transistor MP8 and its drain connected to the drain of the PMOS transistor MP8 and the source of the PMOS transistor MP11; a PMOS transistor MP10 with its gate connected to the gate of the PMOS transistor MP9 and its source connected to the source of the PMOS transistor MP9; and a capacitor C2 connected between the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN4; wherein, the gate and the drain of the PMOS transistor MP9 are interconnected, the source of the PMOS transistor MP7 is connected to the source of the PMOS transistor MP8, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN6, the source of the NMOS transistor MN6 is connected to the source of the NMOS transistor MN4, the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN6 are both connected to the second driving unit, and the source of the PMOS transistor MP10 is connected to VDD.

[0016] Further, in the present invention, the second driving unit is an SMIT2 flip-flop with its input terminal connected to the drain of the PMOS transistor MP10.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention optimizes the ideas in power consumption management and locking timing. It optimizes and manages power consumption in a multi-level interlocking manner, abandons the control function of the enable signal, and performs adaptive sequential control in the dimension of power supply. It is a supplementary power-on timing management method that can adaptively reduce additional power consumption while ensuring logical effective locking, and has positive practical significance and practical value.

[0018] (2) The present invention adopts the domino signal chain control idea, powers off these modules step by step during power-on, saves power while getting rid of the restriction of the enable signal, and ensures strict front and rear timing relationships to avoid incorrect working state introduction caused by timing conflicts. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is the power-on timing diagram of the prior art fuse trimming technology.

[0020] Figure 2 FIG. is the principle block diagram of the prior art fuse trimming technology processing method.

[0021] Figure 3This is the principle block diagram of the domino effect multi - level interlock processing method of the present invention.

[0022] Figure 4 This is the principle block diagram of the multi - level interlock circuit of the present invention.

[0023] Figure 5 This is the schematic diagram of the fuse logic timing lock - in circuit in the present invention.

[0024] Figure 6 This is the schematic diagram of the turn - off signal timing generation circuit in the present invention.

[0025] Figure 7 This is the schematic diagram of the digital - circuit implementation of the timing unit of the present invention.

[0026] Figure 8 This is the schematic diagram of the digital - circuit implementation of the timing end monitoring of the present invention.

[0027] Figure 9 This is the power - on timing diagram of the traditional enable - control fuse logic lock - in.

[0028] Figure 10 This is the power - on timing diagram of the traditional enable - control fuse logic lock - in with turn - off control.

[0029] Figure 11 This is the power - on timing diagram of the power - supply sensing control fuse logic lock - in in the present invention.

[0030] Figure 12 This is the power - on timing diagram of the power - consumption management of the fuse logic lock - in of the present invention. Specific embodiments

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments. The implementation manners of the present invention include but are not limited to the following embodiments.

[0032] Such as Figure 3As shown in the figure, a domino - type multi - stage interlocking power consumption management circuit disclosed by the present invention includes a fuse logic generation circuit, a latch matrix, a subsequent stage module, and a power - aware front - end, and further includes a multi - stage timing interlocking circuit with a domino effect. Among them, the power - aware front - end monitors the power state, generates a starting point control signal through a threshold comparator, and the starting point control signal controls the multi - stage timing interlocking circuit to start the relay timing. When the timing ends, a fuse logic lock signal is generated to the latch matrix, which locks the fuse logic independently of the enable signal and transmits it to the subsequent stage module. After the fuse logic lock signal is generated, the relay timing generates a shutdown signal to the fuse logic generation circuit, and the shutdown signal is also independent of the enable signal and is used to shut down the fuse logic generation circuit. Among them, the fuse logic generation circuit includes a bias circuit and a fuse logic establishment circuit. This not only ensures that the fuse logic is locked to the subsequent circuit but also reduces the power consumption introduced by this part of the circuit in the enabled or disabled state, forming a supplementary chip power - on fuse logic reading method.

[0033] In this embodiment, as Figure 4 shown, the multi - stage timing interlocking circuit includes a fuse logic timing lock circuit and a shutdown signal timing generation circuit, which constitute the core of the timing generation. The fuse logic timing lock circuit is composed of a first timing unit and a first driving unit. The shutdown signal timing generation circuit is composed of a second timing unit and a second driving unit.

[0034] The power - aware front - end monitors the power state, generates a starting point control signal through a threshold comparator, enabling a series of subsequent actions to proceed.

[0035] Cascaded control signal generation: a: The starting point control signal activates the fuse logic timing lock module. After countdown, this module generates two groups of signals. One group is the logic matrix lock signal, which is output to the latch matrix to logically lock the logic signal group generated by the fuse and transmit the locked logic to the subsequent stage module. The other group is the secondary timing control signal, which is used for the subsequent relay timing to ensure strict timing handover.

[0036] b: The secondary timing control signal activates the shutdown signal timing generation module. After countdown, this module generates a bias network shutdown signal, which is used to turn off the bias network in the fuse logic generation circuit to achieve the purpose of reducing power consumption.

[0037] Domino effect timing architecture: Construct a domino - type signal chain: power - aware signal → fuse logic lock enters countdown → countdown ends to generate a logic lock control signal → fuse logic establishment module enters shutdown countdown → generates a shutdown signal to turn off the fuse logic establishment module.

[0038] This idea is not limited to the counting requirements for fuse logic generation and locking, and is also applicable to other power management requirements. For example, after the chip is powered on and starts up, some modules with light decision-making or weak functions need to queue up and import the working state. And after the chip is working, these modules or units do not need to participate in the main signal link. Then, the domino signal chain control idea of this invention can be adopted to power off these modules step by step after power-on, saving power while getting rid of the restriction of the enable signal, and ensuring strict front and back timing relationships to avoid incorrect import of the working state caused by timing conflicts.

[0039] Embodiment 1 The implementation methods of the fuse logic timing locking circuit and the shutdown signal timing generation circuit are generally similar, and the circuit structure is simple and easy to implement. Both are composed of a timing unit and a driving unit. The timing unit is composed of elements such as N and P type transistors, resistors, and capacitors, and the driving unit is composed of elements such as SMIT, RS flip-flops, N and P type transistors.

[0040] In this embodiment, as Figure 5 shown, the first timing unit is an analog circuit, which includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP4 with their gates connected, an NMOS transistor MN2 and a PMOS transistor MP5 with their gates connected to the drain of the PMOS transistor MP1, a resistor R1 connected between the source of the NMOS transistor MN1 and the drain of the PMOS transistor MP5, a PMOS transistor MP2 with its source connected to the source of the PMOS transistor MP4 and its drain connected to the drain of the PMOS transistor MP4 and the source of the PMOS transistor MP5, a PMOS transistor MP3 with its gate connected to the gate of the PMOS transistor MP2 and its source connected to the source of the PMOS transistor MP2, and a capacitor C1 connected between the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN1; wherein, the gate and drain of the PMOS transistor MP2 are interconnected, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP4, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1, the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN2 are both connected to the first driving unit, and the source of the PMOS transistor MP3 is connected to VDD. The first driving unit includes an SMIT1 flip-flop with its input terminal connected to the drain of PMOS transistor MP3, a PMOS transistor MP6 with its source connected to the source of PMOS transistor MP3, an NMOS transistor MN3 with its gate connected to the gate of PMOS transistor MP6, its source connected to the source of NMOS transistor MN2 and grounded, and a second RS flip-flop with its R terminal connected to the drain of NMOS transistor MN3. Among them, the drain and gate of PMOS transistor MP6 are interconnected, and the output terminal of the SMIT1 flip-flop is connected to the S terminal of the second RS flip-flop.

[0041] As Figure 6 shown, the second timing unit is an analog circuit, which includes PMOS transistor MP7, NMOS transistor MN4 and PMOS transistor MP8 with their gates connected, an NMOS transistor MN6 and a PMOS transistor MP11 with their gates connected to the drain of PMOS transistor MP7, a resistor R2 connected between the source of NMOS transistor MN4 and the drain of PMOS transistor MP11, a PMOS transistor MP9 with its source connected to the source of PMOS transistor MP8 and its drain connected to the drain of PMOS transistor MP8 and the source of PMOS transistor MP11, a PMOS transistor MP10 with its gate connected to the gate of PMOS transistor MP9 and its source connected to the source of PMOS transistor MP9, and a capacitor C2 connected between the drain of PMOS transistor MP10 and the source of NMOS transistor MN4. Among them, the gate and drain of PMOS transistor MP9 are interconnected, the source of PMOS transistor MP7 is connected to the source of PMOS transistor MP8, the drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN4, the drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, the source of NMOS transistor MN6 is connected to the source of NMOS transistor MN4, the drain of PMOS transistor MP10 and the source of NMOS transistor MN6 are both connected to the second driving unit, and the source of PMOS transistor MP10 is connected to VDD.

[0042] In this embodiment, the second driving unit is an SMIT2 flip-flop with its input terminal connected to the drain of PMOS transistor MP10.

[0043] For the fuse logic timing locking circuit, at the initial stage when the chip starts to power on, the starting point control signal is at a low level. The starting point control signal passes through the inverter composed of MP1 and MN1, the NET0 node follows the power-on of the power supply, MP5 is in the off state, MP4 pulls up the voltage of the NET1 node to a high level, and the mirror current source composed of MP2 and MP3 does not work. Since the voltage of the NET0 node gradually rises, MN2 is initially turned on, giving the initial state of NET2 as 0, and both the logic matrix locking signal group and the secondary timing control signal are output at a low level.

[0044] When the power sensing front end monitors that the power supply reaches the threshold level and flips to a high level, the NET0 node becomes low level, MP5 is turned on, MP4 is turned off, the voltage of the NET1 node is pulled down through MP5, and the current mirror source composed of MP2 and MP3 starts to work. The current conducted by MP3 charges the capacitor C1, and the voltage of the NET2 node gradually rises. Since the voltage of the NET0 node is pulled down, MN2 is turned off, enabling the voltage of the NET2 node to effectively pass through the SMIT flip-flop. When the voltage rises to the SMIT threshold, both the logic matrix lock signal group and the secondary timing control signal output low-high levels to relay and drive the subsequent circuit to work.

[0045] The idea of the domino signal chain is that once the control signal is triggered, the subsequent stage's linked control timing is started and is irreversible. After the chip is powered on, the gate voltages of MP6 and MN3 float in the intermediate state, forming the TIELOW logic, and MN3 pulls down the NET3 level. At this time, once the SMIT output level becomes high, that is, a logic matrix lock signal is generated, the RS flip-flop will pull up the secondary timing control signal to start the off-signal timer of the subsequent stage. Regardless of whether the SMIT output signal jitters, the secondary timing control is irreversible. Although SMIT has the characteristic of threshold hysteresis, using the RS flip-flop undoubtedly further improves the reliability of the timing. In different engineering environments, the power supply may be unstable during the power-on process. By adopting the domino signal chain control method, the timing conflict problem of logic lock can be avoided.

[0046] By changing the aspect ratio of the width to length of R1 and MP2, the magnitude of the source current of the current mirror can be adjusted. By adjusting the mirror ratio of MP2 and MP3, the charging current ratio of the mirror to the capacitor C1 can be adjusted. By adjusting the size of the capacitor C1, the charging time, that is, the timing time, can be adjusted, and the circuit is simple and flexible to use.

[0047] Compared with the fuse logic timing lock circuit, the input control signal of the off-signal timing generation circuit is the aforementioned secondary timing control signal, and the control principle of the rest of the circuit is basically the same as that of the fuse logic timing lock circuit, so it will not be elaborated. Since there are no more modules participating in the cascade control in the use case of the present invention and there are no more timing requirements for the subsequent stage of the off-signal generation circuit, the RS flip-flop is not used for domino relay cascade in the off-signal timing generation circuit.

[0048] Similarly, the timing time can be adjusted by adjusting the sizes of R2 and C2, as well as the aspect ratio and mirror ratio of MP9 and MP10.

[0049] Embodiment 2 The timing unit of the aforementioned circuit is not limited to being implemented in the form of an analog circuit, and other variant forms of the timing unit can also be used such as Figure 7It is implemented in the following way. A clock is required here, and the circuit that generates the clock can be a ring oscillator, but it is not limited to a specific oscillator.

[0050] When the first timing unit and the second timing unit are digital circuits, the two timing units are composed of a cascaded shift register and a timing end monitoring module.

[0051] For the sake of easy description, taking the timing unit of the fuse logic timing locking circuit as an example, when the power supply sensing front end detects that the power supply reaches the threshold level and flips to a high level, the oscillating clock collects the "high level" information into the cascaded shift register, and pushes the "starting point signal" to the subsequent stage continuously through the clock. The cooperation between the oscillating clock and the cascaded length of the register is the timing length. When the "starting point signal" is pushed to the timing end monitoring module, the timing end monitoring module outputs a "secondary timing control" signal to the subsequent stage for relay timing, and at the same time generates a timing shutdown signal to turn off the operation of the cascaded shift register.

[0052] In order to prevent misflipping during the transmission process caused by internal noise of the chip and improve the reliability of timing, the timing end monitoring module is designed using the blocking and holding technology, which is simple in structure and easy to implement. The timing end monitoring module is composed of four NAND gates N1 to N4 and a first RS flip-flop; among them, the starting point control signal is input from one input terminal of the NAND gate N2, and the output signal of the NAND gate N2 is output to one input terminal of the NAND gate N4 and the NAND gate N1. The output signal of the NAND gate N4 is output to the other input terminal of the NAND gate N2 and the S terminal of the first RS flip-flop. The output signal of the NAND gate N3 is output to the other input terminal of the NAND gate N1, the other input terminal of the NAND gate N4, and the R terminal of the first RS flip-flop. The output signal of the NAND gate N1 is output to one input terminal of the NAND gate N3, and the oscillating clock signal is input to the other input terminal of the NAND gate N3.

[0053] For the sake of easy description, taking the timing unit of the fuse logic timing locking circuit as an example. When the starting point control signal is generated and pushed to the timing end monitoring circuit by the clock. When the oscillating clock is low, the outputs of N3 and N4 are locked by the low level of the clock. Although the state of the starting point signal can affect the output terminals of N1 and N2, it cannot act on N3 and N4, and the state of the RS flip-flop remains unchanged.

[0054] Before the rising edge of the oscillating clock arrives, the start signal is high. Due to the low-level locking of N3 and N4 clocks, the outputs of N3 and N4 are 1, the output of N1 is 1, and the output of N2 is 0. At this time, the output states of N1 and N2 cannot be transmitted to the RS flip-flop through N3 and N4, and the flip-flop maintains its original state. When the rising edge of the oscillating clock arrives, the states of N1 and N2 are reflected on the RS flip-flop. The output of N2 is low, which acts on N4, keeping the output of N4 unchanged. The output of N3 turns low, making the trigger output become 1. Therefore, as long as the high level of the start signal has been pushed to the timing end monitoring circuit before the rising edge of the clock arrives, regardless of the state of the RS flip-flop, after the rising edge of the oscillating clock arrives, the output state of the flip-flop will become 1. At this time, the secondary timing control signal is generated to ensure the smooth progress of the subsequent cascaded timing.

[0055] At the same time, the output of N3 is low, acting on the input terminals of N4 and N1, locking N4 and N1. That is, during the period when the clock is high, regardless of how the serial data changes, the output state of the flip-flop remains 1 and is irreversible, thus ensuring the reliability of the timing end monitoring.

[0056] The above process is applicable to the monitoring scenario where the start signal is high. For the application scenario where the start signal is low, the signal of the timing end monitoring circuit can be reversed, which is also within the scope of the present invention's concept.

[0057] Next, discuss the situation where the start signal has not been established. If the start control signal is low before the rising edge of the clock arrives, due to the low-level locking of N3 and N4 clocks, the outputs of N3 and N4 are 1, the output of N1 is 0, and the output of N2 is 1. Then, at this time, the start control signal cannot be loaded onto N1 and N2 through N3 and N4. When the rising edge of the clock arrives, the output of N1 being 0 causes N3 to continue to be locked. The output of N2 being 1 causes N4 to open, and the output of N4 becomes low, making the output of the RS flip-flop 0. Therefore, as long as the input of the start control signal is low before the rising edge of the serial clock arrives, regardless of the state of the flip-flop, after the rising edge of the serial clock arrives, the output state of the flip-flop will become low.

[0058] At the same time, the output of N4 is low, locking N2. Then, during the period when the clock is high, regardless of how the start control signal changes, the output state of the flip-flop remains low. The aforementioned timing end monitoring module and the cascaded shift register circuit can both adopt Figure 8 the structure. For the case where the noise environment inside the chip is good, according to the design requirements, common edge flip-flops can also be used.

[0059] The working process of the circuit is analyzed with a practical example. The present invention is applicable to the power consumption management of power-on timing control, and the power-on timing of a chip using fuse trimming technology is discussed. The use case simulation uses two fuse channels and is simulated under TSMC 180nm CMOS process.

[0060] Figure 9 , Figure 10 , Figure 11 , Figure 12 A chip power-on situation using fuse trimming technology is simulated. Figure 9 This is the chip power-on simulation with EN turned on for logic locking. "Power" is the chip power supply, "Enable" is the chip enable signal, which turns on the working state of the chip, and "Lock Signal" is the fuse logic lock signal, which is used to lock the logic generated by the fuse module. "Locked logic" means the fuse logic locked by the lock signal and transmitted to the subsequent circuit. "Power supply current" only means the power supply current of the fuse logic generation circuit during simulation, which includes the bias circuit current when the fuse logic is established. The simulation shows that when EN is turned on for logic locking, the "power supply current" is 179uA after power-on. After enabling, the fuse logic is locked and transmitted to the subsequent circuit. The "power supply current" does not change and remains at 179uA.

[0061] In the figure Figure 10 is Figure 9 The shutdown signal is introduced based on the fuse logic. The "shutdown signal" in the figure means that after the fuse logic is locked, a shutdown signal is generated to turn off the module established by the fuse logic. The rest of the signals are the same as Figure 9 As shown in the simulation, after the enable signal, the "power supply current" is reduced to 195nA as the shutdown signal is generated. However, after the chip is powered on, before the enable signal arrives, the "power supply current" remains at 179uA, which adds additional power consumption and is not friendly in the non-enabled state.

[0062] In the figure Figure 11 is Figure 9 On the basis, change "Enable" to "Normal Low", the power sensing front end generates the starting control signal, and the other signals are the same Figure 9 As shown in the simulation, it can be seen that after the "starting signal" is generated, the fuse logic enters the locking process. Although it is freed from the constraints of the enable signal, the "power supply current" remains at 179uA, which increases the additional static power consumption.

[0063] Figure 12This is the simulation of the multi-level interlock power management circuit and method using the power-on timing control of the present invention. The "lock signal" is the fuse logic timing lock circuit and also the secondary timing control logic. For the convenience of understanding, the secondary timing control signal and the lock signal are combined and shown in the figure. After the power supply sensing front end generates the "start signal", through timing, the "lock signal" is generated to lock the fuse logic and transmit it to the subsequent circuit. At the same time, the secondary timing control signal starts the turn-off timing. After the timing ends, the turn-off signal is generated, effectively reducing the "supply current". It can be seen from the simulation that the fuse locking process does not require the participation of the enable signal. From the outside of the chip, after a short delay when the chip is powered on, the extra power consumption can be turned off, and the "supply current" is reduced to 195 nA. Compared with the structure without using the turn-off signal, the power consumption is only about 0.1% of 179 μA.

[0064] The above embodiments are only one of the preferred embodiments of the present invention and should not be used to limit the protection scope of the present invention. Any meaningless changes or touch-ups made on the main design concept and spirit of the present invention, as long as the technical problems solved are still the same as those of the present invention, should be included in the protection scope of the present invention.

Claims

1. A domino - type multi - stage interlocked power consumption management circuit, comprising a fuse logic generation circuit, a latch matrix, a subsequent stage module, and a power supply sensing front - end, characterized in that, It further includes a multi-stage timing interlock circuit with a domino effect; wherein, the power supply sensing front end monitors the power supply state, generates a starting point control signal through a threshold comparator, the starting point control signal controls the multi-stage timing interlock circuit to start the relay timing, and generates a fuse logic locking signal to the latch matrix at the end of the timing, locks the fuse logic independently of the enable signal, and transmits it to the subsequent module; after the fuse logic locking signal is generated, the relay timing generates a shutdown signal to the fuse logic generation circuit, and the shutdown signal is also independent of the enable signal and is used to shut down the fuse logic generation circuit.

2. The domino - type multi - stage interlocked power consumption management circuit according to claim 1, characterized in that, The multi-stage timing interlock circuit includes a fuse logic timing lock circuit and a shutdown signal timing generation circuit; the fuse logic timing lock circuit is composed of a first timing unit and a first driving unit; the shutdown signal timing generation circuit is composed of a second timing unit and a second driving unit.

3. The domino - type multi - stage interlocked power consumption management circuit according to claim 2, characterized in that, When the first timing unit and the second timing unit are digital circuits, the two timing units are composed of a cascaded shift register and a timing end monitoring module; when the power supply sensing front end monitors that the power supply reaches the threshold level and flips to a high level, the oscillation clock collects the "high level" information into the cascaded shift register, and pushes the "starting point signal" to the subsequent stage continuously through the clock. The oscillation clock cooperates with the cascaded length of the cascaded shift register, that is, the timing length. When the "starting point signal" is pushed to the timing end monitoring module, the timing end monitoring module outputs a "secondary timing control" signal to the subsequent stage for relay timing, and at the same time generates a timing shutdown signal to turn off the operation of the cascaded shift register.

4. A domino - type multi - stage interlocked power consumption management circuit according to claim 3, wherein, The timing end monitoring module is composed of four NAND gates N1 to N4 and a first RS flip-flop; wherein, the starting point control signal is input from one input terminal of NAND gate N2, the output terminal of NAND gate N2 outputs a signal to one input terminal of NAND gate N4 and NAND gate N1, the output terminal of NAND gate N4 outputs a signal to the other input terminal of NAND gate N2 and the S terminal of the first RS flip-flop, the output terminal of NAND gate N3 outputs a signal to the other input terminal of NAND gate N1, the other input terminal of NAND gate N4 and the R terminal of the first RS flip-flop, the output terminal of NAND gate N1 outputs a signal to one input terminal of NAND gate N3, and the other input terminal of NAND gate N3 inputs the oscillation clock signal.

5. The domino - type multi - stage interlocking power consumption management circuit according to claim 2, wherein, When the first timing unit is an analog circuit, the first timing unit includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP4 with their gates connected; an NMOS transistor MN2 and a PMOS transistor MP5 with their gates connected to the drain of the PMOS transistor MP1; a resistor R1 connected between the source of the NMOS transistor MN1 and the drain of the PMOS transistor MP5; a PMOS transistor MP2 with its source connected to the source of the PMOS transistor MP4 and its drain connected to the drain of the PMOS transistor MP4 and the source of the PMOS transistor MP5; a PMOS transistor MP3 with its gate connected to the gate of the PMOS transistor MP2 and its source connected to the source of the PMOS transistor MP2; and a capacitor C1 connected between the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN1. Among them, the gate and the drain of the PMOS transistor MP2 are interconnected; the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP4; the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1; the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2; the source of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1; the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN2 are both connected to the first driving unit; and the source of the PMOS transistor MP3 is connected to VDD.

6. The domino - type multi - stage interlocked power consumption management circuit according to claim 5, characterized in that, The first driving unit includes a SMIT1 flip-flop with its input terminal connected to the drain of the PMOS transistor MP3, a PMOS transistor MP6 with its source connected to the source of the PMOS transistor MP3, an NMOS transistor MN3 with its gate connected to the gate of the PMOS transistor MP6 and its source connected to the source of the NMOS transistor MN2 and grounded, and a second RS flip-flop with its R terminal connected to the drain of the NMOS transistor MN3. Among them, the drain and the gate of the PMOS transistor MP6 are interconnected; the output terminal of the SMIT1 flip-flop is connected to the S terminal of the second RS flip-flop.

7. A domino - type multi - stage interlocked power consumption management circuit according to claim 6, characterized in that, When the second timing unit is an analog circuit, the second timing unit includes a PMOS transistor MP7, an NMOS transistor MN4, and a PMOS transistor MP8 with their gates connected; an NMOS transistor MN6 and a PMOS transistor MP11 with their gates connected to the drain of the PMOS transistor MP7; a resistor R2 connected between the source of the NMOS transistor MN4 and the drain of the PMOS transistor MP11; a PMOS transistor MP9 with its source connected to the source of the PMOS transistor MP8 and its drain connected to the drain of the PMOS transistor MP8 and the source of the PMOS transistor MP11; a PMOS transistor MP10 with its gate connected to the gate of the PMOS transistor MP9 and its source connected to the source of the PMOS transistor MP9; and a capacitor C2 connected between the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN4. Among them, the gate and the drain of the PMOS transistor MP9 are interconnected; the source of the PMOS transistor MP7 is connected to the source of the PMOS transistor MP8; the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4; the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN6; the source of the NMOS transistor MN6 is connected to the source of the NMOS transistor MN4; the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN6 are both connected to the second driving unit; and the source of the PMOS transistor MP10 is connected to VDD.

8. A domino - type multi - stage interlocked power consumption management circuit according to claim 7, characterized in that, The second driving unit is an SMIT2 flip-flop with its input terminal connected to the drain of the PMOS transistor MP10.

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