Received signal strength indicator circuit integrated on optical receiving chip

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a received signal strength indicator circuit integrated on an optical receiving chip. Comprising an NMOS tube M1 used for absorbing light current generated by a photodiode D1, a drain electrode of the NMOS tube M1 is connected with a cathode of the photodiode D1 outside a chip and an in-phase input port of an amplifier A1 through chip pins PAD1 and ESD1, and a source electrode of the NMOS tube M1 is grounded gnd; the grid electrode of the NMOS tube M2 is connected with the grid electrode of the NMOS tube M1 and the output end of the amplifier A1, the drain electrode of the NMOS tube M2 is connected with the inverted input port of the amplifier A1 and the source electrode of the NMOS tube M3, and the source electrode of the NMOS tube M2 is grounded gnd; a grid electrode and a drain electrode of the NMOS tube M3 are connected, the NMOS tube M3 is connected with a second port of the off-chip high-precision resistor R1 through chip pins PAD2 and ESD2, and a first port of the resistor R1 is connected with an off-chip power supply vcc. The circuit structure of the invention has a wide measurement range, and can accurately measure light current from microampere magnitude to milliampere magnitude.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a received signal strength indicator circuit integrated in an optical receiving chip. Background Art

[0002] An optical module is one of the core components of an optical fiber communication system and is a basic unit for data center interconnection, 5G bearer networks, and all-optical access networks. Optical modules are divided into optical transmission modules and optical receiving modules. The optical receiving module is responsible for receiving optical signals and converting them into electrical signals. In an optical receiving module, it usually includes a photodiode, an optical receiving chip, and various passive devices. Among them, the photodiode is a device for realizing optical-to-electrical conversion and can convert an optical signal into a current signal. The photodiode is generally connected to the input end of the optical receiving chip by a reverse biasing method. In a lightless environment, the photodiode only generates a dark current in the pA range flowing into the receiver chip. When the photodiode is irradiated with light, the photodiode generates a photocurrent flowing into the optical receiving chip, and as the light intensity increases, the photocurrent gradually increases. In order to measure the intensity of the optical signal received by the optical receiving module, a received signal strength indicator circuit (RSSI) is usually integrated in the optical receiving chip to measure the current value of the photocurrent of the photodiode, thereby indirectly measuring the light intensity.

[0003] When measuring the photocurrent of the photodiode, the photodiode can be regarded as a current source. By connecting a resistor with a known resistance value in series at the output end of the current source, measuring the voltage drop across the resistor and using Ohm's law, the current value can be calculated. However, it is difficult to fabricate a precise resistor inside the chip. Therefore, a typical in-chip RSSI circuit structure is as Figure 1 shown. The photodiode is regarded as an off-chip DC current source. Inside the chip, a one-to-one NMOS type current mirror NMA and NMB are used to mirror the current ipd of the photodiode from the NMA transistor to the NMB transistor. The drain of the NMB transistor is connected to an off-chip resistor R with a precise resistance value. By measuring the voltage drop across the resistor R, the photocurrent value of the photodiode can be measured. This circuit structure uses a mirror circuit to convert the in-chip resistor into an off-chip resistor, avoiding the problem of difficult fabrication of precise resistors inside the chip. However, for the two nodes va and vb in the mirror circuit, as the photocurrent gradually increases, the voltage of node va will gradually increase, and the voltage of node vb will gradually decrease. Therefore, only within a very small range of current changes during the gradual increase of the photocurrent, the voltage values of the two nodes va and vb are close to equal. Due to the channel length modulation effect of MOS transistors, the NMB transistor can mirror the current very precisely only when the voltage values of the two nodes va and vb are close to equal.

[0004] Therefore, this circuit structure is applicable to the situation where the variation range of the photocurrent generated by the photodiode is relatively narrow or the requirement for measurement accuracy is not high. If the variation range of the photocurrent generated by the photodiode is relatively wide, it is difficult to accurately measure the photocurrent. Summary of the Invention

[0005] The object of the present invention is to provide a received signal strength indicator circuit integrated in an optical receiving chip. This circuit structure of the present invention is integrated in the optical receiving chip to help the optical receiving chip measure the photocurrent generated by the photodiode due to light illumination. This circuit structure of the invention has a relatively wide measurement range and can accurately measure the photocurrent from the microampere level to the milliampere level.

[0006] To solve the above technical problems, the present invention provides a received signal strength indicator circuit integrated in an optical receiving chip, including:

[0007] NMOS transistor M1, which is used to absorb the photocurrent generated by photodiode D1. The drain of NMOS transistor M1 is connected to the cathode of the off-chip photodiode D1 and the non-inverting input port of amplifier A1 through chip pin PAD1 and ESD1, and the source of NMOS transistor M1 is grounded to gnd;

[0008] NMOS transistor M2, the gate of NMOS transistor M2 is connected to the gate of NMOS transistor M1 and the output terminal of amplifier A1, and the gate voltages of M1 and M2 are controlled by the output terminal of amplifier A1; the drain of NMOS transistor M2 is connected to the inverting input port of amplifier A1 and the source of NMOS transistor M3, and the source of NMOS transistor M2 is grounded to gnd;

[0009] NMOS transistor M3, the gate and drain of NMOS transistor M3 are connected, and are connected to the second port of the off-chip high-precision resistor R1 through chip pin PAD2 and ESD2. The first port of resistor R1 is connected to the off-chip power supply vcc.

[0010] Preferably, the NMOS transistor M1, NMOS transistor M2, and NMOS transistor M3 are integrated inside the chip.

[0011] Preferably, the drain of NMOS transistor M1 is connected to the non-inverting input port of amplifier A1 to form node vp.

[0012] Preferably, the gate of NMOS transistor M1 is connected to the gate of NMOS transistor M2 and the output terminal of amplifier A1 to form node vout.

[0013] Preferably, the drain of NMOS transistor M2 is connected to the inverting input port of amplifier A1 and the source of NMOS transistor M3 to form node vn.

[0014] Preferably, the NMOS transistor M1, the NMOS transistor M2, and the amplifier A1 form a feedback structure.

[0015] Preferably, the amplifier A1 is a single-stage amplifier structure.

[0016] Preferably, the circuit of the amplifier A1 includes: a non-inverting input terminal INP, an inverting input terminal INN, an output terminal OUT, NMOS transistors MN1 to MN4, PMOS transistors MP1 to MP4, and a tail current source I1; the inverting input terminal INN is connected to the gate of the NMOS transistor MN1, the drain of the NMOS transistor MN1 is connected to the gates and drains of the PMOS transistor MP1 and is also connected to the gate of the PMOS transistor MP3; the source of the NMOS transistor MN1 is connected to the input terminal of the current source I1 and is also connected to the source of the NMOS transistor MN2; the output terminal of the current source I1 is grounded to gnd; the non-inverting input terminal INP is connected to the gate of the NMOS transistor MN2, the drain of the NMOS transistor MN2 is connected to the gates and drains of the PMOS transistor MP2 and is also connected to the gate of the PMOS transistor MP4; the sources of the PMOS transistors MP1 to MP4 are connected to the power supply vcc; the drain of the PMOS transistor MP3 is connected to the gates and drains of the NMOS transistor MN3 and is also connected to the gate of the NMOS transistor MN4; the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor MN4 and serves as the output terminal OUT; the sources of the NMOS transistors MN3 to MN5 are grounded to gnd.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention discloses a structure of a received signal strength indication circuit (RSSI) integrated in an optical receiving chip, belonging to the field of integrated circuit optical chips. This circuit structure is easy to integrate in an optical receiving chip and is used to help the optical receiving chip measure the photocurrent generated by a photodiode due to light illumination. The circuit structure of the present invention has a wide measurement range and can accurately measure photocurrents from the microampere level to the milliampere level. Description of the Drawings

[0019] Figure 1 is a schematic diagram of a typical on-chip RSSI circuit structure.

[0020] Figure 2 is a schematic diagram of the RSSI circuit structure of the present invention integrated in an optical receiving chip.

[0021] Figure 3 is a schematic diagram of the amplifier A1 in the RSSI of the present invention. Detailed Embodiments

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0023] As Figure 2 shown, the present invention provides a circuit structure of a received signal strength indicator (RSSI), including NMOS transistors M1, M2, and M3, and a single-stage amplifier A1. When using this RSSI circuit, the drain of the NMOS transistor M1 of the circuit needs to be connected to the cathode of the off-chip photodiode D1 through the chip pin PAD1 and ESD1. The gate and drain of the NMOS transistor M3 of the circuit need to be connected to the second port of the off-chip resistor R1 through the chip pin PAD2 and ESD2.

[0024] In an embodiment of the present invention, the NMOS transistor M1 is used to absorb the photocurrent generated by the photodiode. Its drain is connected to the cathode of the off-chip photodiode through the chip pin PAD1 and ESD1. The drain of the NMOS transistor M1 is simultaneously connected to the non-inverting input port of the amplifier A1, and the node is vp. The source of the NMOS transistor M1 is grounded to gnd. The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 and is simultaneously connected to the output terminal of the amplifier A1, and the node is vout. The gate voltages of M1 and M2 are controlled by the output terminal of the amplifier A1. The drain of the NMOS transistor M2 is connected to the inverting input port of the amplifier A1, and the node is vn, and is simultaneously connected to the source terminal of the NMOS transistor M3. The source of the NMOS transistor M2 is grounded to gnd. The gate and drain of the NMOS transistor M3 are connected, and are simultaneously connected to the second port of the off-chip high-precision pull-up resistor R1 through the chip pin PAD2 and ESD2. The first port of the off-chip high-precision pull-up resistor R1 is connected to the off-chip power supply vcc.

[0025] In an embodiment of the present invention, the amplifier A1 includes a non-inverting input terminal INP, an inverting input terminal INN, an output terminal OUT, NMOS transistors MN1 to MN4, PMOS transistors MP1 to MP4, and a tail current source I1; the inverting input terminal INN is connected to the gate of the NMOS transistor MN1, and the drain of the NMOS transistor MN1 is connected to the gate and drain of the PMOS transistor MP1, and is also connected to the gate of the PMOS transistor MP3; the source of the NMOS transistor MN1 is connected to the input terminal of the current source I1 and is also connected to the source of the NMOS transistor MN2; the output terminal of the current source I1 is grounded to gnd; the non-inverting input terminal INP is connected to the gate of the NMOS transistor MN2, and the drain of the NMOS transistor MN2 is connected to the gate and drain of the PMOS transistor MP2, and is also connected to the gate of the PMOS transistor MP4; the sources of the PMOS transistors MP1 to MP4 are all connected to the power supply vcc; the drain of the PMOS transistor MP3 is connected to the gate and drain of the NMOS transistor MN3, and is also connected to the gate of the NMOS transistor MN4; the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor MN4 as the output terminal OUT; the sources of the NMOS transistors MN3 to MN5 are grounded to gnd;

[0026] The working principle of the present invention is as follows:

[0027] As Figure 2 shown, in the present invention, the photodiode D1 and the precision resistor R1 are external devices of the chip, and are respectively connected to the internal circuit of the chip through the chip pins PAD1, PAD2 and ESD1, ESD2. The sizes of the on-chip NMOS transistors M1 and M2 are the same, that is, the width-to-length ratios are exactly the same. Among them, the M1 transistor is used to absorb the photocurrent generated by the off-chip photodiode. In order to obtain a wider measurement range, depending on the width-to-length ratios of the M1 and M2 transistors, their width-to-length ratios are set larger to ensure that a larger photocurrent can be absorbed. The drains of the M1 and M2 transistors are respectively connected to the non-inverting input terminal and the inverting input terminal of the amplifier A1, and the nodes are set as vp and vn. The gates of the two NMOS transistors are both connected to the output terminal of the amplifier A1, and the node is set as vout. Therefore, M1, M2 and the amplifier A1 form a feedback structure.

[0028] When the gain of the amplifier A1 is large enough, according to the "virtual short circuit" principle of the amplifier, the voltage values of the non-inverting input terminal and the inverting input terminal are equal, that is, vn = vp. And the gate voltages of M1 and M2 are both vout, and the source voltages are both grounded to gnd. At this time, the voltages of each pole of M1 and the voltages of each pole of M2 are exactly the same. Therefore, no matter what working state the M1 and M2 transistors are in, the currents flowing through M1 and M2 should be exactly the same, and are both equal to the photocurrent i1 generated by the off-chip photodiode. Also, since M2, M3 and the off-chip precision circuit are in series, the current flowing through the M2 transistor is the current i2 flowing through the off-chip precision resistor. Therefore, it can be obtained that the current i1 = i2 = (vcc - v2) / R.

[0029] The current values i1 and i2, i.e., the photocurrent, can be calculated by measuring the voltage value v2 at the second port of the resistor R1. Since the cathode voltage v1 of the photodiode D1 changes with the change of the photocurrent, and v1 and vp are strongly correlated through PAD1 and ESD1, and vp = vn, thus vn is also strongly correlated with v1, and vn changes with the change of the photocurrent.

[0030] To reduce the correlation between the two nodes vn and v2, an NMOS transistor M3 is introduced to isolate the two nodes vn and v2. The NMOS transistor M3 is connected with its gate and drain, which does not require an additional gate biasing circuit, reducing the design cost. The NMOS transistor M3 will always be in the saturation state, will not block this branch, and can effectively reduce the correlation between the two nodes vn and v2. When the variation range of the photocurrent i1 is relatively wide, such as when the current changes from the microampere level to the milliampere level, it may cause the operating states of M1 and M2 to change from the subthreshold region to the saturation region and then to the linear region. However, the currents i1 and i2 flowing through the transistors M1 and M2 can be exactly the same. Therefore, the circuit structure of this invention has a relatively wide measurement range and can accurately measure the photocurrent from the microampere level to the milliampere level.

[0031] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A received signal strength indicator circuit integrated in an optical receiving chip, characterized in that: include: NMOS tube M1, used for absorbing the photocurrent generated by the photodiode D1, the drain of the NMOS tube M1 is connected to the cathode of the off-chip photodiode D1 and the in-phase input port of the amplifier A1 through the chip pins PAD1 and ESD1, and the source of the NMOS tube M1 is grounded gnd; NMOS tube M2, the gate of the NMOS tube M2 is connected to the gate of the NMOS tube M1 and the output end of the amplifier A1, the drain of the NMOS tube M2 is connected to the inverting input port of the amplifier A1 and the source of the NMOS tube M3, and the source of the NMOS tube M2 is grounded gnd; The gate and drain of the NMOS tube M3 are connected and connected to the second port of the high-precision resistor R1 outside the chip through the chip pins PAD2 and ESD2. The first port of the resistor R1 is connected to the power supply vcc outside the chip.

2. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 1, characterized in that: The NMOS transistor M1 , the NMOS transistor M2 and the NMOS transistor M3 are integrated inside the chip.

3. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 1, characterized in that: The drain of the NMOS tube M1 is connected to the in-phase input port of the amplifier A1 to form a node vp.

4. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 1, characterized in that: The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 and the output end of the amplifier A1 to form a node vout.

5. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 1, characterized in that: The drain of the NMOS tube M2 is connected to the inverting input port of the amplifier A1 and the source of the NMOS tube M3 to form a node vn.

6. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 1, characterized in that: The NMOS transistor M1, the NMOS transistor M2 and the amplifier A1 form a feedback structure.

7. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 1, characterized in that: The amplifier A1 is a single-stage amplifier structure.

8. A received signal strength indicator circuit integrated in an optical receiving chip as claimed in claim 7, characterized in that: The circuit of the amplifier A1 includes: a non-inverting input terminal INP, an inverting input terminal INN, an output terminal OUT, NMOS tubes MN1-MN4, PMOS tubes MP1-MP4 and a tail current source I1; the inverting input terminal INN is connected to the gate of the NMOS tube MN1, the drain of the NMOS tube MN1 is connected to the gate and drain of the PMOS tube MP1, and is also connected to the gate of the PMOS tube MP3; the source of the NMOS tube MN1 is connected to the input terminal of the current source I1, and is also connected to the source of the NMOS tube MN2; the output terminal of the current source I1 is connected to the ground gnd The in-phase input terminal INP is connected to the gate of the NMOS tube MN2, the drain of the NMOS tube MN2 is connected to the gate and drain of the PMOS tube MP2, and is also connected to the gate of the PMOS tube MP4; the source of the PMOS tubes MP1 to MP4 is connected to the power supply vcc; the drain of the PMOS tube MP3 is connected to the gate and drain of the NMOS tube MN3, and is also connected to the gate of the NMOS tube MN4; the drain of the PMOS tube MP4 is connected to the drain of the NMOS tube MN4 and serves as the output terminal OUT; the source of the NMOS tubes MN3 to MN5 is connected to the ground gnd.

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