Method and device for configuring boundary router in 2.5 D integrated circuit

Abstract

The invention provides a boundary router configuration method and device in a 2.5 D integrated circuit, and relates to the technical field of semiconductors. When the method is executed, the total flow, namely the first flow, generated by connection of a router and a wafer substrate during operation of a target chip is determined firstly; and then, determining a first parameter corresponding to the layout boundary router in the target chip according to the first flow, thereby setting the number and the position of the boundary router in the target chip. The larger the first flow is, the larger the number of the configured routers is, so that the number of the boundary routers for opening the downlink ports in the target chip is adaptively adjusted according to the interactive flow between the chip and the wafer substrate. According to the technical scheme, all routers on the chip are communicated with the wafer substrate instead of all the routers on the chip, so that the waste of resources is reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a method and device for configuring a boundary router in a 2.5D integrated circuit. Background Art

[0002] 2.5D integrated circuits are gradually moving from the laboratory stage to commercial applications, showing strong growth momentum in the fields of high-performance computing, network communication, and consumer electronics. 2.5D integrated circuits adopt advanced integrated circuit packaging technology. Multiple bare chips are integrated side by side on a wafer substrate in a plane, and at the same time, electrical connections are allowed between the chips and the wafer substrate through vertical interconnections. The wafer substrate is provided with a large number of vias and micro traces for realizing high-speed signal transmission and power distribution.

[0003] Custom chips can be integrated on 2.5D integrated circuits, which involves unit interconnection inside the chips and interconnection between the chips and the wafer substrate, and thus involves the setting of boundary routers. If all routers on the chips communicate with the wafer substrate, it will undoubtedly cause waste of resources and unnecessary power consumption. Summary of the Invention

[0004] In view of this, the present application provides a method and device for configuring a boundary router in a 2.5D integrated circuit, aiming to reasonably configure the boundary router and reduce resource waste and power consumption.

[0005] In a first aspect, the present application provides a method for configuring a boundary router in a 2.5D integrated circuit, including:

[0006] Determining the sum of the traffic transmitted on the links connecting the routers included in the target chip to the wafer substrate to obtain a first traffic, where the target chip is one of the chips connected to the wafer substrate;

[0007] According to the first traffic, determining a first parameter for configuring a boundary router in the target chip, where the boundary router is a router with the downlink port permission open in the target chip;

[0008] Based on the first parameter, determining the layout structure of the boundary router in the corresponding target chip, and setting the boundary router in the target chip; the layout quantity of the boundary router in the target chip is proportional to the first traffic.

[0009] Optionally, the determining, according to the first traffic, a first parameter for setting a boundary router in the target chip includes:

[0010] Determining a second parameter according to the first traffic and a preset traffic threshold;

[0011] Querying the parameter interval to which the second parameter belongs as the first parameter.

[0012] Optionally, determining a second parameter according to the first flow rate and a preset flow rate threshold includes:

[0013] Determining the second parameter according to a ratio of the first flow rate to the flow rate threshold;

[0014] Or, rounding up the value obtained by multiplying the total number of routers in the target chip by a first ratio, to obtain a first number of border routers set in the target chip, and using the first number as the second parameter; the first ratio is the ratio of the first flow rate to the flow rate threshold.

[0015] Optionally, determining a layout structure of border routers in a corresponding target chip based on the first parameter includes:

[0016] Querying a parameter interval to which the second parameter belongs, and determining a layout structure of border routers in the target chip corresponding to the parameter interval; there are multiple parameter intervals, and each parameter interval is correspondingly configured with a layout structure of border routers in a target chip.

[0017] Optionally, when the border routers in the target chip are distributed in a matrix, the step of correspondingly configuring a layout structure of border routers in a target chip for each parameter interval includes:

[0018] Determining a target number of border routers set in the target chip corresponding to each parameter interval, where the target number is greater than or equal to the minimum number of border routers required for the normal operation of the target chip within the range of the parameter interval;

[0019] Determining a first number of rows and a first number of columns of border routers in the target chip according to the target number, the total number of rows and the total number of columns of routers in the target chip;

[0020] Determining a row interval number and a column interval number of border routers in the target chip according to the total number of rows, the total number of columns, the first number of rows, and the first number of columns;

[0021] Determining a layout structure of border routers centrally set in the target chip corresponding to the parameter interval according to the first number of rows, the first number of columns, the row interval number, and the column interval number.

[0022] Optionally, determining a first parameter for configuring border routers in the target chip according to the first flow rate includes: rounding up the value obtained by multiplying the total number of routers in the target chip by a first ratio, to obtain a target number of border routers set in the target chip, and using the target number as the first parameter.

[0023] Optionally, the border routers in the target chip are distributed in a matrix, and determining the layout structure of the border routers in the corresponding target chip based on the first parameter includes:

[0024] Determine the first number of rows and the first number of columns of the border routers in the target chip according to the target quantity, the total number of rows and the total number of columns of the routers in the target chip;

[0025] Determine the row interval number and the column interval number of the border routers in the target chip according to the total number of rows, the total number of columns, the first number of rows and the first number of columns;

[0026] Determine the layout structure of the border routers centrally arranged in the target chip according to the first number of rows, the first number of columns, the row interval number and the column interval number.

[0027] Optionally, the determining the first number of rows and the first number of columns of the border routers in the target chip according to the target quantity, the total number of rows and the total number of columns of the routers in the target chip includes:

[0028] Calculate the square root of the product of the target quantity and the second ratio to obtain a first value; round the first value to obtain the number of rows to be adjusted; the second ratio is the ratio of the total number of rows to the total number of columns;

[0029] Calculate the square root of the product of the target quantity and the third ratio to obtain a second value, round the second value to obtain the number of columns to be adjusted; the third ratio is the ratio of the total number of columns to the total number of rows;

[0030] If the product of the number of rows to be adjusted and the number of columns to be adjusted is less than the target quantity, then increase the number of rows to be adjusted by one or increase the number of columns to be adjusted by one; if the product of the number of rows to be adjusted and the number of columns to be adjusted is greater than the target quantity, then decrease the number of rows to be adjusted by one or decrease the number of columns to be adjusted by one, until the product of the adjusted number of rows to be adjusted and the adjusted number of columns to be adjusted is the target quantity, and use the adjusted number of rows to be adjusted as the first number of rows and the adjusted number of columns to be adjusted as the first number of columns.

[0031] Optionally, the determining the row interval number and the column interval number of the border routers in the target chip according to the total number of rows, the total number of columns, the first number of rows and the first number of columns includes:

[0032] Divide the difference obtained by subtracting one from the total number of rows by the first number of rows to obtain a third value; round the third value to the nearest integer to obtain the row interval number of the border routers in each row of the target chip;

[0033] Subtract 1 from the total number of columns, and then divide the difference by the number of the first column to obtain a fourth value; round the fourth value to an integer to obtain the column interval number of the boundary router in each column of the target chip.

[0034] In a second aspect, the present application further provides a boundary router configuration device in a 2.5D integrated circuit, including:

[0035] An acquisition unit, which includes determining the sum of the traffic transmitted on the vertical link connecting the routers included in the target chip to the wafer substrate to obtain a first traffic, where the target chip is one of the chips connected to the wafer substrate;

[0036] A processing unit, configured to determine a first parameter for configuring a boundary router in the target chip according to the first traffic, where the boundary router is a router with a downward port permission open in the target chip;

[0037] A determination unit, configured to determine the layout structure of the boundary router in the corresponding target chip based on the first parameter, and set the boundary router in the target chip; the layout quantity of the boundary router in the target chip is proportional to the first traffic.

[0038] In a third aspect, the present application provides a device, where the device includes a memory and a processor, the memory is used to store instructions or codes, and the processor is used to execute the instructions or codes so that the device executes a method for configuring a boundary router in a 2.5D integrated circuit according to any one of the foregoing first aspects.

[0039] In a fourth aspect, the present application provides a computer storage medium, where code is stored in the computer storage medium, and when the code is run, the device running the code implements a method for configuring a boundary router in a 2.5D integrated circuit according to any one of the foregoing first aspects.

[0040] The present application provides a method and a device for configuring a boundary router in a 2.5D integrated circuit. When executing the method, first determine the sum of the traffic transmitted through the routers connected to the wafer substrate during the operation of the target chip, that is, the first traffic; then, determine the first parameter corresponding to the layout of the boundary router in the target chip according to the first traffic, determine the layout structure of the boundary router in the target chip according to the first parameter, and open the downward port permission of the routers at the corresponding positions in the target chip, so as to form the boundary router with this layout structure in the target chip. The greater the first traffic, the more routers are configured, so as to adaptively adjust the number of boundary routers with downward ports open in the target chip according to the traffic interaction between the chip and the wafer substrate. Instead of directly communicating all the routers on the chip with the wafer substrate, in this way, resource waste is reduced and power consumption is lowered. Description of the Drawings

[0041] To more clearly illustrate the technical solutions in this embodiment or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiment or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0042] Figure 1 Schematic diagram of a structure for connecting a prefabricated component to a wafer substrate provided by an embodiment of the present application;

[0043] Figure 2 Schematic diagram of a structure for communicatively connecting a prefabricated component to a wafer substrate provided by an embodiment of the present application;

[0044] Figure 3 Schematic flow diagram of a method for configuring a boundary router in a 2.5D integrated circuit provided by an embodiment of the present application;

[0045] Figure 4 Schematic diagram of a connection structure between a router and a wafer substrate in a target chip provided by an embodiment of the present application;

[0046] Figure 5 Schematic layout diagram of a boundary router provided by an embodiment of the present application;

[0047] Figure 6 Schematic diagram of a structure of a boundary router configuration device in a 2.5D integrated circuit provided by an embodiment of the present application. Detailed implementation manners

[0048] Integrated circuit technology is the cornerstone of informatization and intelligence. As the chip process technology continues to approach the quantum effect region, the improvement of single-chip performance has approached the ceiling. Moore's Law and Dennard Scaling Law have gradually failed, and the cost performance of improving chip performance and power consumption through IC process technology upgrades is getting lower and lower. In order to continue the development of chip performance, in recent years, the industry has actively explored in the direction of wafer integration. For example, in 2019, Cerebras Systems released the world's largest chip wafer-scale engine (WSE) at that time, verifying the possibility of wafer-level integration. In August 2021, Tesla released the Dojo system-on-wafer processor, placing the chips on a carrier wafer and performing wafer-level interconnection (InFO_SoW).

[0049] At present, 2.5D integrated circuits incorporate advanced concepts such as prefabricated component assembly and wafer integration. Leveraging the advantages of high bandwidth, low latency, and low power consumption of wafer-level interconnections, a large number of prefabricated component particles such as computing, storage, and sensing can be integrated on a single wafer. Refer to Figure 1 A schematic structural diagram of the connection between a prefabricated component and a wafer substrate as shown. The prefabricated component and the wafer substrate are bonded together through a microbump array at the bottom of the prefabricated component and a microbump array at the top of the wafer substrate. A redistribution layer, through-silicon vias, on-substrate networks, etc. are implemented on the wafer substrate. Among them, the prefabricated component can be an IP core provided by a third party or a custom chip. For the IP core provided by a third party, the internal structure cannot be changed, and existing research has been relatively complete. However, for custom chips, it involves the interconnection of internal units of the chip and the interconnection between the chip and the wafer substrate, and its research has just started. Refer to Figure 2 A schematic structural diagram of the communication connection between a prefabricated component and a wafer substrate as shown. Each prefabricated component has a fixed core array distributed in a mesh pattern, and each core is equipped with a router. When the data traffic is small, if the downlink ports of all routers on the custom chip are open, it will bring unnecessary power consumption and waste resources.

[0050] Therefore, this application mainly aims at the interconnection network of the wafer system integrating custom chips, and proposes a method and device for configuring boundary routers in 2.5D integrated circuits. The number and distribution positions of the routers communicating with the wafer substrate in the custom chip are adjusted according to the size of the data traffic. In this way, the 2.5D integrated circuit is used to break through the limitation of the current microelectronics process limit on improving the chip integration density, and at the same time, the innovation of the ultra-dense integration and assembly process is realized through the collaborative calculation of software and hardware to reduce resource waste and power consumption.

[0051] It should be noted that the execution subject of the above method is not limited in the embodiments of this application. For example, a method for configuring boundary routers in 2.5D integrated circuits in the embodiments of this application can be applied to data processing devices such as terminal devices or servers. Among them, the terminal device can be a smart phone, a computer, a personal digital assistant (Personal Digital Assistant, PDA), or a tablet computer, etc. The server can be an independent server, a cluster server, or a cloud server.

[0052] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only, and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, a sufficient understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be shown in a simplified manner.

[0053] In the description and claims of the embodiments of the present disclosure and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so as to implement the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0054] Unless otherwise specified, the term "plurality" means two or more. In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B. The term "and / or" is a description of the associated relationship of objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B these three relationships.

[0055] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present application.

[0056] See Figure 3 , Figure 3 is a schematic flowchart of a method for configuring a boundary router in a 2.5D integrated circuit provided by an embodiment of the present application. A method for configuring a boundary router in a 2.5D integrated circuit includes:

[0057] S301. Determine the sum of the traffic transmitted on the links connecting the routers included in the target chip to the wafer substrate to obtain a first traffic, where the target chip is one of the chips connected to the wafer substrate.

[0058] Optionally, the routers in the above-mentioned target chip may be distributed in a matrix, and specifically, reference may be made to Figure 4 shown in a schematic diagram of the connection structure between the routers in a target chip and the wafer substrate. The routers included in the target chip (indicated by the blue dots in the Figure 4 target chip) communicate with the wafer substrate through links (such as the Figure 4 vertical link V in) for transmitting the transmission information between the routers in the target chip and the wafer substrate.

[0059] Optionally, the sum of the traffic transmitted on the links connecting all the routers included in the target chip to the wafer substrate within a predicted time period (for example, per second) is calculated.

[0060] S302. Determine a first parameter for configuring a border router in the target chip according to the first traffic, where the border router is a router with open permissions for the downstream port in the target chip.

[0061] Each router in the target chip includes a downstream port, which is connected to the corresponding port of the router on the wafer substrate. Among them, the router with open permissions for the downstream port in the target chip is called a border router.

[0062] Optionally, the above first parameter is used to reflect the configuration of the border router in the target chip, such as the configuration ratio or the configuration quantity.

[0063] S303. Determine the layout structure of the border router in the corresponding target chip based on the first parameter, and set the border router in the target chip; the layout quantity of the border router in the target chip is proportional to the first traffic.

[0064] Optionally, the layout structure of the border router in the target chip includes the layout quantity of the border router (the router with open permissions for the downstream port in the target chip) in the target chip and the relative positions between the border routers. For example, when the routers in the target chip are distributed in a matrix, the layout structure may include the number of rows and columns of the border routers configured in the target chip, as well as the number of row intervals of the border routers in each row (the number of routers between adjacent two border routers in each row of the border routers) and the number of column intervals of the border routers in each column (the number of routers between adjacent two border routers in each column of the border routers).

[0065] Based on the above steps S301 - S303, it can be seen that the number of border routers configured in the target chip is configured according to the magnitude of the first traffic, so as to ensure that there are sufficient links for communication transmission when the traffic is large, and reduce the configuration of border routers and resource waste when the traffic is small.

[0066] In the embodiments of the present application, there are multiple possible implementation manners for the above first parameter to determine the layout structure corresponding to the first traffic, which will be introduced respectively below. It should be noted that the implementation manners given in the following introduction are only exemplary descriptions and do not represent all the implementation manners of the embodiments of the present application.

[0067] In the first possible implementation manner, to determine the first parameter for setting the border router in the target chip according to the first traffic, it can be:

[0068] First, determine a second parameter according to the first traffic and a preset traffic threshold.

[0069] Then, query the parameter interval to which the second parameter belongs as the first parameter.

[0070] The second parameter can be determined based on the comparison between the actual transmitted traffic value (the first traffic) between the target chip and the wafer substrate and a preset traffic threshold. The above parameter range can be set with multiple different value ranges according to the possible values of the second parameter. In this way, when the actual transmitted first traffic is determined, the corresponding parameter range can be quickly determined, and this parameter range is used as the first parameter. Subsequently, the layout structure of the preset boundary router corresponding to this parameter range can be quickly called, reducing the calculation amount.

[0071] Based on the above possible implementation methods, there are multiple possible examples when determining the second parameter. The specific examples can be as follows:

[0072] In one example, the second parameter is determined according to the ratio of the first traffic to the traffic threshold.

[0073] Second parameter = First traffic S ÷ Traffic threshold L.

[0074] Optionally, the above traffic threshold L can be a value set according to human needs.

[0075] Exemplarily, the above traffic threshold can be the maximum value of the traffic transmitted by the communication connection between the target chip and the wafer substrate. Furthermore, based on the second parameter obtained by dividing the first traffic by the traffic threshold, the [0, 100%] can correspondingly be divided into multiple parameter ranges. For example, it can be divided into three parameter ranges of [0, 25%], (25%, 75%], and (75%, 100%].

[0076] In another example, the value obtained by multiplying the total number of routers in the target chip by the first ratio is rounded up to obtain the first number of boundary routers set in the target chip, and this first number is used as the second parameter; the first ratio is the ratio of the first traffic to the traffic threshold.

[0077] Optionally, it is set that the routers in the target chip are distributed in a matrix (see Figure 4 As shown, a layout method of routers in a chip is a 3×4 matrix distribution, and each router is connected to the wafer substrate through a corresponding vertical link V).

[0078] If the total number of rows of routers in the target chip is set as X and the total number of columns of routers in the target chip is set as Y. Then the calculation steps of the second parameter can be:

[0079] First calculate the total number of rows X × the total number of columns Y × the first traffic S ÷ the traffic threshold L, then round up the calculated value to obtain the first number, and use this first number as the second parameter.

[0080] Furthermore, using the first quantity as the second parameter, the range [0, the number of routers in the target chip (X×Y)] can be divided into multiple parameter intervals accordingly. For example, if the total number of rows of routers in the target chip is 5 and the total number of columns is 4, then the total number of routers in the target chip is 20, which can be divided into four parameter intervals: [0,5], (5,10], (10,15], and (15,20].

[0081] Further, based on step S303 above, based on the first parameter, the layout structure of the boundary routers in the target chip can be determined as follows: query the parameter interval to which the second parameter belongs, and determine the layout structure of the boundary routers in the target chip corresponding to the parameter interval; there are multiple parameter intervals, and each parameter interval is correspondingly configured with a layout structure of the boundary routers in the target chip.

[0082] It can be understood that after the above parameter interval division and confirmation, the number of boundary routers set in the target chip corresponding to each parameter interval remains unchanged. The target number of boundary routers set corresponding to each parameter interval can be the minimum number of boundary routers required for the target chip to operate normally within the range corresponding to the parameter interval. Of course, it can also be greater than the minimum number but not exceed the total number of routers in the target chip.

[0083] Optionally, a table can be set based on the divided multiple parameter intervals. Each parameter interval in the table corresponds to the layout structure of the boundary routers with the target number corresponding to this parameter interval in the target chip. This layout structure can be the distribution position of the boundary routers with this target number. Preferably, they can be arranged as evenly as possible to achieve a load-balanced distribution as much as possible.

[0084] In this way, by querying the parameter interval to which the second parameter belongs, the layout structure of the boundary routers in the target chip corresponding to the parameter interval can be determined. By determining the number of boundary routers according to different traffic sizes, the power consumption of the entire system can be saved, unnecessary resource waste can be avoided as much as possible when the traffic is small, and load balance can be taken into account to reduce the occurrence of hotspots. At the same time, multiple parameter intervals can be flexibly set. Once the parameter interval is determined, only need to look up the table to determine the layout structure of the boundary routers corresponding to the parameter interval, and then the boundary routers of the target chip can be set, reducing the calculation of the layout structure corresponding to the second parameter and saving computing resources.

[0085] Further, the specific steps to determine the layout structure correspondingly configured for each parameter interval according to the target number corresponding to each parameter interval can be as follows:

[0086] First, determine the target number of border routers set for the target chip corresponding to each parameter interval, where the target number is greater than or equal to the minimum number of border routers that need to be configured for the normal operation of the target chip within the range of the parameter interval.

[0087] Each parameter interval corresponds to a target number of border routers set in the target chip. By determining the parameter interval to which the second parameter belongs, the target number of border routers set in the target chip can be determined.

[0088] Secondly, according to the target number, the total number of rows and columns of the routers in the target chip, determine the first number of rows and the first number of columns of the border routers in the target chip.

[0089] Optionally, according to the comparison between the total number of rows and the total number of columns of the target chip, arrange the first number of rows and the first number of columns of the border routers in the target chip correspondingly. For example, when the ratio of the total number of rows to the total number of columns of the target chip is relatively large, the ratio of the first number of rows to the first number of columns of the border routers can also be increased correspondingly. In addition, the product of the first number of rows and the second number of rows of the border routers in the target chip is equal to the target number.

[0090] Then, according to the total number of rows, the total number of columns, the first number of rows, and the first number of columns, determine the row interval number and the column interval number of the border routers in the target chip.

[0091] Optionally, try to evenly distribute the border routers in each row and each column among the routers in the corresponding row or column, and try to make the number of router intervals between adjacent two border routers the same.

[0092] Finally, according to the first number of rows, the first number of columns, the row interval number, and the column interval number, determine the layout structure of the border routers centrally set in the target chip corresponding to the parameter interval.

[0093] In this way, after determining the first number of rows, the first number of columns, the row interval number, and the column interval number of the border routers in the target chip, an overall layout structure of the border routers is formed, and this layout structure is preferably set in the middle position of the target chip. In this way, setting the target number of border routers in the target chip can achieve load balancing as much as possible and reduce the occurrence of hotspots, which may affect performance and the lifespan of components.

[0094] In the second possible implementation manner, according to the first traffic, determine the first parameter for setting the border routers in the target chip. It can be that, after multiplying the total number of routers in the target chip by the first ratio and rounding up the obtained value, the target number of border routers set in the target chip is obtained, and this target number is used as the first parameter.

[0095] Thus, determine the target number of border routers in the target chip according to actual calculations, and correspondingly calculate the layout structure of the border routers with this target number in the target chip, and calculate and determine the border router layout structure adapted to the first traffic.

[0096] Further, the border routers in the target chip are distributed in a matrix. The specific steps for determining the layout structure of the border routers in the corresponding target chip based on the first parameter may include:

[0097] First, determine the first number of rows and the first number of columns of the border routers in the target chip according to the target number, the total number of rows and the total number of columns of the routers in the target chip.

[0098] Optionally, according to the comparison between the total number of rows and the total number of columns of the routers in the target chip, correspondingly arrange the first number of rows and the first number of columns of the border routers in the target chip. For example, when the ratio of the total number of rows to the total number of columns of the target chip is relatively large, the ratio of the first number of rows to the first number of columns of the border routers can also be correspondingly increased. In addition, the product of the first number of rows and the second number of rows of the border routers in the target chip is equal to the target number.

[0099] Second, determine the row interval number and the column interval number of the border routers in the target chip according to the total number of rows, the total number of columns, the first number of rows, and the first number of columns.

[0100] Optionally, try to make the number of router intervals between adjacent two border routers the same.

[0101] Finally, determine the layout structure of the border routers centrally arranged in the target chip according to the first number of rows, the first number of columns, the row interval number, and the column interval number.

[0102] Through calculation, more accurately determine the layout structure corresponding to the border routers with the target number specifically adapted to the current first traffic. At the same time, set the border routers with the target number corresponding to the first traffic in the target chip, and distribute the layout structure of the border routers with the target number as much as possible in the middle position of the target chip to achieve load balancing as much as possible and reduce the occurrence of hotspots that affect performance and the lifespan of components.

[0103] Based on the above two possible implementation methods, the calculation steps for determining the first number of rows and the first number of columns of the border routers in the target chip according to the target number, the total number of rows and the total number of columns of the routers in the target chip may be:

[0104] First, calculate the square root of the product of the target number and the second ratio to obtain a first value; round the first value to obtain the number of rows to be adjusted; the second ratio is the ratio of the total number of rows X to the total number of columns Y of the routers in the target chip.

[0105] Optionally, set the target quantity to M, then the number of rows to be adjusted where ROUND is rounding.

[0106] Secondly, calculate the square root of the product of the target quantity and the third ratio to obtain a second value, and round the second value to obtain the number of columns to be adjusted; the third ratio is the ratio of the total number of columns Y to the total number of rows X.

[0107] The number of rows to be adjusted

[0108] Finally, if the product of the number of rows to be adjusted and the number of columns to be adjusted is less than the target quantity, increase the number of rows to be adjusted by one or increase the number of columns to be adjusted by one; if the product of the number of rows to be adjusted and the number of columns to be adjusted is greater than the target quantity, decrease the number of rows to be adjusted by one or decrease the number of columns to be adjusted by one, until the product of the adjusted number of rows to be adjusted and the adjusted number of columns to be adjusted is the target quantity. Take the adjusted number of rows to be adjusted as the first number of rows, and take the adjusted number of columns to be adjusted as the first number of columns.

[0109] It can be understood that if r×c is not equal to M, then r and c can be adjusted, and the adjustment can be made by increasing or decreasing one row or one column until r×c is equal to M to complete the adjustment, and the adjusted r is the first number of rows, and the adjusted c is the first number of columns.

[0110] Exemplarily, refer to Figure 5 the schematic diagram of the layout structure of a border router shown, set the network topology on the custom chip to X×Y, X = 5, Y = 4, and the target quantity M = 4.

[0111] According to determine that the number of rows to be adjusted r = 2, according to determine that the number of columns to be adjusted c = 2. Since r×c = M, no adjustment is required.

[0112] Based on the above two possible implementation methods, the above-mentioned steps for determining the row spacing number and column spacing number of the border routers in the target chip according to the total number of rows, the total number of columns, the first number of rows and the first number of columns may include:

[0113] Divide the difference obtained by subtracting one from the total number of rows by the first number of rows to obtain a third value; round the third value to obtain the row spacing number of the border routers in each row of the target chip.

[0114] Row spacing number

[0115] Divide the difference obtained by subtracting one from the total number of columns by the number of the first column to get a fourth value; round the fourth value to an integer to obtain the number of column intervals of the boundary routers in each column of the target chip.

[0116] Number of column intervals

[0117] In addition, if r = 1, disperse and determine c boundary routers in a relatively centered column. If c = 1, disperse and determine r boundary routers in a relatively centered row. Try to ensure load balancing.

[0118] Based on the above Figure 5 example, after calculating r = 2 and c = 2, determine the number of row intervals w = 2 and the number of column intervals h = 1 through the above calculation steps. Finally, the setting structure of the boundary routers is as Figure 5 shown. Figure 5 In the figure, the routers represented by the black dots are the routers in the custom chip that open the downlink port permission, that is, the boundary routers, while the routers represented by the gray dots are the routers in the custom chip that do not open the downlink port permission.

[0119] The above are some specific implementation manners of the method provided by the embodiments of the present application. Based on this, the present application also provides a corresponding device. Next, the device provided by the embodiments of the present application will be introduced from the perspective of functional modularization.

[0120] Refer to Figure 6 the structural schematic diagram of a boundary router configuration device in a 2.5D integrated circuit shown. A boundary router configuration device in a 2.5D integrated circuit includes:

[0121] An obtaining unit 601, which includes determining the sum of the traffic transmitted on the vertical links connecting the routers included in the target chip to the wafer substrate to obtain a first traffic, where the target chip is one of the chips connected to the wafer substrate.

[0122] A processing unit 602, configured to determine a first parameter for configuring boundary routers in the target chip according to the first traffic, where the boundary routers are the routers in the target chip with open downlink port permissions.

[0123] A determining unit 603, configured to determine the layout structure of the boundary routers in the corresponding target chip based on the first parameter and set the boundary routers in the target chip; the layout quantity of the boundary routers in the target chip is proportional to the first traffic.

[0124] Based on the above structure, in this application, the acquisition unit 601 determines the sum of the traffic transmitted through the connection between the target chip and the wafer substrate via the router during operation, that is, the first traffic. Then, the processing unit 602 determines the first parameter corresponding to the layout boundary router in the target chip according to the first traffic. Finally, the determination unit 603 determines the layout structure of the boundary router in the target chip according to the first parameter, and opens the downlink port permissions of the routers at the corresponding positions in the target chip, so as to form the boundary router with this layout structure in the target chip. The greater the first traffic, the more routers are configured, so as to adaptively adjust the number of boundary routers with open downlink ports in the target chip according to the traffic interaction between the chip and the wafer substrate. Instead of directly communicating all the routers on the chip with the wafer substrate, in this way, resource waste is reduced and power consumption is lowered.

[0125] In a possible implementation manner, the processing unit 602 is specifically configured to determine a second parameter according to the first traffic and a preset traffic threshold; query the parameter interval to which the second parameter belongs as the first parameter.

[0126] Optionally, the processing unit 602 is specifically configured to determine the second parameter according to the ratio of the first traffic to the traffic threshold; or, round up the value obtained by multiplying the total number of routers in the target chip by the first ratio to obtain the first number of boundary routers set in the target chip, and use the first number as the second parameter; the first ratio is the ratio of the first traffic to the traffic threshold.

[0127] Optionally, the determination unit 603 is specifically configured to query the parameter interval to which the second parameter belongs and determine the layout structure of the boundary router in the target chip corresponding to the parameter interval; there are multiple parameter intervals, and each parameter interval is correspondingly configured with a layout structure of the boundary router in the target chip.

[0128] The boundary routers in the target chip are distributed in a matrix. The determination unit 603 is specifically configured to determine the target number of boundary routers set in the target chip corresponding to each parameter interval, and the target number is greater than or equal to the minimum number of boundary routers required for the normal operation of the target chip within the range of the parameter interval; according to the target number, the total number of rows and columns of routers in the target chip, determine the first number of rows and the first number of columns of the boundary routers in the target chip; according to the total number of rows, the total number of columns, the first number of rows and the first number of columns, determine the row interval number and the column interval number of the boundary routers in the target chip; according to the first number of rows, the first number of columns, the row interval number and the column interval number, determine the layout structure of the boundary routers centrally arranged in the target chip corresponding to the parameter interval.

[0129] In a possible implementation, the processing unit 602 is specifically configured to round up the value obtained by multiplying the total number of routers in the target chip by the first ratio, to obtain the target number of boundary routers set in the target chip, and use the target number as the first parameter.

[0130] Optionally, the determining unit 603 is specifically configured to determine the first number of rows and the first number of columns of the boundary routers in the target chip according to the target number, the total number of rows and the total number of columns of the routers in the target chip; determine the row interval number and the column interval number of the boundary routers in the target chip according to the total number of rows, the total number of columns, the first number of rows and the first number of columns; and determine the layout structure of the boundary routers centrally set in the target chip according to the first number of rows, the first number of columns, the row interval number and the column interval number.

[0131] In a possible implementation, the determining unit 603 is specifically configured to calculate the square root of the product of the target number and the second ratio to obtain a first value; round up the first value to obtain the number of rows to be adjusted; the second ratio is the ratio of the total number of rows to the total number of columns; calculate the square root of the product of the target number and the third ratio to obtain a second value, round up the second value to obtain the number of columns to be adjusted; the third ratio is the ratio of the total number of columns to the total number of rows; if the product of the number of rows to be adjusted and the number of columns to be adjusted is less than the target number, increase the number of rows to be adjusted by one or increase the number of columns to be adjusted by one; if the product of the number of rows to be adjusted and the number of columns to be adjusted is greater than the target number, decrease the number of rows to be adjusted by one or decrease the number of columns to be adjusted by one, until the product of the adjusted number of rows to be adjusted and the adjusted number of columns to be adjusted is the target number, use the adjusted number of rows to be adjusted as the first number of rows, and use the adjusted number of columns to be adjusted as the first number of columns.

[0132] In a possible implementation, the determining unit 603 is specifically configured to divide the difference obtained by subtracting one from the total number of rows by the first number of rows to obtain a third value; round the third value to the nearest integer to obtain the row interval number of the boundary routers in each row of the target chip; divide the difference obtained by subtracting one from the total number of columns by the first number of columns to obtain a fourth value; round the fourth value to the nearest integer to obtain the column interval number of the boundary routers in each column of the target chip.

[0133] The embodiments of the present application further provide corresponding devices and computer storage media for implementing the solutions provided by the embodiments of the present application.

[0134] Among them, the device includes a memory and a processor. The memory is used to store instructions or code, and the processor is used to execute the instructions or code so that the device executes a method for configuring a boundary router in a 2.5D integrated circuit according to any embodiment of the present application.

[0135] Code is stored in the computer storage medium. When the code runs, the device running the code implements a method for configuring a boundary router in a 2.5D integrated circuit according to any embodiment of the present application.

[0136] In the embodiments of the present application, the "first", "second" (if any) in the names such as "first" and "second" are only used as name identifiers and do not represent the first and second in order.

[0137] From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as read-only memory (ROM) / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment or some parts of the embodiments of the present application.

[0138] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.

[0139] The above is only an exemplary embodiment of the present application and is not used to limit the protection scope of the present application.

Claims

1. A method for configuring a border router in a 2.5D integrated circuit, characterized in that: include: Determine the sum of traffic transmitted on a link connecting a router included in a target chip and a wafer substrate to obtain a first traffic, wherein the target chip is one of the chips connected to the wafer substrate; Determine, according to the first traffic, a first parameter for configuring a border router in the target chip, wherein the border router is a router with open downlink port permissions in the target chip; The layout structure of the border router in the corresponding target chip is determined based on the first parameter, and the border router in the target chip is set; the layout quantity of the border router in the target chip is proportional to the first traffic.

2. The method according to claim 1, characterized in that The step of determining, according to the first traffic, a first parameter for setting a border router in the target chip includes: Determining a second parameter according to the first flow rate and a preset flow rate threshold; A parameter interval to which the second parameter belongs is queried as the first parameter.

3. The method according to claim 2, characterized in that The determining a second parameter according to the first flow rate and a preset flow rate threshold comprises: determining the second parameter according to a ratio of the first flow rate to the flow rate threshold; Or, round up the value obtained by multiplying the total number of routers in the target chip by the first ratio to obtain the first number of border routers set in the target chip, and use the first number as the second parameter; the first ratio is the ratio of the first traffic to the traffic threshold.

4. The method according to claim 2 or 3, characterized in that: The determining, based on the first parameter, a layout structure of a border router in a corresponding target chip includes: The parameter interval to which the second parameter belongs is queried to determine the layout structure of the border router in the target chip corresponding to the parameter interval; there are multiple parameter intervals, and each parameter interval is correspondingly configured with a layout structure of the border router in the target chip.

5. The method according to claim 4, characterized in that The border routers in the target chip are distributed in a matrix, and the steps of configuring a layout structure of a border router in the target chip corresponding to each parameter interval include: Determine a target number of border routers to be set for the target chip corresponding to each parameter interval, wherein the target number is greater than or equal to a minimum number of border routers required to be configured for normal operation of the target chip within the interval range of the parameter interval; Determine a first number of rows and a first number of columns of edge routers in the target chip according to the target number, the total number of rows and the total number of columns of routers in the target chip; Determine the row interval number and column interval number of the border router in the target chip according to the total number of rows, the total number of columns, the first number of rows, and the first number of columns; A layout structure in which a border router is centrally arranged in a target chip corresponding to the parameter interval is determined according to the first number of rows, the first number of columns, the number of row intervals, and the number of column intervals.

6. The method according to claim 1, characterized in that Determining the first parameter for configuring the border router in the target chip based on the first traffic includes: rounding up the value obtained by multiplying the total number of routers in the target chip by the first ratio to obtain a target number of border routers set in the target chip, and using the target number as the first parameter.

7. The method according to claim 6, characterized in that The border routers in the target chip are distributed in a matrix, and the determining the layout structure of the border routers in the corresponding target chip based on the first parameter includes: Determine a first number of rows and a first number of columns of edge routers in the target chip according to the target number, the total number of rows and the total number of columns of routers in the target chip; Determine the row interval number and column interval number of the border router in the target chip according to the total number of rows, the total number of columns, the first number of rows, and the first number of columns; A layout structure in which a border router is centrally arranged in a target chip is determined according to the first number of rows, the first number of columns, the number of row intervals, and the number of column intervals.

8. The method according to claim 5 or 7, characterized in that: The step of determining the first number of rows and the first number of columns of the border routers in the target chip according to the target number, the total number of rows and the total number of columns of the routers in the target chip, comprises: Calculate the square root of the product of the target number and the second ratio to obtain a first value; round the first value to obtain the number of rows to be adjusted; the second ratio is the ratio of the total number of rows to the total number of columns; Calculate the square root of the product of the target number and a third ratio to obtain a second value, and round the second value to obtain the number of columns to be adjusted; the third ratio is the ratio of the total number of columns to the total number of rows; If the product of the number of rows to be adjusted and the number of columns to be adjusted is less than the target number, the number of rows to be adjusted is increased by one or the number of columns to be adjusted is increased by one; if the product of the number of rows to be adjusted and the number of columns to be adjusted is greater than the target number, the number of rows to be adjusted is reduced by one or the number of columns to be adjusted is reduced by one, until the product of the adjusted number of rows to be adjusted and the number of columns to be adjusted is the target number, and the adjusted number of rows to be adjusted is used as the first row number, and the adjusted number of columns to be adjusted is used as the first column number.

9. The method according to claim 7 or 8, characterized in that: Determining the row interval number and column interval number of the border router in the target chip according to the total number of rows, the total number of columns, the first number of rows, and the first number of columns includes: Divide the difference between the total number of rows and the first number of rows to obtain a third value; round the third value to an integer to obtain the number of row intervals of the boundary reason device of each row in the target chip; The difference value obtained by subtracting one from the total number of columns is divided by the first number of columns to obtain a fourth value; the fourth value is rounded to an integer to obtain the number of column intervals of the boundary reason devices of each column in the target chip.

10. A device for configuring a border router in a 2.5D integrated circuit, characterized in that: include: An acquisition unit, comprising determining a sum of flows transmitted on a vertical link connecting a router included in a target chip and a wafer substrate, to obtain a first flow, wherein the target chip is one of the chips connected to the wafer substrate; A processing unit, configured to determine, according to the first traffic, a first parameter for configuring a border router in the target chip, wherein the border router is a router with open downlink port permissions in the target chip; A determination unit is used to determine the layout structure of the border router in the corresponding target chip based on the first parameter, and set the border router in the target chip; the layout quantity of the border router in the target chip is proportional to the first flow.

Images